Re: [U-Boot] [upstream-release] [PATCH 3/3] armv8: fsl-layerscape: avoid DT fixup warning
> -Original Message-
> From: upstream-release-boun...@linux.nxdi.nxp.com boun...@linux.nxdi.nxp.com> On Behalf Of laurentiu.tu...@nxp.com
> Sent: Wednesday, January 30, 2019 5:31 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Laurentiu Tudor
> Subject: [upstream-release] [PATCH 3/3] armv8: fsl-layerscape: avoid DT
> fixup warning
>
> From: Laurentiu Tudor
>
> sec_firmware reserves JR3 for it's own usage and deletes the JR3 node from
> the device tree. This causes this warning to be issued when doing the device
> tree fixup:
Do you think it is fair to assume that firmware will always reserve JR3?
Thanks
-Bharat
>
> WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
>
> Fix it by excluding the device tree fixup for the JR reserved by sec_firmware.
>
> Signed-off-by: Laurentiu Tudor
> ---
> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> index e7a8801262..f971af8d26 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
>
> struct icid_id_table {
> const char *compat;
> @@ -98,7 +99,13 @@ void fdt_fixup_icid(void *blob);
> CONFIG_SYS_FSL_SEC_ADDR)
>
> #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
> - SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
> + SET_ICID_ENTRY( \
> + (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
> + (FSL_SEC_JR##jr_num##_OFFSET == \
> + SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
> + ? NULL \
> + : "fsl,sec-v4.0-job-ring"), \
> + streamid, \
> (((streamid) << 16) | (streamid)), \
> offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
> CONFIG_SYS_FSL_SEC_ADDR, \
> --
> 2.17.1
>
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Re: [U-Boot] [upstream-release] [PATCH 1/3] fsl_sec: fix register layout on Layerscape architectures
> -Original Message-
> From: upstream-release-boun...@linux.nxdi.nxp.com boun...@linux.nxdi.nxp.com> On Behalf Of laurentiu.tu...@nxp.com
> Sent: Wednesday, January 30, 2019 5:31 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Laurentiu Tudor
> Subject: [upstream-release] [PATCH 1/3] fsl_sec: fix register layout on
> Layerscape architectures
>
> From: Laurentiu Tudor
>
> On Layerscape architectures the SEC memory map is 1MB and the register
> blocks contained in it are 64KB aligned, not 4KB as the ccsr_sec structure
> currently assumes. Fix the layout of the structure for these architectures.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Bharat Bhushan
> ---
> include/fsl_sec.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/include/fsl_sec.h b/include/fsl_sec.h index
> 16e3fcb5a1..be08a2b88b 100644
> --- a/include/fsl_sec.h
> +++ b/include/fsl_sec.h
> @@ -121,10 +121,18 @@ typedef struct ccsr_sec {
> u32 chanum_ls; /* CHA Number Register, LS */
> u32 secvid_ms; /* SEC Version ID Register, MS */
> u32 secvid_ls; /* SEC Version ID Register, LS */
> +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
> + u8 res9[0x6f020];
> +#else
> u8 res9[0x6020];
> +#endif
> u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS
> */
> u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
> +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
> + u8 res10[0x8ffd8];
> +#else
> u8 res10[0x8fd8];
> +#endif
> } ccsr_sec_t;
>
> #define SEC_CTPR_MS_AXI_LIODN0x0800
> --
> 2.17.1
>
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Re: [U-Boot] [upstream-release] [PATCH] pci: layerscape: add option to statically allocate PCI StreamIDs
> -Original Message-
> From: upstream-release-boun...@linux.nxdi.nxp.com boun...@linux.nxdi.nxp.com> On Behalf Of laurentiu.tu...@nxp.com
> Sent: Wednesday, January 30, 2019 5:31 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Laurentiu Tudor
> Subject: [upstream-release] [PATCH] pci: layerscape: add option to statically
> allocate PCI StreamIDs
>
> From: Laurentiu Tudor
>
> Certain PCI scenarios have more dynamic requirements, e.g. endpoints are
> "hot-plugged" later in the system lifetime. Add a Kconfig option that allows
> specifying a maximum number of end-points, per PCI controller and allocate
> a StreamID for each one.
>
> Signed-off-by: Laurentiu Tudor
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 28 +
> drivers/pci/pcie_layerscape_fixup.c | 38 +++
> 2 files changed, 66 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 2b086da79b..1d633d71a8 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -571,3 +571,31 @@ config TFABOOT
> help
> Enabling this will make a U-Boot binary that is capable of being
> booted via TFA.
> +
> +menuconfig FSL_PCIE_STATIC_STREAM_IDS
> + bool "Allocate PCI streamIDs statically"
> + default n
> + depends on PCIE_LAYERSCAPE
> + help
> + Statically allocate a certain number of StreamIDs for each PCI
> + controller, instead of enumerating the connected endpoints and
> + allocate a StreamID for each one. This allocation method can
> + be used in more dynamic PCI scenarios, e.g. where endpoints are
> + "hot-plugged" later in the system bringup, by statically specifying
> + a maximum number of StreamIDs expected for each PCI controller.
> +
> +if FSL_PCIE_STATIC_STREAM_IDS
> +
> +config FSL_PCIE1_STREAM_IDS_COUNT
> + default 3
> + int "Maximum number of streamIDs to allocate for PCI1 controller"
> +
> +config FSL_PCIE2_STREAM_IDS_COUNT
> + default 3
> + int "Maximum number of streamIDs to allocate for PCI2 controller"
> +
> +config FSL_PCIE3_STREAM_IDS_COUNT
> + default 3
> + int "Maximum number of streamIDs to allocate for PCI3 controller"
> +
> +endif
> diff --git a/drivers/pci/pcie_layerscape_fixup.c
> b/drivers/pci/pcie_layerscape_fixup.c
> index 1a17bd98aa..32355cbf2e 100644
> --- a/drivers/pci/pcie_layerscape_fixup.c
> +++ b/drivers/pci/pcie_layerscape_fixup.c
> @@ -177,6 +177,7 @@ static void fdt_pcie_set_iommu_map_entry(void
> *blob, struct ls_pcie *pcie,
>
> static void fdt_fixup_pcie(void *blob)
> {
> +#if !CONFIG_FSL_PCIE_STATIC_STREAM_IDS
> struct udevice *dev, *bus;
> struct ls_pcie *pcie;
> int streamid;
> @@ -215,6 +216,43 @@ static void fdt_fixup_pcie(void *blob)
> fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
>streamid);
> }
> +#else
> + static const int streamid_cnt[] = {
> + CONFIG_FSL_PCIE1_STREAM_IDS_COUNT,
> + CONFIG_FSL_PCIE2_STREAM_IDS_COUNT,
> + CONFIG_FSL_PCIE3_STREAM_IDS_COUNT
Why 3 controllers?
> + };
> + struct ls_pcie *pcie;
> + int i, streamid, index;
> + pci_dev_t bdf;
> +
> + list_for_each_entry(pcie, _pcie_list, list) {
> + for (i = 0; i < streamid_cnt[pcie->idx]; i++) {
> + streamid = ls_pcie_next_streamid();
> + if (streamid < 0) {
> + debug("ERROR: no stream ids free\n");
> + continue;
Why to continue if we are out of stream-ids?
> + }
> +
> + index = ls_pcie_next_lut_index(pcie);
> + if (index < 0) {
> + debug("ERROR: no LUT indexes free\n");
> + continue;
We can error out when out of LUT entry
> + }
> +
> + bdf = PCI_BDF(i, 0, 0);
> + /* map PCI b.d.f to streamID in LUT */
> + ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
> + streamid);
> + /* update msi-map in device tree */
> + fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
> +streamid);
> + /* update iommu-map in device tree */
> + fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >>
> 8,
> + streamid);
> + }
> + }
> +#endif /* !CONFIG_FSL_PCIE_STATIC_STREAM_IDS */
> }
> #endif
>
> --
> 2.17.1
>
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Re: [U-Boot] [PATCH v6 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree
> -Original Message- > From: Horia Geanta > Sent: Tuesday, July 31, 2018 9:49 PM > To: Laurentiu Tudor ; u-boot@lists.denx.de; > Prabhakar Kushwaha ; York Sun > > Cc: Bharat Bhushan > Subject: Re: [PATCH v6 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device > tree > > On 7/31/2018 5:53 PM, laurentiu.tu...@nxp.com wrote: > > From: Laurentiu Tudor > > > > Add support for SEC ICID configuration and apply it for ls1046a. > > Also add code to make the necessary device tree fixups. > > > > Signed-off-by: Laurentiu Tudor > Reviewed-by: Horia Geantă Reviewed-by: Bharat Bhushan Thanks -Bharat > > [snip] > > +#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ > > + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ > > + offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ > > + CONFIG_SYS_FSL_SEC_ADDR, 0) > > + > RTIC nodes have a binding doc in Linux kernel: > Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > Thus, in theory, "fsl,sec-v4.0-rtic-memory" could be used instead of NULL for > the compat string. > PPC code in arch/powerpc/include/asm/fsl_liodn.h does this. > > In practice, this won't make any difference until a RTIC kernel driver is > added. > > Regards, > Horia > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 7/8] armv8: ls1046a: setup fman ports ICIDs and device tree
> -Original Message-
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Tuesday, July 31, 2018 8:22 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Bharat Bhushan ; Horia Geanta
> ; Laurentiu Tudor
> Subject: [PATCH v6 7/8] armv8: ls1046a: setup fman ports ICIDs and device
> tree
>
> From: Laurentiu Tudor
>
> Add support for ICID setting of fman ports and the required device tree
> fixups.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Bharat Bhushan
Thanks
-Bharat
> ---
> arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
> .../asm/arch-fsl-layerscape/fsl_icid.h| 10 +++
> 3 files changed, 122 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> index ae3b8daa95..b1a950e7f9 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> @@ -10,6 +10,7 @@
> #include
> #include
> #include
> +#include
>
> static void set_icid(struct icid_id_table *tbl, int size) { @@ -19,10
> +20,27 @@
> static void set_icid(struct icid_id_table *tbl, int size)
> out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
>
> +#ifdef CONFIG_SYS_DPAA_FMAN
> +void set_fman_icids(struct fman_icid_id_table *tbl, int size) {
> + int i;
> + ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
> +
> + for (i = 0; i < size; i++) {
> + out_be32(>fm_bmi_common.fmbm_ppid[tbl[i].port_id
> - 1],
> + tbl[i].icid);
> + }
> +}
> +#endif
> +
> void set_icids(void)
> {
> /* setup general icid offsets */
> set_icid(icid_tbl, icid_tbl_sz);
> +
> +#ifdef CONFIG_SYS_DPAA_FMAN
> + set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); #endif
> }
>
> int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> num_ids) @@ -75,6 +93,66 @@ int fdt_fixup_icid_tbl(void *blob, int
> smmu_ph,
> return 0;
> }
>
> +#ifdef CONFIG_SYS_DPAA_FMAN
> +int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
> +const int size)
> +{
> + int i;
> +
> + for (i = 0; i < size; i++) {
> + if (tbl[i].port_id == port_id)
> + return tbl[i].icid;
> + }
> +
> + return -1;
> +}
> +
> +void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
> + const char *compat)
> +{
> + int noff, len, icid;
> + const u32 *prop;
> +
> + noff = fdt_node_offset_by_compatible(blob, -1, compat);
> + while (noff > 0) {
> + prop = fdt_getprop(blob, noff, "cell-index", );
> + if (!prop) {
> + printf("WARNING missing cell-index for fman
> port\n");
> + continue;
> + }
> + if (len != 4) {
> + printf("WARNING bad cell-index size for fman
> port\n");
> + continue;
> + }
> +
> + icid = get_fman_port_icid(fdt32_to_cpu(*prop),
> + fman_icid_tbl, fman_icid_tbl_sz);
> + if (icid < 0) {
> + printf("WARNING unknown ICID for fman port
> %d\n",
> +*prop);
> + continue;
> + }
> +
> + fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *), 1);
> +
> + noff = fdt_node_offset_by_compatible(blob, noff, compat);
> + }
> +}
> +
> +void fdt_fixup_fman_icids(void *blob, int smmu_ph) {
> + static const char * const compats[] = {
> + "fsl,fman-v3-port-oh",
> + "fsl,fman-v3-port-rx",
> + "fsl,fman-v3-port-tx",
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(compats); i++)
> + fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph,
> compats[i]); }
> +#endif
> +
> int fdt_get_smmu_phandle(void *blob)
> {
> int noff, smmu_ph;
> @@ -107,4 +185,8 @@ void fdt_fixup_icid(void *blob)
> return;
>
> fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
> +
> +#ifdef CONFIG_SYS_DPAA_FMAN
> + fdt_fixup_fman_icids(blob, smmu_ph);
> +#endif
> }
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> index 80e1ceadc0..30c7d8d28a 100644
> --- a/arch/arm/cpu/
Re: [U-Boot] [PATCH v6 5/8] armv8: ls1046a: initial icid setup support
> -Original Message-
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Tuesday, July 31, 2018 8:22 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Bharat Bhushan ; Horia Geanta
> ; Laurentiu Tudor
> Subject: [PATCH v6 5/8] armv8: ls1046a: initial icid setup support
>
> From: Laurentiu Tudor
>
> Add infrastructure for ICID setup and device tree fixup on ARM platforms.
> This include basic ICID setup for several devices.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Bharat Bhushan
Thanks
-Bharat
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
> arch/arm/cpu/armv8/fsl-layerscape/icid.c | 110 ++
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 29 +
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +
> .../asm/arch-fsl-layerscape/fsl_icid.h| 80 +
> board/freescale/ls1046aqds/ls1046aqds.c | 3 +
> board/freescale/ls1046ardb/ls1046ardb.c | 3 +
> 7 files changed, 229 insertions(+)
> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index 1e9e4680fe..5d6f68aad6 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -37,6 +37,7 @@ endif
>
> ifneq ($(CONFIG_ARCH_LS1046A),)
> obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
> +obj-y += icid.o ls1046_ids.o
> endif
>
> ifneq ($(CONFIG_ARCH_LS1088A),)
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> new file mode 100644
> index 00..ae3b8daa95
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> @@ -0,0 +1,110 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +
> +static void set_icid(struct icid_id_table *tbl, int size) {
> + int i;
> +
> + for (i = 0; i < size; i++)
> + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
> +
> +void set_icids(void)
> +{
> + /* setup general icid offsets */
> + set_icid(icid_tbl, icid_tbl_sz);
> +}
> +
> +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> +num_ids) {
> + int i, ret;
> + u32 prop[8];
> +
> + /*
> + * Note: The "iommus" property definition mentions Stream IDs
> while
> + * this code handles ICIDs. The current implementation assumes that
> + * ICIDs and Stream IDs are equal.
> + */
> + for (i = 0; i < num_ids; i++) {
> + prop[i * 2] = cpu_to_fdt32(smmu_ph);
> + prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
> + }
> + ret = fdt_setprop(blob, off, "iommus",
> + prop, sizeof(u32) * num_ids * 2);
> + if (ret) {
> + printf("WARNING unable to set iommus: %s\n",
> fdt_strerror(ret));
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
> +struct icid_id_table *tbl, int size) {
> + int i, err, off;
> +
> + for (i = 0; i < size; i++) {
> + if (!tbl[i].compat)
> + continue;
> +
> + off = fdt_node_offset_by_compat_reg(blob,
> + tbl[i].compat,
> + tbl[i].compat_addr);
> + if (off > 0) {
> + err = fdt_set_iommu_prop(blob, off, smmu_ph,
> + [i].id, 1);
> + if (err)
> + return err;
> + } else {
> + printf("WARNING could not find node %s: %s.\n",
> +tbl[i].compat, fdt_strerror(off));
> + }
> + }
> +
> + return 0;
> +}
> +
> +int fdt_get_smmu_phandle(void *blob)
> +{
> + int noff, smmu_ph;
> +
> + noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
> + if (noff < 0) {
> + printf("WARNING failed to get smmu node: %s\n",
> +fdt_strerror(noff));
> + return noff;
> + }
> +
> + smmu_ph = fdt_get_phandle(blob, noff);
> + if (!smmu_ph) {
>
Re: [U-Boot] [PATCH v6 6/8] armv8: ls1046a: add icid setup for qman portals
> -Original Message-
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Tuesday, July 31, 2018 8:22 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Bharat Bhushan ; Horia Geanta
> ; Laurentiu Tudor
> Subject: [PATCH v6 6/8] armv8: ls1046a: add icid setup for qman portals
>
> From: Laurentiu Tudor
>
> Add support for ICID setting of qman portals and the required device
> tree fixups. Also fix an endiness issue in portal setup code.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Bharat Bhushan
Thanks
-Bharat
> ---
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
> .../asm/arch-fsl-layerscape/fsl_portals.h | 24 +++
> drivers/misc/fsl_portals.c| 43 +++
> 3 files changed, 75 insertions(+), 8 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> index 1c528ab751..80e1ceadc0 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> @@ -6,6 +6,22 @@
> #include
> #include
> #include
> +#include
> +
> +#ifdef CONFIG_SYS_DPAA_QBMAN
> +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +};
> +#endif
>
> struct icid_id_table icid_tbl[] = {
> #ifdef CONFIG_SYS_DPAA_QBMAN
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> new file mode 100644
> index 00..1577e935a6
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef _FSL_PORTALS_H_
> +#define _FSL_PORTALS_H_
> +
> +struct qportal_info {
> + u16 dicid; /* DQRR ICID */
> + u16 ficid; /* frame data ICID */
> + u16 icid;
> + u8 sdest;
> +};
> +
> +#define SET_QP_INFO(streamid, dest) \
> + { .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \
> + .sdest = (dest) }
> +
> +extern struct qportal_info qp_info[];
> +void fdt_portal(void *blob, const char *compat, const char *container,
> + u64 addr, u32 size);
> +
> +#endif
> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> index 22faf16751..a524510707 100644
> --- a/drivers/misc/fsl_portals.c
> +++ b/drivers/misc/fsl_portals.c
> @@ -13,6 +13,9 @@
> #ifdef CONFIG_PPC
> #include
> #include
> +#else
> +#include
> +#include
> #endif
> #include
>
> @@ -45,6 +48,22 @@ void setup_qbman_portals(void)
> /* set frame liodn */
> out_be32(>qcsp[i].qcsp_io_cfg, (sdest << 16) |
> fliodn);
> }
> +#else
> +#ifdef CONFIG_ARM
> + int i;
> +
> + for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
> + u8 sdest = qp_info[i].sdest;
> + u16 ficid = qp_info[i].ficid;
> + u16 dicid = qp_info[i].dicid;
> + u16 icid = qp_info[i].icid;
> +
> + out_be32(>qcsp[i].qcsp_lio_cfg, (icid << 16) |
> + dicid);
> + /* set frame icid */
> + out_be32(>qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
> + }
> +#endif
> #endif
>
> /* Change default state of BMan ISDR portals to all 1s */
> @@ -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
> char compat[64];
> int compat_len;
>
> +#ifndef CONFIG_PPC
> + int smmu_ph = fdt_get_smmu_phandle(blob);
> +#endif
> +
> maj = (rev_1 >> 8) & 0xff;
> min = rev_1 & 0xff;
> ip_cfg = rev_2 & 0xff;
> @@ -188,7 +211,6 @@ void fdt_fixup_qportals(void *blob)
>
> off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
> while (off != -FDT_ERR_NOTFOUND) {
> -#ifdef CONFIG_PPC
> #ifdef CONFIG_FSL_CORENET
> u32 liodns[2];
> #endif
> @@ -198,12 +220,7 @@ void fd
Re: [U-Boot] [PATCH v6 4/8] armv8: fsl-layerscape: add missing debug stream ID
> -Original Message- > From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com] > Sent: Tuesday, July 31, 2018 8:22 PM > To: u-boot@lists.denx.de; Prabhakar Kushwaha > ; York Sun > Cc: Bharat Bhushan ; Horia Geanta > ; Laurentiu Tudor > Subject: [PATCH v6 4/8] armv8: fsl-layerscape: add missing debug stream ID > > From: Laurentiu Tudor > > Add a define with a value for the missing debug stream ID. > > Signed-off-by: Laurentiu Tudor Reviewed-by: Bharat Bhushan Thanks -Bharat > --- > arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h > b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h > index 61c6e533c6..1b02d484d9 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h > @@ -50,6 +50,7 @@ > #define FSL_QDMA_STREAM_ID 7 > #define FSL_EDMA_STREAM_ID 8 > #define FSL_ETR_STREAM_ID9 > +#define FSL_DEBUG_STREAM_ID 10 > > /* PCI - programmed in PEXn_LUT */ > #define FSL_PEX_STREAM_ID_START 11 > -- > 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 3/8] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
> -Original Message-
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Tuesday, July 31, 2018 8:22 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Bharat Bhushan ; Horia Geanta
> ; Laurentiu Tudor
> Subject: [PATCH v6 3/8] misc: fsl_portals: setup QMAN_BAR{E} also on ARM
> platforms
>
> From: Laurentiu Tudor
>
> QMAN_BAR{E} register setup was disabled on ARM platforms, however the
> register does need to be set. Enable the code also on ARMs and fix the
> CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the
> newly
> enabled code works.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Bharat Bhushan
Thanks
-Bharat
> ---
> arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
> drivers/misc/fsl_portals.c | 2 --
> 2 files changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index 644a16dd30..d22ec70aa5 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -57,8 +57,7 @@
> #define CONFIG_SYS_BMAN_SWP_ISDR_REG0x3E80
> #define CONFIG_SYS_QMAN_NUM_PORTALS 10
> #define CONFIG_SYS_QMAN_MEM_BASE 0x5
> -#define CONFIG_SYS_QMAN_MEM_PHYS (0xfull + \
> -
> CONFIG_SYS_QMAN_MEM_BASE)
> +#define CONFIG_SYS_QMAN_MEM_PHYS
> CONFIG_SYS_QMAN_MEM_BASE
> #define CONFIG_SYS_QMAN_MEM_SIZE 0x0800
> #define CONFIG_SYS_QMAN_SP_CENA_SIZE0x1
> #define CONFIG_SYS_QMAN_SP_CINH_SIZE0x1
> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> index 7c22b8d209..22faf16751 100644
> --- a/drivers/misc/fsl_portals.c
> +++ b/drivers/misc/fsl_portals.c
> @@ -24,7 +24,6 @@ void setup_qbman_portals(void)
> CONFIG_SYS_BMAN_SWP_ISDR_REG;
> void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
> CONFIG_SYS_QMAN_SWP_ISDR_REG;
> -#ifdef CONFIG_PPC
> struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
>
> /* Set the Qman initiator BAR to match the LAW (for DQRR stashing)
> */
> @@ -32,7 +31,6 @@ void setup_qbman_portals(void)
> out_be32(>qcsp_bare,
> (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
> #endif
> out_be32(>qcsp_bar,
> (u32)CONFIG_SYS_QMAN_MEM_PHYS);
> -#endif
> #ifdef CONFIG_FSL_CORENET
> int i;
>
> --
> 2.17.1
___
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U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 2/8] armv8: ls1046a: advertise QMan v3 in configuration
> -Original Message- > From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com] > Sent: Tuesday, July 31, 2018 8:22 PM > To: u-boot@lists.denx.de; Prabhakar Kushwaha > ; York Sun > Cc: Bharat Bhushan ; Horia Geanta > ; Laurentiu Tudor > Subject: [PATCH v6 2/8] armv8: ls1046a: advertise QMan v3 in configuration > > From: Laurentiu Tudor > > The QMan IP block in this SoC is version 3.2 so advertise this in the SoC > configuration header. > > Signed-off-by: Laurentiu Tudor Reviewed-by: Bharat Bhushan Thanks -Bharat > --- > arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > index 23faffd9fc..8a05148136 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > @@ -257,6 +257,7 @@ > > #elif defined(CONFIG_ARCH_LS1046A) > #define CONFIG_SYS_FMAN_V3 > +#define CONFIG_SYS_FSL_QMAN_V3 > #define CONFIG_SYS_NUM_FMAN 1 > #define CONFIG_SYS_NUM_FM1_DTSEC 8 > #define CONFIG_SYS_NUM_FM1_10GEC 2 > -- > 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/8] armv8: fsl-layerscape: add missing register blocks base address defines
> -Original Message- > From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com] > Sent: Tuesday, July 31, 2018 8:22 PM > To: u-boot@lists.denx.de; Prabhakar Kushwaha > ; York Sun > Cc: Bharat Bhushan ; Horia Geanta > ; Laurentiu Tudor > Subject: [PATCH v6 1/8] armv8: fsl-layerscape: add missing register blocks > base address defines > > From: Laurentiu Tudor > > Add defines for the edma and qdma register block base addresses. > > Signed-off-by: Laurentiu Tudor Reviewed-by: Bharat Bhushan Thanks -Bharat > --- > arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > index 5b4767e0fe..644a16dd30 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > @@ -88,8 +88,12 @@ > > #define LPUART_BASE (CONFIG_SYS_IMMR + > 0x0195) > > +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR > + 0x01c0) > + > #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR > + 0x0220) > > +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR > + 0x0738) > + > #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x40ULL > #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x48ULL > #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x50ULL > -- > 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree
> -Original Message- > From: Horia Geanta > Sent: Monday, July 30, 2018 8:03 PM > To: Laurentiu Tudor ; Bharat Bhushan > ; u-boot@lists.denx.de; Prabhakar Kushwaha > ; York Sun > Cc: Alison Wang ; Ruchika Gupta > > Subject: Re: [PATCH v5 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device > tree > > On 7/30/2018 4:58 PM, Laurentiu Tudor wrote: > >> The only way to implement a *mechanism* is to provide different ICIDs > >> for all the blocks. > >> Any other solution would be imposing a *policy*, thus restricting > >> user's possibilities. Admittedly there are use cases less "popular" > >> than others, but if possible it would be best not to decide for the user > >> and > provide full flexibility. > >> > >> Is there a resource (ICID values) shortage? > >> > > No. I can change the patch to have distinct ICIDs and resubmit. Please > > let me know if you agree on this. Yes, please assign separate ICIDs for each. Thanks -Bharat > > > Yes, this is my suggestion. > IIUC it's also similar to the way LIODNs are allocated on PPC. > True, LS102x is the exception - it assigns ICID 0x10 to all SEC blocks. > > Regards, > Horia ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree
> -Original Message-
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Friday, July 27, 2018 3:28 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
> ; York Sun
> Cc: Bharat Bhushan ; Horia Geanta
> ; Laurentiu Tudor
> Subject: [PATCH v5 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device
> tree
>
> From: Laurentiu Tudor
>
> Add support for SEC ICID configuration and apply it for ls1046a.
> Also add code to make the necessary device tree fixups.
>
> Signed-off-by: Laurentiu Tudor
> ---
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 14 +++
> .../asm/arch-fsl-layerscape/fsl_icid.h| 25 +++
> .../asm/arch-fsl-layerscape/immap_lsch2.h | 8 ++
> 3 files changed, 47 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> index 30c7d8d28a..bc2fe283a1 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> @@ -40,6 +40,20 @@ struct icid_id_table icid_tbl[] = {
> SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
> SET_ETR_ICID(FSL_ETR_STREAM_ID),
> SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
> +#ifdef CONFIG_FSL_CAAM
> + SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
> + SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
> + SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
> + SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
> + SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
> + SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
> + SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
> + SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
> + SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 2),
> + SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
> + SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
> + SET_SEC_DECO_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
Here goes my understanding:
RTIC are independent device from JR and QI, So they should be assigned
different unique steam-id. Also each RTIC are independent device, so each RTIC
can also be assigned separate stream-id.
While we can decide to use one stream-id for all RITCs and add a comment that
they are not partitionable.
DECOs can take work from QI or JRs, and in that case they will use the
stream-id of the respective QI or JR, and the stream-id programmed in DECOs is
not used.
While DECOs can be used directly (not via JR and QI) and in that case it will
use the strema-id programmed in it. So in this case also we should be using
unique stream-id for each DECO if partitionable or one for all DECOs
Thanks
-Bharat
> #endif
> };
>
> int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git
> a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> index 5be50a17ab..a70c866651 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> @@ -8,6 +8,7 @@
>
> #include
> #include
> +#include
>
> struct icid_id_table {
> const char *compat;
> @@ -82,6 +83,30 @@ void fdt_fixup_icid(void *blob); #define
> SET_FMAN_ICID_ENTRY(_port_id, streamid) \
> { .port_id = (_port_id), .icid = (streamid) }
>
> +#define SET_SEC_QI_ICID(streamid) \
> + SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
> + (((streamid) << 16) | (streamid)), \
> + offsetof(ccsr_sec_t, qilcr_ls) + \
> + CONFIG_SYS_FSL_SEC_ADDR, \
> + CONFIG_SYS_FSL_SEC_ADDR)
> +
> +#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
> + SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
> + (((streamid) << 16) | (streamid)), \
> + offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
> + CONFIG_SYS_FSL_SEC_ADDR, \
> + FSL_SEC_JR##jr_num##_BASE_ADDR)
> +
> +#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
> + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
> + offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
> + CONFIG_SYS_FSL_SEC_ADDR, 0)
> +
> +#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
> + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
> + offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
> + CONFIG_SYS_FSL_SEC_ADDR, 0)
> +
> extern struct icid_id_table icid_tbl[]; extern struct fman_icid_id_table
> fman_icid_tbl[]; extern int icid_tbl_sz; diff --git
> a/arch/arm/include/asm/arch-fsl-layerscap
Re: [U-Boot] [PATCH v4 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree
> -Original Message-
> From: Horia Geanta
> Sent: Wednesday, July 25, 2018 11:25 PM
> To: Laurentiu Tudor ; York Sun
> ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Cc: Bharat Bhushan
> Subject: Re: [PATCH v4 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device
> tree
>
> On 7/24/2018 5:05 PM, laurentiu.tu...@nxp.com wrote:
> > From: Laurentiu Tudor
> >
> > Add support for SEC ICID configuration and apply it for ls1046a.
> > Also add code to make the necessary device tree fixups.
> > Also included in this patch, while adding the new required JR
> > defines sanitize the preexisting ones by dropping the CONFIG_
> > prefixes.
> >
> > Signed-off-by: Laurentiu Tudor
> > ---
> > .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 15
> > .../asm/arch-fsl-layerscape/fsl_icid.h| 24 +++
> > .../asm/arch-fsl-layerscape/immap_lsch2.h | 11 ++---
> > drivers/crypto/fsl/jr.c | 2 +-
> > scripts/config_whitelist.txt | 2 --
> > 5 files changed, 48 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> > index 30c7d8d28a..84f7665929 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> > @@ -7,6 +7,7 @@
> > #include
> > #include
> > #include
> > +#include
> The header should be included where it's used, in fsl_icid.h.
>
> >
> > #ifdef CONFIG_SYS_DPAA_QBMAN
> > struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
> > @@ -40,6 +41,20 @@ struct icid_id_table icid_tbl[] = {
> > SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
> > SET_ETR_ICID(FSL_ETR_STREAM_ID),
> > SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
> > +#ifdef CONFIG_FSL_CAAM
> > + SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 2),
> > + SET_SEC_DECO_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 2),
> > +#endif
> > };
> >
> PPA firmware running in secure world is using JR3 (what
> sec_firmware_used_jobring_offset() returns).
> I think a different ICID should be allocated for it, considering it has
> different security requirements.
All JR interfaces should be assigned different ICID.
While I am not sure DECO and RTIC are separate devices and can be used by
software independently from JR interface.
>
> BTW, is it clear that U-boot is responsible for ICID programming, and not
> PPA?
We can still boot without PPA/ATF, so keeping in u-boot is good at least for
now. I know about the new ATF architecture and stuff.
>
> > int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> > index 5be50a17ab..bd613219b6 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> > @@ -82,6 +82,30 @@ void fdt_fixup_icid(void *blob);
> > #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
> > { .port_id = (_port_id), .icid = (streamid) }
> >
> > +#define SET_SEC_QI_ICID(streamid) \
> > + SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
> > + (((streamid) << 16) | (streamid)), \
> > + offsetof(struct ccsr_sec, qilcr_ls) + \
> s/struct ccsr_sec/ccsr_sec_t
>
> > + CONFIG_SYS_FSL_SEC_ADDR, \
> > + CONFIG_SYS_FSL_SEC_ADDR)
> > +
> > +#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
> > + SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
> > + (((streamid) << 16) | (streamid)), \
> > + offsetof(struct ccsr_sec, jrliodnr[jr_num].ls) + \
> > + CONFIG_SYS_FSL_SEC_ADDR, \
> > + FSL_SEC_JR##jr_num##_BASE_ADDR)
> > +
> > +#define SET_SEC_DECO_ICID_ENTRY(deco_num, st
Re: [U-Boot] [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals
> -Original Message-
> From: Laurentiu Tudor
> Sent: Monday, July 9, 2018 7:23 PM
> To: Bharat Bhushan ; York Sun
> ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals
>
> Hi Bharat,
>
> On 09.07.2018 15:21, Bharat Bhushan wrote:
> >
> >
> >> -Original Message-
> >> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
> >> Sent: Wednesday, July 4, 2018 7:44 PM
> >> To: York Sun ; Prabhakar Kushwaha
> >> ; u-boot@lists.denx.de
> >> Cc: Bharat Bhushan ; Laurentiu Tudor
> >>
> >> Subject: [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman
> >> portals
> >>
> >> Add support for ICID setting of qman portals and the required device
> >> tree fixups.
> >> Also fix an endiness issue in portal setup code.
> >>
> >> Signed-off-by: Laurentiu Tudor
> >> ---
> >> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
> >> .../asm/arch-fsl-layerscape/fsl_portals.h | 23 ++
> >> drivers/misc/fsl_portals.c| 43 +++
> >> 3 files changed, 74 insertions(+), 8 deletions(-)
> >> create mode 100644
> >> arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> >>
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> index 1c528ab751..80e1ceadc0 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> @@ -6,6 +6,22 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >> +
> >> +#ifdef CONFIG_SYS_DPAA_QBMAN
> >> +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >
> > FSL_DPAA1_STREAM_ID_END is "Stream-ID" while SET_QP_INFO is
> defined as
> >
> > #define SET_QP_INFO(_icid, dest) \
> > { .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
> >
> > It expects "icid"
> >
> > Can we use consistent names, either "streamed" or "icid" at both places.
>
> The problem is that the streamid defines where defined some time ago (see
> file ./arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h).
>
> > In fact this structure is used to finally program the h/w, so we should use
> same name as in h/w to avoid any confusion.
>
> The RefMan uses the term "icid" so i'd stick with it.
>
> In order to make this consistent I think i should rename the existing
> *_STREAM_ID_* defines to *_ICID_* but also the header that contains them
> from stream_id_lsch2.h to something like icid_lsch2.h. This implies that also
> the PCI related defines would be renamed. Is that ok?
> Let me know what you think.
Other way is
- use stream-id in common code (header files etc)
- above is used to update the device-tree and device tree should use stream-id
and not icid
- pass stream-id to platform/device init code
- finally when programming to h/w convert them to ICID, STREAMUID_TO_ICID(),
which is one-o-one.
In this ICID is limited to h/w definition/programming while remaining common
framework use streamed.
Does that look ok?
Thanks
-Bharat
>
> ---
> Best Regards, Laurentiu
>
> >
> > Thanks
> > -Bharat
> >
> >> +};
> >> +#endif
> >>
> >> struct icid_id_table icid_tbl[] = {
> >> #ifdef CONFIG_SYS_DPAA_QBMAN
> >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> >> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> >> new file mode 100644
> >> index 00..bd8d3fb49a
> >> --- /dev/null
> >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> >> @@ -0,0 +1,23 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * Copyright 2018 NXP
> >> + */
> >> +
> >> +#ifndef _F
Re: [U-Boot] [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
> -Original Message-
> From: Laurentiu Tudor
> Sent: Monday, July 9, 2018 6:42 PM
> To: Bharat Bhushan ; York Sun
> ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
>
> Hi Bharat,
>
> On 09.07.2018 15:13, Bharat Bhushan wrote:
> >
> >
> >> -Original Message-
> >> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
> >> Sent: Wednesday, July 4, 2018 7:44 PM
> >> To: York Sun ; Prabhakar Kushwaha
> >> ; u-boot@lists.denx.de
> >> Cc: Bharat Bhushan ; Laurentiu Tudor
> >>
> >> Subject: [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
> >>
> >> Add infrastructure for ICID setup and device tree fixup on ARM platforms.
> >> This include basic ICID setup for several devices.
> >>
> >> Signed-off-by: Laurentiu Tudor
> >> ---
> >> arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
> >> arch/arm/cpu/armv8/fsl-layerscape/icid.c | 111
> ++
> >> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 29 +
> >> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +
> >> .../asm/arch-fsl-layerscape/fsl_icid.h| 80 +
> >> board/freescale/ls1046aqds/ls1046aqds.c | 2 +
> >> board/freescale/ls1046ardb/ls1046ardb.c | 3 +
> >> 7 files changed, 229 insertions(+)
> >> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
> >> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> create mode 100644
> >> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> >>
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> >> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> >> index 1e9e4680fe..5d6f68aad6 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> >> @@ -37,6 +37,7 @@ endif
> >>
> >> ifneq ($(CONFIG_ARCH_LS1046A),)
> >> obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
> >> +obj-y += icid.o ls1046_ids.o
> >> endif
> >>
> >> ifneq ($(CONFIG_ARCH_LS1088A),)
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> >> new file mode 100644
> >> index 00..8694bd6fa1
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> >> @@ -0,0 +1,111 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * Copyright 2018 NXP
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +
> >> +static void set_icid(struct icid_id_table *tbl, int size) {
> >> + int i;
> >> +
> >> + for (i = 0; i < size; i++)
> >> + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
> >> +
> >> +void set_icids(void)
> >> +{
> >> + /* setup general icid offsets */
> >> + set_icid(icid_tbl, icid_tbl_sz);
> >> +}
> >> +
> >> +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids,
> >> +int
> >> +num_ids) {
> >> + int i, ret;
> >> + u32 prop[8];
> >> +
> >> + for (i = 0; i < num_ids; i++) {
> >> + prop[i * 2] = cpu_to_fdt32(smmu_ph);
> >> + prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
> >> + }
> >> + ret = fdt_setprop(blob, off, "iommus",
> >> +prop, sizeof(u32) * num_ids * 2);
> >> + if (ret > 0) {
> >> + printf("WARNING unable to set iommus: %s\n",
> >> fdt_strerror(off));
> >> + return off;
> >> + }
> >> + ret = fdt_setprop_empty(blob, off, "dma-coherent");
> >
> > This forces "dma-coherent" for all SOCs, although there is no current
> known SOCs which does not support non-coherent but maybe safe not to
> set from common code.
>
> I see your point and will drop this.
> Now, regarding a replacement solution, I don't have any other idea than
> updating the device trees directly. Thoughts?
dma-coherent will be default in device tree and u-boot code should check if
dma-coherent already set.
Have another function exposed from generic code which set "dma-coherent" and
platforms code will call that function if it is
Re: [U-Boot] [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
> -Original Message-
> From: Laurentiu Tudor
> Sent: Monday, July 9, 2018 6:10 PM
> To: Bharat Bhushan ; York Sun
> ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on
> ARM platforms
>
> Hi Bharat,
>
> On 09.07.2018 15:06, Bharat Bhushan wrote:
> >
> >
> >> -Original Message-
> >> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
> >> Sent: Wednesday, July 4, 2018 7:44 PM
> >> To: York Sun ; Prabhakar Kushwaha
> >> ; u-boot@lists.denx.de
> >> Cc: Bharat Bhushan ; Laurentiu Tudor
> >>
> >> Subject: [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on
> >> ARM platforms
> >>
> >> QMAN_BAR{E} register setup was disabled on ARM platforms, however
> the
> >> register does need to be set. Enable the code also on ARMs and fix
> >> the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that
> the
> >> newly enabled code works.
> >>
> >> Signed-off-by: Laurentiu Tudor
> >> ---
> >> arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
> >> drivers/misc/fsl_portals.c | 2 --
> >> 2 files changed, 1 insertion(+), 4 deletions(-)
> >>
> >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> >> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> >> index 644a16dd30..d22ec70aa5 100644
> >> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> >> @@ -57,8 +57,7 @@
> >> #define CONFIG_SYS_BMAN_SWP_ISDR_REG0x3E80
> >> #define CONFIG_SYS_QMAN_NUM_PORTALS 10
> >> #define CONFIG_SYS_QMAN_MEM_BASE 0x5
> >> -#define CONFIG_SYS_QMAN_MEM_PHYS (0xfull + \
> >> -
> >>CONFIG_SYS_QMAN_MEM_BASE)
> >> +#define CONFIG_SYS_QMAN_MEM_PHYS
> >>CONFIG_SYS_QMAN_MEM_BASE
> >
> > Are you sure that these changes works for PowerPC ?
> >
>
> Can't imagine how it could happen. immap_lsch2.h is a ls104xa specific file.
Ahh yes, just missed
Thanks
-Bharat
>
> ---
> Thanks & Best Regards, Laurentiu
___
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Re: [U-Boot] [PATCH v3 7/7] armv8: ls1046a: setup fman ports ICIDs and device tree
> -Original Message-
> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
> Sent: Wednesday, July 4, 2018 7:44 PM
> To: York Sun ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Cc: Bharat Bhushan ; Laurentiu Tudor
>
> Subject: [PATCH v3 7/7] armv8: ls1046a: setup fman ports ICIDs and device
> tree
>
> Add support for ICID setting of fman ports and
> the required device tree fixups.
>
> Signed-off-by: Laurentiu Tudor
> ---
> arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 +++
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++
> .../asm/arch-fsl-layerscape/fsl_icid.h| 10 +++
> 3 files changed, 122 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> index 8694bd6fa1..9502f83ac8 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> @@ -10,6 +10,7 @@
> #include
> #include
> #include
> +#include
>
> static void set_icid(struct icid_id_table *tbl, int size)
> {
> @@ -19,10 +20,27 @@ static void set_icid(struct icid_id_table *tbl, int size)
> out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
> }
>
> +#ifdef CONFIG_SYS_FMAN_V3
> +void set_fman_icids(struct fman_icid_id_table *tbl, int size)
> +{
> + int i;
> + ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
> +
> + for (i = 0; i < size; i++) {
> + out_be32(>fm_bmi_common.fmbm_ppid[tbl[i].port_id
> - 1],
> + tbl[i].icid);
> + }
> +}
> +#endif
> +
> void set_icids(void)
> {
> /* setup general icid offsets */
> set_icid(icid_tbl, icid_tbl_sz);
> +
> +#ifdef CONFIG_SYS_FMAN_V3
> + set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
> +#endif
> }
>
> int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> num_ids)
> @@ -76,6 +94,66 @@ int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
> return 0;
> }
>
> +#ifdef CONFIG_SYS_FMAN_V3
> +int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
> +const int size)
> +{
> + int i;
> +
> + for (i = 0; i < size; i++) {
> + if (tbl[i].port_id == port_id)
> + return tbl[i].icid;
> + }
> +
> + return -1;
> +}
> +
> +void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
> + const char *compat)
> +{
> + int noff, len, icid;
> + const u32 *prop;
> +
> + noff = fdt_node_offset_by_compatible(blob, -1, compat);
> + while (noff > 0) {
> + prop = fdt_getprop(blob, noff, "cell-index", );
> + if (!prop) {
> + printf("WARNING missing cell-index for fman
> port\n");
> + continue;
> + }
> + if (len != 4) {
> + printf("WARNING bad cell-index size for fman
> port\n");
> + continue;
> + }
> +
> + icid = get_fman_port_icid(fdt32_to_cpu(*prop),
> + fman_icid_tbl, fman_icid_tbl_sz);
> + if (icid < 0) {
> + printf("WARNING unknown ICID for fman port
> %d\n",
> +*prop);
> + continue;
> + }
> +
> + fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *), 1);
> +
> + noff = fdt_node_offset_by_compatible(blob, noff, compat);
> + }
> +}
> +
> +void fdt_fixup_fman_icids(void *blob, int smmu_ph)
> +{
> + static const char * const compats[] = {
> + "fsl,fman-v3-port-oh",
> + "fsl,fman-v3-port-rx",
> + "fsl,fman-v3-port-tx",
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(compats); i++)
> + fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph,
> compats[i]);
> +}
> +#endif
> +
> int fdt_get_smmu_phandle(void *blob)
> {
> int noff, smmu_ph;
> @@ -108,4 +186,8 @@ void fdt_fixup_icid(void *blob)
> return;
>
> fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
> +
> +#ifdef CONFIG_SYS_FMAN_V3
> + fdt_fixup_fman_icids(blob, smmu_ph);
> +#endif
> }
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> index 80e1ceadc0..30c7d8d28a 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape
Re: [U-Boot] [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals
> -Original Message-
> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
> Sent: Wednesday, July 4, 2018 7:44 PM
> To: York Sun ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Cc: Bharat Bhushan ; Laurentiu Tudor
>
> Subject: [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals
>
> Add support for ICID setting of qman portals and
> the required device tree fixups.
> Also fix an endiness issue in portal setup code.
>
> Signed-off-by: Laurentiu Tudor
> ---
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++
> .../asm/arch-fsl-layerscape/fsl_portals.h | 23 ++
> drivers/misc/fsl_portals.c| 43 +++
> 3 files changed, 74 insertions(+), 8 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> index 1c528ab751..80e1ceadc0 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> @@ -6,6 +6,22 @@
> #include
> #include
> #include
> +#include
> +
> +#ifdef CONFIG_SYS_DPAA_QBMAN
> +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
FSL_DPAA1_STREAM_ID_END is "Stream-ID" while SET_QP_INFO is defined as
#define SET_QP_INFO(_icid, dest) \
{ .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
It expects "icid"
Can we use consistent names, either "streamed" or "icid" at both places.
In fact this structure is used to finally program the h/w, so we should use
same name as in h/w to avoid any confusion.
Thanks
-Bharat
> +};
> +#endif
>
> struct icid_id_table icid_tbl[] = {
> #ifdef CONFIG_SYS_DPAA_QBMAN
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> new file mode 100644
> index 00..bd8d3fb49a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef _FSL_PORTALS_H_
> +#define _FSL_PORTALS_H_
> +
> +struct qportal_info {
> + u16 dicid; /* DQRR ICID */
> + u16 ficid; /* frame data ICID */
> + u16 icid;
> + u8 sdest;
> +};
> +
> +#define SET_QP_INFO(_icid, dest) \
> + { .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
> +
> +extern struct qportal_info qp_info[];
> +void fdt_portal(void *blob, const char *compat, const char *container,
> + u64 addr, u32 size);
> +
> +#endif
> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> index 22faf16751..a524510707 100644
> --- a/drivers/misc/fsl_portals.c
> +++ b/drivers/misc/fsl_portals.c
> @@ -13,6 +13,9 @@
> #ifdef CONFIG_PPC
> #include
> #include
> +#else
> +#include
> +#include
> #endif
> #include
>
> @@ -45,6 +48,22 @@ void setup_qbman_portals(void)
> /* set frame liodn */
> out_be32(>qcsp[i].qcsp_io_cfg, (sdest << 16) |
> fliodn);
> }
> +#else
> +#ifdef CONFIG_ARM
> + int i;
> +
> + for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
> + u8 sdest = qp_info[i].sdest;
> + u16 ficid = qp_info[i].ficid;
> + u16 dicid = qp_info[i].dicid;
> + u16 icid = qp_info[i].icid;
> +
> + out_be32(>qcsp[i].qcsp_lio_cfg, (icid << 16) |
> + dicid);
> + /* set frame icid */
> + out_be32(>qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
> + }
> +#endif
> #endif
>
> /* Change default state of BMan ISDR portals to all 1s */
> @@ -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
> char compat[64];
> int compat_len;
>
> +#ifndef CONFIG_PPC
> + int smmu_ph = fdt_get_smmu_phandle(blob);
> +#endif
> +
> maj = (rev_1 >> 8) & 0xff;
> min = rev_1 & 0xff;
> ip_cfg = rev_2 & 0xff;
> @@ -188,7 +211,
Re: [U-Boot] [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
> -Original Message-
> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
> Sent: Wednesday, July 4, 2018 7:44 PM
> To: York Sun ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Cc: Bharat Bhushan ; Laurentiu Tudor
>
> Subject: [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
>
> Add infrastructure for ICID setup and device tree fixup on ARM platforms.
> This include basic ICID setup for several devices.
>
> Signed-off-by: Laurentiu Tudor
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
> arch/arm/cpu/armv8/fsl-layerscape/icid.c | 111 ++
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 29 +
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +
> .../asm/arch-fsl-layerscape/fsl_icid.h| 80 +
> board/freescale/ls1046aqds/ls1046aqds.c | 2 +
> board/freescale/ls1046ardb/ls1046ardb.c | 3 +
> 7 files changed, 229 insertions(+)
> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index 1e9e4680fe..5d6f68aad6 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -37,6 +37,7 @@ endif
>
> ifneq ($(CONFIG_ARCH_LS1046A),)
> obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
> +obj-y += icid.o ls1046_ids.o
> endif
>
> ifneq ($(CONFIG_ARCH_LS1088A),)
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> new file mode 100644
> index 00..8694bd6fa1
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +
> +static void set_icid(struct icid_id_table *tbl, int size) {
> + int i;
> +
> + for (i = 0; i < size; i++)
> + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
> +
> +void set_icids(void)
> +{
> + /* setup general icid offsets */
> + set_icid(icid_tbl, icid_tbl_sz);
> +}
> +
> +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> +num_ids) {
> + int i, ret;
> + u32 prop[8];
> +
> + for (i = 0; i < num_ids; i++) {
> + prop[i * 2] = cpu_to_fdt32(smmu_ph);
> + prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
> + }
> + ret = fdt_setprop(blob, off, "iommus",
> + prop, sizeof(u32) * num_ids * 2);
> + if (ret > 0) {
> + printf("WARNING unable to set iommus: %s\n",
> fdt_strerror(off));
> + return off;
> + }
> + ret = fdt_setprop_empty(blob, off, "dma-coherent");
This forces "dma-coherent" for all SOCs, although there is no current known
SOCs which does not support non-coherent but maybe safe not to set from common
code.
> + if (ret > 0) {
> + printf("WARNING unable to set dma-coherent: %s\n",
> +fdt_strerror(off));
> + return off;
> + }
> +
> + return 0;
> +}
> +
> +int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
> +struct icid_id_table *tbl, int size) {
> + int i, err, off;
> +
> + for (i = 0; i < size; i++) {
> + if (!tbl[i].compat)
> + continue;
> +
> + off = fdt_node_offset_by_compat_reg(blob,
> + tbl[i].compat,
> + tbl[i].compat_addr);
> + if (off > 0) {
> + err = fdt_set_iommu_prop(blob, off, smmu_ph,
> + [i].id, 1);
> + if (err)
> + return err;
> + } else {
> + printf("WARNING could not find node %s: %s.\n",
> +tbl[i].compat, fdt_strerror(off));
> + }
> + }
> +
> + return 0;
> +}
> +
> +int fdt_get_smmu_phandle(void *blob)
> +{
> + int noff, smmu_ph;
> +
> + noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
> + if (noff < 0) {
> + printf("WARNING failed to get smmu node: %s\n",
> +fdt_strerror(noff));
> +
Re: [U-Boot] [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
> -Original Message-
> From: Laurentiu Tudor [mailto:laurentiu.tu...@nxp.com]
> Sent: Wednesday, July 4, 2018 7:44 PM
> To: York Sun ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Cc: Bharat Bhushan ; Laurentiu Tudor
>
> Subject: [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM
> platforms
>
> QMAN_BAR{E} register setup was disabled on ARM platforms, however the
> register does need to be set. Enable the code also on ARMs and fix the
> CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the
> newly
> enabled code works.
>
> Signed-off-by: Laurentiu Tudor
> ---
> arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
> drivers/misc/fsl_portals.c | 2 --
> 2 files changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index 644a16dd30..d22ec70aa5 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -57,8 +57,7 @@
> #define CONFIG_SYS_BMAN_SWP_ISDR_REG0x3E80
> #define CONFIG_SYS_QMAN_NUM_PORTALS 10
> #define CONFIG_SYS_QMAN_MEM_BASE 0x5
> -#define CONFIG_SYS_QMAN_MEM_PHYS (0xfull + \
> -
> CONFIG_SYS_QMAN_MEM_BASE)
> +#define CONFIG_SYS_QMAN_MEM_PHYS
> CONFIG_SYS_QMAN_MEM_BASE
Are you sure that these changes works for PowerPC ?
Thanks
-Bharat
> #define CONFIG_SYS_QMAN_MEM_SIZE 0x0800
> #define CONFIG_SYS_QMAN_SP_CENA_SIZE0x1
> #define CONFIG_SYS_QMAN_SP_CINH_SIZE0x1
> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> index 7c22b8d209..22faf16751 100644
> --- a/drivers/misc/fsl_portals.c
> +++ b/drivers/misc/fsl_portals.c
> @@ -24,7 +24,6 @@ void setup_qbman_portals(void)
> CONFIG_SYS_BMAN_SWP_ISDR_REG;
> void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
> CONFIG_SYS_QMAN_SWP_ISDR_REG;
> -#ifdef CONFIG_PPC
> struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
>
> /* Set the Qman initiator BAR to match the LAW (for DQRR stashing)
> */
> @@ -32,7 +31,6 @@ void setup_qbman_portals(void)
> out_be32(>qcsp_bare,
> (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
> #endif
> out_be32(>qcsp_bar,
> (u32)CONFIG_SYS_QMAN_MEM_PHYS);
> -#endif
> #ifdef CONFIG_FSL_CORENET
> int i;
>
> --
> 2.17.1
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Re: [U-Boot] [upstream-release] [PATCH v2 5/7] armv8: ls1046a: initial icid setup support
> -Original Message-
> From: upstream-release-boun...@linux.freescale.net [mailto:upstream-
> release-boun...@linux.freescale.net] On Behalf Of Laurentiu Tudor
> Sent: Tuesday, July 3, 2018 5:42 PM
> To: York Sun ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Cc: Laurentiu Tudor
> Subject: [upstream-release] [PATCH v2 5/7] armv8: ls1046a: initial icid setup
> support
>
> Add infrastructure for ICID setup and device tree
> fixup on ARM platforms. This include basic ICID setup
> for several devices.
>
> Signed-off-by: Laurentiu Tudor
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
> arch/arm/cpu/armv8/fsl-layerscape/icid.c | 111 ++
> .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 29 +
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +
> .../asm/arch-fsl-layerscape/fsl_icid.h| 80 +
> board/freescale/ls1046aqds/ls1046aqds.c | 2 +
> board/freescale/ls1046ardb/ls1046ardb.c | 3 +
> 7 files changed, 229 insertions(+)
> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
> create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index 1e9e4680fe..5d6f68aad6 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -37,6 +37,7 @@ endif
>
> ifneq ($(CONFIG_ARCH_LS1046A),)
> obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
> +obj-y += icid.o ls1046_ids.o
> endif
>
> ifneq ($(CONFIG_ARCH_LS1088A),)
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> new file mode 100644
> index 00..8694bd6fa1
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +
> +static void set_icid(struct icid_id_table *tbl, int size)
> +{
> + int i;
> +
> + for (i = 0; i < size; i++)
> + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
> +}
> +
> +void set_icids(void)
> +{
> + /* setup general icid offsets */
> + set_icid(icid_tbl, icid_tbl_sz);
Icid_tbl[] is currently defined for ls1046 but this code is generic and later
can be used for ls1043 later.
We can let caller provide table pointer and size.
> +}
> +
> +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> num_ids)
> +{
> + int i, ret;
> + u32 prop[8];
> +
> + for (i = 0; i < num_ids; i++) {
> + prop[i * 2] = cpu_to_fdt32(smmu_ph);
> + prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
> + }
> + ret = fdt_setprop(blob, off, "iommus",
> + prop, sizeof(u32) * num_ids * 2);
> + if (ret > 0) {
> + printf("WARNING unable to set iommus: %s\n",
> fdt_strerror(off));
> + return off;
> + }
> + ret = fdt_setprop_empty(blob, off, "dma-coherent");
> + if (ret > 0) {
> + printf("WARNING unable to set dma-coherent: %s\n",
> +fdt_strerror(off));
> + return off;
> + }
> +
> + return 0;
> +}
> +
> +int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
> +struct icid_id_table *tbl, int size)
What we set in device tree is stream-id, while stream-id is = [PL: BMT : ICID];
I think we should use stream-id to the point when we are patching device-tree
and value set in h/w.
We can say PL = BMT = 0 for now and leave space for setting this in future for
any specific device for any platform?
> +{
> + int i, err, off;
> +
> + for (i = 0; i < size; i++) {
> + if (!tbl[i].compat)
> + continue;
> +
> + off = fdt_node_offset_by_compat_reg(blob,
> + tbl[i].compat,
> + tbl[i].compat_addr);
> + if (off > 0) {
> + err = fdt_set_iommu_prop(blob, off, smmu_ph,
> + [i].id, 1);
> + if (err)
> + return err;
> + } else {
> + printf("WARNING could not find node %s: %s.\n",
> +tbl[i].compat, fdt_strerror(off));
> + }
> + }
> +
> + return 0;
> +}
> +
> +int fdt_get_smmu_phandle(void *blob)
> +{
> + int noff, smmu_ph;
> +
> + noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
> + if (noff < 0) {
> + printf("WARNING failed to get smmu node: %s\n",
> +fdt_strerror(noff));
> + return noff;
> + }
> +
> + smmu_ph = fdt_get_phandle(blob, noff);
> + if (!smmu_ph) {
> +
Re: [U-Boot] [upstream-release] [PATCH v2 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
> -Original Message-
> From: upstream-release-boun...@linux.freescale.net [mailto:upstream-
> release-boun...@linux.freescale.net] On Behalf Of Laurentiu Tudor
> Sent: Tuesday, July 3, 2018 5:42 PM
> To: York Sun ; Prabhakar Kushwaha
> ; u-boot@lists.denx.de
> Cc: Laurentiu Tudor
> Subject: [upstream-release] [PATCH v2 3/7] misc: fsl_portals: setup
> QMAN_BAR{E} also on ARM platforms
>
> QMAN_BAR{E} register setup was disabled on ARM platforms,
> however the register does need to be set. Add code that
> sets it up on ARMs.
>
> Signed-off-by: Laurentiu Tudor
> ---
> drivers/misc/fsl_portals.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> index 7c22b8d209..5b1233740b 100644
> --- a/drivers/misc/fsl_portals.c
> +++ b/drivers/misc/fsl_portals.c
> @@ -24,14 +24,19 @@ void setup_qbman_portals(void)
> CONFIG_SYS_BMAN_SWP_ISDR_REG;
> void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
> CONFIG_SYS_QMAN_SWP_ISDR_REG;
> -#ifdef CONFIG_PPC
> struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
>
> /* Set the Qman initiator BAR to match the LAW (for DQRR stashing)
> */
> +#ifdef CONFIG_PPC32
> #ifdef CONFIG_PHYS_64BIT
> out_be32(>qcsp_bare,
> (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
> #endif
> out_be32(>qcsp_bar,
> (u32)CONFIG_SYS_QMAN_MEM_PHYS);
> +#else
> +#ifdef CONFIG_PHYS_64BIT
> + out_be32(>qcsp_bare,
> (u32)(CONFIG_SYS_QMAN_MEM_BASE >> 32));
> +#endif
> + out_be32(>qcsp_bar,
> (u32)CONFIG_SYS_QMAN_MEM_BASE);
> #endif
Can we have same hash define name for PPC and non-PPC?
We do not need then if-else
Thanks
-Bharat
> #ifdef CONFIG_FSL_CORENET
> int i;
> --
> 2.17.1
>
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[U-Boot] [PATCH] pci: layerscape: Fixup iommu-map for LS208xA
"pci: layerscape: Fixup device tree node for ls2088a" added
support for LS208xA devices but fixing iommu-map property
is missing. This patch adds support for fixing iommu-map.
Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.cior...@nxp.com>
---
drivers/pci/pcie_layerscape_fixup.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 9e6c2f5..3dae201 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -130,19 +130,28 @@ static void fdt_pcie_set_iommu_map_entry(void *blob,
struct ls_pcie *pcie,
u32 iommu_map[4];
int nodeoffset;
int lenp;
+ uint svr;
+ char *compat = NULL;
/* find pci controller node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
pcie->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- nodeoffset = fdt_node_offset_by_compat_reg(blob,
- CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
+ svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
+ if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A)
+ compat = "fsl,ls2088a-pcie";
+ else
+ compat = CONFIG_FSL_PCIE_COMPAT;
+
+ if (compat)
+ nodeoffset = fdt_node_offset_by_compat_reg(blob,
+ compat, pcie->dbi_res.start);
+#endif
if (nodeoffset < 0)
return;
-#else
- return;
-#endif
}
/* get phandle to iommu controller */
--
1.9.3
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Re: [U-Boot] [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
> -Original Message- > From: york sun > Sent: Wednesday, March 22, 2017 9:50 PM > To: Bharat Bhushan <bharat.bhus...@nxp.com>; u-boot@lists.denx.de > Cc: M.H. Lian <minghuan.l...@nxp.com>; s...@chromium.org; Z.Q. Hou > <zhiqiang@nxp.com>; Diana Madalina Craciun > <diana.crac...@nxp.com> > Subject: Re: [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to > stream_id_lsch3.h > > On 03/21/2017 11:38 PM, Bharat Bhushan wrote: > > The stream ID allocation for Chasis3.0 devices, LS1088, LS2088 and > > LS2080, can be shared. > > > > This patch renames this accordingly. > > > > Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> > > --- > > You missed the change log. What change did you make for this version? > I didn't see your respond to Diana's comment for patch 3 of version 1. Patch 0/6 (cover letter) describes that only change in this series are in 3/6 and 4/6 and that describe the change as well (which is what Diana's comment) Thanks -Bharat > > York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 0/6] pcie-layerscape: Enable PCI-LUT initialization for NXP-Chasis-2
This patch series enables PCI-LUT table initialization
for NXP Chassis-2 (for example ls1043, ls1046 and LS1012) devices.
As part of this, stream-ids allocation is added which is similar
to Chassis-3 (ls2080a)
Also this series have a minor cleanup, as stream-id definition file
is given generic name for chassis-3 devices. This allows new SOCs,
ls2088, ls1088 etc to use same allocation mechanism.
v1->v2
- Patch 2/6 and 3/6 have changes describing iommu-map property
updates in PCI node
- Other patches are same
Bharat Bhushan (6):
fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
fsl-lsch3: Rewording to support other Chassis-3 Socs
pcie-layerscape: Define stream-ids for Layerscape Chassis-2
fsl-lsch2: Use Chassis-2 streamid definition for ls1046a
fsl-lsch2: Use Chassis-2 streamid definition for ls1012a
pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs
.../asm/arch-fsl-layerscape/stream_id_lsch2.h | 63 ++
.../{ls2080a_stream_id.h => stream_id_lsch3.h} | 15 +++---
drivers/pci/pcie_layerscape_fixup.c| 4 +-
include/configs/ls1012a_common.h | 1 +
include/configs/ls1043a_common.h | 1 +
include/configs/ls1046a_common.h | 1 +
include/configs/ls2080a_common.h | 2 +-
7 files changed, 78 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h =>
stream_id_lsch3.h} (80%)
--
1.9.3
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[U-Boot] [PATCH v2] pcie-layerscape: Fixup iommu-map property of pci node
This patch fixup iommu-map property on pci node to have
a valid mapping of requester-id to stream-id.
The requester-id to stream-id mapping is based on
PCI-LUT table initialization.
Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com>
---
v1->v2
- Typo error in comment about phandle of MSI node rather than iommu
drivers/pci/pcie_layerscape_fixup.c | 53 +
1 file changed, 53 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 8f8f6b6..3aea587 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -103,6 +103,56 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct
ls_pcie *pcie,
fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
}
+/*
+ * An iommu-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
+{
+ u32 *prop;
+ u32 iommu_map[4];
+ int nodeoffset;
+ int lenp;
+
+ /* find pci controller node */
+ nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
+ pcie->dbi_res.start);
+ if (nodeoffset < 0) {
+#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+ nodeoffset = fdt_node_offset_by_compat_reg(blob,
+ CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
+ if (nodeoffset < 0)
+ return;
+#else
+ return;
+#endif
+ }
+
+ /* get phandle to iommu controller */
+ prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", );
+ if (prop == NULL) {
+ debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
+ __func__, pcie->idx);
+ return;
+ }
+
+ /* set iommu-map row */
+ iommu_map[0] = cpu_to_fdt32(devid);
+ iommu_map[1] = *++prop;
+ iommu_map[2] = cpu_to_fdt32(streamid);
+ iommu_map[3] = cpu_to_fdt32(1);
+
+ if (devid == 0)
+ fdt_setprop_inplace(blob, nodeoffset, "iommu-map", iommu_map,
16);
+ else
+ fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
+}
+
static void fdt_fixup_pcie(void *blob)
{
struct udevice *dev, *bus;
@@ -139,6 +189,9 @@ static void fdt_fixup_pcie(void *blob)
/* update msi-map in device tree */
fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
streamid);
+ /* update iommu-map in device tree */
+ fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
+ streamid);
}
}
#endif
--
1.9.3
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[U-Boot] [PATCH v2 3/6] pcie-layerscape: Define stream-ids for Layerscape Chassis-2
Layerscape Chassis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they lies behind SMMU. This patch defines the stream-ids for Chassis-2 devices. stream-ids for DPAA1 are reserved for future use. Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 63 ++ include/configs/ls1043a_common.h | 1 + 2 files changed, 64 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 000..b326fe5 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,63 @@ +/* + * Copyright 2017 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices + * are not hardwired and are programmed by sw. There are a limited number + * of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, PCI, + * and DPAA1 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * -set a iommu-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt + * for more info on the iommu-map definition) + * + * -DPAA1 + * - Stream ids for DPAA1 use are reserved for future usecase. + * + */ + + +#define FSL_INVALID_STREAM_ID 0 + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START11 +#define FSL_PEX_STREAM_ID_END 26 + +/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END63 + +#endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 5a5f951..c9d4fd7 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -13,6 +13,7 @@ #define CONFIG_MP #define CONFIG_GICV2 +#include #include /* Link Definitions */ -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 5/6] fsl-lsch2: Use Chassis-2 streamid definition for ls1012a
As ls1012a is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for ls1012a Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- include/configs/ls1012a_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index af07672..1a0c7f8 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -11,6 +11,7 @@ #define CONFIG_GICV2 #include +#include #define CONFIG_SUPPORT_RAW_INITRD -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/6] fsl-lsch2: Use Chassis-2 streamid definition for ls1046a
As ls1046a is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for ls1046 Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- include/configs/ls1046a_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 1ed7517..cb79296 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -13,6 +13,7 @@ #define CONFIG_GICV2 #include +#include /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 6/6] pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs
From: Bharat Bhushan <bharat.bhus...@nxp.com> Layerscape Chasis-2 also uses same PCIe controller as used in Chasis-3 and have similar PCI-Lut. We need to initialize the pcie-lut for Chasis-2 also as in Chasis-3. Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- drivers/pci/pcie_layerscape_fixup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 19ede2f..8f8f6b6 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -15,7 +15,7 @@ #include #include "pcie_layerscape.h" -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) /* * Return next available LUT index. */ @@ -175,7 +175,7 @@ void ft_pci_setup(void *blob, bd_t *bd) list_for_each_entry(pcie, _pcie_list, list) ft_pcie_ls_setup(blob, pcie); -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) fdt_fixup_pcie(blob); #endif } -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/6] fsl-lsch3: Rewording to support other Chassis-3 Socs
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs. Also have changes in description about iommu-map property updates in PCI node. Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- .../arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index ee28323..d7d527d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -8,11 +8,11 @@ #define __FSL_STREAM_ID_H /* - * Stream IDs on ls2080a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. + * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) + * devices are not hardwired and are programmed by sw. There are a limited + * number of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, + * PCI, and DPAA2 devices. * * This partitioning can be customized in this file depending * on the specific hardware config: @@ -29,6 +29,9 @@ * -set a msi-map entry in the PEXn controller node in the * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt * for more info on the msi-map definition) + * -set a iommu-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt + * for more info on the iommu-map definition) * * -DPAA2 * -u-boot will allocate a range of stream IDs to be used by the Management @@ -36,7 +39,7 @@ * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * - * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for + * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bitstreamID bit -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
The stream ID allocation for Chasis3.0 devices,
LS1088, LS2088 and LS2080, can be shared.
This patch renames this accordingly.
Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com>
---
.../asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} | 0
include/configs/ls2080a_common.h| 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h =>
stream_id_lsch3.h} (100%)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
similarity index 100%
rename from arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
rename to arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 5072e20..427f623 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -13,7 +13,7 @@
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
-#include
+#include
#include
/* Link Definitions */
--
1.9.3
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Re: [U-Boot] [PATCH] pcie-layerscape: Fixup iommu-map property of pci node
> -Original Message-
> From: Diana Madalina Craciun
> Sent: Friday, March 10, 2017 8:54 PM
> To: Bharat Bhushan <bharat.bhus...@nxp.com>; york sun
> <york@nxp.com>; u-boot@lists.denx.de
> Cc: Z.Q. Hou <zhiqiang@nxp.com>
> Subject: Re: [U-Boot] [PATCH] pcie-layerscape: Fixup iommu-map property
> of pci node
>
> On 2/24/2017 10:04 AM, Bharat Bhushan wrote:
> > This patch fixup iommu-map property on pci node to have a valid
> > mapping of requester-id to stream-id.
> > The requester-id to stream-id mapping is based on PCI-LUT table
> > initialization.
> >
> > Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com>
> > ---
> > drivers/pci/pcie_layerscape_fixup.c | 53
> > +
> > 1 file changed, 53 insertions(+)
> >
> > diff --git a/drivers/pci/pcie_layerscape_fixup.c
> > b/drivers/pci/pcie_layerscape_fixup.c
> > index 8f8f6b6..301afee 100644
> > --- a/drivers/pci/pcie_layerscape_fixup.c
> > +++ b/drivers/pci/pcie_layerscape_fixup.c
> > @@ -103,6 +103,56 @@ static void fdt_pcie_set_msi_map_entry(void
> *blob, struct ls_pcie *pcie,
> > fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); }
> >
> > +/*
> > + * An iommu-map is a property to be added to the pci controller
> > + * node. It is a table, where each entry consists of 4 fields
> > + * e.g.:
> > + *
> > + * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
> > + * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
> > + */
> > +static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie
> *pcie,
> > + u32 devid, u32 streamid)
> > +{
> > + u32 *prop;
> > + u32 iommu_map[4];
> > + int nodeoffset;
> > + int lenp;
> > +
> > + /* find pci controller node */
> > + nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
> > + pcie->dbi_res.start);
> > + if (nodeoffset < 0) {
> > +#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of
> dts node */
> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
> > + CONFIG_FSL_PCIE_COMPAT, pcie-
> >dbi_res.start);
> > + if (nodeoffset < 0)
> > + return;
> > +#else
> > + return;
> > +#endif
> > + }
> > +
> > + /* get phandle to MSI controller */
>
> I guess that the phandle is to the iommu node, not to the MSI controller.
Yes, Thanks I will correct this in next version.
Thanks
-Bharat
>
> > + prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", );
> > + if (prop == NULL) {
> > + debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
> > + __func__, pcie->idx);
> > + return;
> > + }
> > +
> > + /* set iommu-map row */
> > + iommu_map[0] = cpu_to_fdt32(devid);
> > + iommu_map[1] = *++prop;
> > + iommu_map[2] = cpu_to_fdt32(streamid);
> > + iommu_map[3] = cpu_to_fdt32(1);
> > +
> > + if (devid == 0)
> > + fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
> iommu_map, 16);
> > + else
> > + fdt_appendprop(blob, nodeoffset, "iommu-map",
> iommu_map, 16); }
> > +
> > static void fdt_fixup_pcie(void *blob) {
> > struct udevice *dev, *bus;
> > @@ -139,6 +189,9 @@ static void fdt_fixup_pcie(void *blob)
> > /* update msi-map in device tree */
> > fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
> >streamid);
> > + /* update iommu-map in device tree */
> > + fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
> > + streamid);
> > }
> > }
> > #endif
>
> Diana
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[U-Boot] [PATCH 4/6] fsl-lsch2: Use Chassis-2 streamid definition for ls1046a
As ls1046a is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for ls1046 Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- include/configs/ls1046a_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index be65e4f..b4b198b 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -13,6 +13,7 @@ #define CONFIG_GICV2 #include +#include /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] pcie-layerscape: Fixup iommu-map property of pci node
This patch fixup iommu-map property on pci node to have
a valid mapping of requester-id to stream-id.
The requester-id to stream-id mapping is based on
PCI-LUT table initialization.
Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com>
---
drivers/pci/pcie_layerscape_fixup.c | 53 +
1 file changed, 53 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 8f8f6b6..301afee 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -103,6 +103,56 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct
ls_pcie *pcie,
fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
}
+/*
+ * An iommu-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
+{
+ u32 *prop;
+ u32 iommu_map[4];
+ int nodeoffset;
+ int lenp;
+
+ /* find pci controller node */
+ nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
+ pcie->dbi_res.start);
+ if (nodeoffset < 0) {
+#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+ nodeoffset = fdt_node_offset_by_compat_reg(blob,
+ CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
+ if (nodeoffset < 0)
+ return;
+#else
+ return;
+#endif
+ }
+
+ /* get phandle to MSI controller */
+ prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", );
+ if (prop == NULL) {
+ debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
+ __func__, pcie->idx);
+ return;
+ }
+
+ /* set iommu-map row */
+ iommu_map[0] = cpu_to_fdt32(devid);
+ iommu_map[1] = *++prop;
+ iommu_map[2] = cpu_to_fdt32(streamid);
+ iommu_map[3] = cpu_to_fdt32(1);
+
+ if (devid == 0)
+ fdt_setprop_inplace(blob, nodeoffset, "iommu-map", iommu_map,
16);
+ else
+ fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
+}
+
static void fdt_fixup_pcie(void *blob)
{
struct udevice *dev, *bus;
@@ -139,6 +189,9 @@ static void fdt_fixup_pcie(void *blob)
/* update msi-map in device tree */
fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
streamid);
+ /* update iommu-map in device tree */
+ fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
+ streamid);
}
}
#endif
--
1.9.3
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[U-Boot] [PATCH 5/6] fsl-lsch2: Use Chassis-2 streamid definition for ls1012a
As ls1012a is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for ls1012a Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- include/configs/ls1012a_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index e556c92..5765181 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -11,6 +11,7 @@ #define CONFIG_GICV2 #include +#include #define CONFIG_SUPPORT_RAW_INITRD -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/6] pcie-layerscape: Define stream-ids for Layerscape Chassis-2
Layerscape Chassis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they lies behind SMMU. This patch defines the stream-ids for Chassis-2 devices. stream-ids for DPAA1 are reserved for future use. Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 ++ include/configs/ls1043a_common.h | 1 + 2 files changed, 61 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 000..d41dd2e --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices + * are not hardwired and are programmed by sw. There are a limited number + * of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, PCI, + * and DPAA1 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * + * -DPAA1 + * - Stream ids for DPAA1 use are reserved for future usecase. + * + */ + + +#define FSL_INVALID_STREAM_ID 0 + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START11 +#define FSL_PEX_STREAM_ID_END 26 + +/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END63 + +#endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index c4b05e0..5f84497 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -13,6 +13,7 @@ #define CONFIG_MP #define CONFIG_GICV2 +#include #include /* Link Definitions */ -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
The stream ID allocation for Chasis3.0 devices,
LS1088, LS2088 and LS2080, can be shared.
This patch renames this accordingly.
Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com>
---
.../asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} | 0
include/configs/ls2080a_common.h| 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h =>
stream_id_lsch3.h} (100%)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
similarity index 100%
rename from arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
rename to arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 4bfd0ac..ee432ae 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -13,7 +13,7 @@
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
-#include
+#include
#include
/* Link Definitions */
--
1.9.3
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[U-Boot] [PATCH 0/6] pcie-layerscape: Enable PCI-LUT initialization for NXP-Chasis-2
This patch series enables PCI-LUT table initialization
for NXP Chassis-2 (for example ls1043, ls1046 and LS1012) devices.
As part of this, stream-ids allocation is added which is similar
to Chassis-3 (ls2080a)
Also this series have a minor cleanup, as stream-id definition file
is given generic name for chassis-3 devices. This allows new SOCs,
ls2088, ls1088 etc to use same allocation mechanism.
Bharat Bhushan (6):
fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
fsl-lsch3: Rewording to support other Chassis-3 Socs
pcie-layerscape: Define stream-ids for Layerscape Chassis-2
fsl-lsch2: Use Chassis-2 streamid definition for ls1046a
fsl-lsch2: Use Chassis-2 streamid definition for ls1012a
pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs
.../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 ++
.../{ls2080a_stream_id.h => stream_id_lsch3.h} | 12 ++---
drivers/pci/pcie_layerscape_fixup.c| 4 +-
include/configs/ls1012a_common.h | 1 +
include/configs/ls1043a_common.h | 1 +
include/configs/ls1046a_common.h | 1 +
include/configs/ls2080a_common.h | 2 +-
7 files changed, 72 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h =>
stream_id_lsch3.h} (86%)
--
1.9.3
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[U-Boot] [PATCH 2/6] fsl-lsch3: Rewording to support other Chassis-3 Socs
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs. Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index ee28323..6e97909 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -8,11 +8,11 @@ #define __FSL_STREAM_ID_H /* - * Stream IDs on ls2080a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. + * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) + * devices are not hardwired and are programmed by sw. There are a limited + * number of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, + * PCI, and DPAA2 devices. * * This partitioning can be customized in this file depending * on the specific hardware config: @@ -36,7 +36,7 @@ * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * - * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for + * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bitstreamID bit -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/6] pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs
From: Bharat Bhushan <bharat.bhus...@nxp.com> Layerscape Chasis-2 also uses same PCIe controller as used in Chasis-3 and have similar PCI-Lut. We need to initialize the pcie-lut for Chasis-2 also as in Chasis-3. Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- drivers/pci/pcie_layerscape_fixup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 19ede2f..8f8f6b6 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -15,7 +15,7 @@ #include #include "pcie_layerscape.h" -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) /* * Return next available LUT index. */ @@ -175,7 +175,7 @@ void ft_pci_setup(void *blob, bd_t *bd) list_for_each_entry(pcie, _pcie_list, list) ft_pcie_ls_setup(blob, pcie); -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) fdt_fixup_pcie(blob); #endif } -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
> -Original Message-
> From: york sun
> Sent: Monday, January 30, 2017 9:44 PM
> To: Bharat Bhushan <bharat.bhus...@nxp.com>; Z.Q. Hou
> <zhiqiang@nxp.com>; M.H. Lian <minghuan.l...@nxp.com>; u-
> b...@lists.denx.de
> Cc: albert.u.b...@aribaud.net; s...@chromium.org
> Subject: Re: [PATCH 1/3] fsl-lsch3: rename ls2080a_stream_id.h to
> stream_id_lsch3.h
>
> On 01/30/2017 02:45 AM, Bharat Bhushan wrote:
> > The stream ID allocation for Chasis3.0 devices, LS1088, LS2088 and
> > LS2080, can be shared.
> >
> > This patch renames this accordingly.
> >
> > Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com>
> > ---
> > .../asm/arch-fsl-layerscape/ls2080a_stream_id.h| 77
> > --
> > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 77
> ++
> > include/configs/ls2080a_common.h | 2 +-
> > 3 files changed, 78 insertions(+), 78 deletions(-) delete mode
> > 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
> > create mode 100644
> > arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
> >
>
> Bharat,
>
> When you create patches, please use tools/patman/patman. It automatically
> does many things for you. If you have to create it manually, make sure you
> use -M -C flag for "git format-patch". This patch should show changes as
>
> .../asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h}
> | 0
> include/configs/ls2080a_common.h
> | 2 +-
> 2 files changed, 1 insertion(+), 1 deletion(-)
> rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h
> => stream_id_lsch3.h} (100%)
>
> It would be lot easier to review.
Thanks York, , will ensure from next time.
Thanks
-Bharat
>
> York
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[U-Boot] [PATCH 0/3] pcie-layerscape: Enable PCI-LUT initialization for NXP-Chasis-2
First patch is rename the stream-id defination file to generic so that this can be leveraged for new SOCs, ls2088, ls1088 etc. Second add stream-ids allocation for NXP Chasis-2 based SOCs, ls1043, ls1046 etc. and Third patch enables PCI-LUT initialization. Bharat Bhushan (3): fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h pcie-layerscape: Define stream-ids for Layerscape Chasis-2 pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs .../asm/arch-fsl-layerscape/ls2080a_stream_id.h| 77 -- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 77 ++ drivers/pci/pcie_layerscape_fixup.c| 4 -- include/configs/ls1043a_common.h | 1 + include/configs/ls2080a_common.h | 2 +- 6 files changed, 139 insertions(+), 82 deletions(-) delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs
Layerscape Chasis-2 also uses same PCIe controller
as used in Chasis-3 and have similar PCI-Lut.
We need to initialize the pcie-lut for Chasis-2 also
as in Chasis-3.
Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com>
---
drivers/pci/pcie_layerscape_fixup.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 19ede2f..2f13e1f 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -15,7 +15,6 @@
#include
#include "pcie_layerscape.h"
-#ifdef CONFIG_FSL_LSCH3
/*
* Return next available LUT index.
*/
@@ -141,7 +140,6 @@ static void fdt_fixup_pcie(void *blob)
streamid);
}
}
-#endif
static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
{
@@ -175,9 +173,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
list_for_each_entry(pcie, _pcie_list, list)
ft_pcie_ls_setup(blob, pcie);
-#ifdef CONFIG_FSL_LSCH3
fdt_fixup_pcie(blob);
-#endif
}
#else /* !CONFIG_OF_BOARD_SETUP */
--
1.9.3
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[U-Boot] [PATCH 2/3] pcie-layerscape: Define stream-ids for Layerscape Chasis-2
Layerscape Chasis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they lies behind SMMU. This patch defines the stream-ids for Chasis-2 devices. stream-ids for DPAA1 are reserved for future use. Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 ++ include/configs/ls1043a_common.h | 1 + 2 files changed, 61 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 000..bdfed83 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on ls1043a devices are not hardwired and are + * programmed by sw. There are a limited number of stream IDs + * available, and the partitioning of them is scenario dependent. + * This header defines the partitioning between legacy, PCI, + * and DPAA1 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * + * -DPAA1 + * - Stream ids for DPAA1 use are reserved for future usecase. + * + */ + + +#define FSL_INVALID_STREAM_ID 0 + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START11 +#define FSL_PEX_STREAM_ID_END 26 + +/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END63 + +#endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index aa2b6f1..eee6fad 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -13,6 +13,7 @@ #define CONFIG_MP #define CONFIG_GICV2 +#include #include /* Link Definitions */ -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
The stream ID allocation for Chasis3.0 devices, LS1088, LS2088 and LS2080, can be shared. This patch renames this accordingly. Signed-off-by: Bharat Bhushan <bharat.bhus...@nxp.com> --- .../asm/arch-fsl-layerscape/ls2080a_stream_id.h| 77 -- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 77 ++ include/configs/ls2080a_common.h | 2 +- 3 files changed, 78 insertions(+), 78 deletions(-) delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h deleted file mode 100644 index ee28323..000 --- a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier:GPL-2.0+ - * - */ -#ifndef __FSL_STREAM_ID_H -#define __FSL_STREAM_ID_H - -/* - * Stream IDs on ls2080a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. - * - * This partitioning can be customized in this file depending - * on the specific hardware config: - * - * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) - * -all legacy devices get a unique stream ID assigned and programmed in - * their AMQR registers by u-boot - * - * -PCIe - * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: - * -allocate a streamID - * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' - * -set a msi-map entry in the PEXn controller node in the - * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt - * for more info on the msi-map definition) - * - * -DPAA2 - * -u-boot will allocate a range of stream IDs to be used by the Management - * Complex for containers and will set these values in the MC DPC image. - * -the MC is responsible for allocating and setting up 'isolation context - * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. - * - * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for - * each of the different bus masters. The relationship between - * the AMQ registers and stream IDs is defined in the table below: - * AMQ bitstreamID bit - * --- - * PL[18] 9// privilege bit - * BMT[17] 8// bypass translation - * VA[16] 7// reserved - * [15] -// unused - * ICID[14:7] -// unused - * ICID[6:0]6-0 // isolation context id - * - * - */ - -#define AMQ_PL_MASK(0x1 << 18) /* priviledge bit */ -#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ - -#define FSL_INVALID_STREAM_ID 0 - -#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) - -/* legacy devices */ -#define FSL_USB1_STREAM_ID 1 -#define FSL_USB2_STREAM_ID 2 -#define FSL_SDMMC_STREAM_ID3 -#define FSL_SATA1_STREAM_ID4 -#define FSL_SATA2_STREAM_ID5 -#define FSL_DMA_STREAM_ID 6 - -/* PCI - programmed in PEXn_LUT */ -#define FSL_PEX_STREAM_ID_START7 -#define FSL_PEX_STREAM_ID_END 22 - -/* DPAA2 - set in MC DPC and alloced by MC */ -#define FSL_DPAA2_STREAM_ID_START 23 -#define FSL_DPAA2_STREAM_ID_END63 - -#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h new file mode 100644 index 000..ee28323 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -0,0 +1,77 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on ls2080a devices are not hardwired and are + * programmed by sw. There are a limited number of stream IDs + * available, and the partitioning of them is scenario dependent. + * This header defines the partitioning between legacy, PCI, + * and DPAA2 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of st
Re: [U-Boot] uboot kernel rejects filesystem
Hi Detlev, Seems there was an issue with my kernel code that you correctly pointed out in previous mail. Now I could pass bootarg board='myboard'. For myboard, I have done relevent changes in kernel code, so kernel does init for my hardware. Earlier while choosing mips machine, it was choosing generic mips machine which did not mtdpartitions defined. Now with added support of myboard, everything seems to be good. Thanks for the promptly helps you have given. Regards, Bharat ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] uboot kernel rejects filesystem
Hi Detlev, I have gone thru the kernel code. I could only figure out that m25p80 is spi driver which is register as spi-driver. Registration is done, which I could see from early printk's. But this module is never probed. Next, kernel iterates through the list of devices and tries to find out mtdpart, which it can not see. Since your mail gave very good pointer where to look for with ref to another nor flash. Regards, Bharat Seems I quoted text in previous mail which annoyed you. Sorry for being naive. I hope I will not repeat the same. -- Bharat ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] uboot kernel rejects filesystem
Hi Detlev, On Tue, May 12, 2009 at 9:10 PM, Detlev Zundel d...@denx.de wrote: Hi Bharat, [re-adding the mailing list as others may also profit from the discussion] Thank you for the prompt reply. Unfortunately in linux tree, my board specific MTD partition info is not preset. Is there any quick way round. Yep - thinking some more, I see two possible (quick) solutions. M/M Layout: 0xBF00 : U-BOOT 0xBF04 : u_boot_config_area 0xBF06: vm_linux_image (with u-boot header : created by mkimage and LZMA) 0xBF26: root_fs area... Here I have flashed squashfs (without u-boot hdr) Should I? 0xBFFC: root_fs_data .. JFFS RW filesystem Just as a sidenote - are you able to use the JFFS (really JFFS, not JFFS2?) image? If so, then you _do_ have an MTD partition in Linux which you only need to tweak. I do following on u-boot prompt boardbootm 0xBF06 0xBF26 This command only makes sense, if the image at 0xbf26 is wrapped with mkimage. This is exactly the first solution that you can try, i.e. use mkimage with -T ramdisk to wrap your image and use the it with the two argument bootm version like you tried. Maybe you will need to specify rootfstype=squashfs on the command line also, you will have to check this. Having said this, if you are on an ARM platform, the above will very likely not work, so you will have to turn to the other solution I have in mind: NO SUCCESS again I try: with modification to include/configs/my_board.h file as #define MTDIDS_DEFAULT nor0=app #define MTDPARTS_DEFAULT \ mtdparts=app:64k(u-boot),64k(boot_config),64k(board_config),2048k (kernel),13696(rootfs),256kb(roots_data) #define CONFIG_BOOTARGS root=/dev/mtdblock4 rootfstype=squashfs console= ttyS1,115200 boardbootm 0xbf06 I have modified in kernel for mtd support. in U_BOOT following is the info: u-bflinfo Bank # 1: 256x64K=16MB, Spansion SL25FL128P (0x012018) u-bmtdparts device nor0 m25p80, # parts = 5 #: namesizeoffset mask_flags 0: boot0x0004 0x 0 1: boot_config 0x0001 0x0004 0 2: board_config0x0001 0x0005 0 3: kernel 0x0020 0x0006 0 4: filesystem 0x0040 0x0026 0 active partition: nor0,0 - (boot) 0x0004 @ 0x defaults: mtdids : nor0=m25p80 mtdparts: mtdparts=m25p80:256k(boot),64k(boot_config),64k(board_config),2048k(kernel),4m(filesystem) u-bbootm 0xbf06000 Log messages from kernel: ## Booting kernel from Legacy Image at bf06 ... Image Name: MIPS OpenWrt Linux-2.6.28.9 Image Type: MIPS Linux Kernel Image (lzma compressed) Data Size:767717 Bytes = 749.7 kB Load Address: 8006 Entry Point: 8006 Verifying Checksum ... OK ## No init Ramdisk ramdisk start = 0x, ramdisk end = 0x Uncompressing Kernel Image ... OK linux_argv[0]:NULL linux_env a3f9c3c0 theKernel 8006 Starting kernel ... Linux version 2.6.28.9 (bha...@debian) (gcc version 4.1.2) #5 Thu May 14 22:15:40 IST 2009 console [early0] enabled CPU revision is: 00019374 (MIPS 24Kc) Atheros AR7161 rev 2 (id:0xaa), CPU:680.000 MHz, AHB:170.000 MHz, DDR:340.000 MHz Determined physical RAM map: memory: 0400 @ (usable) Initrd not found or empty - disabling initrd Zone PFN ranges: Normal 0x - 0x4000 Movable zone start PFN for each node early_node_map[1] active PFN ranges 0: 0x - 0x4000 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256 Kernel command line: root=/dev/mtdpart4 rootfstype=squashfs,yaffs,jffs2 noinitrd console=ttyS0,115200 init=/etc/preinit Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes. Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes Writing ErrCtl register=1c10 Readback ErrCtl register=1c10 PID hash table entries: 256 (order: 8, 1024 bytes) Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 62120k/65536k available (1820k kernel code, 3340k reserved, 330k data, 132k init, 0k highmem) SLUB: Genslabs=6, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 Calibrating delay loop... 452.19 BogoMIPS (lpj=2260992) Mount-cache hash table entries: 512 net_namespace: 480 bytes NET: Registered protocol family 16 MIPS: machine is Generic AR71xx board NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 2048 (order: 2, 16384 bytes) TCP bind hash table entries: 2048 (order: 1, 8192 bytes) TCP: Hash tables configured (established 2048 bind 2048) TCP reno registered NET: Registered protocol family 1 squashfs: version 3.0 (2006/03/15) Phillip Lougher Registering mini_fo version $Id$ JFFS2 version 2.2. (NAND) (SUMMARY) ©
[U-Boot] uboot kernel rejects filesystem
Hi All,
I am very new to u-boot.
I have kernel image, which I loaded to NOR of my board and with bootm,
control passes to kernel and it starts booting.
There is panic in kernel: since it can not find the file-system. I am
afraid, I did make trivial mistake.
I have flashed squashfs filesystem image to NOR @ address NOR1 I did not
define any partition.
I do not have MTD support.
Now I tried booting like after setting
setenv kernel_addr 0xBF06Note this has u-boot hdr generated
form mkimage
setenv ramdisk_addr 0xBF26Note this does not have u-boot hdr
generated form mkimage
setenv bootargs 'filesystem=squashfs'
I do bootm ${kernel_addr} ${ramdisk_addr}
I do get error from U_BOOT that :
*Wrong Ramdisk Image Format
Ramdisk image is corrupt or invalid
*I am sure that I have done something wrong in this process:
Few Questions which I could not find the answer:
1. Can I nor-flash the image without u-boot hdr.
2. Is it necessary to have MTD partition defined.
3. Do we have any document which specify the boot arguments in context of
U_BOOT. I tried denx website. I could not figure out much. May be I do not
what to search for.
Any help would be highly appreciated.
Regards,
Bharat
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