Re: [U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to switch QSPI bank

[Calvin Johnson]

Hi York,

> -Original Message-
> From: York Sun
> Sent: Tuesday, July 31, 2018 8:37 PM
> To: Calvin Johnson ; Scott Wood
> ; Calvin Johnson 
> Cc: Jagdish Gediya ; U-Boot Mailing List  b...@lists.denx.de>
> Subject: Re: [U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to
> switch QSPI bank
> 
> On 04/19/2018 06:53 PM, Calvin Johnson wrote:
> >>
> >>> would be better. What this patch currently does can be done with
> >>> simple env vars, like :
> >>>
> >>> setenv boot_bank_1 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf5'
> >>> setenv boot_bank_2 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf4'
> >>
> >> ...if the user knows to env reset those variables after the update
> >> (versus something that shows up in help), and if they don't get
> >> corrupted in a multi- user board farm environment, etc.
> >
> > Make sense. Thanks!
> >
> 
> Calvin,
> 
> Do you want to stay with env, or still want this patch, or standardize the
> command?

Ideally, a fully standardized generic command interface supporting all similar 
platforms with multiple banks as well as other boot sources such as NAND and 
MMC, 
is the best option.

This patch looks good as an interim solution.

Regards
Calvin
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Re: [U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to switch QSPI bank

[Calvin Johnson]

> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Friday, April 20, 2018 6:40 AM
> To: Calvin Johnson <linux...@gmail.com>
> Cc: Jagdish Gediya <jagdish.ged...@nxp.com>; U-Boot Mailing List  b...@lists.denx.de>; Calvin Johnson <calvin.john...@nxp.com>; York Sun
> <york@nxp.com>
> Subject: Re: [U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to
> switch QSPI bank
> 
> On Thu, 2018-04-19 at 14:09 +0530, Calvin Johnson wrote:
> > On Thu, Apr 19, 2018 at 12:17 PM, Scott Wood <o...@buserror.net> wrote:
> > > On Mon, 2018-04-16 at 08:40 +0530, Calvin Johnson wrote:
> > > > On Fri, Apr 13, 2018 at 12:18 AM, Jagdish Gediya <jagdish.ged...@nxp.com
> > > > >
> > > > wrote:
> > > > > Add command "boot_bank X" to switch the boot bank to either
> > > > > 1 or 2.
> > > >
> > > > Are these functions required as this can be handled by new env vars to
> > > > switch banks?
> > >
> > > If you're going to add something new, a command is much more pleasant
> than
> > > env
> > > vars -- particularly if you stick to something like the familiar
> > > interfaces
> > > ("pix altbank", "qix altbank", etc), and include reporting of which bank
> > > was
> > > booted from if it's not there already.  Of course, a fully standardized
> > > interface would be even better.
> >
> > Yes, a fully standardized generic interface supporting all similar
> > platforms with multiple banks
> 
> And other boot sources such as NAND and MMC.
> 
> > would be better. What this patch currently does can be done with
> > simple env vars, like :
> >
> > setenv boot_bank_1 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf5'
> > setenv boot_bank_2 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf4'
> 
> ...if the user knows to env reset those variables after the update (versus
> something that shows up in help), and if they don't get corrupted in a multi-
> user board farm environment, etc.

Make sense. Thanks!

Calvin
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Re: [U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to switch QSPI bank

[Calvin Johnson]

On Thu, Apr 19, 2018 at 12:17 PM, Scott Wood <o...@buserror.net> wrote:
> On Mon, 2018-04-16 at 08:40 +0530, Calvin Johnson wrote:
>> On Fri, Apr 13, 2018 at 12:18 AM, Jagdish Gediya <jagdish.ged...@nxp.com>
>> wrote:
>> > Add command "boot_bank X" to switch the boot bank to either
>> > 1 or 2.
>>
>> Are these functions required as this can be handled by new env vars to
>> switch banks?
>
> If you're going to add something new, a command is much more pleasant than env
> vars -- particularly if you stick to something like the familiar interfaces
> ("pix altbank", "qix altbank", etc), and include reporting of which bank was
> booted from if it's not there already.  Of course, a fully standardized
> interface would be even better.

Yes, a fully standardized generic interface supporting all similar
platforms with multiple banks
would be better. What this patch currently does can be done with
simple env vars, like :

setenv boot_bank_1 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf5'
setenv boot_bank_2 'i2c mw 0x24 0x7 0xfc; i2c mw 0x24 0x3 0xf4'

regards
Calvin
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Re: [U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to switch QSPI bank

[Calvin Johnson]

On Fri, Apr 13, 2018 at 12:18 AM, Jagdish Gediya  wrote:
> Add command "boot_bank X" to switch the boot bank to either
> 1 or 2.

Are these functions required as this can be handled by new env vars to
switch banks?

>
> Signed-off-by: Jagdish Gediya 
> ---
>  board/freescale/ls1012ardb/ls1012ardb.c | 85 
> +
>  1 file changed, 85 insertions(+)
>
> diff --git a/board/freescale/ls1012ardb/ls1012ardb.c 
> b/board/freescale/ls1012ardb/ls1012ardb.c
> index ed5a8e6..4d4f6fb 100644
> --- a/board/freescale/ls1012ardb/ls1012ardb.c
> +++ b/board/freescale/ls1012ardb/ls1012ardb.c
> @@ -26,6 +26,9 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> +#define BOOT_FROM_UPPER_BANK   0x2
> +#define BOOT_FROM_LOWER_BANK   0x1
> +
>  int checkboard(void)
>  {
>  #ifdef CONFIG_TARGET_LS1012ARDB
> @@ -212,3 +215,85 @@ int ft_board_setup(void *blob, bd_t *bd)
>
> return 0;
>  }
> +
> +static int switch_to_bank1(void)
> +{
> +   u8 data;
> +   int ret;
> +
> +   i2c_set_bus_num(0);
> +
> +   data = 0xf4;
> +   ret = i2c_write(0x24, 0x3, 1, , 1);
> +   if (ret) {
> +   printf("i2c write error to chip : %u, addr : %u, data : %u\n",
> +  0x24, 0x3, data);
> +   }
> +
> +   return ret;
> +}
> +
> +static int switch_to_bank2(void)
> +{
> +   u8 data;
> +   int ret;
> +
> +   i2c_set_bus_num(0);
> +
> +   data = 0xfc;
> +   ret = i2c_write(0x24, 0x7, 1, , 1);
> +   if (ret) {
> +   printf("i2c write error to chip : %u, addr : %u, data : %u\n",
> +  0x24, 0x7, data);
> +   goto err;
> +   }
> +
> +   data = 0xf5;
> +   ret = i2c_write(0x24, 0x3, 1, , 1);
> +   if (ret) {
> +   printf("i2c write error to chip : %u, addr : %u, data : %u\n",
> +  0x24, 0x3, data);
> +   }
> +err:
> +   return ret;
> +}
> +
> +static int convert_flash_bank(int bank)
> +{
> +   int ret = 0;
> +
> +   switch (bank) {
> +   case BOOT_FROM_UPPER_BANK:
> +   ret = switch_to_bank2();
> +   break;
> +   case BOOT_FROM_LOWER_BANK:
> +   ret = switch_to_bank1();
> +   break;
> +   default:
> +   ret = CMD_RET_USAGE;
> +   break;
> +   };
> +
> +   return ret;
> +}
> +
> +static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
> + char * const argv[])
> +{
> +   if (argc != 2)
> +   return CMD_RET_USAGE;
> +   if (strcmp(argv[1], "1") == 0)
> +   convert_flash_bank(BOOT_FROM_LOWER_BANK);
> +   else if (strcmp(argv[1], "2") == 0)
> +   convert_flash_bank(BOOT_FROM_UPPER_BANK);
> +   else
> +   return CMD_RET_USAGE;
> +
> +   return 0;
> +}
> +
> +U_BOOT_CMD(
> +   boot_bank, 2, 0, flash_bank_cmd,
> +   "Flash bank Selection Control",
> +   "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
> +);
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH 3/4] elf: Add a very simple elf64 loader

[Calvin Johnson]

On Mon, Apr 09, 2018 at 11:28:30PM -0700, Bin Meng wrote:
> This adds a very simple elf64 loader via program headers, similar
> to load_elf_image_phdr() that we already have.
> 
> Signed-off-by: Bin Meng 
> ---
> 
>  cmd/elf.c | 34 ++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/cmd/elf.c b/cmd/elf.c
> index 501f935..91a04da 100644
> --- a/cmd/elf.c
> +++ b/cmd/elf.c
> @@ -24,6 +24,37 @@
>  #endif
>  
>  /*
> + * A very simple elf64 loader, assumes the image is valid, returns the
> + * entry point address.
> + */
> +static unsigned long load_elf64_image_phdr(unsigned long addr)
> +{
> + Elf64_Ehdr *ehdr; /* Elf header structure pointer */
> + Elf64_Phdr *phdr; /* Program header structure pointer */
> + int i;
> +
> + ehdr = (Elf64_Ehdr *)addr;
> + phdr = (Elf64_Phdr *)(addr + (ulong)ehdr->e_phoff);
> +
> + /* Load each program header */
> + for (i = 0; i < ehdr->e_phnum; ++i) {
> + void *dst = (void *)(ulong)phdr->p_paddr;
> + void *src = (void *)addr + phdr->p_offset;
> + debug("Loading phdr %i to 0x%p (%lu bytes)\n",
> +   i, dst, (ulong)phdr->p_filesz);
> + if (phdr->p_filesz)
> + memcpy(dst, src, phdr->p_filesz);
> + if (phdr->p_filesz != phdr->p_memsz)
> + memset(dst + phdr->p_filesz, 0x00,
> +phdr->p_memsz - phdr->p_filesz);
> + flush_cache((unsigned long)dst, phdr->p_filesz);
> + ++phdr;
> + }
> +
> + return ehdr->e_entry;
> +}
> +
> +/*
>   * A very simple elf loader, assumes the image is valid, returns the
Would it be good to modify this comment to indicate elf32 loader?
>   * entry point address.
>   */
> @@ -34,6 +65,9 @@ static unsigned long load_elf_image_phdr(unsigned long addr)
>   int i;
>  
>   ehdr = (Elf32_Ehdr *)addr;
> + if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
> + return load_elf64_image_phdr(addr);
> +
>   phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
>  
>   /* Load each program header */
> -- 
> 2.7.4
> 
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Re: [U-Boot] configs: ls1012a: add pfe configuration for LS1012A

[Calvin Johnson]

Thanks Joe for reviewing and merging the PFE driver patches.

Calvin

> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> Sent: Tuesday, March 27, 2018 12:56 AM
> To: Calvin Johnson <calvin.john...@nxp.com>
> Cc: u-boot <u-boot@lists.denx.de>
> Subject: Re: configs: ls1012a: add pfe configuration for LS1012A
> 
> Hi Calvin,
> 
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchw
> ork.ozlabs.org%2Fpatch%2F883033%2F=02%7C01%7Ccalvin.johnson%40nx
> p.com%7Cc29bdd41dec24a2d3ce508d593474d51%7C686ea1d3bc2b4c6fa92cd99c5
> c301635%7C0%7C0%7C636576856821377657=kBw6DEIqgWsx8fZT%2BP9tV
> pViKJ1DBYDSQaQKqBisDQU%3D=0 was applied to
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fgit.denx
> .de%2F%3Fp%3Du-boot%2Fu-boot-
> net.git=02%7C01%7Ccalvin.johnson%40nxp.com%7Cc29bdd41dec24a2d3ce
> 508d593474d51%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636576856
> 821377657=zC3N6DAoV9zpQfPYO%2FJaoB%2BCH68ofXhvnR%2BTu9iM8pI
> %3D=0
> 
> Thanks!
> -Joe
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Re: [U-Boot] [PATCH V2 4/5] net: fec: sharing MDIO for two enet controllers

[Calvin Johnson]

Hi Joe,

> >>>
> >>> No, I think we can do this with adding new DM MDIO similar to DM PHY
> which
> >>> recently done. May be some sort of efforts but it is permanent.
> >> We do not have that driver now, so could we first have this patch? When
> >> DM MDIO ready, this piece code could be removed then?
> >
> > ie. up to Joe. Honestly this macro become removed in future, my point
> > here is why we need to maintain dead macro instead of adding proper
> > maintainable stuff. I'm pretty sure adding DM_MDIO is straight forward
> > and as of now just add what we need and rest will implement future.
> > You may become victim to others to move DM_ETH as soon as possible :)
> 
> It would be ideal if you wanted to implement DM MDIO, but I can also
> appreciate that this is not already there for you to use. As I
> commented when I acked this, the I'm OK with this approach at this
> time due to the state of the DM support in eth.
> 
> As a side note, maybe moving other boards that use this NIC to DM_ETH
> and removing non-DM support would be a better cleanup to start with.

Is someone already working on DM MDIO? 
Are there any patches already submitted for this? I couldn't find any.

Thanks
Calvin


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Re: [U-Boot] [PATCH v8 1/3] Adding TCP and wget into u-boot

[Calvin Johnson]

> > It would be good to have this cosmetic change into a separate patch.
> 
> Ok. But at this stage I'm at the "Forgive me Lord for I know not what
> I do"

 . 
Let me know, if you need steps to separate this out. 
To me, it is okay even If you keep this in the same patch.


 
> > >  /* Set IP header */
> > > -void net_set_ip_header(uchar *pkt, struct in_addr dest, struct
> > > in_addr source); +void net_set_ip_header(uchar *pkt, struct in_addr
> > > dest, struct in_addr source,
> > > +u16  pkt_len, u8 prot);
> > >  void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport,
> > > - int sport, int len);
> > > -
> > > + int sport, int len);
> >
> Why do you need this change in the set_udp_header?
> 
> This is a shim to bridge between the original udp to ip procedure call
> and the extra parameters in the enhanced ip procedure call to the ip
> layer for TCP.
> 
> The original udp call is unchanged, because I did not want a
> change to a procedure call to ripple through many applications.

For now, I'm okay with the change you made to net_set_ip_header.

-   int sport, int len);
-
+   int sport, int len);
I'm concerned about above 3 line change. Here, you are decreasing indent 
and removing an empty line.  This change may not be required.

Regards
Calvin
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Re: [U-Boot] [PATCH v8 1/3] Adding TCP and wget into u-boot

[Calvin Johnson]

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of
> d...@synoia.com
> Sent: Thursday, March 8, 2018 10:14 AM
> To: duncanch...@yahoo.com
> Cc: Duncan Hare ; Joe Hershberger
> ; u-boot@lists.denx.de
> Subject: [U-Boot] [PATCH v8 1/3] Adding TCP and wget into u-boot



> diff --git a/include/net.h b/include/net.h
> index 455b48f6c7..7e5f5a6a5b 100644
> --- a/include/net.h
> +++ b/include/net.h
> @@ -15,17 +15,26 @@
>  #include 
>  #include/* for nton* / ntoh* stuff */
> 
> -#define DEBUG_LL_STATE 0 /* Link local state machine changes */
> -#define DEBUG_DEV_PKT 0  /* Packets or info directed to the 
> device
> */
> -#define DEBUG_NET_PKT 0  /* Packets on info on the network at 
> large
> */
> +#define DEBUG_LL_STATE  0/* Link local state machine changes */
> +#define DEBUG_DEV_PKT   0/* Packets or info directed to the device */
> +#define DEBUG_NET_PKT   0/* Packets on info on the network at large */
>  #define DEBUG_INT_STATE 0/* Internal network state changes */

It would be good to have this cosmetic change into a separate patch. 

>  /*
>   *   The number of receive packet buffers, and the required packet buffer
>   *   alignment in memory.
>   *
> + *   The number of buffers for TCP is used to calculate a static TCP window
> + *   size, becuse TCP window size is a promise to the sending TCP to be able
> + *   to buffer up to the window size of data.
> + *   When the sending TCP has a window size of outstanding
> unacknowledged
> + *   data, the sending TCP will stop sending.
>   */
> 
> +#if defined(CONFIG_TCP)
> +#define CONFIG_SYS_RX_ETH_BUFFER 12  /* For TCP */
> +#endif
> +

IMO, better place for this definition and associated explanation would be above 
the comment
describing PKTBUFSRX, i.e after immediately after below line.
#define DEBUG_INT_STATE 0   /* Internal network state changes */

>  #ifdef CONFIG_SYS_RX_ETH_BUFFER
>  # define PKTBUFSRX   CONFIG_SYS_RX_ETH_BUFFER
>  #else
> @@ -354,6 +363,7 @@ struct vlan_ethernet_hdr {
> 
>  #define IPPROTO_ICMP  1  /* Internet Control Message Protocol*/
>  #define IPPROTO_UDP  17  /* User Datagram Protocol   */
> +#define IPPROTO_TCP   6  /* Transmission Control Protocol*/

Better to sort IPPROTO in ascending order

> 
>  /*
>   *   Internet Protocol (IP) header.
> @@ -596,10 +606,10 @@ int net_set_ether(uchar *xet, const uchar
> *dest_ethaddr, uint prot);
>  int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot);
> 
>  /* Set IP header */
> -void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr 
> source);
> +void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr 
> source,
> +u16  pkt_len, u8 prot);
>  void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport,
> - int sport, int len);
> -
> + int sport, int len);

Why do you need this change in the set_udp_header? 

>  /**
>   * compute_ip_checksum() - Compute IP checksum
>   *
> @@ -670,6 +680,9 @@ static inline void net_send_packet(uchar *pkt, int len)
>   * @param sport Source UDP port
>   * @param payload_len Length of data after the UDP header
>   */
> +int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int 
> sport,
> +int payload_len, int proto);
> +

Place it above comments for net_send_udp_packet.

Regards
Calvin
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Re: [U-Boot] [PATCH v8 1/3] Adding TCP and wget into u-boot

[Calvin Johnson]

Hi Duncan,

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Joe
> Hershberger
> Sent: Friday, March 9, 2018 12:23 AM
> To: Duncan Hare 
> Cc: Duncan Hare ; Joe Hershberger
> ; Duncan Hare ; u-boot
> 
> Subject: Re: [U-Boot] [PATCH v8 1/3] Adding TCP and wget into u-boot
> 
> Hi Duncan,
> 
> Still some issues, but getting closer to parsable.
> 
> The subject of this should be something like, "net: Adjust UDP
> implementation to prepare for TCP support"
> 
> On Wed, Mar 7, 2018 at 10:43 PM,   wrote:
> > From: Duncan Hare 
> >
> >>
> > 
> 
> I think these are coming from your commit log. You should remove them.
> 
> >
> > cover-letter:
> 
> You need to use the exact tags in the documentation. That means that
> you need to capitalize the 'C'.

Whenever, I like to see how my patches appear in mail, I would send it ONLY to 
my mail id
and then compare with patches in the mailing list from experts .
Once I'm confident that my patches are following the guidelines, I'll send them 
to mailing list. 
Still, there can be mistakes , but most of them will be resolved by my own 
review.

Regards
Calvin

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[U-Boot] [PATCH v4 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure

[Calvin Johnson]

SoC specific PFE macros are defined and structure ccsr_scfg
is updated with members defined for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4: None
Changes in v3:
-Use BIT macro wherever applicable

Changes in v2: None

 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 38 --
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b195005..d6f0c5b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -395,6 +395,21 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
 #define SCFG_SNPCNFGCR_SATAWRSNP   0x0040
 
+/* RGMIIPCR bit definitions*/
+#define SCFG_RGMIIPCR_EN_AUTO  BIT(3)
+#define SCFG_RGMIIPCR_SETSP_1000M  BIT(2)
+#define SCFG_RGMIIPCR_SETSP_100M   0
+#define SCFG_RGMIIPCR_SETSP_10MBIT(1)
+#define SCFG_RGMIIPCR_SETFDBIT(0)
+
+/* PFEASBCR bit definitions */
+#define SCFG_PFEASBCR_ARCACHE0 BIT(31)
+#define SCFG_PFEASBCR_AWCACHE0 BIT(30)
+#define SCFG_PFEASBCR_ARCACHE1 BIT(29)
+#define SCFG_PFEASBCR_AWCACHE1 BIT(28)
+#define SCFG_PFEASBCR_ARSNPBIT(27)
+#define SCFG_PFEASBCR_AWSNPBIT(26)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u8 res_000[0x100-0x000];
@@ -412,7 +427,12 @@ struct ccsr_scfg {
u8 res_140[0x158-0x140];
u32 altcbar;
u32 qspi_cfg;
-   u8 res_160[0x180-0x160];
+   u8 res_160[0x164 - 0x160];
+   u32 wr_qos1;
+   u32 wr_qos2;
+   u32 rd_qos1;
+   u32 rd_qos2;
+   u8 res_174[0x180 - 0x174];
u32 dmamcr;
u8 res_184[0x188-0x184];
u32 gic_align;
@@ -443,7 +463,21 @@ struct ccsr_scfg {
u32 usb_refclk_selcr1;
u32 usb_refclk_selcr2;
u32 usb_refclk_selcr3;
-   u8 res_424[0x600-0x424];
+   u8 res_424[0x434 - 0x424];
+   u32 rgmiipcr;
+   u32 res_438;
+   u32 rgmiipsr;
+   u32 pfepfcssr1;
+   u32 pfeintencr1;
+   u32 pfepfcssr2;
+   u32 pfeintencr2;
+   u32 pfeerrcr;
+   u32 pfeeerrintencr;
+   u32 pfeasbcr;
+   u32 pfebsbcr;
+   u8 res_460[0x484 - 0x460];
+   u32 mdioselcr;
+   u8 res_468[0x600 - 0x488];
u32 scratchrw[4];
u8 res_610[0x680-0x610];
u32 corebcr;
-- 
2.7.4

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[U-Boot] [PATCH v4 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb

[Calvin Johnson]

This patch enables ethernet support for ls1012a2g5rdb.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Bhaskar Upadhaya <bhaskar.upadh...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4: None
Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Prefix CONFIG_PFE_ to appropriate macros
-Indent properly

Changes in v2:
-New patch added to series to enable ethernet support for
ls1012a2g5rdb

 board/freescale/ls1012ardb/Kconfig | 30 +
 board/freescale/ls1012ardb/eth.c   | 45 +++---
 2 files changed, 67 insertions(+), 8 deletions(-)

diff --git a/board/freescale/ls1012ardb/Kconfig 
b/board/freescale/ls1012ardb/Kconfig
index af35a01..493d477 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -59,6 +59,36 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 default "ls1012a2g5rdb"
 
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select PHYLIB
+   imply CONFIG_PHYLIB_10G
+   imply CONFIG_PHY_AQUANTIA
+
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+
+config PFE_EMAC1_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index e6379a3..8e6cd0a 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -26,6 +26,7 @@
 
 static inline void ls1012ardb_reset_phy(void)
 {
+#ifdef CONFIG_TARGET_LS1012ARDB
/* Through reset IO expander reset both RGMII and SGMII PHYs */
i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
@@ -34,6 +35,7 @@ static inline void ls1012ardb_reset_phy(void)
mdelay(10);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
mdelay(50);
+#endif
 }
 
 int pfe_eth_board_init(struct udevice *dev)
@@ -42,6 +44,11 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev);
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+   int srds_s1 = in_be32(>rcwsr[4]) &
+   FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+   srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
if (!init_done) {
ls1012ardb_reset_phy();
@@ -59,14 +66,36 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_mdio(priv->gemac_port,
 miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
 
-   if (!priv->gemac_port) {
-   /* MAC1 */
-   pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
-PHY_INTERFACE_MODE_SGMII);
-   } else {
-   /* MAC2 */
-   pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
-PHY_INTERFACE_MODE_RGMII_TXID);
+   switch (srds_s1) {
+   case 0x3508:
+   if (!priv->gemac_port) {
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   } else {
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_RGMII_TXID);
+   }
+   break;
+   case 0x2208:
+   if (!priv->gemac_port) {
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII_2500);
+   } else {
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII_2500);
+   }
+   break;
+   default:
+   printf("unsupported SerDes PRCTL= %d\n", srds_s1);
+   break;
}
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH v4 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb

[Calvin Johnson]

This patch enables ethernet support for ls1012ardb.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4:
-Compile pfe driver conditionally with CONFIG_FSL_PFE

Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth

Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"

 board/freescale/ls1012ardb/Kconfig  |  29 +
 board/freescale/ls1012ardb/Makefile |   1 +
 board/freescale/ls1012ardb/eth.c| 106 
 board/freescale/ls1012ardb/ls1012ardb.c |   4 --
 include/configs/ls1012ardb.h|   4 ++
 5 files changed, 140 insertions(+), 4 deletions(-)
 create mode 100644 board/freescale/ls1012ardb/eth.c

diff --git a/board/freescale/ls1012ardb/Kconfig 
b/board/freescale/ls1012ardb/Kconfig
index d13b08e..af35a01 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -12,6 +12,35 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1012ardb"
 
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select PHYLIB
+   imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+
+config PFE_EMAC1_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012ardb/Makefile 
b/board/freescale/ls1012ardb/Makefile
index 05fa9d9..70c7b33 100644
--- a/board/freescale/ls1012ardb/Makefile
+++ b/board/freescale/ls1012ardb/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012ardb.o
+obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
new file mode 100644
index 000..e6379a3
--- /dev/null
+++ b/board/freescale/ls1012ardb/eth.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+static inline void ls1012ardb_reset_phy(void)
+{
+   /* Through reset IO expander reset both RGMII and SGMII PHYs */
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
+   mdelay(10);
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
+   mdelay(10);
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+   mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+   static int init_done;
+   struct mii_dev *bus;
+   struct pfe_mdio_info mac_mdio_info;
+   struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+   if (!init_done) {
+   ls1012ardb_reset_phy();
+   mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+   mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+   bus = pfe_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+   init_done = 1;
+   }
+
+   pfe_set_mdio(priv->gemac_port,
+miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+
+   if (!priv->gemac_port) {
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   } else {
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_RGMII_TXID);
+   }
+   return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+   .pfe_eth_pdata_mac = {
+   .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+   .phy_interface = 0,
+   },
+
+   .pfe_ddr_addr = {
+   .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+   .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+   },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+   .pfe_eth_pdata_mac = {
+   .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+   .phy_interface = 1,
+   },
+
+   .pfe_ddr_addr = {
+   .ddr_pfe_baseaddr = (void *)CONFIG_DDR

[U-Boot] [PATCH v4 12/13] armv8: layerscape: csu: enable ns access to PFE registers

[Calvin Johnson]

Enable all types of non-secure access to PFE block registers.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
-Improved commit message to provide more description

 arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h 
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index f46f1d8..fe97a93 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -26,6 +26,7 @@ enum csu_cslx_ind {
CSU_CSLX_PCIE3_IO,
CSU_CSLX_USB3 = 20,
CSU_CSLX_USB2,
+   CSU_CSLX_PFE = 23,
CSU_CSLX_SERDES = 32,
CSU_CSLX_QDMA,
CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
 {CSU_CSLX_USB3, CSU_ALL_RW},
 {CSU_CSLX_USB2, CSU_ALL_RW},
+{CSU_CSLX_PFE, CSU_ALL_RW},
 {CSU_CSLX_SERDES, CSU_ALL_RW},
 {CSU_CSLX_QDMA, CSU_ALL_RW},
 {CSU_CSLX_LPUART2, CSU_ALL_RW},
-- 
2.7.4

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[U-Boot] [PATCH v4 13/13] configs: ls1012a: add pfe configuration for LS1012A

[Calvin Johnson]

Add configurations for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>
---

Changes in v4:
-Fix typo "ppfe stop"

Changes in v3:
-Move PFE macros to Kconfig
-Remove unused UTIL_PE_DISABLED config

Changes in v2:
-Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
-Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files

 configs/ls1012a2g5rdb_qspi_defconfig |  2 ++
 configs/ls1012afrdm_qspi_defconfig   |  2 ++
 configs/ls1012aqds_qspi_defconfig|  2 ++
 configs/ls1012ardb_qspi_defconfig|  2 ++
 drivers/net/Kconfig  |  1 +
 drivers/net/Makefile |  1 +
 drivers/net/pfe_eth/Kconfig  | 12 
 drivers/net/pfe_eth/Makefile | 12 
 include/configs/ls1012a2g5rdb.h  | 11 +--
 include/configs/ls1012a_common.h |  6 +++---
 include/configs/ls1012afrdm.h|  2 +-
 include/configs/ls1012ardb.h |  2 +-
 12 files changed, 40 insertions(+), 15 deletions(-)
 create mode 100644 drivers/net/pfe_eth/Kconfig
 create mode 100644 drivers/net/pfe_eth/Makefile

diff --git a/configs/ls1012a2g5rdb_qspi_defconfig 
b/configs/ls1012a2g5rdb_qspi_defconfig
index 26dcb1a..af676e2 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -31,7 +31,9 @@ CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1012afrdm_qspi_defconfig 
b/configs/ls1012afrdm_qspi_defconfig
index 1164361..c02e520 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -29,8 +29,10 @@ CONFIG_DM=y
 # CONFIG_MMC is not set
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012aqds_qspi_defconfig 
b/configs/ls1012aqds_qspi_defconfig
index 9fdf333..25470cb 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -36,8 +36,10 @@ CONFIG_SCSI_AHCI=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012ardb_qspi_defconfig 
b/configs/ls1012ardb_qspi_defconfig
index 4347263..1f62953 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -32,8 +32,10 @@ CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index de1947c..f589978 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,4 +1,5 @@
 source "drivers/net/phy/Kconfig"
+source "drivers/net/pfe_eth/Kconfig"
 
 config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4a16c62..95cb7bb 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -73,3 +73,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_FSL_PFE) += pfe_eth/
diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
new file mode 100644
index 000..a13b331
--- /dev/null
+++ b/drivers/net/pfe_eth/Kconfig
@@ -0,0 +1,12 @@
+menuconfig FSL_PFE
+   bool "NXP PFE Ethernet driver"
+   help
+ This driver provides support for NXP's Packet Forwarding Engine.
+
+if FSL_PFE
+
+config SYS_FSL_PFE_ADDR
+   hex "PFE base address"
+   default 0x0400
+
+endif
diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
new file mode 100644
index 000..6b5248f
--- /dev/null
+++ b/drivers/net/pfe_eth/Makefile
@@ -0,0 +1,12 @@
+# Copyright 2015-2016 Freescale Semiconductor, Inc.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:GPL-2.0+
+
+# Layerscape PFE driver
+obj-y += pfe_cmd.o \
+pfe_driver.o   \
+pfe_eth.o  \
+pfe_firmware.o \
+pfe_hw.o   \
+pfe_mdio.o
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 25df103..dbb0fcc 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -9,15 +9,6 @@
 
 #include "ls1012a_common.h"
 
-/* PFE Ethernet */
-#ifdef CONFIG_FSL_PFE
-#define EMAC1_PHY_ADDR  0x2
-#define EMAC2_PHY_ADDR  0x1
-#define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_AQUANTIA
-#endif
-
 /* DDR */
 #define CONFIG

[U-Boot] [PATCH v4 11/13] armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC

[Calvin Johnson]

1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4: None
Changes in v3:
-Cosmetic change

Changes in v2:
-Improved commit message to provide more description
-Replaced magic numbers with proper definitions

 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 23 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 10 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  3 +++
 3 files changed, 36 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b9f837d..18fb937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -612,6 +612,29 @@ int setup_chip_volt(void)
return 0;
 }
 
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+   u32 ecccr2;
+
+   out_be32(>pfeasbcr,
+in_be32(>pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+   out_be32(>pfebsbcr,
+in_be32(>pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+   /* CCI-400 QoS settings for PFE */
+   out_be32(>wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
+| SCFG_WR_QOS1_PFE2_QOS));
+   out_be32(>rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
+| SCFG_RD_QOS1_PFE2_QOS));
+
+   ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+   out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+ecccr2 | (unsigned int)DISABLE_PFE_ECC);
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d6f0c5b..af68af4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -205,6 +205,8 @@ struct sys_info {
 
 /* Device Configuration and Pin Control */
 #define DCFG_DCSR_PORCR1   0x0
+#define DCFG_DCSR_ECCCR2   0x524
+#define DISABLE_PFE_ECCBIT(13)
 
 struct ccsr_gur {
u32 porsr1; /* POR status 1 */
@@ -410,6 +412,14 @@ struct ccsr_gur {
 #define SCFG_PFEASBCR_ARSNPBIT(27)
 #define SCFG_PFEASBCR_AWSNPBIT(26)
 
+/* WR_QoS1 PFE bit definitions */
+#define SCFG_WR_QOS1_PFE1_QOS  GENMASK(27, 24)
+#define SCFG_WR_QOS1_PFE2_QOS  GENMASK(23, 20)
+
+/* RD_QoS1 PFE bit definitions */
+#define SCFG_RD_QOS1_PFE1_QOS  GENMASK(27, 24)
+#define SCFG_RD_QOS1_PFE2_QOS  GENMASK(23, 20)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u8 res_000[0x100-0x000];
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index cb760b5..d9bfddb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -127,6 +127,9 @@ void fsl_lsch2_early_init_f(void);
 int setup_chip_volt(void);
 /* Setup core vdd in unit mV */
 int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
 #endif
 
 void cpu_name(char *name);
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v4 07/13] board: freescale: ls1012afrdm: enable network support on ls1012afrdm

[Calvin Johnson]

This patch enables ethernet support for ls1012afrdm.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4:
-Compile pfe driver conditionally with CONFIG_FSL_PFE

Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Prefix CONFIG_PFE_ to appropriate macros

Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"

 board/freescale/ls1012afrdm/Kconfig   |  29 +++
 board/freescale/ls1012afrdm/Makefile  |   1 +
 board/freescale/ls1012afrdm/eth.c | 124 ++
 board/freescale/ls1012afrdm/ls1012afrdm.c |   5 --
 4 files changed, 154 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/ls1012afrdm/eth.c

diff --git a/board/freescale/ls1012afrdm/Kconfig 
b/board/freescale/ls1012afrdm/Kconfig
index 38bd91b..22d521b 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -12,6 +12,35 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1012afrdm"
 
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select PHYLIB
+   imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+
+config PFE_EMAC1_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012afrdm/Makefile 
b/board/freescale/ls1012afrdm/Makefile
index dbfa2ce..1e53c96 100644
--- a/board/freescale/ls1012afrdm/Makefile
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012afrdm.o
+obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/board/freescale/ls1012afrdm/eth.c 
b/board/freescale/ls1012afrdm/eth.c
new file mode 100644
index 000..cc6deb2
--- /dev/null
+++ b/board/freescale/ls1012afrdm/eth.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#define MASK_ETH_PHY_RST   0x0100
+
+static inline void ls1012afrdm_reset_phy(void)
+{
+   unsigned int val;
+   struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+
+   setbits_be32(>gpdir, MASK_ETH_PHY_RST);
+
+   val = in_be32(>gpdat);
+   setbits_be32(>gpdat, val & ~MASK_ETH_PHY_RST);
+   mdelay(10);
+
+   val = in_be32(>gpdat);
+   setbits_be32(>gpdat, val | MASK_ETH_PHY_RST);
+   mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+   static int init_done;
+   struct mii_dev *bus;
+   struct pfe_mdio_info mac_mdio_info;
+   struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+   if (!init_done) {
+   ls1012afrdm_reset_phy();
+
+   mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+   mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+   bus = pfe_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+
+   init_done = 1;
+   }
+
+   if (priv->gemac_port) {
+   mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+   mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+   bus = pfe_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+   }
+
+   pfe_set_mdio(priv->gemac_port,
+miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+   if (!priv->gemac_port)
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   else
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   return 0;
+}
+
+static struct pfe_eth_pdata 

[U-Boot] [PATCH v4 04/13] drivers: net: pfe_eth: provide pfe commands

[Calvin Johnson]

pfe_command provides command line support for several features that
support pfe, like starting or stopping the pfe, checking the health
of the processor engines and checking status of different units inside
pfe.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4: None
Changes in v3:
-Update header location to include/net/pfe_eth

Changes in v2:
-remove unused code under CONFIG_UTIL_PE_DISABLED
-remove unused code under CONFIG_PFE_WARN_WA

 drivers/net/pfe_eth/pfe_cmd.c | 497 ++
 1 file changed, 497 insertions(+)
 create mode 100644 drivers/net/pfe_eth/pfe_cmd.c

diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
new file mode 100644
index 000..822dc0f
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_cmd.c
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * @file
+ * @brief PFE utility commands
+ */
+
+#include 
+
+static inline void pfe_command_help(void)
+{
+   printf("Usage: pfe [pe | status | expt ] \n");
+}
+
+static void pfe_command_pe(int argc, char * const argv[])
+{
+   if (argc >= 3 && strcmp(argv[2], "pmem") == 0) {
+   if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+   int i;
+   int num;
+   int id;
+   u32 addr;
+   u32 size;
+   u32 val;
+
+   if (argc == 7) {
+   num = simple_strtoul(argv[6], NULL, 0);
+   } else if (argc == 6) {
+   num = 1;
+   } else {
+   printf("Usage: pfe pe pmem read   
[]\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   addr = simple_strtoul(argv[5], NULL, 16);
+   size = 4;
+
+   for (i = 0; i < num; i++, addr += 4) {
+   val = pe_pmem_read(id, addr, size);
+   val = be32_to_cpu(val);
+   if (!(i & 3))
+   printf("%08x: ", addr);
+   printf("%08x%s", val, i == num - 1 || (i & 3)
+  == 3 ? "\n" : " ");
+   }
+
+   } else {
+   printf("Usage: pfe pe pmem read \n");
+   }
+   } else if (argc >= 3 && strcmp(argv[2], "dmem") == 0) {
+   if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+   int i;
+   int num;
+   int id;
+   u32 addr;
+   u32 size;
+   u32 val;
+
+   if (argc == 7) {
+   num = simple_strtoul(argv[6], NULL, 0);
+   } else if (argc == 6) {
+   num = 1;
+   } else {
+   printf("Usage: pfe pe dmem read   
[]\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   addr = simple_strtoul(argv[5], NULL, 16);
+   size = 4;
+
+   for (i = 0; i < num; i++, addr += 4) {
+   val = pe_dmem_read(id, addr, size);
+   val = be32_to_cpu(val);
+   if (!(i & 3))
+   printf("%08x: ", addr);
+   printf("%08x%s", val, i == num - 1 || (i & 3)
+  == 3 ? "\n" : " ");
+   }
+
+   } else if (argc >= 4 && strcmp(argv[3], "write") == 0) {
+   int id;
+   u32 val;
+   u32 addr;
+   u32 size;
+
+   if (argc != 7) {
+   printf("Usage: pfe pe dmem write   
\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   val = simple_strtoul(argv[5], NULL, 16);
+   val = cpu_to_be32(val);
+   addr = simple_strtoul(argv[6], NULL, 16);
+  

[U-Boot] [PATCH v4 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds

[Calvin Johnson]

This patch enables ethernet support for ls1012aqds.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4:
-Compile pfe driver conditionally with CONFIG_FSL_PFE

Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Cosmetic changes

Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"

 board/freescale/ls1012aqds/Kconfig|  45 
 board/freescale/ls1012aqds/Makefile   |   1 +
 board/freescale/ls1012aqds/eth.c  | 309 ++
 board/freescale/ls1012aqds/ls1012aqds.c   |  97 +++-
 board/freescale/ls1012aqds/ls1012aqds_pfe.h   |  45 
 board/freescale/ls1012aqds/ls1012aqds_qixis.h |   2 +-
 6 files changed, 492 insertions(+), 7 deletions(-)
 create mode 100644 board/freescale/ls1012aqds/eth.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h

diff --git a/board/freescale/ls1012aqds/Kconfig 
b/board/freescale/ls1012aqds/Kconfig
index fc9250b..c0b12ed 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -12,6 +12,51 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1012aqds"
 
+
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select PHYLIB
+   imply PHY_VITESSE
+   imply PHY_REALTEK
+   imply PHY_AQUANTIA
+   imply PHYLIB_10G
+
+config PFE_RGMII_RESET_WA
+   def_bool y
+
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+
+config PFE_EMAC1_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1e
+
+config PFE_EMAC2_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+config PFE_SGMII_2500_PHY1_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+config PFE_SGMII_2500_PHY2_ADDR
+   hex "PFE DDR base address"
+   default 0x2
+
+endif
+
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012aqds/Makefile 
b/board/freescale/ls1012aqds/Makefile
index 0b813f9..5aba9ca 100644
--- a/board/freescale/ls1012aqds/Makefile
+++ b/board/freescale/ls1012aqds/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012aqds.o
+obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
new file mode 100644
index 000..f8026a2
--- /dev/null
+++ b/board/freescale/ls1012aqds/eth.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "../common/qixis.h"
+#include 
+#include 
+#include "ls1012aqds_qixis.h"
+
+#define EMI_NONE   0xFF
+#define EMI1_RGMII 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+static const char * const mdio_names[] = {
+   "NULL",
+   "LS1012AQDS_MDIO_RGMII",
+   "LS1012AQDS_MDIO_SLOT1",
+   "LS1012AQDS_MDIO_SLOT2",
+   "NULL",
+};
+
+static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
+{
+   return mdio_names[muxval];
+}
+
+struct ls1012aqds_mdio {
+   u8 muxval;
+   struct mii_dev *realbus;
+};
+
+static void ls1012aqds_mux_mdio(u8 muxval)
+{
+   u8 brdcfg4;
+
+   if (muxval < 7) {
+   brdcfg4 = QIXIS_READ(brdcfg[4]);
+   brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+   brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+   QIXIS_WRITE(brdcfg[4], brdcfg4);
+   }
+}
+
+static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+   int regnum)
+{
+   struct ls1012aqds_mdio *priv = bus->priv;
+
+   ls1012aqds_mux_mdio(priv->muxval);
+
+   return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+int regnum, u16 value)
+{
+   struct ls1012aqds_mdio *priv = bus->priv;
+
+   ls1012aqds_mux_mdio(priv->muxval);
+
+   return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1012aqds_mdio_reset(struct mii_dev *bus)
+{
+   struct ls1012aqds_mdio *priv = bus->priv;
+
+   

[U-Boot] [PATCH v4 05/13] drivers: net: pfe_eth: LS1012A PFE headers

[Calvin Johnson]

Contains all the pfe header files.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4: None
Changes in v3:
-Move pfe_eth header files to include/net/pfe_eth
-Use BIT macro wherever applicable

Changes in v2:
-Add pfe_rx_done to clear bd after packet processing
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Used BIT and GENMASK macros wherever applicable
-Removed generic definitions that pollutes namespace
-File names pfe.h renamed to pfe_hw.h to be more clear as it contains
 low level functions that directly access pfe hardware block
-Added pfe_dm_eth.h for new driver model

 include/dm/platform_data/pfe_dm_eth.h|  21 
 include/net/pfe_eth/pfe/cbus.h   |  77 +
 include/net/pfe_eth/pfe/cbus/bmu.h   |  40 +++
 include/net/pfe_eth/pfe/cbus/class_csr.h | 180 +++
 include/net/pfe_eth/pfe/cbus/emac.h  | 140 
 include/net/pfe_eth/pfe/cbus/gpi.h   |  62 +++
 include/net/pfe_eth/pfe/cbus/hif.h   |  68 
 include/net/pfe_eth/pfe/cbus/hif_nocpy.h |  40 +++
 include/net/pfe_eth/pfe/cbus/tmu_csr.h   | 148 +
 include/net/pfe_eth/pfe/cbus/util_csr.h  |  47 
 include/net/pfe_eth/pfe/pfe_hw.h | 163 
 include/net/pfe_eth/pfe_driver.h |  59 ++
 include/net/pfe_eth/pfe_eth.h| 104 ++
 include/net/pfe_eth/pfe_firmware.h   |  17 +++
 include/net/pfe_eth/pfe_mdio.h   |  13 +++
 15 files changed, 1179 insertions(+)
 create mode 100644 include/dm/platform_data/pfe_dm_eth.h
 create mode 100644 include/net/pfe_eth/pfe/cbus.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/bmu.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/class_csr.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/emac.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/gpi.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/hif.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/hif_nocpy.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/tmu_csr.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/util_csr.h
 create mode 100644 include/net/pfe_eth/pfe/pfe_hw.h
 create mode 100644 include/net/pfe_eth/pfe_driver.h
 create mode 100644 include/net/pfe_eth/pfe_eth.h
 create mode 100644 include/net/pfe_eth/pfe_firmware.h
 create mode 100644 include/net/pfe_eth/pfe_mdio.h

diff --git a/include/dm/platform_data/pfe_dm_eth.h 
b/include/dm/platform_data/pfe_dm_eth.h
new file mode 100644
index 000..7943c67
--- /dev/null
+++ b/include/dm/platform_data/pfe_dm_eth.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __PFE_DM_ETH_H__
+#define __PFE_DM_ETH_H__
+#include 
+
+struct pfe_ddr_address {
+   void *ddr_pfe_baseaddr;
+   unsigned long ddr_pfe_phys_baseaddr;
+};
+
+struct pfe_eth_pdata {
+   struct eth_pdata pfe_eth_pdata_mac;
+   struct pfe_ddr_address pfe_ddr_addr;
+};
+#endif /* __PFE_DM_ETH_H__ */
diff --git a/include/net/pfe_eth/pfe/cbus.h b/include/net/pfe_eth/pfe/cbus.h
new file mode 100644
index 000..002041c
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#include "cbus/emac.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+
+#define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR)
+
+/* PFE Control and Status Register Desciption */
+#define EMAC1_BASE_ADDR(CBUS_BASE_ADDR + 0x20)
+#define EGPI1_BASE_ADDR(CBUS_BASE_ADDR + 0x21)
+#define EMAC2_BASE_ADDR(CBUS_BASE_ADDR + 0x22)
+#define EGPI2_BASE_ADDR(CBUS_BASE_ADDR + 0x23)
+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x24)
+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x25)
+#define ARB_BASE_ADDR  (CBUS_BASE_ADDR + 0x26)
+#define DDR_CONFIG_BASE_ADDR   (CBUS_BASE_ADDR + 0x27)
+#define HIF_BASE_ADDR  (CBUS_BASE_ADDR + 0x28)
+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x29)
+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x30)
+#define LMEM_SIZE  0x1
+#define LMEM_END   (LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR  (CBUS_BASE_ADDR + 0x31)
+#define CLASS_CSR_BASE_ADDR(CBUS_BASE_ADDR + 0x32)
+#define HIF_NOCPY_BASE_ADDR(CBUS_BASE_ADDR + 0x35)
+#define UTIL_CSR_BA

[U-Boot] [PATCH v4 02/13] armv8: fsl-layerscape: Add support of GPIO structure

[Calvin Johnson]

From: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>

Layerscape Gen2 SoC supports GPIO registers to control GPIO
signals. Adding support of GPIO structure to access GPIO
registers.

Signed-off-by: Pratiyush Srivastava <pratiyush.srivast...@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>
Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1ff5cac..b195005 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -82,6 +82,11 @@
 #define QSPI0_BASE_ADDR(CONFIG_SYS_IMMR + 
0x0055)
 #define DSPI1_BASE_ADDR(CONFIG_SYS_IMMR + 
0x0110)
 
+#define GPIO1_BASE_ADDR(CONFIG_SYS_IMMR + 
0x130)
+#define GPIO2_BASE_ADDR(CONFIG_SYS_IMMR + 
0x131)
+#define GPIO3_BASE_ADDR(CONFIG_SYS_IMMR + 
0x132)
+#define GPIO4_BASE_ADDR(CONFIG_SYS_IMMR + 
0x133)
+
 #define LPUART_BASE(CONFIG_SYS_IMMR + 0x0195)
 
 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220)
@@ -591,6 +596,16 @@ struct ccsr_serdes {
u8  res_19a0[0x2000-0x19a0];/* from 0x19a0 to 0x1fff */
 };
 
+struct ccsr_gpio {
+   u32 gpdir;
+   u32 gpodr;
+   u32 gpdat;
+   u32 gpier;
+   u32 gpimr;
+   u32 gpicr;
+   u32 gpibe;
+};
+
 /* MMU 500 */
 #define SMMU_SCR0  (SMMU_BASE + 0x0)
 #define SMMU_SCR1  (SMMU_BASE + 0x4)
-- 
2.7.4

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[U-Boot] [PATCH v4 03/13] drivers: net: pfe_eth: LS1012A PFE driver introduction

[Calvin Johnson]

This patch adds PFE driver to U-Boot

Following are the main driver files:-
pfe_hw.c: provides low level helper functions to initialize PFE
internal processor engines and other hardware blocks
pfe_driver.c: provides initialization functions
and packet send and receive functions
pfe_eth.c: provides high level gemac initialization functions
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.
pfe_mdio.c: provides functions to initialize phy and mdio.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v4: None
Changes in v3:
-Update header location to include/net/pfe_eth
-Replace EMACX_PHY_ADDR with CONFIG_PFE_EMACX_PHY_ADDR

Changes in v2:
-fix RGMII TX-delay issue
-add pfe_rx_done to clear bd after packet processing
-use writel/readl to access hw bds
-cleanup typos and indent
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Consolidate code in pfe_lib_init
-Corrected typo receive
-Magic numbers replaced with proper definitions
-File names pfe.c renamed to pfe_hw.c to be more clear as it contains
 low level functions that directly access pfe hardware block.
-MDIO related code is also moved from pfe_eth.c to a new file
 pfe_mdio.c.

 drivers/net/pfe_eth/pfe_driver.c   | 643 
 drivers/net/pfe_eth/pfe_eth.c  | 297 +++
 drivers/net/pfe_eth/pfe_firmware.c | 230 +
 drivers/net/pfe_eth/pfe_hw.c   | 999 +
 drivers/net/pfe_eth/pfe_mdio.c | 291 +++
 5 files changed, 2460 insertions(+)
 create mode 100644 drivers/net/pfe_eth/pfe_driver.c
 create mode 100644 drivers/net/pfe_eth/pfe_eth.c
 create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
 create mode 100644 drivers/net/pfe_eth/pfe_hw.c
 create mode 100644 drivers/net/pfe_eth/pfe_mdio.c

diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
new file mode 100644
index 000..a9991f5
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_driver.c
@@ -0,0 +1,643 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+static struct tx_desc_s *g_tx_desc;
+static struct rx_desc_s *g_rx_desc;
+
+/*
+ * HIF Rx interface function
+ * Reads the rx descriptor from the current location (rx_to_read).
+ * - If the descriptor has a valid data/pkt, then get the data pointer
+ * - check for the input rx phy number
+ * - increment the rx data pointer by pkt_head_room_size
+ * - decrement the data length by pkt_head_room_size
+ * - handover the packet to caller.
+ *
+ * @param[out] pkt_ptr - Pointer to store rx packet
+ * @param[out] phy_port - Pointer to store recv phy port
+ *
+ * @return -1 if no packet, else return length of packet.
+ */
+int pfe_recv(uchar **pkt_ptr, int *phy_port)
+{
+   struct rx_desc_s *rx_desc = g_rx_desc;
+   struct buf_desc *bd;
+   int len = 0;
+
+   struct hif_header_s *hif_header;
+
+   bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+   if (readl(>ctrl) & BD_CTRL_DESC_EN)
+   return len; /* No pending Rx packet */
+
+   /* this len include hif_header(8 bytes) */
+   len = readl(>ctrl) & 0x;
+
+   hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(>data));
+
+   /* Get the receive port info from the packet */
+   debug("Pkt received:");
+   debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
+ hif_header, len, hif_header->port_no, readl(>status));
+#ifdef DEBUG
+   {
+   int i;
+   unsigned char *p = (unsigned char *)hif_header;
+
+   for (i = 0; i < len; i++) {
+   if (!(i % 16))
+   printf("\n");
+   printf(" %02x", p[i]);
+   }
+   printf("\n");
+   }
+#endif
+
+   *pkt_ptr = (uchar *)(hif_header + 1);
+   *phy_port = hif_header->port_no;
+   len -= sizeof(struct hif_header_s);
+
+   return len;
+}
+
+/*
+ * HIF function to check the Rx done
+ * This function will check the rx done indication of the current rx_to_read
+ * locations
+ * if success, moves the rx_to_read to next location.
+ */
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+   struct rx_desc_s *rx_desc = g_rx_desc;
+   struct buf_desc *bd;
+
+   debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
+ rx_desc->rx_to_read);
+
+   bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+   /* reset the control field */
+   writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
+   | BD_CTRL_DIR), >ctrl);
+   writel(0, >status);
+
+   debug(

[U-Boot] [PATCH v4 01/13] drivers: net: phy: Fix aquantia compilation with DM

[Calvin Johnson]

With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.

drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
  phydev->dev->name);
 ^~

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/phy/aquantia.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ad12f6d..6678147 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -7,6 +7,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 
 #ifndef CONFIG_PHYLIB_10G
-- 
2.7.4

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[U-Boot] [PATCH v4 00/13] LS1012A PFE driver patch series

[Calvin Johnson]

This patch series introduces U-Boot support for NXP's LS1012A Packet
Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
engine to provide high performance Ethernet interfaces. The device
includes two Ethernet ports.


Changes in v4:
-Compile pfe driver conditionally with CONFIG_FSL_PFE
-Compile pfe driver conditionally with CONFIG_FSL_PFE
-Compile pfe driver conditionally with CONFIG_FSL_PFE
-Fix typo "ppfe stop"

Changes in v3:
-Update header location to include/net/pfe_eth
-Replace EMACX_PHY_ADDR with CONFIG_PFE_EMACX_PHY_ADDR
-Update header location to include/net/pfe_eth
-Move pfe_eth header files to include/net/pfe_eth
-Use BIT macro wherever applicable
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Cosmetic changes
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Prefix CONFIG_PFE_ to appropriate macros
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Prefix CONFIG_PFE_ to appropriate macros
-Indent properly
-Use BIT macro wherever applicable
-Cosmetic change
-Move PFE macros to Kconfig
-Remove unused UTIL_PE_DISABLED config

Changes in v2:
-fix RGMII TX-delay issue
-add pfe_rx_done to clear bd after packet processing
-use writel/readl to access hw bds
-cleanup typos and indent
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Consolidate code in pfe_lib_init
-Corrected typo receive
-Magic numbers replaced with proper definitions
-File names pfe.c renamed to pfe_hw.c to be more clear as it contains
 low level functions that directly access pfe hardware block.
-MDIO related code is also moved from pfe_eth.c to a new file
 pfe_mdio.c.
-remove unused code under CONFIG_UTIL_PE_DISABLED
-remove unused code under CONFIG_PFE_WARN_WA
-Add pfe_rx_done to clear bd after packet processing
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Used BIT and GENMASK macros wherever applicable
-Removed generic definitions that pollutes namespace
-File names pfe.h renamed to pfe_hw.h to be more clear as it contains
 low level functions that directly access pfe hardware block
-Added pfe_dm_eth.h for new driver model
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
-New patch added to series to enable ethernet support for
ls1012a2g5rdb
-Improved commit message to provide more description
-Replaced magic numbers with proper definitions
-Improved commit message to provide more description
-Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
-Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files

Calvin Johnson (12):
  drivers: net: phy: Fix aquantia compilation with DM
  drivers: net: pfe_eth: LS1012A PFE driver introduction
  drivers: net: pfe_eth: provide pfe commands
  drivers: net: pfe_eth: LS1012A PFE headers
  board: freescale: ls1012aqds: enable network support on ls1012aqds
  board: freescale: ls1012afrdm: enable network support on ls1012afrdm
  board: freescale: ls1012ardb: enable network support on ls1012ardb
  board: freescale: ls1012a2g5rdb: enable network support on
ls1012a2g5rdb
  armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
  armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
  armv8: layerscape: csu: enable ns access to PFE registers
  configs: ls1012a: add pfe configuration for LS1012A

Prabhakar Kushwaha (1):
  armv8: fsl-layerscape: Add support of GPIO structure

 arch/arm/cpu/armv8/fsl-layerscape/soc.c|  23 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  63 +-
 .../include/asm/arch-fsl-layerscape/ns_access.h|   2 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   3 +
 board/freescale/ls1012afrdm/Kconfig|  29 +
 board/freescale/ls1012afrdm/Makefile   |   1 +
 board/freescale/ls1012afrdm/eth.c  | 124 +++
 board/freescale/ls1012afrdm/ls1012afrdm.c  |   5 -
 board/freescale/ls1012aqds/Kconfig |  45 +
 board/freescale/ls1012aqds/Makefile|   1 +
 board/freescale/ls1012aqds/eth.c   | 309 +++
 board/freescale/ls1012aqds/ls1012aqds.c|  97 +-
 board/freescale/ls1012aqds/ls1012aqds_pfe.h|  45 +
 board/freescale/ls1012aqds/ls1012aqds_qixis.h  |   2 +-
 board/freescale/ls1012ardb/Kconfig |  59 ++
 board/freescale/ls1012ardb/Makefile|   1 +
 board/freescale/ls1012ardb/eth.c   | 135 +++
 board/freescale/ls1012ardb/ls1012ardb.c|   4 -
 configs/ls1012a2g5rdb_qspi_defconfig   |   2 +
 configs/ls1012afrdm_qspi_defconfig |   2 +
 configs/ls1012aqds_qspi_defconfig  

Re: [U-Boot] [PATCH v3 00/13] LS1012A PFE driver patch series

[Calvin Johnson]

Joe,

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Joe
> Hershberger
> Sent: Wednesday, March 7, 2018 1:09 AM
> To: York Sun <york@nxp.com>
> Cc: Joe Hershberger <joe.hershber...@ni.com>; Bhaskar Upadhaya
> <bhaskar.upadh...@nxp.com>; Anji Jagarlmudi <anji.jagarlm...@nxp.com>; u-
> b...@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v3 00/13] LS1012A PFE driver patch series
> 
> On Tue, Mar 6, 2018 at 10:28 AM, York Sun <york....@nxp.com> wrote:
> > On 03/06/2018 06:28 AM, Calvin Johnson wrote:
> >> Hi Joe,
> >>
> >> Thanks for reviewing all the patches.
> >
> > Joe,
> >
> > Do you want to bring them in, or leave them to me?
> 
> I'll bring them in through my tree.
> 
> Calvin,
> 
> It seems we have an issue with the series.  Please have a look:
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-
> ci.org%2Fjhershbe%2Fu-
> boot%2Fbuilds%2F349955957=02%7C01%7Ccalvin.johnson%40nxp.com%7C
> c9c0274c79314e401a3808d58399f600%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
> 0%7C0%7C636559619645909270=JBjuSIsksYnir2qNkMqzJqjlkBFSrpF62nS5B
> FcvU7M%3D=0

Sorry, I had missed ls1012ardb_qspi_SECURE_BOOT_defconfig and this is causing 
the problem.
Working towards fixing this.

Thanks
Calvin
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Re: [U-Boot] [PATCH v3 00/13] LS1012A PFE driver patch series

[Calvin Johnson]

Hi Joe,

Thanks for reviewing all the patches.

> -Original Message-
> From: Calvin Johnson [mailto:calvin.john...@nxp.com]
> Sent: Saturday, March 3, 2018 11:14 PM
> To: u-boot@lists.denx.de; Joe Hershberger <joe.hershber...@ni.com>
> Cc: Anji Jagarlmudi <anji.jagarlm...@nxp.com>; York Sun <york....@nxp.com>;
> Calvin Johnson <calvin.john...@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com>; Bhaskar Upadhaya
> <bhaskar.upadh...@nxp.com>
> Subject: [PATCH v3 00/13] LS1012A PFE driver patch series
> 
> 
> This patch series introduces U-Boot support for NXP's LS1012A Packet
> Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
> engine to provide high performance Ethernet interfaces. The device
> includes two Ethernet ports.
 

Regards
Calvin

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[U-Boot] [PATCH v3 13/13] configs: ls1012a: add pfe configuration for LS1012A

[Calvin Johnson]

Add configurations for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---

Changes in v3:
-Move PFE macros to Kconfig
-Remove unused UTIL_PE_DISABLED config

Changes in v2:
-Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
-Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files

 configs/ls1012a2g5rdb_qspi_defconfig |  2 ++
 configs/ls1012afrdm_qspi_defconfig   |  2 ++
 configs/ls1012aqds_qspi_defconfig|  2 ++
 configs/ls1012ardb_qspi_defconfig|  2 ++
 drivers/net/Kconfig  |  1 +
 drivers/net/Makefile |  1 +
 drivers/net/pfe_eth/Kconfig  | 12 
 drivers/net/pfe_eth/Makefile | 12 
 include/configs/ls1012a2g5rdb.h  | 11 +--
 include/configs/ls1012a_common.h |  6 +++---
 include/configs/ls1012afrdm.h|  2 +-
 include/configs/ls1012ardb.h |  2 +-
 12 files changed, 40 insertions(+), 15 deletions(-)
 create mode 100644 drivers/net/pfe_eth/Kconfig
 create mode 100644 drivers/net/pfe_eth/Makefile

diff --git a/configs/ls1012a2g5rdb_qspi_defconfig 
b/configs/ls1012a2g5rdb_qspi_defconfig
index 26dcb1a..af676e2 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -31,7 +31,9 @@ CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1012afrdm_qspi_defconfig 
b/configs/ls1012afrdm_qspi_defconfig
index 1164361..c02e520 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -29,8 +29,10 @@ CONFIG_DM=y
 # CONFIG_MMC is not set
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012aqds_qspi_defconfig 
b/configs/ls1012aqds_qspi_defconfig
index 9fdf333..25470cb 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -36,8 +36,10 @@ CONFIG_SCSI_AHCI=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012ardb_qspi_defconfig 
b/configs/ls1012ardb_qspi_defconfig
index 4347263..1f62953 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -32,8 +32,10 @@ CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index de1947c..f589978 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,4 +1,5 @@
 source "drivers/net/phy/Kconfig"
+source "drivers/net/pfe_eth/Kconfig"
 
 config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4a16c62..95cb7bb 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -73,3 +73,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_FSL_PFE) += pfe_eth/
diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
new file mode 100644
index 000..a13b331
--- /dev/null
+++ b/drivers/net/pfe_eth/Kconfig
@@ -0,0 +1,12 @@
+menuconfig FSL_PFE
+   bool "NXP PFE Ethernet driver"
+   help
+ This driver provides support for NXP's Packet Forwarding Engine.
+
+if FSL_PFE
+
+config SYS_FSL_PFE_ADDR
+   hex "PFE base address"
+   default 0x0400
+
+endif
diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
new file mode 100644
index 000..6b5248f
--- /dev/null
+++ b/drivers/net/pfe_eth/Makefile
@@ -0,0 +1,12 @@
+# Copyright 2015-2016 Freescale Semiconductor, Inc.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:GPL-2.0+
+
+# Layerscape PFE driver
+obj-y += pfe_cmd.o \
+pfe_driver.o   \
+pfe_eth.o  \
+pfe_firmware.o \
+pfe_hw.o   \
+pfe_mdio.o
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 25df103..dbb0fcc 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -9,15 +9,6 @@
 
 #include "ls1012a_common.h"
 
-/* PFE Ethernet */
-#ifdef CONFIG_FSL_PFE
-#define EMAC1_PHY_ADDR  0x2
-#define EMAC2_PHY_ADDR  0x1
-#define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_AQUANTIA
-#endif
-
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   1
@@ -110,7 +101,7 @@
 
 #unde

[U-Boot] [PATCH v3 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure

[Calvin Johnson]

SoC specific PFE macros are defined and structure ccsr_scfg
is updated with members defined for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>

---

Changes in v3:
-Use BIT macro wherever applicable

Changes in v2: None

 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 38 --
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b195005..d6f0c5b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -395,6 +395,21 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
 #define SCFG_SNPCNFGCR_SATAWRSNP   0x0040
 
+/* RGMIIPCR bit definitions*/
+#define SCFG_RGMIIPCR_EN_AUTO  BIT(3)
+#define SCFG_RGMIIPCR_SETSP_1000M  BIT(2)
+#define SCFG_RGMIIPCR_SETSP_100M   0
+#define SCFG_RGMIIPCR_SETSP_10MBIT(1)
+#define SCFG_RGMIIPCR_SETFDBIT(0)
+
+/* PFEASBCR bit definitions */
+#define SCFG_PFEASBCR_ARCACHE0 BIT(31)
+#define SCFG_PFEASBCR_AWCACHE0 BIT(30)
+#define SCFG_PFEASBCR_ARCACHE1 BIT(29)
+#define SCFG_PFEASBCR_AWCACHE1 BIT(28)
+#define SCFG_PFEASBCR_ARSNPBIT(27)
+#define SCFG_PFEASBCR_AWSNPBIT(26)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u8 res_000[0x100-0x000];
@@ -412,7 +427,12 @@ struct ccsr_scfg {
u8 res_140[0x158-0x140];
u32 altcbar;
u32 qspi_cfg;
-   u8 res_160[0x180-0x160];
+   u8 res_160[0x164 - 0x160];
+   u32 wr_qos1;
+   u32 wr_qos2;
+   u32 rd_qos1;
+   u32 rd_qos2;
+   u8 res_174[0x180 - 0x174];
u32 dmamcr;
u8 res_184[0x188-0x184];
u32 gic_align;
@@ -443,7 +463,21 @@ struct ccsr_scfg {
u32 usb_refclk_selcr1;
u32 usb_refclk_selcr2;
u32 usb_refclk_selcr3;
-   u8 res_424[0x600-0x424];
+   u8 res_424[0x434 - 0x424];
+   u32 rgmiipcr;
+   u32 res_438;
+   u32 rgmiipsr;
+   u32 pfepfcssr1;
+   u32 pfeintencr1;
+   u32 pfepfcssr2;
+   u32 pfeintencr2;
+   u32 pfeerrcr;
+   u32 pfeeerrintencr;
+   u32 pfeasbcr;
+   u32 pfebsbcr;
+   u8 res_460[0x484 - 0x460];
+   u32 mdioselcr;
+   u8 res_468[0x600 - 0x488];
u32 scratchrw[4];
u8 res_610[0x680-0x610];
u32 corebcr;
-- 
2.7.4

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[U-Boot] [PATCH v3 12/13] armv8: layerscape: csu: enable ns access to PFE registers

[Calvin Johnson]

Enable all types of non-secure access to PFE block registers.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v3: None
Changes in v2:
-Improved commit message to provide more description

 arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h 
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index f46f1d8..fe97a93 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -26,6 +26,7 @@ enum csu_cslx_ind {
CSU_CSLX_PCIE3_IO,
CSU_CSLX_USB3 = 20,
CSU_CSLX_USB2,
+   CSU_CSLX_PFE = 23,
CSU_CSLX_SERDES = 32,
CSU_CSLX_QDMA,
CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
 {CSU_CSLX_USB3, CSU_ALL_RW},
 {CSU_CSLX_USB2, CSU_ALL_RW},
+{CSU_CSLX_PFE, CSU_ALL_RW},
 {CSU_CSLX_SERDES, CSU_ALL_RW},
 {CSU_CSLX_QDMA, CSU_ALL_RW},
 {CSU_CSLX_LPUART2, CSU_ALL_RW},
-- 
2.7.4

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[U-Boot] [PATCH v3 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds

[Calvin Johnson]

This patch enables ethernet support for ls1012aqds.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>

---

Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Cosmetic changes

Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"

 board/freescale/ls1012aqds/Kconfig|  45 
 board/freescale/ls1012aqds/Makefile   |   1 +
 board/freescale/ls1012aqds/eth.c  | 309 ++
 board/freescale/ls1012aqds/ls1012aqds.c   |  97 +++-
 board/freescale/ls1012aqds/ls1012aqds_pfe.h   |  45 
 board/freescale/ls1012aqds/ls1012aqds_qixis.h |   2 +-
 6 files changed, 492 insertions(+), 7 deletions(-)
 create mode 100644 board/freescale/ls1012aqds/eth.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h

diff --git a/board/freescale/ls1012aqds/Kconfig 
b/board/freescale/ls1012aqds/Kconfig
index fc9250b..c0b12ed 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -12,6 +12,51 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1012aqds"
 
+
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select PHYLIB
+   imply PHY_VITESSE
+   imply PHY_REALTEK
+   imply PHY_AQUANTIA
+   imply PHYLIB_10G
+
+config PFE_RGMII_RESET_WA
+   def_bool y
+
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+
+config PFE_EMAC1_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1e
+
+config PFE_EMAC2_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+config PFE_SGMII_2500_PHY1_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+config PFE_SGMII_2500_PHY2_ADDR
+   hex "PFE DDR base address"
+   default 0x2
+
+endif
+
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012aqds/Makefile 
b/board/freescale/ls1012aqds/Makefile
index 0b813f9..b18494a 100644
--- a/board/freescale/ls1012aqds/Makefile
+++ b/board/freescale/ls1012aqds/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012aqds.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
new file mode 100644
index 000..f8026a2
--- /dev/null
+++ b/board/freescale/ls1012aqds/eth.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "../common/qixis.h"
+#include 
+#include 
+#include "ls1012aqds_qixis.h"
+
+#define EMI_NONE   0xFF
+#define EMI1_RGMII 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+static const char * const mdio_names[] = {
+   "NULL",
+   "LS1012AQDS_MDIO_RGMII",
+   "LS1012AQDS_MDIO_SLOT1",
+   "LS1012AQDS_MDIO_SLOT2",
+   "NULL",
+};
+
+static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
+{
+   return mdio_names[muxval];
+}
+
+struct ls1012aqds_mdio {
+   u8 muxval;
+   struct mii_dev *realbus;
+};
+
+static void ls1012aqds_mux_mdio(u8 muxval)
+{
+   u8 brdcfg4;
+
+   if (muxval < 7) {
+   brdcfg4 = QIXIS_READ(brdcfg[4]);
+   brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+   brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+   QIXIS_WRITE(brdcfg[4], brdcfg4);
+   }
+}
+
+static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+   int regnum)
+{
+   struct ls1012aqds_mdio *priv = bus->priv;
+
+   ls1012aqds_mux_mdio(priv->muxval);
+
+   return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+int regnum, u16 value)
+{
+   struct ls1012aqds_mdio *priv = bus->priv;
+
+   ls1012aqds_mux_mdio(priv->muxval);
+
+   return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1012aqds_mdio_reset(struct mii_dev *bus)
+{
+   struct ls1012aqds_mdio *priv = bus->priv;
+
+   if (priv->realbus->reset)
+   return priv->realbus->reset(priv->realbus);
+   else
+   

[U-Boot] [PATCH v3 11/13] armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC

[Calvin Johnson]

1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v3:
-Cosmetic change

Changes in v2:
-Improved commit message to provide more description
-Replaced magic numbers with proper definitions

 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 23 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 10 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  3 +++
 3 files changed, 36 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b9f837d..18fb937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -612,6 +612,29 @@ int setup_chip_volt(void)
return 0;
 }
 
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+   u32 ecccr2;
+
+   out_be32(>pfeasbcr,
+in_be32(>pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+   out_be32(>pfebsbcr,
+in_be32(>pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+   /* CCI-400 QoS settings for PFE */
+   out_be32(>wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
+| SCFG_WR_QOS1_PFE2_QOS));
+   out_be32(>rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
+| SCFG_RD_QOS1_PFE2_QOS));
+
+   ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+   out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+ecccr2 | (unsigned int)DISABLE_PFE_ECC);
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d6f0c5b..af68af4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -205,6 +205,8 @@ struct sys_info {
 
 /* Device Configuration and Pin Control */
 #define DCFG_DCSR_PORCR1   0x0
+#define DCFG_DCSR_ECCCR2   0x524
+#define DISABLE_PFE_ECCBIT(13)
 
 struct ccsr_gur {
u32 porsr1; /* POR status 1 */
@@ -410,6 +412,14 @@ struct ccsr_gur {
 #define SCFG_PFEASBCR_ARSNPBIT(27)
 #define SCFG_PFEASBCR_AWSNPBIT(26)
 
+/* WR_QoS1 PFE bit definitions */
+#define SCFG_WR_QOS1_PFE1_QOS  GENMASK(27, 24)
+#define SCFG_WR_QOS1_PFE2_QOS  GENMASK(23, 20)
+
+/* RD_QoS1 PFE bit definitions */
+#define SCFG_RD_QOS1_PFE1_QOS  GENMASK(27, 24)
+#define SCFG_RD_QOS1_PFE2_QOS  GENMASK(23, 20)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u8 res_000[0x100-0x000];
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index cb760b5..d9bfddb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -127,6 +127,9 @@ void fsl_lsch2_early_init_f(void);
 int setup_chip_volt(void);
 /* Setup core vdd in unit mV */
 int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
 #endif
 
 void cpu_name(char *name);
-- 
2.7.4

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[U-Boot] [PATCH v3 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb

[Calvin Johnson]

This patch enables ethernet support for ls1012a2g5rdb.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Bhaskar Upadhaya <bhaskar.upadh...@nxp.com>

---

Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Prefix CONFIG_PFE_ to appropriate macros
-Indent properly

Changes in v2:
-New patch added to series to enable ethernet support for
ls1012a2g5rdb

 board/freescale/ls1012ardb/Kconfig | 30 +
 board/freescale/ls1012ardb/eth.c   | 45 +++---
 2 files changed, 67 insertions(+), 8 deletions(-)

diff --git a/board/freescale/ls1012ardb/Kconfig 
b/board/freescale/ls1012ardb/Kconfig
index af35a01..493d477 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -59,6 +59,36 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 default "ls1012a2g5rdb"
 
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select PHYLIB
+   imply CONFIG_PHYLIB_10G
+   imply CONFIG_PHY_AQUANTIA
+
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+
+config PFE_EMAC1_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index e6379a3..8e6cd0a 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -26,6 +26,7 @@
 
 static inline void ls1012ardb_reset_phy(void)
 {
+#ifdef CONFIG_TARGET_LS1012ARDB
/* Through reset IO expander reset both RGMII and SGMII PHYs */
i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
@@ -34,6 +35,7 @@ static inline void ls1012ardb_reset_phy(void)
mdelay(10);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
mdelay(50);
+#endif
 }
 
 int pfe_eth_board_init(struct udevice *dev)
@@ -42,6 +44,11 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev);
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+   int srds_s1 = in_be32(>rcwsr[4]) &
+   FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+   srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
if (!init_done) {
ls1012ardb_reset_phy();
@@ -59,14 +66,36 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_mdio(priv->gemac_port,
 miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
 
-   if (!priv->gemac_port) {
-   /* MAC1 */
-   pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
-PHY_INTERFACE_MODE_SGMII);
-   } else {
-   /* MAC2 */
-   pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
-PHY_INTERFACE_MODE_RGMII_TXID);
+   switch (srds_s1) {
+   case 0x3508:
+   if (!priv->gemac_port) {
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   } else {
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_RGMII_TXID);
+   }
+   break;
+   case 0x2208:
+   if (!priv->gemac_port) {
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII_2500);
+   } else {
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII_2500);
+   }
+   break;
+   default:
+   printf("unsupported SerDes PRCTL= %d\n", srds_s1);
+   break;
}
return 0;
 }
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 07/13] board: freescale: ls1012afrdm: enable network support on ls1012afrdm

[Calvin Johnson]

This patch enables ethernet support for ls1012afrdm.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Prefix CONFIG_PFE_ to appropriate macros

Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"

 board/freescale/ls1012afrdm/Kconfig   |  29 +++
 board/freescale/ls1012afrdm/Makefile  |   1 +
 board/freescale/ls1012afrdm/eth.c | 124 ++
 board/freescale/ls1012afrdm/ls1012afrdm.c |   5 --
 4 files changed, 154 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/ls1012afrdm/eth.c

diff --git a/board/freescale/ls1012afrdm/Kconfig 
b/board/freescale/ls1012afrdm/Kconfig
index 38bd91b..22d521b 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -12,6 +12,35 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1012afrdm"
 
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select PHYLIB
+   imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+
+config PFE_EMAC1_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012afrdm/Makefile 
b/board/freescale/ls1012afrdm/Makefile
index dbfa2ce..1364f22 100644
--- a/board/freescale/ls1012afrdm/Makefile
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012afrdm.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012afrdm/eth.c 
b/board/freescale/ls1012afrdm/eth.c
new file mode 100644
index 000..cc6deb2
--- /dev/null
+++ b/board/freescale/ls1012afrdm/eth.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#define MASK_ETH_PHY_RST   0x0100
+
+static inline void ls1012afrdm_reset_phy(void)
+{
+   unsigned int val;
+   struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+
+   setbits_be32(>gpdir, MASK_ETH_PHY_RST);
+
+   val = in_be32(>gpdat);
+   setbits_be32(>gpdat, val & ~MASK_ETH_PHY_RST);
+   mdelay(10);
+
+   val = in_be32(>gpdat);
+   setbits_be32(>gpdat, val | MASK_ETH_PHY_RST);
+   mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+   static int init_done;
+   struct mii_dev *bus;
+   struct pfe_mdio_info mac_mdio_info;
+   struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+   if (!init_done) {
+   ls1012afrdm_reset_phy();
+
+   mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+   mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+   bus = pfe_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+
+   init_done = 1;
+   }
+
+   if (priv->gemac_port) {
+   mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+   mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+   bus = pfe_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+   }
+
+   pfe_set_mdio(priv->gemac_port,
+miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+   if (!priv->gemac_port)
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   else
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port,
+CONFIG_PFE_EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+   .pfe_eth_pdata_mac = {
+   .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+ 

[U-Boot] [PATCH v3 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb

[Calvin Johnson]

This patch enables ethernet support for ls1012ardb.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth

Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"

 board/freescale/ls1012ardb/Kconfig  |  29 +
 board/freescale/ls1012ardb/Makefile |   1 +
 board/freescale/ls1012ardb/eth.c| 106 
 board/freescale/ls1012ardb/ls1012ardb.c |   4 --
 include/configs/ls1012ardb.h|   4 ++
 5 files changed, 140 insertions(+), 4 deletions(-)
 create mode 100644 board/freescale/ls1012ardb/eth.c

diff --git a/board/freescale/ls1012ardb/Kconfig 
b/board/freescale/ls1012ardb/Kconfig
index d13b08e..af35a01 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -12,6 +12,35 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1012ardb"
 
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select PHYLIB
+   imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+
+config PFE_EMAC1_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+   hex "PFE DDR base address"
+   default 0x1
+
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012ardb/Makefile 
b/board/freescale/ls1012ardb/Makefile
index 05fa9d9..bd80ce5 100644
--- a/board/freescale/ls1012ardb/Makefile
+++ b/board/freescale/ls1012ardb/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012ardb.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
new file mode 100644
index 000..e6379a3
--- /dev/null
+++ b/board/freescale/ls1012ardb/eth.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+static inline void ls1012ardb_reset_phy(void)
+{
+   /* Through reset IO expander reset both RGMII and SGMII PHYs */
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
+   mdelay(10);
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
+   mdelay(10);
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+   mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+   static int init_done;
+   struct mii_dev *bus;
+   struct pfe_mdio_info mac_mdio_info;
+   struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+   if (!init_done) {
+   ls1012ardb_reset_phy();
+   mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+   mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+   bus = pfe_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+   init_done = 1;
+   }
+
+   pfe_set_mdio(priv->gemac_port,
+miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+
+   if (!priv->gemac_port) {
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   } else {
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_RGMII_TXID);
+   }
+   return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+   .pfe_eth_pdata_mac = {
+   .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+   .phy_interface = 0,
+   },
+
+   .pfe_ddr_addr = {
+   .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+   .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+   },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+   .pfe_eth_pdata_mac = {
+   .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+   .phy_interface = 1,
+   },
+
+   .pfe_ddr_addr = {
+   .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+   .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+   }

[U-Boot] [PATCH v3 05/13] drivers: net: pfe_eth: LS1012A PFE headers

[Calvin Johnson]

Contains all the pfe header files.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>

---

Changes in v3:
-Move pfe_eth header files to include/net/pfe_eth
-Use BIT macro wherever applicable

Changes in v2:
-Add pfe_rx_done to clear bd after packet processing
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Used BIT and GENMASK macros wherever applicable
-Removed generic definitions that pollutes namespace
-File names pfe.h renamed to pfe_hw.h to be more clear as it contains
 low level functions that directly access pfe hardware block
-Added pfe_dm_eth.h for new driver model

 include/dm/platform_data/pfe_dm_eth.h|  21 
 include/net/pfe_eth/pfe/cbus.h   |  77 +
 include/net/pfe_eth/pfe/cbus/bmu.h   |  40 +++
 include/net/pfe_eth/pfe/cbus/class_csr.h | 180 +++
 include/net/pfe_eth/pfe/cbus/emac.h  | 140 
 include/net/pfe_eth/pfe/cbus/gpi.h   |  62 +++
 include/net/pfe_eth/pfe/cbus/hif.h   |  68 
 include/net/pfe_eth/pfe/cbus/hif_nocpy.h |  40 +++
 include/net/pfe_eth/pfe/cbus/tmu_csr.h   | 148 +
 include/net/pfe_eth/pfe/cbus/util_csr.h  |  47 
 include/net/pfe_eth/pfe/pfe_hw.h | 163 
 include/net/pfe_eth/pfe_driver.h |  59 ++
 include/net/pfe_eth/pfe_eth.h| 104 ++
 include/net/pfe_eth/pfe_firmware.h   |  17 +++
 include/net/pfe_eth/pfe_mdio.h   |  13 +++
 15 files changed, 1179 insertions(+)
 create mode 100644 include/dm/platform_data/pfe_dm_eth.h
 create mode 100644 include/net/pfe_eth/pfe/cbus.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/bmu.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/class_csr.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/emac.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/gpi.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/hif.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/hif_nocpy.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/tmu_csr.h
 create mode 100644 include/net/pfe_eth/pfe/cbus/util_csr.h
 create mode 100644 include/net/pfe_eth/pfe/pfe_hw.h
 create mode 100644 include/net/pfe_eth/pfe_driver.h
 create mode 100644 include/net/pfe_eth/pfe_eth.h
 create mode 100644 include/net/pfe_eth/pfe_firmware.h
 create mode 100644 include/net/pfe_eth/pfe_mdio.h

diff --git a/include/dm/platform_data/pfe_dm_eth.h 
b/include/dm/platform_data/pfe_dm_eth.h
new file mode 100644
index 000..7943c67
--- /dev/null
+++ b/include/dm/platform_data/pfe_dm_eth.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __PFE_DM_ETH_H__
+#define __PFE_DM_ETH_H__
+#include 
+
+struct pfe_ddr_address {
+   void *ddr_pfe_baseaddr;
+   unsigned long ddr_pfe_phys_baseaddr;
+};
+
+struct pfe_eth_pdata {
+   struct eth_pdata pfe_eth_pdata_mac;
+   struct pfe_ddr_address pfe_ddr_addr;
+};
+#endif /* __PFE_DM_ETH_H__ */
diff --git a/include/net/pfe_eth/pfe/cbus.h b/include/net/pfe_eth/pfe/cbus.h
new file mode 100644
index 000..002041c
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#include "cbus/emac.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+
+#define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR)
+
+/* PFE Control and Status Register Desciption */
+#define EMAC1_BASE_ADDR(CBUS_BASE_ADDR + 0x20)
+#define EGPI1_BASE_ADDR(CBUS_BASE_ADDR + 0x21)
+#define EMAC2_BASE_ADDR(CBUS_BASE_ADDR + 0x22)
+#define EGPI2_BASE_ADDR(CBUS_BASE_ADDR + 0x23)
+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x24)
+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x25)
+#define ARB_BASE_ADDR  (CBUS_BASE_ADDR + 0x26)
+#define DDR_CONFIG_BASE_ADDR   (CBUS_BASE_ADDR + 0x27)
+#define HIF_BASE_ADDR  (CBUS_BASE_ADDR + 0x28)
+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x29)
+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x30)
+#define LMEM_SIZE  0x1
+#define LMEM_END   (LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR  (CBUS_BASE_ADDR + 0x31)
+#define CLASS_CSR_BASE_ADDR(CBUS_BASE_ADDR + 0x32)
+#define HIF_NOCPY_BASE_ADDR(CBUS_BASE_ADDR + 0x35)
+#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x36)
+#define CBUS_GPT_BASE_ADDR (CB

[U-Boot] [PATCH v3 04/13] drivers: net: pfe_eth: provide pfe commands

[Calvin Johnson]

pfe_command provides command line support for several features that
support pfe, like starting or stopping the pfe, checking the health
of the processor engines and checking status of different units inside
pfe.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v3:
-Update header location to include/net/pfe_eth

Changes in v2:
-remove unused code under CONFIG_UTIL_PE_DISABLED
-remove unused code under CONFIG_PFE_WARN_WA

 drivers/net/pfe_eth/pfe_cmd.c | 497 ++
 1 file changed, 497 insertions(+)
 create mode 100644 drivers/net/pfe_eth/pfe_cmd.c

diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
new file mode 100644
index 000..822dc0f
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_cmd.c
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * @file
+ * @brief PFE utility commands
+ */
+
+#include 
+
+static inline void pfe_command_help(void)
+{
+   printf("Usage: pfe [pe | status | expt ] \n");
+}
+
+static void pfe_command_pe(int argc, char * const argv[])
+{
+   if (argc >= 3 && strcmp(argv[2], "pmem") == 0) {
+   if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+   int i;
+   int num;
+   int id;
+   u32 addr;
+   u32 size;
+   u32 val;
+
+   if (argc == 7) {
+   num = simple_strtoul(argv[6], NULL, 0);
+   } else if (argc == 6) {
+   num = 1;
+   } else {
+   printf("Usage: pfe pe pmem read   
[]\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   addr = simple_strtoul(argv[5], NULL, 16);
+   size = 4;
+
+   for (i = 0; i < num; i++, addr += 4) {
+   val = pe_pmem_read(id, addr, size);
+   val = be32_to_cpu(val);
+   if (!(i & 3))
+   printf("%08x: ", addr);
+   printf("%08x%s", val, i == num - 1 || (i & 3)
+  == 3 ? "\n" : " ");
+   }
+
+   } else {
+   printf("Usage: pfe pe pmem read \n");
+   }
+   } else if (argc >= 3 && strcmp(argv[2], "dmem") == 0) {
+   if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+   int i;
+   int num;
+   int id;
+   u32 addr;
+   u32 size;
+   u32 val;
+
+   if (argc == 7) {
+   num = simple_strtoul(argv[6], NULL, 0);
+   } else if (argc == 6) {
+   num = 1;
+   } else {
+   printf("Usage: pfe pe dmem read   
[]\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   addr = simple_strtoul(argv[5], NULL, 16);
+   size = 4;
+
+   for (i = 0; i < num; i++, addr += 4) {
+   val = pe_dmem_read(id, addr, size);
+   val = be32_to_cpu(val);
+   if (!(i & 3))
+   printf("%08x: ", addr);
+   printf("%08x%s", val, i == num - 1 || (i & 3)
+  == 3 ? "\n" : " ");
+   }
+
+   } else if (argc >= 4 && strcmp(argv[3], "write") == 0) {
+   int id;
+   u32 val;
+   u32 addr;
+   u32 size;
+
+   if (argc != 7) {
+   printf("Usage: pfe pe dmem write   
\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   val = simple_strtoul(argv[5], NULL, 16);
+   val = cpu_to_be32(val);
+   addr = simple_strtoul(argv[6], NULL, 16);
+   size = 4;
+

[U-Boot] [PATCH v3 02/13] armv8: fsl-layerscape: Add support of GPIO structure

[Calvin Johnson]

From: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>

Layerscape Gen2 SoC supports GPIO registers to control GPIO
signals. Adding support of GPIO structure to access GPIO
registers.

Signed-off-by: Pratiyush Srivastava <pratiyush.srivast...@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>
Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1ff5cac..b195005 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -82,6 +82,11 @@
 #define QSPI0_BASE_ADDR(CONFIG_SYS_IMMR + 
0x0055)
 #define DSPI1_BASE_ADDR(CONFIG_SYS_IMMR + 
0x0110)
 
+#define GPIO1_BASE_ADDR(CONFIG_SYS_IMMR + 
0x130)
+#define GPIO2_BASE_ADDR(CONFIG_SYS_IMMR + 
0x131)
+#define GPIO3_BASE_ADDR(CONFIG_SYS_IMMR + 
0x132)
+#define GPIO4_BASE_ADDR(CONFIG_SYS_IMMR + 
0x133)
+
 #define LPUART_BASE(CONFIG_SYS_IMMR + 0x0195)
 
 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220)
@@ -591,6 +596,16 @@ struct ccsr_serdes {
u8  res_19a0[0x2000-0x19a0];/* from 0x19a0 to 0x1fff */
 };
 
+struct ccsr_gpio {
+   u32 gpdir;
+   u32 gpodr;
+   u32 gpdat;
+   u32 gpier;
+   u32 gpimr;
+   u32 gpicr;
+   u32 gpibe;
+};
+
 /* MMU 500 */
 #define SMMU_SCR0  (SMMU_BASE + 0x0)
 #define SMMU_SCR1  (SMMU_BASE + 0x4)
-- 
2.7.4

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[U-Boot] [PATCH v3 03/13] drivers: net: pfe_eth: LS1012A PFE driver introduction

[Calvin Johnson]

This patch adds PFE driver to U-Boot

Following are the main driver files:-
pfe_hw.c: provides low level helper functions to initialize PFE
internal processor engines and other hardware blocks
pfe_driver.c: provides initialization functions
and packet send and receive functions
pfe_eth.c: provides high level gemac initialization functions
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.
pfe_mdio.c: provides functions to initialize phy and mdio.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>

---

Changes in v3:
-Update header location to include/net/pfe_eth
-Replace EMACX_PHY_ADDR with CONFIG_PFE_EMACX_PHY_ADDR

Changes in v2:
-fix RGMII TX-delay issue
-add pfe_rx_done to clear bd after packet processing
-use writel/readl to access hw bds
-cleanup typos and indent
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Consolidate code in pfe_lib_init
-Corrected typo receive
-Magic numbers replaced with proper definitions
-File names pfe.c renamed to pfe_hw.c to be more clear as it contains
 low level functions that directly access pfe hardware block.
-MDIO related code is also moved from pfe_eth.c to a new file
 pfe_mdio.c.

 drivers/net/pfe_eth/pfe_driver.c   | 643 
 drivers/net/pfe_eth/pfe_eth.c  | 297 +++
 drivers/net/pfe_eth/pfe_firmware.c | 230 +
 drivers/net/pfe_eth/pfe_hw.c   | 999 +
 drivers/net/pfe_eth/pfe_mdio.c | 291 +++
 5 files changed, 2460 insertions(+)
 create mode 100644 drivers/net/pfe_eth/pfe_driver.c
 create mode 100644 drivers/net/pfe_eth/pfe_eth.c
 create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
 create mode 100644 drivers/net/pfe_eth/pfe_hw.c
 create mode 100644 drivers/net/pfe_eth/pfe_mdio.c

diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
new file mode 100644
index 000..a9991f5
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_driver.c
@@ -0,0 +1,643 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+static struct tx_desc_s *g_tx_desc;
+static struct rx_desc_s *g_rx_desc;
+
+/*
+ * HIF Rx interface function
+ * Reads the rx descriptor from the current location (rx_to_read).
+ * - If the descriptor has a valid data/pkt, then get the data pointer
+ * - check for the input rx phy number
+ * - increment the rx data pointer by pkt_head_room_size
+ * - decrement the data length by pkt_head_room_size
+ * - handover the packet to caller.
+ *
+ * @param[out] pkt_ptr - Pointer to store rx packet
+ * @param[out] phy_port - Pointer to store recv phy port
+ *
+ * @return -1 if no packet, else return length of packet.
+ */
+int pfe_recv(uchar **pkt_ptr, int *phy_port)
+{
+   struct rx_desc_s *rx_desc = g_rx_desc;
+   struct buf_desc *bd;
+   int len = 0;
+
+   struct hif_header_s *hif_header;
+
+   bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+   if (readl(>ctrl) & BD_CTRL_DESC_EN)
+   return len; /* No pending Rx packet */
+
+   /* this len include hif_header(8 bytes) */
+   len = readl(>ctrl) & 0x;
+
+   hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(>data));
+
+   /* Get the receive port info from the packet */
+   debug("Pkt received:");
+   debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
+ hif_header, len, hif_header->port_no, readl(>status));
+#ifdef DEBUG
+   {
+   int i;
+   unsigned char *p = (unsigned char *)hif_header;
+
+   for (i = 0; i < len; i++) {
+   if (!(i % 16))
+   printf("\n");
+   printf(" %02x", p[i]);
+   }
+   printf("\n");
+   }
+#endif
+
+   *pkt_ptr = (uchar *)(hif_header + 1);
+   *phy_port = hif_header->port_no;
+   len -= sizeof(struct hif_header_s);
+
+   return len;
+}
+
+/*
+ * HIF function to check the Rx done
+ * This function will check the rx done indication of the current rx_to_read
+ * locations
+ * if success, moves the rx_to_read to next location.
+ */
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+   struct rx_desc_s *rx_desc = g_rx_desc;
+   struct buf_desc *bd;
+
+   debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
+ rx_desc->rx_to_read);
+
+   bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+   /* reset the control field */
+   writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
+   | BD_CTRL_DIR), >ctrl);
+   writel(0, >status);
+
+   debug("Rx Done : status:

[U-Boot] [PATCH v3 01/13] drivers: net: phy: Fix aquantia compilation with DM

[Calvin Johnson]

With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.

drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
  phydev->dev->name);
 ^~

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>
---

Changes in v3: None
Changes in v2: None

 drivers/net/phy/aquantia.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ad12f6d..6678147 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -7,6 +7,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 
 #ifndef CONFIG_PHYLIB_10G
-- 
2.7.4

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[U-Boot] [PATCH v3 00/13] LS1012A PFE driver patch series

[Calvin Johnson]

This patch series introduces U-Boot support for NXP's LS1012A Packet
Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
engine to provide high performance Ethernet interfaces. The device
includes two Ethernet ports.


Changes in v3:
-Update header location to include/net/pfe_eth
-Replace EMACX_PHY_ADDR with CONFIG_PFE_EMACX_PHY_ADDR
-Update header location to include/net/pfe_eth
-Move pfe_eth header files to include/net/pfe_eth
-Use BIT macro wherever applicable
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Cosmetic changes
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Prefix CONFIG_PFE_ to appropriate macros
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Prefix CONFIG_PFE_ to appropriate macros
-Indent properly
-Use BIT macro wherever applicable
-Cosmetic change
-Move PFE macros to Kconfig
-Remove unused UTIL_PE_DISABLED config

Changes in v2:
-fix RGMII TX-delay issue
-add pfe_rx_done to clear bd after packet processing
-use writel/readl to access hw bds
-cleanup typos and indent
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Consolidate code in pfe_lib_init
-Corrected typo receive
-Magic numbers replaced with proper definitions
-File names pfe.c renamed to pfe_hw.c to be more clear as it contains
 low level functions that directly access pfe hardware block.
-MDIO related code is also moved from pfe_eth.c to a new file
 pfe_mdio.c.
-remove unused code under CONFIG_UTIL_PE_DISABLED
-remove unused code under CONFIG_PFE_WARN_WA
-Add pfe_rx_done to clear bd after packet processing
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Used BIT and GENMASK macros wherever applicable
-Removed generic definitions that pollutes namespace
-File names pfe.h renamed to pfe_hw.h to be more clear as it contains
 low level functions that directly access pfe hardware block
-Added pfe_dm_eth.h for new driver model
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
-New patch added to series to enable ethernet support for
ls1012a2g5rdb
-Improved commit message to provide more description
-Replaced magic numbers with proper definitions
-Improved commit message to provide more description
-Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
-Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files

Calvin Johnson (12):
  drivers: net: phy: Fix aquantia compilation with DM
  drivers: net: pfe_eth: LS1012A PFE driver introduction
  drivers: net: pfe_eth: provide pfe commands
  drivers: net: pfe_eth: LS1012A PFE headers
  board: freescale: ls1012aqds: enable network support on ls1012aqds
  board: freescale: ls1012afrdm: enable network support on ls1012afrdm
  board: freescale: ls1012ardb: enable network support on ls1012ardb
  board: freescale: ls1012a2g5rdb: enable network support on
ls1012a2g5rdb
  armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
  armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
  armv8: layerscape: csu: enable ns access to PFE registers
  configs: ls1012a: add pfe configuration for LS1012A

Prabhakar Kushwaha (1):
  armv8: fsl-layerscape: Add support of GPIO structure

 arch/arm/cpu/armv8/fsl-layerscape/soc.c|  23 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  63 +-
 .../include/asm/arch-fsl-layerscape/ns_access.h|   2 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   3 +
 board/freescale/ls1012afrdm/Kconfig|  29 +
 board/freescale/ls1012afrdm/Makefile   |   1 +
 board/freescale/ls1012afrdm/eth.c  | 124 +++
 board/freescale/ls1012afrdm/ls1012afrdm.c  |   5 -
 board/freescale/ls1012aqds/Kconfig |  45 +
 board/freescale/ls1012aqds/Makefile|   1 +
 board/freescale/ls1012aqds/eth.c   | 309 +++
 board/freescale/ls1012aqds/ls1012aqds.c|  97 +-
 board/freescale/ls1012aqds/ls1012aqds_pfe.h|  45 +
 board/freescale/ls1012aqds/ls1012aqds_qixis.h  |   2 +-
 board/freescale/ls1012ardb/Kconfig |  59 ++
 board/freescale/ls1012ardb/Makefile|   1 +
 board/freescale/ls1012ardb/eth.c   | 135 +++
 board/freescale/ls1012ardb/ls1012ardb.c|   4 -
 configs/ls1012a2g5rdb_qspi_defconfig   |   2 +
 configs/ls1012afrdm_qspi_defconfig |   2 +
 configs/ls1012aqds_qspi_defconfig  |   2 +
 configs/ls1012ardb_qspi_defconfig  |   2 +
 drivers/net/Kconfig|   1 +
 drivers/net/Makefile   |   1 +
 drivers/net/pfe_

Re: [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A

[Calvin Johnson]

Hi Joe,

> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> Sent: Wednesday, February 28, 2018 1:47 AM
> To: Calvin Johnson <calvin.john...@nxp.com>
> Cc: u-boot <u-boot@lists.denx.de>; Joe Hershberger
> <joe.hershber...@ni.com>; Anji Jagarlmudi <anji.jagarlm...@nxp.com>
> Subject: Re: [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe 
> configuration for
> LS1012A
> 
> On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.john...@nxp.com>
> wrote:
> > Add configurations for PFE.
> >
> > Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
> > Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
> > ---
> > Changes in v2:
> > -Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
> > -Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files
> > ---
> >  configs/ls1012a2g5rdb_qspi_defconfig |  2 ++
> >  configs/ls1012afrdm_qspi_defconfig   |  2 ++
> >  configs/ls1012aqds_qspi_defconfig|  2 ++
> >  configs/ls1012ardb_qspi_defconfig|  2 ++
> >  drivers/net/Kconfig  |  1 +
> >  drivers/net/Makefile |  1 +
> >  drivers/net/pfe_eth/Kconfig  | 17 +
> >  drivers/net/pfe_eth/Makefile | 12 
> >  include/configs/ls1012a2g5rdb.h  |  2 +-
> >  include/configs/ls1012a_common.h |  6 +++---
> >  include/configs/ls1012afrdm.h|  9 -
> >  include/configs/ls1012aqds.h | 14 ++
> >  include/configs/ls1012ardb.h | 10 +-
> >  13 files changed, 74 insertions(+), 6 deletions(-)
> >  create mode 100644 drivers/net/pfe_eth/Kconfig
> >  create mode 100644 drivers/net/pfe_eth/Makefile
> >



> > diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
> > new file mode 100644
> > index 000..6f99710
> > --- /dev/null
> > +++ b/drivers/net/pfe_eth/Kconfig
> > @@ -0,0 +1,17 @@
> > +menuconfig FSL_PFE
> > +   bool "Freescale PFE driver"
> 
> Is NXP more appropriate at this point? Or Qualcomm? Or Broadcom? :D

Yes, I think NXP is more appropriate right now.
If required, we can change it later. 

> 
> Seriously, though, maybe it should include "Ethernet driver".
> 
> > +   help
> > + This driver provides support for Freescale PFE.
> 
> It probably makes sense here to spell out the acronym.
> 
> > +
> > +if FSL_PFE
> > +
> > +config UTIL_PE_DISABLED
> > +   bool
> > +   help
> > + Disable UTIL processor engine of PFE
> > +
> > +config SYS_FSL_PFE_ADDR
> > +   hex "PFE base address"
> > +   default 0x0400
> > +
> > +endif
> > diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
> > new file mode 100644
> > index 000..6b5248f
> > --- /dev/null
> > +++ b/drivers/net/pfe_eth/Makefile
> > @@ -0,0 +1,12 @@
> > +# Copyright 2015-2016 Freescale Semiconductor, Inc.
> > +# Copyright 2017 NXP
> > +#
> > +# SPDX-License-Identifier:GPL-2.0+
> > +
> > +# Layerscape PFE driver
> > +obj-y += pfe_cmd.o \
> > +pfe_driver.o   \
> > +pfe_eth.o  \
> > +pfe_firmware.o \
> > +pfe_hw.o   \
> > +pfe_mdio.o
> > diff --git a/include/configs/ls1012a2g5rdb.h 
> > b/include/configs/ls1012a2g5rdb.h
> > index 25df103..2d18f3c 100644
> > --- a/include/configs/ls1012a2g5rdb.h
> > +++ b/include/configs/ls1012a2g5rdb.h
> > @@ -110,7 +110,7 @@
> >
> >  #undef CONFIG_BOOTCOMMAND
> >  #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
> > -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "
> \
> > +#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run
> qspi_bootcmd; " \
> >"env exists secureboot && esbc_halt;"
> >  #endif
> >
> > diff --git a/include/configs/ls1012a_common.h
> b/include/configs/ls1012a_common.h
> > index 7dbe231..b590d7a 100644
> > --- a/include/configs/ls1012a_common.h
> > +++ b/include/configs/ls1012a_common.h
> > @@ -118,9 +118,9 @@
> > "kernel_size=0x280\0"   \
> >
> >  #undef CONFIG_BOOTCOMMAND
> > -#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load 
> > "\
> > -   "$kernel_start $kernel_size && "\
&

Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series

[Calvin Johnson]

> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> Sent: Tuesday, February 27, 2018 9:18 PM
> To: Calvin Johnson <calvin.john...@nxp.com>
> Cc: joe.hershber...@ni.com; u-boot@lists.denx.de; Anji Jagarlmudi
> <anji.jagarlm...@nxp.com>; York Sun <york@nxp.com>
> Subject: Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
> 
> On Mon, Feb 26, 2018 at 10:49 PM, Calvin Johnson <calvin.john...@nxp.com>
> wrote:
> > Hi Joe,
> >
> >> -Original Message-
> >> From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> >> Sent: Tuesday, February 27, 2018 1:31 AM
> >> To: Calvin Johnson <calvin.john...@nxp.com>
> >> Cc: joe.hershber...@ni.com; u-boot@lists.denx.de; Anji Jagarlmudi
> >> <anji.jagarlm...@nxp.com>
> >> Subject: Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
> >>
> >> Hi Calvin,
> >>
> >> On Wed, Feb 21, 2018 at 10:32 PM, Calvin Johnson <calvin.john...@nxp.com>
> >> wrote:
> >> > Hi Joe,
> >> >
> >> >> -Original Message-
> >> >> From: Calvin Johnson [mailto:calvin.john...@nxp.com]
> >> >> Sent: Thursday, February 15, 2018 7:47 PM
> >> >> To: u-boot@lists.denx.de
> >> >> Cc: joe.hershber...@ni.com; York Sun <york@nxp.com>; Anji
> Jagarlmudi
> >> >> <anji.jagarlm...@nxp.com>; Calvin Johnson <calvin.john...@nxp.com>
> >> >> Subject: [PATCH v2 00/13] LS1012A PFE driver patch series
> >> >>
> >> >
> >> > 
> >> >
> >> >> Changes in v2 series:
> >> >> 1. PFE patches submitted on top of this base patch are now merged to
> >> >> this patch.
> >> >> 2. Platform changes are segregated into different patches.
> >> >> 3. Network enabled on 2g5rdb platform
> >> >> 4. Moved from legacy to new driver model.
> >> >
> >> > Gentle reminder. Hope the PFE patches didn't miss your sight.
> >>
> >> I tried applying your series and it had many checkpatch issues. Please
> >> resolve those and resend.
> >>
> >> Thanks,
> >> -Joe
> >>
> >> -
> >>
> >>
> >> Fetched U-Boot-1-9-drivers-net-pfe_eth-LS1012A-PFE-driver-introduction
> >> (823206.mbox)
> >> 823206.mbox:46: WARNING: added, moved or deleted file(s), does
> >> MAINTAINERS need updating?
> >> 823206.mbox:534: CHECK: Avoid CamelCase: 
> >> 823206.mbox:551: CHECK: No space is necessary after a cast
> >> 823206.mbox:669: CHECK: spaces preferred around that '&' (ctx:ExV)
> >
> > 
> >
> > Looks like you have run checkpatch on the v1 series (9 patches).
> > I had submitted the v2 series (13 patches).
> >
> > However, in the v2 series, there are some checkpatch warnings like ' line 
> > over
> 80 characters'
> > which I had to ignore due to valid reasons. If there is any concern on 
> > these, I
> can work on them
> > after discussion.
> 
> Sorry about that - Only your V1 was assigned to me in patchwork, so I missed 
> it.
> 
> Looks like V2 is assigned to York at the moment, but I'm going to
> assign it to myself since it is all about networking.

Not sure, how it got assigned to York. Thanks for taking up the patches.

Regards
Calvin
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Re: [U-Boot] [PATCH] board: freescale: ls1012a: fix RGMII TX-delay issue

[Calvin Johnson]

> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> Sent: Tuesday, February 27, 2018 9:28 PM
> To: Calvin Johnson <calvin.john...@nxp.com>
> Cc: u-boot <u-boot@lists.denx.de>; Joe Hershberger
> <joe.hershber...@ni.com>; Anji Jagarlmudi <anji.jagarlm...@nxp.com>
> Subject: Re: [U-Boot] [PATCH] board: freescale: ls1012a: fix RGMII TX-delay 
> issue
> 
> On Thu, Oct 26, 2017 at 12:01 AM, Calvin Johnson <calvin.john...@nxp.com>
> wrote:
> > Recently logic to enable RGMII TX-delay was changed by
> > commit 05b29aa0cb68 ("net: phy: realtek: fix enabling of the TX-delay
> > for RTL8211F")
> >
> > Based on this, here we are enabling the TX-delay again using
> > PHY_INTERFACE_MODE_RGMII_TXID.
> >
> > Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
> > Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
> > ---
> >
> >  board/freescale/ls1012ardb/eth.c | 2 +-
> >  drivers/net/pfe_eth/pfe_eth.c| 2 +-
> >  2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/board/freescale/ls1012ardb/eth.c
> b/board/freescale/ls1012ardb/eth.c
> > index 286bc8a..c0f6306 100644
> > --- a/board/freescale/ls1012ardb/eth.c
> > +++ b/board/freescale/ls1012ardb/eth.c
> > @@ -62,7 +62,7 @@ int board_eth_init(bd_t *bis)
> > /* MAC2 */
> > ls1012a_set_mdio(1,
> miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
> > ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR,
> > -PHY_INTERFACE_MODE_RGMII);
> > +PHY_INTERFACE_MODE_RGMII_TXID);
> >
> > cpu_eth_init(bis);
> >  #endif
> > diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
> > index 8d8de40..4db823f 100644
> > --- a/drivers/net/pfe_eth/pfe_eth.c
> > +++ b/drivers/net/pfe_eth/pfe_eth.c
> 
> Is this still needed with v2 of your patch?

No. It is already squashed into v2.

Along with this, following patches also were squashed as you and York suggested.
[U-Boot,1/3] drivers: net: pfe_eth: add pfe_rx_done to clear bd after packet 
processing
[U-Boot,2/3] drivers: net: pfe_eth: use writel/readl to access hw bds
[U-Boot,3/3] drivers: net: pfe_eth: cleanup typos and indent
[U-Boot,1/2] drivers: net: pfe_eth: remove unused code under 
CONFIG_UTIL_PE_DISABLED
[U-Boot,2/2] drivers: net: pfe_eth: remove unused code under CONFIG_PFE_WARN_WA

Thanks
Calvin
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Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series

[Calvin Johnson]

Hi Joe,

> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> Sent: Tuesday, February 27, 2018 1:31 AM
> To: Calvin Johnson <calvin.john...@nxp.com>
> Cc: joe.hershber...@ni.com; u-boot@lists.denx.de; Anji Jagarlmudi
> <anji.jagarlm...@nxp.com>
> Subject: Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
> 
> Hi Calvin,
> 
> On Wed, Feb 21, 2018 at 10:32 PM, Calvin Johnson <calvin.john...@nxp.com>
> wrote:
> > Hi Joe,
> >
> >> -Original Message-
> >> From: Calvin Johnson [mailto:calvin.john...@nxp.com]
> >> Sent: Thursday, February 15, 2018 7:47 PM
> >> To: u-boot@lists.denx.de
> >> Cc: joe.hershber...@ni.com; York Sun <york@nxp.com>; Anji Jagarlmudi
> >> <anji.jagarlm...@nxp.com>; Calvin Johnson <calvin.john...@nxp.com>
> >> Subject: [PATCH v2 00/13] LS1012A PFE driver patch series
> >>
> >
> > 
> >
> >> Changes in v2 series:
> >> 1. PFE patches submitted on top of this base patch are now merged to
> >> this patch.
> >> 2. Platform changes are segregated into different patches.
> >> 3. Network enabled on 2g5rdb platform
> >> 4. Moved from legacy to new driver model.
> >
> > Gentle reminder. Hope the PFE patches didn't miss your sight.
> 
> I tried applying your series and it had many checkpatch issues. Please
> resolve those and resend.
> 
> Thanks,
> -Joe
> 
> -
> 
> 
> Fetched U-Boot-1-9-drivers-net-pfe_eth-LS1012A-PFE-driver-introduction
> (823206.mbox)
> 823206.mbox:46: WARNING: added, moved or deleted file(s), does
> MAINTAINERS need updating?
> 823206.mbox:534: CHECK: Avoid CamelCase: 
> 823206.mbox:551: CHECK: No space is necessary after a cast
> 823206.mbox:669: CHECK: spaces preferred around that '&' (ctx:ExV)



Looks like you have run checkpatch on the v1 series (9 patches). 
I had submitted the v2 series (13 patches).  

However, in the v2 series, there are some checkpatch warnings like ' line over 
80 characters'  
which I had to ignore due to valid reasons. If there is any concern on these, I 
can work on them
after discussion.

Thanks
Calvin
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Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series

[Calvin Johnson]

Hi Joe,

> -Original Message-
> From: Calvin Johnson [mailto:calvin.john...@nxp.com]
> Sent: Thursday, February 15, 2018 7:47 PM
> To: u-boot@lists.denx.de
> Cc: joe.hershber...@ni.com; York Sun <york@nxp.com>; Anji Jagarlmudi
> <anji.jagarlm...@nxp.com>; Calvin Johnson <calvin.john...@nxp.com>
> Subject: [PATCH v2 00/13] LS1012A PFE driver patch series
> 



> Changes in v2 series:
> 1. PFE patches submitted on top of this base patch are now merged to
> this patch.
> 2. Platform changes are segregated into different patches.
> 3. Network enabled on 2g5rdb platform
> 4. Moved from legacy to new driver model.

Gentle reminder. Hope the PFE patches didn't miss your sight.

Thanks & Regards
Calvin
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Re: [U-Boot] [PATCH] usb: dwc2: Reduce data buffer size to 16kB

[Calvin Johnson]

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Alexey
> Brodkin
> Sent: Wednesday, February 21, 2018 3:18 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Alexey Brodkin
> 
> Subject: [U-Boot] [PATCH] usb: dwc2: Reduce data buffer size to 16kB
> 
> If we use hardware with very small RAM (let's consider just a couple
> of hundreds of kB but not megabytes) it is not super convenient to lose
> 64kB for statically allocated bufer which most probably won't be used
> as big as it is. Typically we'll have much shorter data packages to
> excahnge and in the worst case longer packets will be split on separate

s/ excahnge /exchange

Regards
Calvin
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Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series

[Calvin Johnson]

Hi York,

> -Original Message-
> From: York Sun
> Sent: Thursday, February 15, 2018 9:19 PM
> To: Calvin Johnson <calvin.john...@nxp.com>; u-boot@lists.denx.de
> Cc: joe.hershber...@ni.com; Anji Jagarlmudi <anji.jagarlm...@nxp.com>
> Subject: Re: [PATCH v2 00/13] LS1012A PFE driver patch series
> 
> On 02/15/2018 06:10 AM, Calvin Johnson wrote:
> > Hi,
> >
> > This patch series introduces U-Boot support for NXP's LS1012A Packet
> > Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
> > engine to provide high performance Ethernet interfaces. The device
> > includes two Ethernet ports.
> >
> > Changes in v2 series:
> > 1. PFE patches submitted on top of this base patch are now merged to
> > this patch.
> > 2. Platform changes are segregated into different patches.
> > 3. Network enabled on 2g5rdb platform
> > 4. Moved from legacy to new driver model.
> >
> > Calvin Johnson (12):
> >   drivers: net: phy: Fix aquantia compilation with DM
> >   drivers: net: pfe_eth: LS1012A PFE driver introduction
> >   drivers: net: pfe_eth: provide pfe commands
> >   drivers: net: pfe_eth: LS1012A PFE headers
> >   board: freescale: ls1012aqds: enable network support on ls1012aqds
> >   board: freescale: ls1012afrdm: enable network support on ls1012afrdm
> >   board: freescale: ls1012ardb: enable network support on ls1012ardb
> >   board: freescale: ls1012a2g5rdb: enable network support on
> > ls1012a2g5rdb
> >   armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
> >   armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
> >   armv8: layerscape: csu: enable ns access to PFE registers
> >   configs: ls1012a: add pfe configuration for LS1012A
> >
> > Prabhakar Kushwaha (1):
> >   armv8: fsl-layerscape: Add support of GPIO structure
> 
> Calvin,
> 
> I think you should update your copyright year. Is it right to add
> 2015-2016 copyright year? Did you have these files then?

I think most of the pfe driver files, except for board files were present 
during that period. 

However, I would wait for Anji to respond on this. Based on his response
I can update copyright year if required.

Thanks
Calvin
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[U-Boot] [PATCH v2 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds

[Calvin Johnson]

This patch enables ethernet support for ls1012aqds.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
---
 board/freescale/ls1012aqds/Kconfig|  14 ++
 board/freescale/ls1012aqds/Makefile   |   1 +
 board/freescale/ls1012aqds/eth.c  | 304 ++
 board/freescale/ls1012aqds/ls1012aqds.c   |  97 +++-
 board/freescale/ls1012aqds/ls1012aqds_pfe.h   |  48 
 board/freescale/ls1012aqds/ls1012aqds_qixis.h |   2 +-
 6 files changed, 459 insertions(+), 7 deletions(-)
 create mode 100644 board/freescale/ls1012aqds/eth.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h

diff --git a/board/freescale/ls1012aqds/Kconfig 
b/board/freescale/ls1012aqds/Kconfig
index fc9250b..e6c2aa2 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -12,6 +12,20 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1012aqds"
 
+if FSL_PFE
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012aqds/Makefile 
b/board/freescale/ls1012aqds/Makefile
index 0b813f9..b18494a 100644
--- a/board/freescale/ls1012aqds/Makefile
+++ b/board/freescale/ls1012aqds/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012aqds.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
new file mode 100644
index 000..41d077a
--- /dev/null
+++ b/board/freescale/ls1012aqds/eth.c
@@ -0,0 +1,304 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "../common/qixis.h"
+#include 
+#include 
+#include "ls1012aqds_qixis.h"
+
+#define EMI_NONE   0xFF
+#define EMI1_RGMII 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+static const char * const mdio_names[] = {
+   "NULL",
+   "LS1012AQDS_MDIO_RGMII",
+   "LS1012AQDS_MDIO_SLOT1",
+   "LS1012AQDS_MDIO_SLOT2",
+   "NULL",
+};
+
+static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
+{
+   return mdio_names[muxval];
+}
+
+struct ls1012aqds_mdio {
+   u8 muxval;
+   struct mii_dev *realbus;
+};
+
+static void ls1012aqds_mux_mdio(u8 muxval)
+{
+   u8 brdcfg4;
+
+   if (muxval < 7) {
+   brdcfg4 = QIXIS_READ(brdcfg[4]);
+   brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+   brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+   QIXIS_WRITE(brdcfg[4], brdcfg4);
+   }
+}
+
+static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+   int regnum)
+{
+   struct ls1012aqds_mdio *priv = bus->priv;
+
+   ls1012aqds_mux_mdio(priv->muxval);
+
+   return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+int regnum, u16 value)
+{
+   struct ls1012aqds_mdio *priv = bus->priv;
+
+   ls1012aqds_mux_mdio(priv->muxval);
+
+   return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1012aqds_mdio_reset(struct mii_dev *bus)
+{
+   struct ls1012aqds_mdio *priv = bus->priv;
+
+   if (priv->realbus->reset)
+   return priv->realbus->reset(priv->realbus);
+   else
+   return -1;
+}
+
+static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
+{
+   struct ls1012aqds_mdio *pmdio;
+   struct mii_dev *bus = mdio_alloc();
+
+   if (!bus) {
+   printf("Failed to allocate ls1012aqds MDIO bus\n");
+   return -1;
+   }
+
+   pmdio = malloc(sizeof(*pmdio));
+   if (!pmdio) {
+   printf("Failed to allocate ls1012aqds private data\n");
+   free(bus);
+   return -1;
+   }
+
+   bus->read = ls1012aqds_mdio_read;
+   bus->write = ls1012aqds_mdio_write;
+   bus->reset = ls1012aqds_mdio_reset;
+   sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
+
+   pmdio->

[U-Boot] [PATCH v2 07/13] board: freescale: ls1012afrdm: enable network support on ls1012afrdm

[Calvin Johnson]

This patch enables ethernet support for ls1012afrdm.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
---
 board/freescale/ls1012afrdm/Kconfig   |  14 
 board/freescale/ls1012afrdm/Makefile  |   1 +
 board/freescale/ls1012afrdm/eth.c | 122 ++
 board/freescale/ls1012afrdm/ls1012afrdm.c |   5 --
 4 files changed, 137 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/ls1012afrdm/eth.c

diff --git a/board/freescale/ls1012afrdm/Kconfig 
b/board/freescale/ls1012afrdm/Kconfig
index 38bd91b..adb 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -12,6 +12,20 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1012afrdm"
 
+if FSL_PFE
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012afrdm/Makefile 
b/board/freescale/ls1012afrdm/Makefile
index dbfa2ce..1364f22 100644
--- a/board/freescale/ls1012afrdm/Makefile
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012afrdm.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012afrdm/eth.c 
b/board/freescale/ls1012afrdm/eth.c
new file mode 100644
index 000..4f4fff8
--- /dev/null
+++ b/board/freescale/ls1012afrdm/eth.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#define MASK_ETH_PHY_RST   0x0100
+
+static inline void ls1012afrdm_reset_phy(void)
+{
+   unsigned int val;
+   struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+
+   setbits_be32(>gpdir, MASK_ETH_PHY_RST);
+
+   val = in_be32(>gpdat);
+   setbits_be32(>gpdat, val & ~MASK_ETH_PHY_RST);
+   mdelay(10);
+
+   val = in_be32(>gpdat);
+   setbits_be32(>gpdat, val | MASK_ETH_PHY_RST);
+   mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+   static int init_done;
+   struct mii_dev *bus;
+   struct pfe_mdio_info mac_mdio_info;
+   struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+   if (!init_done) {
+   ls1012afrdm_reset_phy();
+
+   mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+   mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+   bus = pfe_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+
+   init_done = 1;
+   }
+
+   if (priv->gemac_port) {
+   mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+   mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+   bus = pfe_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+   }
+
+   pfe_set_mdio(priv->gemac_port,
+miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+   if (!priv->gemac_port)
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   else
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+   .pfe_eth_pdata_mac = {
+   .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+   .phy_interface = 0,
+   },
+
+   .pfe_ddr_addr = {
+   .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+   .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+   },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+   .pfe_eth_pdata_mac = {
+   .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+   .phy_interface = 1,
+   },
+
+   .pfe_ddr_addr = {
+   .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+   .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+   },
+};
+
+U_BOO

[U-Boot] [PATCH v2 12/13] armv8: layerscape: csu: enable ns access to PFE registers

[Calvin Johnson]

Enable all types of non-secure access to PFE block registers.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2:
-Improved commit message to provide more description
---
 arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h 
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index f46f1d8..fe97a93 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -26,6 +26,7 @@ enum csu_cslx_ind {
CSU_CSLX_PCIE3_IO,
CSU_CSLX_USB3 = 20,
CSU_CSLX_USB2,
+   CSU_CSLX_PFE = 23,
CSU_CSLX_SERDES = 32,
CSU_CSLX_QDMA,
CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
 {CSU_CSLX_USB3, CSU_ALL_RW},
 {CSU_CSLX_USB2, CSU_ALL_RW},
+{CSU_CSLX_PFE, CSU_ALL_RW},
 {CSU_CSLX_SERDES, CSU_ALL_RW},
 {CSU_CSLX_QDMA, CSU_ALL_RW},
 {CSU_CSLX_LPUART2, CSU_ALL_RW},
-- 
2.7.4

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[U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A

[Calvin Johnson]

Add configurations for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2:
-Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
-Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files
---
 configs/ls1012a2g5rdb_qspi_defconfig |  2 ++
 configs/ls1012afrdm_qspi_defconfig   |  2 ++
 configs/ls1012aqds_qspi_defconfig|  2 ++
 configs/ls1012ardb_qspi_defconfig|  2 ++
 drivers/net/Kconfig  |  1 +
 drivers/net/Makefile |  1 +
 drivers/net/pfe_eth/Kconfig  | 17 +
 drivers/net/pfe_eth/Makefile | 12 
 include/configs/ls1012a2g5rdb.h  |  2 +-
 include/configs/ls1012a_common.h |  6 +++---
 include/configs/ls1012afrdm.h|  9 -
 include/configs/ls1012aqds.h | 14 ++
 include/configs/ls1012ardb.h | 10 +-
 13 files changed, 74 insertions(+), 6 deletions(-)
 create mode 100644 drivers/net/pfe_eth/Kconfig
 create mode 100644 drivers/net/pfe_eth/Makefile

diff --git a/configs/ls1012a2g5rdb_qspi_defconfig 
b/configs/ls1012a2g5rdb_qspi_defconfig
index 140a4e1..a979211 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -30,7 +30,9 @@ CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
diff --git a/configs/ls1012afrdm_qspi_defconfig 
b/configs/ls1012afrdm_qspi_defconfig
index 060f073..d0bf081 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -28,8 +28,10 @@ CONFIG_DM=y
 # CONFIG_MMC is not set
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012aqds_qspi_defconfig 
b/configs/ls1012aqds_qspi_defconfig
index 0435d51..40fbdd8 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -39,8 +39,10 @@ CONFIG_SCSI_AHCI=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012ardb_qspi_defconfig 
b/configs/ls1012ardb_qspi_defconfig
index ea28953..6262351 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -31,8 +31,10 @@ CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index de1947c..f589978 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,4 +1,5 @@
 source "drivers/net/phy/Kconfig"
+source "drivers/net/pfe_eth/Kconfig"
 
 config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index ac5443c..102e65a 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_FSL_PFE) += pfe_eth/
diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
new file mode 100644
index 000..6f99710
--- /dev/null
+++ b/drivers/net/pfe_eth/Kconfig
@@ -0,0 +1,17 @@
+menuconfig FSL_PFE
+   bool "Freescale PFE driver"
+   help
+ This driver provides support for Freescale PFE.
+
+if FSL_PFE
+
+config UTIL_PE_DISABLED
+   bool
+   help
+ Disable UTIL processor engine of PFE
+
+config SYS_FSL_PFE_ADDR
+   hex "PFE base address"
+   default 0x0400
+
+endif
diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
new file mode 100644
index 000..6b5248f
--- /dev/null
+++ b/drivers/net/pfe_eth/Makefile
@@ -0,0 +1,12 @@
+# Copyright 2015-2016 Freescale Semiconductor, Inc.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:GPL-2.0+
+
+# Layerscape PFE driver
+obj-y += pfe_cmd.o \
+pfe_driver.o   \
+pfe_eth.o  \
+pfe_firmware.o \
+pfe_hw.o   \
+pfe_mdio.o
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 25df103..2d18f3c 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -110,7 +110,7 @@
 
 #undef CONFIG_BOOTCOMMAND
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
   "env exists se

[U-Boot] [PATCH v2 05/13] drivers: net: pfe_eth: LS1012A PFE headers

[Calvin Johnson]

Contains all the pfe header files.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2:
-Add pfe_rx_done to clear bd after packet processing
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Used BIT and GENMASK macros wherever applicable
-Removed generic definitions that pollutes namespace
-File names pfe.h renamed to pfe_hw.h to be more clear as it contains
 low level functions that directly access pfe hardware block
-Added pfe_dm_eth.h for new driver model
---
 include/dm/platform_data/pfe_dm_eth.h |  21 
 include/pfe_eth/pfe/cbus.h|  77 +++
 include/pfe_eth/pfe/cbus/bmu.h|  40 
 include/pfe_eth/pfe/cbus/class_csr.h  | 180 ++
 include/pfe_eth/pfe/cbus/emac.h   | 140 ++
 include/pfe_eth/pfe/cbus/gpi.h|  62 
 include/pfe_eth/pfe/cbus/hif.h|  68 +
 include/pfe_eth/pfe/cbus/hif_nocpy.h  |  40 
 include/pfe_eth/pfe/cbus/tmu_csr.h| 148 
 include/pfe_eth/pfe/cbus/util_csr.h   |  47 +
 include/pfe_eth/pfe/pfe_hw.h  | 163 ++
 include/pfe_eth/pfe_driver.h  |  59 +++
 include/pfe_eth/pfe_eth.h | 104 
 include/pfe_eth/pfe_firmware.h|  17 
 include/pfe_eth/pfe_mdio.h|  13 +++
 15 files changed, 1179 insertions(+)
 create mode 100644 include/dm/platform_data/pfe_dm_eth.h
 create mode 100644 include/pfe_eth/pfe/cbus.h
 create mode 100644 include/pfe_eth/pfe/cbus/bmu.h
 create mode 100644 include/pfe_eth/pfe/cbus/class_csr.h
 create mode 100644 include/pfe_eth/pfe/cbus/emac.h
 create mode 100644 include/pfe_eth/pfe/cbus/gpi.h
 create mode 100644 include/pfe_eth/pfe/cbus/hif.h
 create mode 100644 include/pfe_eth/pfe/cbus/hif_nocpy.h
 create mode 100644 include/pfe_eth/pfe/cbus/tmu_csr.h
 create mode 100644 include/pfe_eth/pfe/cbus/util_csr.h
 create mode 100644 include/pfe_eth/pfe/pfe_hw.h
 create mode 100644 include/pfe_eth/pfe_driver.h
 create mode 100644 include/pfe_eth/pfe_eth.h
 create mode 100644 include/pfe_eth/pfe_firmware.h
 create mode 100644 include/pfe_eth/pfe_mdio.h

diff --git a/include/dm/platform_data/pfe_dm_eth.h 
b/include/dm/platform_data/pfe_dm_eth.h
new file mode 100644
index 000..7943c67
--- /dev/null
+++ b/include/dm/platform_data/pfe_dm_eth.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __PFE_DM_ETH_H__
+#define __PFE_DM_ETH_H__
+#include 
+
+struct pfe_ddr_address {
+   void *ddr_pfe_baseaddr;
+   unsigned long ddr_pfe_phys_baseaddr;
+};
+
+struct pfe_eth_pdata {
+   struct eth_pdata pfe_eth_pdata_mac;
+   struct pfe_ddr_address pfe_ddr_addr;
+};
+#endif /* __PFE_DM_ETH_H__ */
diff --git a/include/pfe_eth/pfe/cbus.h b/include/pfe_eth/pfe/cbus.h
new file mode 100644
index 000..002041c
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#include "cbus/emac.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+
+#define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR)
+
+/* PFE Control and Status Register Desciption */
+#define EMAC1_BASE_ADDR(CBUS_BASE_ADDR + 0x20)
+#define EGPI1_BASE_ADDR(CBUS_BASE_ADDR + 0x21)
+#define EMAC2_BASE_ADDR(CBUS_BASE_ADDR + 0x22)
+#define EGPI2_BASE_ADDR(CBUS_BASE_ADDR + 0x23)
+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x24)
+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x25)
+#define ARB_BASE_ADDR  (CBUS_BASE_ADDR + 0x26)
+#define DDR_CONFIG_BASE_ADDR   (CBUS_BASE_ADDR + 0x27)
+#define HIF_BASE_ADDR  (CBUS_BASE_ADDR + 0x28)
+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x29)
+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x30)
+#define LMEM_SIZE  0x1
+#define LMEM_END   (LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR  (CBUS_BASE_ADDR + 0x31)
+#define CLASS_CSR_BASE_ADDR(CBUS_BASE_ADDR + 0x32)
+#define HIF_NOCPY_BASE_ADDR(CBUS_BASE_ADDR + 0x35)
+#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x36)
+#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x37)
+
+/*
+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
+ * XXX_MEM_ACCESS_ADDR register bit definitions.
+ */
+/* Internal Memory Write. */
+#define PE_MEM_ACCESS_WRITE 

[U-Boot] [PATCH v2 04/13] drivers: net: pfe_eth: provide pfe commands

[Calvin Johnson]

pfe_command provides command line support for several features that
support pfe, like starting or stopping the pfe, checking the health
of the processor engines and checking status of different units inside
pfe.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2:
-remove unused code under CONFIG_UTIL_PE_DISABLED
-remove unused code under CONFIG_PFE_WARN_WA
---
 drivers/net/pfe_eth/pfe_cmd.c | 497 ++
 1 file changed, 497 insertions(+)
 create mode 100644 drivers/net/pfe_eth/pfe_cmd.c

diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
new file mode 100644
index 000..41c9c9b
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_cmd.c
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * @file
+ * @brief PFE utility commands
+ */
+
+#include 
+
+static inline void pfe_command_help(void)
+{
+   printf("Usage: pfe [pe | status | expt ] \n");
+}
+
+static void pfe_command_pe(int argc, char * const argv[])
+{
+   if (argc >= 3 && strcmp(argv[2], "pmem") == 0) {
+   if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+   int i;
+   int num;
+   int id;
+   u32 addr;
+   u32 size;
+   u32 val;
+
+   if (argc == 7) {
+   num = simple_strtoul(argv[6], NULL, 0);
+   } else if (argc == 6) {
+   num = 1;
+   } else {
+   printf("Usage: pfe pe pmem read   
[]\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   addr = simple_strtoul(argv[5], NULL, 16);
+   size = 4;
+
+   for (i = 0; i < num; i++, addr += 4) {
+   val = pe_pmem_read(id, addr, size);
+   val = be32_to_cpu(val);
+   if (!(i & 3))
+   printf("%08x: ", addr);
+   printf("%08x%s", val, i == num - 1 || (i & 3)
+  == 3 ? "\n" : " ");
+   }
+
+   } else {
+   printf("Usage: pfe pe pmem read \n");
+   }
+   } else if (argc >= 3 && strcmp(argv[2], "dmem") == 0) {
+   if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+   int i;
+   int num;
+   int id;
+   u32 addr;
+   u32 size;
+   u32 val;
+
+   if (argc == 7) {
+   num = simple_strtoul(argv[6], NULL, 0);
+   } else if (argc == 6) {
+   num = 1;
+   } else {
+   printf("Usage: pfe pe dmem read   
[]\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   addr = simple_strtoul(argv[5], NULL, 16);
+   size = 4;
+
+   for (i = 0; i < num; i++, addr += 4) {
+   val = pe_dmem_read(id, addr, size);
+   val = be32_to_cpu(val);
+   if (!(i & 3))
+   printf("%08x: ", addr);
+   printf("%08x%s", val, i == num - 1 || (i & 3)
+  == 3 ? "\n" : " ");
+   }
+
+   } else if (argc >= 4 && strcmp(argv[3], "write") == 0) {
+   int id;
+   u32 val;
+   u32 addr;
+   u32 size;
+
+   if (argc != 7) {
+   printf("Usage: pfe pe dmem write   
\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   val = simple_strtoul(argv[5], NULL, 16);
+   val = cpu_to_be32(val);
+   addr = simple_strtoul(argv[6], NULL, 16);
+   size = 4;
+   pe_dmem_write(id, val, addr, size);
+   } else {
+   printf("Usage

[U-Boot] [PATCH v2 03/13] drivers: net: pfe_eth: LS1012A PFE driver introduction

[Calvin Johnson]

This patch adds PFE driver to U-Boot

Following are the main driver files:-
pfe_hw.c: provides low level helper functions to initialize PFE
internal processor engines and other hardware blocks
pfe_driver.c: provides initialization functions
and packet send and receive functions
pfe_eth.c: provides high level gemac initialization functions
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.
pfe_mdio.c: provides functions to initialize phy and mdio.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2:
-fix RGMII TX-delay issue
-add pfe_rx_done to clear bd after packet processing
-use writel/readl to access hw bds
-cleanup typos and indent
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Consolidate code in pfe_lib_init
-Corrected typo receive
-Magic numbers replaced with proper definitions
-File names pfe.c renamed to pfe_hw.c to be more clear as it contains
 low level functions that directly access pfe hardware block.
-MDIO related code is also moved from pfe_eth.c to a new file
 pfe_mdio.c.
---
 drivers/net/pfe_eth/pfe_driver.c   | 643 
 drivers/net/pfe_eth/pfe_eth.c  | 297 +++
 drivers/net/pfe_eth/pfe_firmware.c | 230 +
 drivers/net/pfe_eth/pfe_hw.c   | 999 +
 drivers/net/pfe_eth/pfe_mdio.c | 291 +++
 5 files changed, 2460 insertions(+)
 create mode 100644 drivers/net/pfe_eth/pfe_driver.c
 create mode 100644 drivers/net/pfe_eth/pfe_eth.c
 create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
 create mode 100644 drivers/net/pfe_eth/pfe_hw.c
 create mode 100644 drivers/net/pfe_eth/pfe_mdio.c

diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
new file mode 100644
index 000..3122d5a
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_driver.c
@@ -0,0 +1,643 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+static struct tx_desc_s *g_tx_desc;
+static struct rx_desc_s *g_rx_desc;
+
+/*
+ * HIF Rx interface function
+ * Reads the rx descriptor from the current location (rx_to_read).
+ * - If the descriptor has a valid data/pkt, then get the data pointer
+ * - check for the input rx phy number
+ * - increment the rx data pointer by pkt_head_room_size
+ * - decrement the data length by pkt_head_room_size
+ * - handover the packet to caller.
+ *
+ * @param[out] pkt_ptr - Pointer to store rx packet
+ * @param[out] phy_port - Pointer to store recv phy port
+ *
+ * @return -1 if no packet, else return length of packet.
+ */
+int pfe_recv(uchar **pkt_ptr, int *phy_port)
+{
+   struct rx_desc_s *rx_desc = g_rx_desc;
+   struct buf_desc *bd;
+   int len = 0;
+
+   struct hif_header_s *hif_header;
+
+   bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+   if (readl(>ctrl) & BD_CTRL_DESC_EN)
+   return len; /* No pending Rx packet */
+
+   /* this len include hif_header(8 bytes) */
+   len = readl(>ctrl) & 0x;
+
+   hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(>data));
+
+   /* Get the receive port info from the packet */
+   debug("Pkt received:");
+   debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
+ hif_header, len, hif_header->port_no, readl(>status));
+#ifdef DEBUG
+   {
+   int i;
+   unsigned char *p = (unsigned char *)hif_header;
+
+   for (i = 0; i < len; i++) {
+   if (!(i % 16))
+   printf("\n");
+   printf(" %02x", p[i]);
+   }
+   printf("\n");
+   }
+#endif
+
+   *pkt_ptr = (uchar *)(hif_header + 1);
+   *phy_port = hif_header->port_no;
+   len -= sizeof(struct hif_header_s);
+
+   return len;
+}
+
+/*
+ * HIF function to check the Rx done
+ * This function will check the rx done indication of the current rx_to_read
+ * locations
+ * if success, moves the rx_to_read to next location.
+ */
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+   struct rx_desc_s *rx_desc = g_rx_desc;
+   struct buf_desc *bd;
+
+   debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
+ rx_desc->rx_to_read);
+
+   bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+   /* reset the control field */
+   writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
+   | BD_CTRL_DIR), >ctrl);
+   writel(0, >status);
+
+   debug("Rx Done : status: %08x, ctrl: %08x\n", readl(>status),
+ readl(>ctrl));
+
+   /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
+* BDP need not

[U-Boot] [PATCH v2 02/13] armv8: fsl-layerscape: Add support of GPIO structure

[Calvin Johnson]

From: Prabhakar Kushwaha 

Layerscape Gen2 SoC supports GPIO registers to control GPIO
signals. Adding support of GPIO structure to access GPIO
registers.

Signed-off-by: Pratiyush Srivastava 
Signed-off-by: Prabhakar Kushwaha 
---
Changes in v2: None
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1ff5cac..b195005 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -82,6 +82,11 @@
 #define QSPI0_BASE_ADDR(CONFIG_SYS_IMMR + 
0x0055)
 #define DSPI1_BASE_ADDR(CONFIG_SYS_IMMR + 
0x0110)
 
+#define GPIO1_BASE_ADDR(CONFIG_SYS_IMMR + 
0x130)
+#define GPIO2_BASE_ADDR(CONFIG_SYS_IMMR + 
0x131)
+#define GPIO3_BASE_ADDR(CONFIG_SYS_IMMR + 
0x132)
+#define GPIO4_BASE_ADDR(CONFIG_SYS_IMMR + 
0x133)
+
 #define LPUART_BASE(CONFIG_SYS_IMMR + 0x0195)
 
 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220)
@@ -591,6 +596,16 @@ struct ccsr_serdes {
u8  res_19a0[0x2000-0x19a0];/* from 0x19a0 to 0x1fff */
 };
 
+struct ccsr_gpio {
+   u32 gpdir;
+   u32 gpodr;
+   u32 gpdat;
+   u32 gpier;
+   u32 gpimr;
+   u32 gpicr;
+   u32 gpibe;
+};
+
 /* MMU 500 */
 #define SMMU_SCR0  (SMMU_BASE + 0x0)
 #define SMMU_SCR1  (SMMU_BASE + 0x4)
-- 
2.7.4

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[U-Boot] [PATCH v2 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb

[Calvin Johnson]

This patch enables ethernet support for ls1012ardb.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
---
 board/freescale/ls1012ardb/Kconfig  |  14 +
 board/freescale/ls1012ardb/Makefile |   1 +
 board/freescale/ls1012ardb/eth.c| 106 
 board/freescale/ls1012ardb/ls1012ardb.c |   4 --
 include/configs/ls1012ardb.h|   4 ++
 5 files changed, 125 insertions(+), 4 deletions(-)
 create mode 100644 board/freescale/ls1012ardb/eth.c

diff --git a/board/freescale/ls1012ardb/Kconfig 
b/board/freescale/ls1012ardb/Kconfig
index d13b08e..6e6197a 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -12,6 +12,20 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1012ardb"
 
+if FSL_PFE
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012ardb/Makefile 
b/board/freescale/ls1012ardb/Makefile
index 05fa9d9..bd80ce5 100644
--- a/board/freescale/ls1012ardb/Makefile
+++ b/board/freescale/ls1012ardb/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012ardb.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
new file mode 100644
index 000..bf67590
--- /dev/null
+++ b/board/freescale/ls1012ardb/eth.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+static inline void ls1012ardb_reset_phy(void)
+{
+   /* Through reset IO expander reset both RGMII and SGMII PHYs */
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
+   mdelay(10);
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
+   mdelay(10);
+   i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+   mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+   static int init_done;
+   struct mii_dev *bus;
+   struct pfe_mdio_info mac_mdio_info;
+   struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+   if (!init_done) {
+   ls1012ardb_reset_phy();
+   mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+   mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+   bus = pfe_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+   init_done = 1;
+   }
+
+   pfe_set_mdio(priv->gemac_port,
+miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+
+   if (!priv->gemac_port) {
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+   } else {
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_RGMII_TXID);
+   }
+   return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+   .pfe_eth_pdata_mac = {
+   .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+   .phy_interface = 0,
+   },
+
+   .pfe_ddr_addr = {
+   .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+   .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+   },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+   .pfe_eth_pdata_mac = {
+   .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+   .phy_interface = 1,
+   },
+
+   .pfe_ddr_addr = {
+   .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+   .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+   },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+   .name = "pfe_eth",
+   .platdata = _pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+   .name = "pfe_eth",
+   .platdata = _pdata1,
+};
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c 
b/board/freescale/ls1012ardb/ls1012ardb.c
index c9557bb..ed5a8e6 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -1

[U-Boot] [PATCH v2 11/13] armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC

[Calvin Johnson]

1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2:
-Improved commit message to provide more description
-Replaced magic numbers with proper definitions
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 23 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 12 ++-
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  3 +++
 3 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b9f837d..18fb937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -612,6 +612,29 @@ int setup_chip_volt(void)
return 0;
 }
 
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+   u32 ecccr2;
+
+   out_be32(>pfeasbcr,
+in_be32(>pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+   out_be32(>pfebsbcr,
+in_be32(>pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+   /* CCI-400 QoS settings for PFE */
+   out_be32(>wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
+| SCFG_WR_QOS1_PFE2_QOS));
+   out_be32(>rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
+| SCFG_RD_QOS1_PFE2_QOS));
+
+   ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+   out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+ecccr2 | (unsigned int)DISABLE_PFE_ECC);
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index e1a57de..11cf35c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -205,6 +205,8 @@ struct sys_info {
 
 /* Device Configuration and Pin Control */
 #define DCFG_DCSR_PORCR1   0x0
+#define DCFG_DCSR_ECCCR2   0x524
+#define DISABLE_PFE_ECCBIT(13)
 
 struct ccsr_gur {
u32 porsr1; /* POR status 1 */
@@ -402,7 +404,7 @@ struct ccsr_gur {
 #define SCFG_RGMIIPCR_SETSP_10M(0x0002)
 #define SCFG_RGMIIPCR_SETFD(0x0001)
 
-/*PFEASBCR bit definitions */
+/* PFEASBCR bit definitions */
 #define SCFG_PFEASBCR_ARCACHE0 (0x8000)
 #define SCFG_PFEASBCR_AWCACHE0 (0x4000)
 #define SCFG_PFEASBCR_ARCACHE1 (0x2000)
@@ -410,6 +412,14 @@ struct ccsr_gur {
 #define SCFG_PFEASBCR_ARSNP(0x0800)
 #define SCFG_PFEASBCR_AWSNP(0x0400)
 
+/* WR_QoS1 PFE bit definitions */
+#define SCFG_WR_QOS1_PFE1_QOS  GENMASK(27, 24)
+#define SCFG_WR_QOS1_PFE2_QOS  GENMASK(23, 20)
+
+/* RD_QoS1 PFE bit definitions */
+#define SCFG_RD_QOS1_PFE1_QOS  GENMASK(27, 24)
+#define SCFG_RD_QOS1_PFE2_QOS  GENMASK(23, 20)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u8 res_000[0x100-0x000];
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index cb760b5..d9bfddb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -127,6 +127,9 @@ void fsl_lsch2_early_init_f(void);
 int setup_chip_volt(void);
 /* Setup core vdd in unit mV */
 int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
 #endif
 
 void cpu_name(char *name);
-- 
2.7.4

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[U-Boot] [PATCH v2 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure

[Calvin Johnson]

SoC specific PFE macros are defined and structure ccsr_scfg
is updated with members defined for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
Changes in v2: None
---
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 38 --
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b195005..e1a57de 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -395,6 +395,21 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
 #define SCFG_SNPCNFGCR_SATAWRSNP   0x0040
 
+/* RGMIIPCR bit definitions*/
+#define SCFG_RGMIIPCR_EN_AUTO  (0x0008)
+#define SCFG_RGMIIPCR_SETSP_1000M  (0x0004)
+#define SCFG_RGMIIPCR_SETSP_100M   (0x)
+#define SCFG_RGMIIPCR_SETSP_10M(0x0002)
+#define SCFG_RGMIIPCR_SETFD(0x0001)
+
+/*PFEASBCR bit definitions */
+#define SCFG_PFEASBCR_ARCACHE0 (0x8000)
+#define SCFG_PFEASBCR_AWCACHE0 (0x4000)
+#define SCFG_PFEASBCR_ARCACHE1 (0x2000)
+#define SCFG_PFEASBCR_AWCACHE1 (0x1000)
+#define SCFG_PFEASBCR_ARSNP(0x0800)
+#define SCFG_PFEASBCR_AWSNP(0x0400)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u8 res_000[0x100-0x000];
@@ -412,7 +427,12 @@ struct ccsr_scfg {
u8 res_140[0x158-0x140];
u32 altcbar;
u32 qspi_cfg;
-   u8 res_160[0x180-0x160];
+   u8 res_160[0x164 - 0x160];
+   u32 wr_qos1;
+   u32 wr_qos2;
+   u32 rd_qos1;
+   u32 rd_qos2;
+   u8 res_174[0x180 - 0x174];
u32 dmamcr;
u8 res_184[0x188-0x184];
u32 gic_align;
@@ -443,7 +463,21 @@ struct ccsr_scfg {
u32 usb_refclk_selcr1;
u32 usb_refclk_selcr2;
u32 usb_refclk_selcr3;
-   u8 res_424[0x600-0x424];
+   u8 res_424[0x434 - 0x424];
+   u32 rgmiipcr;
+   u32 res_438;
+   u32 rgmiipsr;
+   u32 pfepfcssr1;
+   u32 pfeintencr1;
+   u32 pfepfcssr2;
+   u32 pfeintencr2;
+   u32 pfeerrcr;
+   u32 pfeeerrintencr;
+   u32 pfeasbcr;
+   u32 pfebsbcr;
+   u8 res_460[0x484 - 0x460];
+   u32 mdioselcr;
+   u8 res_468[0x600 - 0x488];
u32 scratchrw[4];
u8 res_610[0x680-0x610];
u32 corebcr;
-- 
2.7.4

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[U-Boot] [PATCH v2 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb

[Calvin Johnson]

This patch enables ethernet support for ls1012a2g5rdb.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Bhaskar Upadhaya <bhaskar.upadh...@nxp.com>
---
Changes in v2:
-New patch added to series to enable ethernet support for
ls1012a2g5rdb
---
 board/freescale/ls1012ardb/Kconfig | 14 ++
 board/freescale/ls1012ardb/eth.c   | 25 +
 2 files changed, 39 insertions(+)

diff --git a/board/freescale/ls1012ardb/Kconfig 
b/board/freescale/ls1012ardb/Kconfig
index 6e6197a..4bb672c 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -44,6 +44,20 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 default "ls1012a2g5rdb"
 
+if FSL_PFE
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index bf67590..fc062cf 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -26,6 +26,7 @@
 
 static inline void ls1012ardb_reset_phy(void)
 {
+#ifdef CONFIG_TARGET_LS1012ARDB
/* Through reset IO expander reset both RGMII and SGMII PHYs */
i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
@@ -34,6 +35,7 @@ static inline void ls1012ardb_reset_phy(void)
mdelay(10);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
mdelay(50);
+#endif
 }
 
 int pfe_eth_board_init(struct udevice *dev)
@@ -42,6 +44,11 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev);
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+   int srds_s1 = in_be32(>rcwsr[4]) &
+   FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+   srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
if (!init_done) {
ls1012ardb_reset_phy();
@@ -59,6 +66,8 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_mdio(priv->gemac_port,
 miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
 
+   switch (srds_s1) {
+   case 0x3508:
if (!priv->gemac_port) {
/* MAC1 */
pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
@@ -68,6 +77,22 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
 PHY_INTERFACE_MODE_RGMII_TXID);
}
+   break;
+   case 0x2208:
+   if (!priv->gemac_port) {
+   /* MAC1 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII_2500);
+   } else {
+   /* MAC2 */
+   pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII_2500);
+   }
+   break;
+   default:
+   printf("unsupported SerDes PRCTL= %d\n", srds_s1);
+   break;
+   }
return 0;
 }
 
-- 
2.7.4

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[U-Boot] [PATCH v2 01/13] drivers: net: phy: Fix aquantia compilation with DM

[Calvin Johnson]

With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.

drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
  phydev->dev->name);
 ^~

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
---
Changes in v2: None
---
 drivers/net/phy/aquantia.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ad12f6d..6678147 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -7,6 +7,7 @@
  */
 #include 
 #include 
+#include 
 #include 
 
 #ifndef CONFIG_PHYLIB_10G
-- 
2.7.4

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[U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series

[Calvin Johnson]

Hi,
 
This patch series introduces U-Boot support for NXP's LS1012A Packet
Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
engine to provide high performance Ethernet interfaces. The device
includes two Ethernet ports.
 
Changes in v2 series:
1. PFE patches submitted on top of this base patch are now merged to
this patch.
2. Platform changes are segregated into different patches.
3. Network enabled on 2g5rdb platform
4. Moved from legacy to new driver model.

Calvin Johnson (12):
  drivers: net: phy: Fix aquantia compilation with DM
  drivers: net: pfe_eth: LS1012A PFE driver introduction
  drivers: net: pfe_eth: provide pfe commands
  drivers: net: pfe_eth: LS1012A PFE headers
  board: freescale: ls1012aqds: enable network support on ls1012aqds
  board: freescale: ls1012afrdm: enable network support on ls1012afrdm
  board: freescale: ls1012ardb: enable network support on ls1012ardb
  board: freescale: ls1012a2g5rdb: enable network support on
ls1012a2g5rdb
  armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
  armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
  armv8: layerscape: csu: enable ns access to PFE registers
  configs: ls1012a: add pfe configuration for LS1012A

Prabhakar Kushwaha (1):
  armv8: fsl-layerscape: Add support of GPIO structure

 arch/arm/cpu/armv8/fsl-layerscape/soc.c|  23 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  63 +-
 .../include/asm/arch-fsl-layerscape/ns_access.h|   2 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   3 +
 board/freescale/ls1012afrdm/Kconfig|  14 +
 board/freescale/ls1012afrdm/Makefile   |   1 +
 board/freescale/ls1012afrdm/eth.c  | 122 +++
 board/freescale/ls1012afrdm/ls1012afrdm.c  |   5 -
 board/freescale/ls1012aqds/Kconfig |  14 +
 board/freescale/ls1012aqds/Makefile|   1 +
 board/freescale/ls1012aqds/eth.c   | 304 +++
 board/freescale/ls1012aqds/ls1012aqds.c|  97 +-
 board/freescale/ls1012aqds/ls1012aqds_pfe.h|  48 +
 board/freescale/ls1012aqds/ls1012aqds_qixis.h  |   2 +-
 board/freescale/ls1012ardb/Kconfig |  28 +
 board/freescale/ls1012ardb/Makefile|   1 +
 board/freescale/ls1012ardb/eth.c   | 131 +++
 board/freescale/ls1012ardb/ls1012ardb.c|   4 -
 configs/ls1012a2g5rdb_qspi_defconfig   |   2 +
 configs/ls1012afrdm_qspi_defconfig |   2 +
 configs/ls1012aqds_qspi_defconfig  |   2 +
 configs/ls1012ardb_qspi_defconfig  |   2 +
 drivers/net/Kconfig|   1 +
 drivers/net/Makefile   |   1 +
 drivers/net/pfe_eth/Kconfig|  17 +
 drivers/net/pfe_eth/Makefile   |  12 +
 drivers/net/pfe_eth/pfe_cmd.c  | 497 ++
 drivers/net/pfe_eth/pfe_driver.c   | 643 +
 drivers/net/pfe_eth/pfe_eth.c  | 297 ++
 drivers/net/pfe_eth/pfe_firmware.c | 230 +
 drivers/net/pfe_eth/pfe_hw.c   | 999 +
 drivers/net/pfe_eth/pfe_mdio.c | 291 ++
 drivers/net/phy/aquantia.c |   1 +
 include/configs/ls1012a2g5rdb.h|   2 +-
 include/configs/ls1012a_common.h   |   6 +-
 include/configs/ls1012afrdm.h  |   9 +-
 include/configs/ls1012aqds.h   |  14 +
 include/configs/ls1012ardb.h   |  14 +-
 include/dm/platform_data/pfe_dm_eth.h  |  21 +
 include/pfe_eth/pfe/cbus.h |  77 ++
 include/pfe_eth/pfe/cbus/bmu.h |  40 +
 include/pfe_eth/pfe/cbus/class_csr.h   | 180 
 include/pfe_eth/pfe/cbus/emac.h| 140 +++
 include/pfe_eth/pfe/cbus/gpi.h |  62 ++
 include/pfe_eth/pfe/cbus/hif.h |  68 ++
 include/pfe_eth/pfe/cbus/hif_nocpy.h   |  40 +
 include/pfe_eth/pfe/cbus/tmu_csr.h | 148 +++
 include/pfe_eth/pfe/cbus/util_csr.h|  47 +
 include/pfe_eth/pfe/pfe_hw.h   | 163 
 include/pfe_eth/pfe_driver.h   |  59 ++
 include/pfe_eth/pfe_eth.h  | 104 +++
 include/pfe_eth/pfe_firmware.h |  17 +
 include/pfe_eth/pfe_mdio.h |  13 +
 53 files changed, 5060 insertions(+), 24 deletions(-)
 create mode 100644 board/freescale/ls1012afrdm/eth.c
 create mode 100644 board/freescale/ls1012aqds/eth.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h
 create mode 100644 board/freescale/ls1012ardb/eth.c
 create mode 100644 drivers/net/pfe_eth/Kconfig
 create mode 100644 drivers/net/pfe_eth/Makefile
 create mode 100644 drivers

Re: [U-Boot] [PATCH v1 2/4] Convert CONFIG_WATCHDOG_TIMEOUT_MSECS to Kconfig

[Calvin Johnson]

Hi,

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Lukasz
> Majewski
> Sent: Wednesday, February 7, 2018 1:30 AM



> +config WATCHDOG_TIMEOUT_MSECS
> + int "Specify watchdog timeout in mili seconds"

s/mili/milli

Regards
Calvin
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Re: [U-Boot] [PATCH v2 1/3] Move CONFIG_PHY_ADDR to Kconfig

[Calvin Johnson]

Hi,

> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> 
> On Mon, Feb 05, 2018 at 09:07:40AM +0100, Maxime Ripard wrote:
> > On Sat, Feb 03, 2018 at 04:37:15AM +0000, Calvin Johnson wrote:
> > > > Hi,
> > > >
> > > > > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of
> > > > > Stefan Mavrodiev
> > > > > Sent: Friday, February 2, 2018 7:24 PM
> > > >
> > > > 
> > > >
> > > > > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> > > > > index 95b7534..c934aed 100644
> > > > > --- a/drivers/net/phy/Kconfig
> > > > > +++ b/drivers/net/phy/Kconfig
> > > > > @@ -12,6 +12,13 @@ menuconfig PHYLIB
> > > > >
> > > > >  if PHYLIB
> > > > >
> > > > > +config PHY_ADDR
> > > > > + int "PHY address"
> > > > > + default 1 if ARCH_SUNXI
> > >
> > > Sorry, I meant the  default value can be defined in board/sunxi/Kconfig.
> > > Remaining definition of PHY_ADDR config can be here.
> >
> > Tom has asked a few times not to do this but to put the defaults where
> > the Kconfig option is defined. I'm not sure I remember the details
> > though.
> 
> For now, yes, the preferred way of dealing with this is 'default FOO if BAR' 
> in
> the main Kconfig entry line.  What I wish for long term is for 'imply' to get
> extended to support 'imply FOO BAR' but I've not had more to add there
> other than "Gee, this would make life easier".

Got it. Thanks!

Calvin
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Re: [U-Boot] [PATCH v2 1/3] Move CONFIG_PHY_ADDR to Kconfig

[Calvin Johnson]

> Hi,
> 
> > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Stefan
> > Mavrodiev
> > Sent: Friday, February 2, 2018 7:24 PM
> 
> 
> 
> > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index
> > 95b7534..c934aed 100644
> > --- a/drivers/net/phy/Kconfig
> > +++ b/drivers/net/phy/Kconfig
> > @@ -12,6 +12,13 @@ menuconfig PHYLIB
> >
> >  if PHYLIB
> >
> > +config PHY_ADDR
> > +   int "PHY address"
> > +   default 1 if ARCH_SUNXI

Sorry, I meant the  default value can be defined in board/sunxi/Kconfig.
Remaining definition of PHY_ADDR config can be here.

> > +   default 0
> > +   help
> > + The address of PHY on MII bus. Usually in range of 0 to 31.
> 
> Isn't board Kconfig, the right place to keep this?
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Re: [U-Boot] [PATCH v2 1/3] Move CONFIG_PHY_ADDR to Kconfig

[Calvin Johnson]

Hi,

> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Stefan
> Mavrodiev
> Sent: Friday, February 2, 2018 7:24 PM



> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index
> 95b7534..c934aed 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -12,6 +12,13 @@ menuconfig PHYLIB
> 
>  if PHYLIB
> 
> +config PHY_ADDR
> + int "PHY address"
> + default 1 if ARCH_SUNXI
> + default 0
> + help
> +   The address of PHY on MII bus. Usually in range of 0 to 31.

Isn't board Kconfig, the right place to keep this?

Regards
Calvin
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Re: [U-Boot] [PATCH] sunxi: support fuse cmd to read/write fuse

[Calvin Johnson]

Hi,

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Jun Nie
> Sent: Monday, January 29, 2018 12:59 PM
> To: André Przywara 
> Cc: U-Boot Mailing List ; Icenowy Zheng
> ; 370719...@qq.com
> Subject: Re: [U-Boot] [PATCH] sunxi: support fuse cmd to read/write fuse

[snip]

> >> +int fuse_prog(u32 bank, u32 word, u32 val)
> >> +{
> >
> > I would feel better if we have the write access protected by a separate
> > Kconfig symbol. So without this being defined either nothing happens or
> > the user gets a warning.
> 
> Good idea.

Yes, fuse programming should be disabled by default and should be enabled 
only by user who really knows what he is doing.

Also, it will be good to get a confirmation from the user whether user really 
wants
to program the fuse.

Regards
Calvin
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Re: [U-Boot] [PATCH] TCP and wget implementation. Patch V5, 3 of 3.

[Calvin Johnson]

Hi Duncan Hare,

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of
> d...@synoia.com
> Sent: Monday, January 29, 2018 9:24 AM
> To: duncanch...@yahoo.com
> Cc: u-boot@lists.denx.de; Joe Hershberger ;
> Maxime Ripard ; Jagan Teki
> 
> Subject: [U-Boot] [PATCH] TCP and wget implementation. Patch V5, 3 of 3.

I guess you are manually adding the patch version and number.
If so, I would suggest to use the following command, to allow git to prefix 
"PATCH v5" tag to the series and to prepare a cover letter.

git format-patch --subject-prefix="PATCH v5" -3 --cover-letter

While using git send-email command the following command can be used:

git send-email --to=u-b...@linux.freescale.net *.patch

Refer:- https://www.denx.de/wiki/U-Boot/Patches

Patman is a nice tool for all this.

http://git.denx.de/?p=u-boot.git;a=blob;f=tools/patman/README

regards
Calvin
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Re: [U-Boot] [PATCH 1/9] drivers: net: pfe_eth: LS1012A PFE driver introduction

[Calvin Johnson]

Hi Joe,

> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> Sent: Wednesday, December 06, 2017 1:44 AM
> To: Calvin Johnson <calvin.john...@nxp.com>
> Cc: u-boot <u-boot@lists.denx.de>; Joe Hershberger
> <joe.hershber...@ni.com>; Anji Jagarlmudi <anji.jagarlm...@nxp.com>
> Subject: Re: [U-Boot] [PATCH 1/9] drivers: net: pfe_eth: LS1012A PFE driver
> introduction
> 
> On Mon, Oct 9, 2017 at 4:11 AM, Calvin Johnson <calvin.john...@nxp.com>
> wrote:
> > This patch adds PFE driver into U-Boot.

[snip]

> > +   if (dev_id > 1) {
> > +   printf("Invalid port\n");
> > +   return -1;
> > +   }
> > +
> > +   dev = (struct eth_device *)malloc(sizeof(struct eth_device));
> 
> Please don't add a new driver that uses the legacy API. Make this a
> driver model driver.

PFE IP has two MACs.  
In the legacy driver model, we were registering two ethernet 
devices/interfaces, pfe_eth0 and pfe_eth1.

With the new driver model, I'm wondering whether we can do the same.
IIUC, U_BOOT_DEVICE corresponds to PFE IP on the LS1012A platform and  struct 
eth_pdata corresponds to
each MAC. Is this correct?

If yes, how can we register two interfaces, pfe_eth0 and pfe_eth1? Please 
advice.

Thanks
Calvin


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Re: [U-Boot] [PATCH 7/9] armv8: fsl-lsch2: configure pfe's scfg & dcfg registers

[Calvin Johnson]

Hi Poonam,

> -Original Message-
> From: Poonam Aggrwal
> Sent: Friday, November 24, 2017 11:25 AM
> To: Calvin Johnson <calvin.john...@nxp.com>; u-boot@lists.denx.de
> Cc: joe.hershber...@ni.com; Anji Jagarlmudi <anji.jagarlm...@nxp.com>
> Subject: RE: [U-Boot] [PATCH 7/9] armv8: fsl-lsch2: configure pfe's scfg & 
> dcfg
> registers
> 
> Hello Calvin
> 
> Please find few comments inline.
> 
> Regards
> Poonam
> 
> > -Original Message-
> > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Calvin
> > Johnson
> > Sent: Monday, October 09, 2017 2:42 PM
> > To: u-boot@lists.denx.de
> > Cc: joe.hershber...@ni.com; Anji Jagarlmudi <anji.jagarlm...@nxp.com>
> > Subject: [U-Boot] [PATCH 7/9] armv8: fsl-lsch2: configure pfe's scfg & dcfg
> > registers
> Reword: configure Qos, cacheable...attributes for PFE by programming SCFG
> and DFCG registers
> >
> > Define init_pfe_scfg_dcfg_regs to configure scfg and dcfg registers of pfe.
> Consider to reword for more explanation
> Configure "xyz cacheable attributes, via scfg
> PFE QoS settings configured as   via scfg
> dcfg ??
> >
> > Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
> > Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 ++
> >  arch/arm/include/asm/arch-fsl-layerscape/soc.h |  3 +++
> >  2 files changed, 21 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 5c429d4..c6815f3 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -577,6 +577,24 @@ int setup_chip_volt(void)
> > return 0;
> >  }
> >
> > +#ifdef CONFIG_FSL_PFE
> > +void init_pfe_scfg_dcfg_regs(void)
> > +{
> > +   struct ccsr_scfg *scfg = (struct ccsr_scfg
> > *)CONFIG_SYS_FSL_SCFG_ADDR;
> > +
> > +   out_be32(>pfeasbcr,
> > +in_be32(>pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
> > +   out_be32(>pfebsbcr,
> > +in_be32(>pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
> > +
> > +   /* CCI-400 QoS settings for PFE */
> This is incomplete sentence, we should also tell what settings are being
> done.
> > +   out_be32(>wr_qos1, 0x0ff0);
> > +   out_be32(>rd_qos1, 0x0ff0);
> Avoid hardcoding/magic numbers
> > +
> > +   out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x524, 0x2000);
> Should remove hardcoded values , 0x524, 0x2000.
> 0x524 does not show up in the LS1012A RM (Rev 0). Please check once.
> Also adding one liner telling what the above settings mean will help .

Thanks for your comments. Will take care of them in v2 of the series.

Regards
Calvin

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Re: [U-Boot] [PATCH 0/3] ls1012a: fix tftp failure

[Calvin Johnson]

Hi Joe,

> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
> Sent: Wednesday, December 06, 2017 2:35 AM


> >
> 
>  Your PFE patch set is not fully reviewed or accepted. If I were you, I
>  would probably send v2 version to include all the changes.
> 
>  It is up to Joe to decide to take a new version, or patches on top of
>  patches.
> >>
> >> It's assigned to York in patchwork. would you prefer I take them?
> >>
> >
> > Yes, please.
> > I also advised Calvin to squash his patches into one set, instead of
> > patching the patches.
> 
> Ah - I didn't realize this wasn't already in. I see that now.
> 
> Yes, I'll review those patches and they should be squashed and resent.

Thanks for reviewing the pfe patches. 
I'll work on all the comments and also squash the follow up patches into the 
pfe-series v2.

Regards
Calvin
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Re: [U-Boot] [PATCH 0/3] ls1012a: fix tftp failure

[Calvin Johnson]

Hi York,

> -Original Message-
> From: York Sun
> Sent: Thursday, November 23, 2017 12:00 AM
> To: Calvin Johnson <calvin.john...@nxp.com>; u-boot@lists.denx.de
> Cc: Anji Jagarlmudi <anji.jagarlm...@nxp.com>; Joe Hershberger
> <joe.hershber...@ni.com>; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com>
> Subject: Re: [PATCH 0/3] ls1012a: fix tftp failure
> 
> On 11/21/2017 10:26 PM, Calvin Johnson wrote:
> > This patch series fixes bug which fails tftp sometimes
> > while using the pfe interfaces and also has some code clean up.
> >
> >
> > Calvin Johnson (3):
> >   drivers: net: pfe_eth: add pfe_rx_done to clear bd after packet
> > processing
> >   drivers: net: pfe_eth: use writel/readl to access hw bds
> >   drivers: net: pfe_eth: cleanup typos and indent
> >
> >  drivers/net/pfe_eth/pfe_driver.c | 126 +++-
> ---
> >  drivers/net/pfe_eth/pfe_eth.c|  13 ++--
> >  include/pfe_eth/pfe_driver.h |   1 +
> >  3 files changed, 82 insertions(+), 58 deletions(-)
> >
> 
> Your PFE patch set is not fully reviewed or accepted. If I were you, I
> would probably send v2 version to include all the changes.
> 
> It is up to Joe to decide to take a new version, or patches on top of
> patches.

I can squash all these follow up patches to v2 of the base pfe patch series.
Yes, it will be better than having these patches on top of it as the base is 
not yet merged.

Thanks
Calvin


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[U-Boot] [PATCH 2/2] drivers: net: pfe_eth: remove unused code under CONFIG_PFE_WARN_WA

[Calvin Johnson]

remove unused code under CONFIG_PFE_WARN_WA

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>

---

 drivers/net/pfe_eth/pfe_cmd.c | 28 +---
 1 file changed, 1 insertion(+), 27 deletions(-)

diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
index 03a2690..559f8f0 100644
--- a/drivers/net/pfe_eth/pfe_cmd.c
+++ b/drivers/net/pfe_eth/pfe_cmd.c
@@ -283,11 +283,7 @@ static void pfe_pe_status(int argc, char * const argv[])
u32 drop;
char statebuf[5];
u32 class_debug_reg = 0;
-#ifdef CONFIG_PFE_WARN_WA
-   u32 debug_indicator;
-   u32 debug[16];
-   int j;
-#endif
+
if (argc == 4 && strcmp(argv[3], "clear") == 0)
do_clear = 1;
 
@@ -337,28 +333,6 @@ static void pfe_pe_status(int argc, char * const argv[])
   cpu_to_be32(rx), cpu_to_be32(tx),
   cpu_to_be32(drop));
}
-
-#ifdef CONFIG_PFE_WARN_WA
-   debug_indicator = pe_dmem_read(id, dmem_addr, 4);
-   dmem_addr += 4;
-   if (debug_indicator == cpu_to_be32('DBUG')) {
-   int last = 0;
-   for (j = 0; j < 16; j++) {
-   debug[j] = pe_dmem_read(id, dmem_addr, 4);
-   if (debug[j]) {
-   last = j + 1;
-   if (do_clear)
-   pe_dmem_write(id, 0,
- dmem_addr, 4);
-   }
-   dmem_addr += 4;
-   }
-   for (j = 0; j < last; j++)
-   printf("%08x%s", cpu_to_be32(debug[j]),
-  (j & 0x7) == 0x7 || j
-  == last - 1 ? "\n" : " ")
-   }
-#endif
}
 }
 
-- 
2.7.4

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[U-Boot] [PATCH 1/2] drivers: net: pfe_eth: remove unused code under CONFIG_UTIL_PE_DISABLED

[Calvin Johnson]

remove unused code under CONFIG_UTIL_PE_DISABLED

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
---

 drivers/net/pfe_eth/pfe.c  | 98 --
 drivers/net/pfe_eth/pfe_cmd.c  | 16 +--
 drivers/net/pfe_eth/pfe_driver.c   | 15 --
 drivers/net/pfe_eth/pfe_firmware.c |  3 --
 include/pfe_eth/pfe/pfe.h  |  8 
 5 files changed, 2 insertions(+), 138 deletions(-)

diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
index fc6631e..d477192 100644
--- a/drivers/net/pfe_eth/pfe.c
+++ b/drivers/net/pfe_eth/pfe.c
@@ -89,13 +89,6 @@ void pfe_lib_init(void *ddr_base, unsigned long 
ddr_phys_base)
pe[TMU3_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
pe[TMU3_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
pe[TMU3_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
-
-#if !defined(CONFIG_UTIL_PE_DISABLED)
-   pe[UTIL_ID].dmem_base_addr = (u32)UTIL_DMEM_BASE_ADDR;
-   pe[UTIL_ID].mem_access_wdata = (void *)UTIL_MEM_ACCESS_WDATA;
-   pe[UTIL_ID].mem_access_addr = (void *)UTIL_MEM_ACCESS_ADDR;
-   pe[UTIL_ID].mem_access_rdata = (void *)UTIL_MEM_ACCESS_RDATA;
-#endif
 }
 
 /*
@@ -387,60 +380,6 @@ void pe_lmem_write(u32 *src, u32 len, u32 offset)
0x03));
 }
 
-#if !defined(CONFIG_UTIL_PE_DISABLED)
-/*
- * Writes UTIL program memory (DDR) from the host.
- *
- * @param[in] addr Address to write (virtual, must be aligned on size)
- * @param[in] val  Value to write (in PE endianness, i.e BE)
- * @param[in] size Number of bytes to write (2 or 4)
- */
-static void util_pmem_write(u32 val, void *addr, u8 size)
-{
-   void *addr64 = (void *)((unsigned long)addr & ~0x7);
-   unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
-
-   /* IMEM should  be loaded as a 64bit swapped value in a 64bit aligned
-* location
-*/
-   if (size == 4)
-   writel(be32_to_cpu(val), addr64 + off);
-   else
-   writew(be16_to_cpu((u16)val), addr64 + off);
-}
-
-/*
- * Writes a buffer to UTIL program memory (DDR) from the host.
- *
- * @param[in] dst  Address to write (virtual, must be at least 16bit
- * aligned)
- * @param[in] src  Buffer to write (in PE endianness, i.e BE, must have
- * same alignment as dst)
- * @param[in] len  Number of bytes to write (must be at least 16bit
- * aligned)
- */
-static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
-{
-   unsigned int len32;
-   int i;
-
-   if ((unsigned long)src & 0x2) {
-   util_pmem_write(*(u16 *)src, dst, 2);
-   src += 2;
-   dst += 2;
-   len -= 2;
-   }
-
-   len32 = len >> 2;
-
-   for (i = 0; i < len32; i++, dst += 4, src += 4)
-   util_pmem_write(*(u32 *)src, dst, 4);
-
-   if (len & 0x2)
-   util_pmem_write(*(u16 *)src, dst, len & 0x2);
-}
-#endif
-
 /*
  * Loads an elf section into pmem
  * Code needs to be at least 16bit aligned and only PROGBITS sections are
@@ -458,13 +397,6 @@ static int pe_load_pmem_section(int id, const void *data, 
Elf32_Shdr *shdr)
u32 size = be32_to_cpu(shdr->sh_size);
u32 type = be32_to_cpu(shdr->sh_type);
 
-#if !defined(CONFIG_UTIL_PE_DISABLED)
-   if (id == UTIL_ID) {
-   printf("%s: unsupported pmem section for UTIL\n", __func__);
-   return -1;
-   }
-#endif
-
if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
printf(
"%s: load address(%x) and elf file address(%lx) don't 
have the same alignment\n",
@@ -615,36 +547,6 @@ static int pe_load_ddr_section(int id, const void *data, 
Elf32_Shdr *shdr)
}
}
 
-#if !defined(CONFIG_UTIL_PE_DISABLED)
-   else if (id == UTIL_ID) {
-   if (((unsigned long)(data + offset) & 0x3)
-   != (addr & 0x3)) {
-   printf(
-   "%s: load address(%x) and elf 
file address(%lx) don't have the same alignment\n",
-   __func__, addr,
-   (unsigned long)data + offset);
-
-   return -1;
-   }
-
-   if (addr & 0x1) {
-   printf(
-   "%s: load address(%x) is not 
16bit aligned\n"
-   , __func__, addr);
- 

[U-Boot] [PATCH 0/2] Remove unused pfe_eth code

[Calvin Johnson]

This patch series cleans up unused PFE code under CONFIG_PFE_WARN_WA
and CONFIG_UTIL_PE_DISABLED.


Calvin Johnson (2):
  drivers: net: pfe_eth: remove unused code under
CONFIG_UTIL_PE_DISABLED
  drivers: net: pfe_eth: remove unused code under CONFIG_PFE_WARN_WA

 drivers/net/pfe_eth/pfe.c  | 98 --
 drivers/net/pfe_eth/pfe_cmd.c  | 42 +---
 drivers/net/pfe_eth/pfe_driver.c   | 15 --
 drivers/net/pfe_eth/pfe_firmware.c |  3 --
 include/pfe_eth/pfe/pfe.h  |  8 
 5 files changed, 2 insertions(+), 164 deletions(-)

-- 
2.7.4

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[U-Boot] [PATCH 3/3] drivers: net: pfe_eth: cleanup typos and indent

[Calvin Johnson]

Typos are corrected.
Some sentences are rephrased.
Proper indentation added.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
---

 drivers/net/pfe_eth/pfe_driver.c | 33 +++--
 drivers/net/pfe_eth/pfe_eth.c| 12 ++--
 2 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
index 730aca2..2bb257a 100644
--- a/drivers/net/pfe_eth/pfe_driver.c
+++ b/drivers/net/pfe_eth/pfe_driver.c
@@ -16,14 +16,14 @@ static struct rx_desc_s *g_rx_desc;
  * Reads the rx descriptor from the current location (rx_to_read).
  * - If the descriptor has a valid data/pkt, then get the data pointer
  * - check for the input rx phy number
- * - increments the rx data pointer by pkt_head_room_size
- * - decrements the data length by pkt_head_room_size
+ * - increment the rx data pointer by pkt_head_room_size
+ * - decrement the data length by pkt_head_room_size
  * - handover the packet to caller.
  *
- * @param[out] pkt_ptr Pointer to store rx packet pointer
- * @param[out] phy_port Pointer to store recv phy port
+ * @param[out] pkt_ptr - Pointer to store rx packet
+ * @param[out] phy_port - Pointer to store recv phy port
  *
- * @return -1 if no packet, else returns length of packet.
+ * @return -1 if no packet, else return length of packet.
  */
 int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
 {
@@ -70,11 +70,10 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
 }
 
 /*
- * HIF to check the Rx done
- *  This function will check the rx done indication of the current rx_to_read
+ * HIF function to check the Rx done
+ * This function will check the rx done indication of the current rx_to_read
  * locations
- *  if success, moves the rx_to_read to next location.
- *
+ * if success, moves the rx_to_read to next location.
  */
 void pfe_rx_done(void)
 {
@@ -95,7 +94,7 @@ void pfe_rx_done(void)
  readl(>ctrl));
 
/* Give START_STROBE to BDP to fetch the descriptor __NOW__,
-* BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
+* BDP need not wait for rx_poll_cycle time to fetch the descriptor,
 * In idle state (ie., no rx pkt), BDP will not fetch
 * the descriptor even if strobe is given.
 */
@@ -107,16 +106,14 @@ void pfe_rx_done(void)
 
debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
 
-   return 0;
 }
 
 /*
  * HIF Tx interface function
  * This function sends a single packet to PFE from HIF interface.
  * - No interrupt indication on tx completion.
- * - After tx descriptor is updated and TX DMA is enabled.
- * - To support both chipit and read c2k environment, data is copied to
- *   tx buffers. After verification this copied can be avoided.
+ * - Data is copied to tx buffers before tx descriptor is updated
+ *   and TX DMA is enabled.
  *
  * @param[in] phy_port Phy port number to send out this packet
  * @param[in] data Pointer to the data
@@ -186,13 +183,13 @@ int pfe_send(int phy_port, void *data, int length)
 }
 
 /*
- * HIF to check the Tx done
- *  This function will chceck the tx done indication of the current tx_to_send
- * locations
+ * HIF function to check the Tx done
+ *  This function will check the tx done indication of the current tx_to_send
+ *  locations
  *  if success, moves the tx_to_send to next location.
  *
  * @return -1 if TX ownership bit is not cleared by hw.
- * else on success (tx done copletion) returns zero.
+ * else on success (tx done completion) return zero.
  */
 int pfe_tx_done(void)
 {
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
index 6d2906f..eccc2d6 100644
--- a/drivers/net/pfe_eth/pfe_eth.c
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -157,7 +157,7 @@ static int ls1012a_eth_send(struct eth_device *dev, void 
*data, int length)
rc = pfe_send(priv->gemac_port, data, length);
 
if (rc < 0) {
-   printf("Tx Q full\n");
+   printf("Tx Queue full\n");
return 0;
}
 
@@ -166,11 +166,11 @@ static int ls1012a_eth_send(struct eth_device *dev, void 
*data, int length)
if (rc == 0)
break;
 
-   udelay(100);
-   i++;
-   if (i == 3)
-   printf("Tx timeout, send failed\n");
-   break;
+   udelay(100);
+   i++;
+   if (i == 3)
+   printf("Tx timeout, send failed\n");
+   break;
}
 
return 0;
-- 
2.7.4

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[U-Boot] [PATCH 2/3] drivers: net: pfe_eth: use writel/readl to access hw bds

[Calvin Johnson]

writel/readl accessors should be used to access hardware
buffer descriptors.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---

 drivers/net/pfe_eth/pfe_driver.c | 70 
 1 file changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
index 55fc145..730aca2 100644
--- a/drivers/net/pfe_eth/pfe_driver.c
+++ b/drivers/net/pfe_eth/pfe_driver.c
@@ -35,18 +35,18 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
 
bd = rx_desc->rx_base + rx_desc->rx_to_read;
 
-   if (bd->ctrl & BD_CTRL_DESC_EN)
+   if (readl(>ctrl) & BD_CTRL_DESC_EN)
return len; /* No pending Rx packet */
 
-   /* this len include hif_header(8bytes) */
-   len = bd->ctrl & 0x;
+   /* this len include hif_header(8 bytes) */
+   len = readl(>ctrl) & 0x;
 
-   hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(bd->data);
+   hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(>data));
 
/* Get the recive port info from the packet */
debug(
"Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) 
status(%08x)\n",
-   hif_header, len, hif_header->port_no, bd->status);
+   hif_header, len, hif_header->port_no, readl(>status));
 
 #ifdef DEBUG
{
@@ -87,11 +87,12 @@ void pfe_rx_done(void)
bd = rx_desc->rx_base + rx_desc->rx_to_read;
 
/* reset the control field */
-   bd->ctrl = (MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
-   | BD_CTRL_DIR);
-   bd->status = 0;
+   writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
+   | BD_CTRL_DIR), >ctrl);
+   writel(0, >status);
 
-   debug("Rx Done : status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
+   debug("Rx Done : status: %08x, ctrl: %08x\n", readl(>status),
+ readl(>ctrl));
 
/* Give START_STROBE to BDP to fetch the descriptor __NOW__,
 * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
@@ -137,18 +138,16 @@ int pfe_send(int phy_port, void *data, int length)
bd = tx_desc->tx_base + tx_desc->tx_to_send;
 
/* check queue-full condition */
-   if (bd->ctrl & BD_CTRL_DESC_EN) {
-   printf("Tx queue full\n");
+   if (readl(>ctrl) & BD_CTRL_DESC_EN)
return -1;
-   }
 
/* PFE checks for min pkt size */
if (length < MIN_PKT_SIZE)
length = MIN_PKT_SIZE;
 
-   tx_buf_va = (void *)DDR_PFE_TO_VIRT(bd->data);
+   tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(>data));
debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va,
- bd->data);
+ readl(>data));
 
/* Fill the gemac/phy port number to send this packet out */
memset(_header, 0, sizeof(struct hif_header_s));
@@ -171,15 +170,13 @@ int pfe_send(int phy_port, void *data, int length)
}
 #endif
 
-   debug("before0: Tx Done, status: %08x, ctrl: %08x\n", bd->status,
- bd->ctrl);
+   debug("Tx Done: status: %08x, ctrl: %08x\n", readl(>status),
+ readl(>ctrl));
 
/* fill the tx desc */
-   bd->ctrl = (u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0x));
-   bd->status = 0;
-
-   /* NOTE: This code can be removed after verification */
-   bd->status = 0xF0;
+   writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0x)),
+  >ctrl);
+   writel(0, >status);
 
writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
 
@@ -208,15 +205,15 @@ int pfe_tx_done(void)
bd = tx_desc->tx_base + tx_desc->tx_to_send;
 
/* check queue-full condition */
-   if (bd->ctrl & BD_CTRL_DESC_EN)
+   if (readl(>ctrl) & BD_CTRL_DESC_EN)
return -1;
 
/* reset the control field */
-   bd->ctrl = 0;
-   /* bd->data = (u32)NULL; */
-   bd->status = 0;
+   writel(0, >ctrl);
+   writel(0, >status);
 
-   debug("Tx Done : status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
+   debug("Tx Done : status: %08x, ctrl: %08x\n", readl(>status),
+ readl(>ctrl));
 
/* increment the txtosend index to next location */
tx_desc->tx_to_send = (tx_desc->tx_to_send + 1)
@@ -248,7 +245,10 @@ static inline void hif_rx_desc_dump(void)
  rx_desc->rx_base_pa);
for (i = 0; i < rx_desc->rx_ring_size; i++) {
debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n",
-

[U-Boot] [PATCH 1/3] drivers: net: pfe_eth: add pfe_rx_done to clear bd after packet processing

[Calvin Johnson]

Create pfe_rx_done function to clear buffer descriptor
after the packet is processed by the network stack.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---

 drivers/net/pfe_eth/pfe_driver.c | 35 ++-
 drivers/net/pfe_eth/pfe_eth.c|  1 +
 include/pfe_eth/pfe_driver.h |  1 +
 3 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
index 5336ba7..55fc145 100644
--- a/drivers/net/pfe_eth/pfe_driver.c
+++ b/drivers/net/pfe_eth/pfe_driver.c
@@ -66,22 +66,47 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
*phy_port = hif_header->port_no;
len -= sizeof(struct hif_header_s);
 
-   rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
-  & (rx_desc->rx_ring_size - 1);
+   return len;
+}
+
+/*
+ * HIF to check the Rx done
+ *  This function will check the rx done indication of the current rx_to_read
+ * locations
+ *  if success, moves the rx_to_read to next location.
+ *
+ */
+void pfe_rx_done(void)
+{
+   struct rx_desc_s *rx_desc = g_rx_desc;
+   struct buf_desc *bd;
 
-   /* reset bd control field */
+   debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
+ rx_desc->rx_to_read);
+
+   bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+   /* reset the control field */
bd->ctrl = (MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
| BD_CTRL_DIR);
bd->status = 0;
 
+   debug("Rx Done : status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
+
/* Give START_STROBE to BDP to fetch the descriptor __NOW__,
 * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
 * In idle state (ie., no rx pkt), BDP will not fetch
-* the descriptor even if strobe is given(I think)
+* the descriptor even if strobe is given.
 */
writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
 
-   return len;
+   /* increment the rx_to_read index to next location */
+   rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
+  & (rx_desc->rx_ring_size - 1);
+
+   debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
+
+   return 0;
 }
 
 /*
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
index 4db823f..6d2906f 100644
--- a/drivers/net/pfe_eth/pfe_eth.c
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -198,6 +198,7 @@ static int ls1012a_eth_recv(struct eth_device *dev)
/* Pass the packet up to the protocol layers. */
net_process_received_packet((void *)(long int)pkt_buf, len);
 
+   pfe_rx_done();
return 0;
 }
 
diff --git a/include/pfe_eth/pfe_driver.h b/include/pfe_eth/pfe_driver.h
index 28997b4..2a539e2 100644
--- a/include/pfe_eth/pfe_driver.h
+++ b/include/pfe_eth/pfe_driver.h
@@ -51,5 +51,6 @@ struct tx_desc_s {
 int pfe_send(int phy_port, void *data, int length);
 int pfe_recv(unsigned int *pkt_ptr, int *phy_port);
 int pfe_tx_done(void);
+void pfe_rx_done(void);
 
 #endif
-- 
2.7.4

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[U-Boot] [PATCH 0/3] ls1012a: fix tftp failure

[Calvin Johnson]

This patch series fixes bug which fails tftp sometimes
while using the pfe interfaces and also has some code clean up.


Calvin Johnson (3):
  drivers: net: pfe_eth: add pfe_rx_done to clear bd after packet
processing
  drivers: net: pfe_eth: use writel/readl to access hw bds
  drivers: net: pfe_eth: cleanup typos and indent

 drivers/net/pfe_eth/pfe_driver.c | 126 +++
 drivers/net/pfe_eth/pfe_eth.c|  13 ++--
 include/pfe_eth/pfe_driver.h |   1 +
 3 files changed, 82 insertions(+), 58 deletions(-)

-- 
2.7.4

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Re: [U-Boot] Commands to use U-boot in fpga

[Calvin Johnson]

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Lukasz
> Majewski
> Sent: Friday, October 27, 2017 5:18 PM
> To: Ammu Lakshmy 
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] Commands to use U-boot in fpga
> 
> On Fri, 27 Oct 2017 16:45:16 +0530
> Ammu Lakshmy  wrote:
> 
> > Architecture is LEON2 and is supported by U-Boot.
> > But the steps involved in my work are
> >
> > *1. Implement LEON2 processor in FPGA(Spartan3E or any other fpga)*
> 
> Ok.
> 
> > *2. Deploy OS in that processor.*
> 
> When you have working soft core of LEON2 - then you would need:
> 
> - U-boot ported to it (and this is not the problem - since you say that
>   it is supported in U-Boot)

Ammu,  once you have working LEON2, I guess you can use U-Boot from 
https://github.com/qoriq-open-source/u-boot/tree/master/arch/sparc/cpu/leon2

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Re: [U-Boot] [PATCH 5/7] bootcount: add support for bootcounter on EXT filesystem

[Calvin Johnson]

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Martyn
> Welch
> Sent: Thursday, October 26, 2017 8:18 PM

> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index 5ee1601..b9580b9 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -175,6 +175,7 @@ CONFIG_BOOTCOMMAND
>  CONFIG_BOOTCOUNT_ALEN
>  CONFIG_BOOTCOUNT_AM33XX
>  CONFIG_BOOTCOUNT_ENV
> +CONFIG_BOOTCOUNT_EXT
>  CONFIG_BOOTCOUNT_I2C
>  CONFIG_BOOTCOUNT_LIMIT
>  CONFIG_BOOTCOUNT_RAM
> @@ -2368,6 +2369,9 @@ CONFIG_SYS_BOARD_VERSION
>  CONFIG_SYS_BOOK3E_HV
>  CONFIG_SYS_BOOTCOUNT_ADDR
>  CONFIG_SYS_BOOTCOUNT_BE
> +CONFIG_SYS_BOOTCOUNT_EXT_DEVPART
> +CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE
> +CONFIG_SYS_BOOTCOUNT_EXT_NAME
>  CONFIG_SYS_BOOTCOUNT_LE
>  CONFIG_SYS_BOOTCOUNT_SINGLEWORD
>  CONFIG_SYS_BOOTFILE_PREFIX

I think you have add these new configs to Kconfig instead of 
config_whitelist.txt.

Calvin
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[U-Boot] [PATCH] board: freescale: ls1012a: fix RGMII TX-delay issue

[Calvin Johnson]

Recently logic to enable RGMII TX-delay was changed by
commit 05b29aa0cb68 ("net: phy: realtek: fix enabling of the TX-delay
for RTL8211F")

Based on this, here we are enabling the TX-delay again using
PHY_INTERFACE_MODE_RGMII_TXID.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---

 board/freescale/ls1012ardb/eth.c | 2 +-
 drivers/net/pfe_eth/pfe_eth.c| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index 286bc8a..c0f6306 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -62,7 +62,7 @@ int board_eth_init(bd_t *bis)
/* MAC2 */
ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR,
-PHY_INTERFACE_MODE_RGMII);
+PHY_INTERFACE_MODE_RGMII_TXID);
 
cpu_eth_init(bis);
 #endif
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
index 8d8de40..4db823f 100644
--- a/drivers/net/pfe_eth/pfe_eth.c
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -27,7 +27,7 @@ struct gemac_s gem_info[] = {
 
/* phy iface */
.phy_address = EMAC2_PHY_ADDR,
-   .phy_mode = PHY_INTERFACE_MODE_RGMII,
+   .phy_mode = PHY_INTERFACE_MODE_RGMII_TXID,
},
 };
 
-- 
2.7.4

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[U-Boot] [PATCH 9/9] configs: ls1012a: add pfe configuration for LS1012A

[Calvin Johnson]

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
 configs/ls1012afrdm_qspi_defconfig |  1 +
 configs/ls1012aqds_qspi_defconfig  |  1 +
 configs/ls1012ardb_qspi_defconfig  |  1 +
 drivers/net/Kconfig|  1 +
 drivers/net/Makefile   |  1 +
 drivers/net/pfe_eth/Kconfig| 23 ++-
 include/configs/ls1012a_common.h   |  6 +++---
 include/configs/ls1012afrdm.h  |  7 +++
 include/configs/ls1012aqds.h   | 14 ++
 include/configs/ls1012ardb.h   |  8 
 10 files changed, 59 insertions(+), 4 deletions(-)

diff --git a/configs/ls1012afrdm_qspi_defconfig 
b/configs/ls1012afrdm_qspi_defconfig
index 84b5577..7db7a18 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -32,6 +32,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012aqds_qspi_defconfig 
b/configs/ls1012aqds_qspi_defconfig
index 2124273..4b9fdf5 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -37,6 +37,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012ardb_qspi_defconfig 
b/configs/ls1012ardb_qspi_defconfig
index 40349ce..d63e736 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -35,6 +35,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 736aab2..c82c63b 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -304,4 +304,5 @@ config FEC2_PHY_NORXERR
  The PHY does not have a RXERR line (RMII only).
  (so program the FEC to ignore it).
 
+source "drivers/net/pfe_eth/Kconfig"
 endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 94a4fd8..0572cde 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_FSL_PFE) += pfe_eth/
diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
index b9996df..c05aeda 100644
--- a/drivers/net/pfe_eth/Kconfig
+++ b/drivers/net/pfe_eth/Kconfig
@@ -1,8 +1,29 @@
+menuconfig FSL_PFE
+   bool "Freescale PFE driver"
+   help
+ This driver provides support for Freescale PFE.
+
+if FSL_PFE
+
 config UTIL_PE_DISABLED
bool
help
  Disable UTIL processor engine of PFE
 
-config SYS_FSL_PPFE_ADDR
+config SYS_FSL_PFE_ADDR
hex "PFE base address"
default 0x0400
+
+config SYS_LS_PFE_FW_ADDR
+   hex "Flash address of PFE firmware"
+   default 0x40a0
+
+config DDR_PFE_PHYS_BASEADDR
+   hex "PFE DDR physical base address"
+   default 0x0380
+
+config DDR_PFE_BASEADDR
+   hex "PFE DDR base address"
+   default 0x8380
+
+endif
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 52c2c3a..3df5586 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -113,9 +113,9 @@
 #define CONFIG_BOOTARGS"console=ttyS0,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500 quiet 
lpj=25"
 #undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
-   "$kernel_start $kernel_size && "\
-   "bootm $kernel_load"
+#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
+   "$kernel_start $kernel_size && "\
+   "bootm $kernel_load"
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE  512 /* Console I/O Buffer Size */
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index 544dea0..a3f8824 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -9,6 +9,13 @@
 
 #include "ls1012a_common.h"
 
+#ifdef CONFIG_FSL_PFE
+#define EMAC1_PHY_ADDR  0x2
+#define EMAC2_PHY_ADDR  0x1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_REALTEK
+#endif
+
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   1
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 16714bb..9873339 

[U-Boot] [PATCH 8/9] fsl: csu: enable ns access for PFE

[Calvin Johnson]

Enable non-secure access for PFE block.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h 
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index f46f1d8..fe97a93 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -26,6 +26,7 @@ enum csu_cslx_ind {
CSU_CSLX_PCIE3_IO,
CSU_CSLX_USB3 = 20,
CSU_CSLX_USB2,
+   CSU_CSLX_PFE = 23,
CSU_CSLX_SERDES = 32,
CSU_CSLX_QDMA,
CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
 {CSU_CSLX_USB3, CSU_ALL_RW},
 {CSU_CSLX_USB2, CSU_ALL_RW},
+{CSU_CSLX_PFE, CSU_ALL_RW},
 {CSU_CSLX_SERDES, CSU_ALL_RW},
 {CSU_CSLX_QDMA, CSU_ALL_RW},
 {CSU_CSLX_LPUART2, CSU_ALL_RW},
-- 
2.7.4

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[U-Boot] [PATCH 7/9] armv8: fsl-lsch2: configure pfe's scfg & dcfg registers

[Calvin Johnson]

Define init_pfe_scfg_dcfg_regs to configure scfg and dcfg
registers of pfe.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 18 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  3 +++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 5c429d4..c6815f3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -577,6 +577,24 @@ int setup_chip_volt(void)
return 0;
 }
 
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   out_be32(>pfeasbcr,
+in_be32(>pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+   out_be32(>pfebsbcr,
+in_be32(>pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+   /* CCI-400 QoS settings for PFE */
+   out_be32(>wr_qos1, 0x0ff0);
+   out_be32(>rd_qos1, 0x0ff0);
+
+   out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x524, 0x2000);
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 697f072..08a42b9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -120,6 +120,9 @@ void fsl_lsch2_early_init_f(void);
 int setup_chip_volt(void);
 /* Setup core vdd in unit mV */
 int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
 #endif
 void ddr_enable_0v9_volt(bool en);
 
-- 
2.7.4

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[U-Boot] [PATCH 6/9] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure

[Calvin Johnson]

SoC specific PFE macros are defined and structure ccsr_scfg
is updated with members defined for PFE.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 38 --
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 0f43832..a395a2f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -398,6 +398,21 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
 #define SCFG_SNPCNFGCR_SATAWRSNP   0x0040
 
+/* RGMIIPCR bit definitions*/
+#define SCFG_RGMIIPCR_EN_AUTO  (0x0008)
+#define SCFG_RGMIIPCR_SETSP_1000M  (0x0004)
+#define SCFG_RGMIIPCR_SETSP_100M   (0x)
+#define SCFG_RGMIIPCR_SETSP_10M(0x0002)
+#define SCFG_RGMIIPCR_SETFD(0x0001)
+
+/*PFEASBCR bit definitions */
+#define SCFG_PFEASBCR_ARCACHE0 (0x8000)
+#define SCFG_PFEASBCR_AWCACHE0 (0x4000)
+#define SCFG_PFEASBCR_ARCACHE1 (0x2000)
+#define SCFG_PFEASBCR_AWCACHE1 (0x1000)
+#define SCFG_PFEASBCR_ARSNP(0x0800)
+#define SCFG_PFEASBCR_AWSNP(0x0400)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u8 res_000[0x100-0x000];
@@ -415,7 +430,12 @@ struct ccsr_scfg {
u8 res_140[0x158-0x140];
u32 altcbar;
u32 qspi_cfg;
-   u8 res_160[0x180-0x160];
+   u8 res_160[0x164-0x160];
+   u32 wr_qos1;
+   u32 wr_qos2;
+   u32 rd_qos1;
+   u32 rd_qos2;
+   u8 res_174[0x180-0x174];
u32 dmamcr;
u8 res_184[0x188-0x184];
u32 gic_align;
@@ -446,7 +466,21 @@ struct ccsr_scfg {
u32 usb_refclk_selcr1;
u32 usb_refclk_selcr2;
u32 usb_refclk_selcr3;
-   u8 res_424[0x600-0x424];
+   u8 res_424[0x434-0x424];
+   u32 rgmiipcr;
+   u32 res_438;
+   u32 rgmiipsr;
+   u32 pfepfcssr1;
+   u32 pfeintencr1;
+   u32 pfepfcssr2;
+   u32 pfeintencr2;
+   u32 pfeerrcr;
+   u32 pfeeerrintencr;
+   u32 pfeasbcr;
+   u32 pfebsbcr;
+   u8 res_460[0x484-0x460];
+   u32 mdioselcr;
+   u8 res_468[0x600-0x488];
u32 scratchrw[4];
u8 res_610[0x680-0x610];
u32 corebcr;
-- 
2.7.4

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[U-Boot] [PATCH 5/9] armv8: fsl-lsch2: initialize pfe gemac

[Calvin Johnson]

Call gemac_initialize to initialize both gemacs of pfe.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ef3e300..25cd8d7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -21,6 +21,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_FSL_PFE
+#include 
+#endif
 #ifdef CONFIG_FSL_ESDHC
 #include 
 #endif
@@ -476,6 +479,11 @@ int cpu_eth_init(bd_t *bis)
 {
int error = 0;
 
+#if defined(CONFIG_FSL_PFE)
+   gemac_initialize(bis, 0 , "pfe_eth0");
+   gemac_initialize(bis, 1 , "pfe_eth1");
+#endif
+
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
error = fsl_mc_ldpaa_init(bis);
 #endif
-- 
2.7.4

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[U-Boot] [PATCH 4/9] board: freescale: ls1012a: enable network support on ls1012a platforms

[Calvin Johnson]

Ethernet support on all three LS1012A platforms(FRDM, QDS and RDB) is
enabled with this patch.

eth.c files for all 3 platforms contain board ethernet initialization
function and also function to reset phy.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
 board/freescale/ls1012afrdm/Makefile  |   1 +
 board/freescale/ls1012afrdm/eth.c |  86 +
 board/freescale/ls1012afrdm/ls1012afrdm.c |   5 -
 board/freescale/ls1012aqds/Makefile   |   1 +
 board/freescale/ls1012aqds/eth.c  | 263 ++
 board/freescale/ls1012aqds/ls1012aqds.c   |  97 +-
 board/freescale/ls1012aqds/ls1012aqds_pfe.h   |  48 +
 board/freescale/ls1012aqds/ls1012aqds_qixis.h |   2 +-
 board/freescale/ls1012ardb/Makefile   |   1 +
 board/freescale/ls1012ardb/eth.c  |  70 +++
 board/freescale/ls1012ardb/ls1012ardb.c   |   4 -
 include/configs/ls1012ardb.h  |   5 +
 12 files changed, 568 insertions(+), 15 deletions(-)
 create mode 100644 board/freescale/ls1012afrdm/eth.c
 create mode 100644 board/freescale/ls1012aqds/eth.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h
 create mode 100644 board/freescale/ls1012ardb/eth.c

diff --git a/board/freescale/ls1012afrdm/Makefile 
b/board/freescale/ls1012afrdm/Makefile
index dbfa2ce..1364f22 100644
--- a/board/freescale/ls1012afrdm/Makefile
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012afrdm.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012afrdm/eth.c 
b/board/freescale/ls1012afrdm/eth.c
new file mode 100644
index 000..d9583ce
--- /dev/null
+++ b/board/freescale/ls1012afrdm/eth.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#define MASK_ETH_PHY_RST   0x0100
+
+void reset_phy(void)
+{
+   unsigned int val;
+   struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+
+   setbits_be32(>gpdir, MASK_ETH_PHY_RST);
+
+   val = in_be32(>gpdat);
+   setbits_be32(>gpdat, val & ~MASK_ETH_PHY_RST);
+   mdelay(10);
+
+   val = in_be32(>gpdat);
+   setbits_be32(>gpdat, val | MASK_ETH_PHY_RST);
+   mdelay(50);
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_PFE
+   struct mii_dev *bus;
+   struct mdio_info mac1_mdio_info;
+
+   reset_phy();
+
+   init_pfe_scfg_dcfg_regs();
+
+   mac1_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+   mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+   bus = ls1012a_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+
+   /* We don't really need this MDIO bus,
+* this is called just to initialize EMAC2 MDIO interface */
+   mac1_mdio_info.reg_base = (void *)0x0422; /*EMAC2_BASE_ADDR*/
+   mac1_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+
+   bus = ls1012a_mdio_init(_mdio_info);
+   if (!bus) {
+   printf("Failed to register mdio\n");
+   return -1;
+   }
+
+   /* MAC1 */
+   ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+   ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+
+   /* MAC2 */
+   ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+   ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR,
+PHY_INTERFACE_MODE_SGMII);
+
+
+   return cpu_eth_init(bis);
+#endif
+}
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c 
b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 9afd1c4..0145886 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -57,11 +57,6 @@ int dram_init(void)
return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-   return pci_eth_init(bis);
-}
-
 int board_early_init_f(void)
 {
fsl_lsch2_early_init_f();
diff --git a/board/freescale/ls1012aqds/Makefile 
b/board/freescale/ls1012aqds/Makefile
index 0b813f9..b18494a 100644
--- a/board/freescale/ls1012aqds/Makefile
+++ b/board/freescale/ls1012aqds/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012aqds.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
new file mode 100644
index 000..bf916f3
--- /dev/null
+++ b/board/freescale/ls1012aqds/eth.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:  

[U-Boot] [PATCH 3/9] drivers: net: pfe_eth: LS1012A PFE headers

[Calvin Johnson]

Contains all the pfe header files.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
 include/pfe_eth/pfe/cbus.h   |  75 +++
 include/pfe_eth/pfe/cbus/bmu.h   |  40 
 include/pfe_eth/pfe/cbus/class_csr.h | 181 +++
 include/pfe_eth/pfe/cbus/emac.h  | 150 +
 include/pfe_eth/pfe/cbus/gpi.h   |  62 
 include/pfe_eth/pfe/cbus/hif.h   |  68 +
 include/pfe_eth/pfe/cbus/hif_nocpy.h |  40 
 include/pfe_eth/pfe/cbus/tmu_csr.h   | 148 
 include/pfe_eth/pfe/cbus/util_csr.h  |  47 +
 include/pfe_eth/pfe/pfe.h| 178 ++
 include/pfe_eth/pfe_driver.h |  55 +++
 include/pfe_eth/pfe_eth.h| 111 +
 include/pfe_eth/pfe_firmware.h   |  17 
 13 files changed, 1172 insertions(+)
 create mode 100644 include/pfe_eth/pfe/cbus.h
 create mode 100644 include/pfe_eth/pfe/cbus/bmu.h
 create mode 100644 include/pfe_eth/pfe/cbus/class_csr.h
 create mode 100644 include/pfe_eth/pfe/cbus/emac.h
 create mode 100644 include/pfe_eth/pfe/cbus/gpi.h
 create mode 100644 include/pfe_eth/pfe/cbus/hif.h
 create mode 100644 include/pfe_eth/pfe/cbus/hif_nocpy.h
 create mode 100644 include/pfe_eth/pfe/cbus/tmu_csr.h
 create mode 100644 include/pfe_eth/pfe/cbus/util_csr.h
 create mode 100644 include/pfe_eth/pfe/pfe.h
 create mode 100644 include/pfe_eth/pfe_driver.h
 create mode 100644 include/pfe_eth/pfe_eth.h
 create mode 100644 include/pfe_eth/pfe_firmware.h

diff --git a/include/pfe_eth/pfe/cbus.h b/include/pfe_eth/pfe/cbus.h
new file mode 100644
index 000..ec31481
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#include "cbus/emac.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+
+#define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR)
+
+/* PFE Control and Status Register Desciption */
+#define EMAC1_BASE_ADDR(CBUS_BASE_ADDR + 0x20)
+#define EGPI1_BASE_ADDR(CBUS_BASE_ADDR + 0x21)
+#define EMAC2_BASE_ADDR(CBUS_BASE_ADDR + 0x22)
+#define EGPI2_BASE_ADDR(CBUS_BASE_ADDR + 0x23)
+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x24)
+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x25)
+#define ARB_BASE_ADDR  (CBUS_BASE_ADDR + 0x26)
+#define DDR_CONFIG_BASE_ADDR   (CBUS_BASE_ADDR + 0x27)
+#define HIF_BASE_ADDR  (CBUS_BASE_ADDR + 0x28)
+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x29)
+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x30)
+#define LMEM_SIZE  0x1
+#define LMEM_END   (LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR  (CBUS_BASE_ADDR + 0x31)
+#define CLASS_CSR_BASE_ADDR(CBUS_BASE_ADDR + 0x32)
+#define HIF_NOCPY_BASE_ADDR(CBUS_BASE_ADDR + 0x35)
+#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x36)
+#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x37)
+
+/*
+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
+ * XXX_MEM_ACCESS_ADDR register bit definitions.
+ */
+/* Internal Memory Write. */
+#define PE_MEM_ACCESS_WRITE(1<<31)
+/* Internal Memory Read. */
+#define PE_MEM_ACCESS_READ (0<<31)
+
+#define PE_MEM_ACCESS_IMEM (1<<15)
+#define PE_MEM_ACCESS_DMEM (1<<16)
+/* Byte Enables of the Internal memory access. These are interpred in BE */
+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size)(1 << (size)) - 1) 
<< (4 \
+   - (offset) - (size)))\
+   & 0xf) << 24)
+/* PFE cores states */
+#define CORE_DISABLE   0x
+#define CORE_ENABLE0x0001
+#define CORE_SW_RESET  0x0002
+
+/* LMEM defines */
+#define LMEM_HDR_SIZE  0x0010
+#define LMEM_BUF_SIZE_LN2  0x7
+#define LMEM_BUF_SIZE  (1 << LMEM_BUF_SIZE_LN2)
+
+/* DDR defines */
+#define DDR_HDR_SIZE   0x0100
+#define DDR_BUF_SIZE_LN2   0xb
+#define DDR_BUF_SIZE   (1 << DDR_BUF_SIZE_LN2)
+
+/* Clock generation through PLL */
+#define PLL_CLK_EN 1
+
+#endif /* _CBUS_H_ */
diff --git a/include/pfe_eth/pfe/cbus/bmu.h b/include/pfe_eth/pfe/cbus/bmu.h
new file mode 100644
index 000..f707cc3
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus/bmu.h
@@ -0,0 +1,40 @@

[U-Boot] [PATCH 2/9] drivers: net: pfe_eth: provide pfe commands

[Calvin Johnson]

pfe_command provides command line support for several features that
support pfe like starting or stopping the pfe, checking the health
of the processor engines and checking status of different unit inside
pfe.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
 drivers/net/pfe_eth/Makefile  |   1 +
 drivers/net/pfe_eth/pfe_cmd.c | 537 ++
 2 files changed, 538 insertions(+)
 create mode 100644 drivers/net/pfe_eth/pfe_cmd.c

diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
index e78f1bf..3e88e53 100644
--- a/drivers/net/pfe_eth/Makefile
+++ b/drivers/net/pfe_eth/Makefile
@@ -5,6 +5,7 @@
 
 # Layerscape PFE driver
 obj-y += pfe.o \
+pfe_cmd.o  \
 pfe_driver.o   \
 pfe_eth.o  \
 pfe_firmware.o
diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
new file mode 100644
index 000..74f7c3d
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_cmd.c
@@ -0,0 +1,537 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * @file
+ * @brief PFE utility commands
+ */
+
+#include 
+
+static inline void pfe_command_help(void)
+{
+   printf("Usage: pfe [pe | status | expt ] \n");
+}
+
+static void pfe_command_pe(int argc, char * const argv[])
+{
+   if (argc >= 3 && strcmp(argv[2], "pmem") == 0) {
+   if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+   int i;
+   int num;
+   int id;
+   u32 addr;
+   u32 size;
+   u32 val;
+
+   if (argc == 7) {
+   num = simple_strtoul(argv[6], NULL, 0);
+   } else if (argc == 6) {
+   num = 1;
+   } else {
+   printf("Usage: pfe pe pmem read   
[]\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   addr = simple_strtoul(argv[5], NULL, 16);
+   size = 4;
+
+   for (i = 0; i < num; i++, addr += 4) {
+   val = pe_pmem_read(id, addr, size);
+   val = be32_to_cpu(val);
+   if (!(i&3))
+   printf("%08x: ", addr);
+   printf("%08x%s", val, i == num - 1 || (i & 3)
+  == 3 ? "\n" : " ");
+   }
+
+   } else {
+   printf("Usage: pfe pe pmem read \n");
+   }
+   } else if (argc >= 3 && strcmp(argv[2], "dmem") == 0) {
+   if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+   int i;
+   int num;
+   int id;
+   u32 addr;
+   u32 size;
+   u32 val;
+
+   if (argc == 7) {
+   num = simple_strtoul(argv[6], NULL, 0);
+   } else if (argc == 6) {
+   num = 1;
+   } else {
+   printf("Usage: pfe pe dmem read   
[]\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   addr = simple_strtoul(argv[5], NULL, 16);
+   size = 4;
+
+   for (i = 0; i < num; i++, addr += 4) {
+   val = pe_dmem_read(id, addr, size);
+   val = be32_to_cpu(val);
+   if (!(i&3))
+   printf("%08x: ", addr);
+   printf("%08x%s", val, i == num - 1 || (i & 3)
+  == 3 ? "\n" : " ");
+   }
+
+   } else if (argc >= 4 && strcmp(argv[3], "write") == 0) {
+   int id;
+   u32 val;
+   u32 addr;
+   u32 size;
+
+   if (argc != 7) {
+   printf("Usage: pfe pe dmem write   
\n");
+   return;
+   }
+
+   id = simple_strtoul(argv[4], NULL, 0);
+   val = simple_strtoul(argv[5], NULL, 16);
+

[U-Boot] [PATCH 1/9] drivers: net: pfe_eth: LS1012A PFE driver introduction

[Calvin Johnson]

This patch adds PFE driver into U-Boot.

Following are the main driver files:-
pfe.c: provides low level helper functions to initialize PFE internal
processor engines and other hardware blocks.
pfe_driver.c: provides probe functions, initialization functions
and packet send and receive functions.
pfe_eth.c: provides high level gemac, phy and mdio initialization
functions.
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.

Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
---
 drivers/net/pfe_eth/Kconfig|8 +
 drivers/net/pfe_eth/Makefile   |   10 +
 drivers/net/pfe_eth/pfe.c  | 1161 
 drivers/net/pfe_eth/pfe_driver.c   |  626 +++
 drivers/net/pfe_eth/pfe_eth.c  |  545 +
 drivers/net/pfe_eth/pfe_firmware.c |  230 +++
 6 files changed, 2580 insertions(+)
 create mode 100644 drivers/net/pfe_eth/Kconfig
 create mode 100644 drivers/net/pfe_eth/Makefile
 create mode 100644 drivers/net/pfe_eth/pfe.c
 create mode 100644 drivers/net/pfe_eth/pfe_driver.c
 create mode 100644 drivers/net/pfe_eth/pfe_eth.c
 create mode 100644 drivers/net/pfe_eth/pfe_firmware.c

diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
new file mode 100644
index 000..b9996df
--- /dev/null
+++ b/drivers/net/pfe_eth/Kconfig
@@ -0,0 +1,8 @@
+config UTIL_PE_DISABLED
+   bool
+   help
+ Disable UTIL processor engine of PFE
+
+config SYS_FSL_PPFE_ADDR
+   hex "PFE base address"
+   default 0x0400
diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
new file mode 100644
index 000..e78f1bf
--- /dev/null
+++ b/drivers/net/pfe_eth/Makefile
@@ -0,0 +1,10 @@
+# Copyright 2015-2016 Freescale Semiconductor, Inc.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:GPL-2.0+
+
+# Layerscape PFE driver
+obj-y += pfe.o \
+pfe_driver.o   \
+pfe_eth.o  \
+pfe_firmware.o
diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
new file mode 100644
index 000..fc6631e
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe.c
@@ -0,0 +1,1161 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+
+void *ddr_base_addr;
+unsigned long ddr_phys_base_addr;
+static struct pe_info pe[MAX_PE];
+
+/*
+ * Initializes the PFE library.
+ * Must be called before using any of the library functions.
+ *
+ * @param[in] cbus_baseCBUS virtual base address (as mapped in
+ * the host CPU address space)
+ * @param[in] ddr_base DDR virtual base address (as mapped in
+ * the host CPU address space)
+ * @param[in] ddr_phys_baseDDR physical base address (as mapped in
+ * platform)
+ */
+void pfe_lib_init(void *ddr_base, unsigned long ddr_phys_base)
+{
+   ddr_base_addr = ddr_base;
+   ddr_phys_base_addr = ddr_phys_base;
+
+   pe[CLASS0_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(0);
+   pe[CLASS0_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(0);
+   pe[CLASS0_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
+   pe[CLASS0_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
+   pe[CLASS0_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
+   pe[CLASS0_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
+
+   pe[CLASS1_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(1);
+   pe[CLASS1_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(1);
+   pe[CLASS1_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
+   pe[CLASS1_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
+   pe[CLASS1_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
+   pe[CLASS1_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
+
+   pe[CLASS2_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(2);
+   pe[CLASS2_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(2);
+   pe[CLASS2_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
+   pe[CLASS2_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
+   pe[CLASS2_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
+   pe[CLASS2_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
+
+   pe[CLASS3_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(3);
+   pe[CLASS3_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(3);
+   pe[CLASS3_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
+   pe[CLASS3_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
+   pe[CLASS3_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
+   pe[CLASS3_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
+
+   pe[CLASS4_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(4);
+   pe[CLASS4_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(4);
+   pe[CLASS4_ID].pmem_size = (u32)CLASS_IMEM_SIZE

[U-Boot] [PATCH 0/9] LS1012A PFE driver patch series

[Calvin Johnson]

Hi,

This patch series introduces U-Boot support for NXP's LS1012A Packet Forwarding
Engine (pfe_eth). LS1012A uses hardware packet forwarding engine to provide
high performance Ethernet interfaces. The device includes two Ethernet ports.

Depends on https://patchwork.ozlabs.org/patch/704305

Regards
Calvin

Calvin Johnson (9):
  drivers: net: pfe_eth: LS1012A PFE driver introduction
  drivers: net: pfe_eth: provide pfe commands
  drivers: net: pfe_eth: LS1012A PFE headers
  board: freescale: ls1012a: enable network support on ls1012a platforms
  armv8: fsl-lsch2: initialize pfe gemac
  armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
  armv8: fsl-lsch2: configure pfe's scfg & dcfg registers
  fsl: csu: enable ns access for PFE
  configs: ls1012a: add pfe configuration for LS1012A

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|8 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   18 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   38 +-
 .../include/asm/arch-fsl-layerscape/ns_access.h|2 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |3 +
 board/freescale/ls1012afrdm/Makefile   |1 +
 board/freescale/ls1012afrdm/eth.c  |   86 ++
 board/freescale/ls1012afrdm/ls1012afrdm.c  |5 -
 board/freescale/ls1012aqds/Makefile|1 +
 board/freescale/ls1012aqds/eth.c   |  263 +
 board/freescale/ls1012aqds/ls1012aqds.c|   97 +-
 board/freescale/ls1012aqds/ls1012aqds_pfe.h|   48 +
 board/freescale/ls1012aqds/ls1012aqds_qixis.h  |2 +-
 board/freescale/ls1012ardb/Makefile|1 +
 board/freescale/ls1012ardb/eth.c   |   70 ++
 board/freescale/ls1012ardb/ls1012ardb.c|4 -
 configs/ls1012afrdm_qspi_defconfig |1 +
 configs/ls1012aqds_qspi_defconfig  |1 +
 configs/ls1012ardb_qspi_defconfig  |1 +
 drivers/net/Kconfig|1 +
 drivers/net/Makefile   |1 +
 drivers/net/pfe_eth/Kconfig|   29 +
 drivers/net/pfe_eth/Makefile   |   11 +
 drivers/net/pfe_eth/pfe.c  | 1161 
 drivers/net/pfe_eth/pfe_cmd.c  |  537 +
 drivers/net/pfe_eth/pfe_driver.c   |  626 +++
 drivers/net/pfe_eth/pfe_eth.c  |  545 +
 drivers/net/pfe_eth/pfe_firmware.c |  230 
 include/configs/ls1012a_common.h   |6 +-
 include/configs/ls1012afrdm.h  |7 +
 include/configs/ls1012aqds.h   |   14 +
 include/configs/ls1012ardb.h   |   13 +
 include/pfe_eth/pfe/cbus.h |   75 ++
 include/pfe_eth/pfe/cbus/bmu.h |   40 +
 include/pfe_eth/pfe/cbus/class_csr.h   |  181 +++
 include/pfe_eth/pfe/cbus/emac.h|  150 +++
 include/pfe_eth/pfe/cbus/gpi.h |   62 ++
 include/pfe_eth/pfe/cbus/hif.h |   68 ++
 include/pfe_eth/pfe/cbus/hif_nocpy.h   |   40 +
 include/pfe_eth/pfe/cbus/tmu_csr.h |  148 +++
 include/pfe_eth/pfe/cbus/util_csr.h|   47 +
 include/pfe_eth/pfe/pfe.h  |  178 +++
 include/pfe_eth/pfe_driver.h   |   55 +
 include/pfe_eth/pfe_eth.h  |  111 ++
 include/pfe_eth/pfe_firmware.h |   17 +
 45 files changed, 4983 insertions(+), 20 deletions(-)
 create mode 100644 board/freescale/ls1012afrdm/eth.c
 create mode 100644 board/freescale/ls1012aqds/eth.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h
 create mode 100644 board/freescale/ls1012ardb/eth.c
 create mode 100644 drivers/net/pfe_eth/Kconfig
 create mode 100644 drivers/net/pfe_eth/Makefile
 create mode 100644 drivers/net/pfe_eth/pfe.c
 create mode 100644 drivers/net/pfe_eth/pfe_cmd.c
 create mode 100644 drivers/net/pfe_eth/pfe_driver.c
 create mode 100644 drivers/net/pfe_eth/pfe_eth.c
 create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
 create mode 100644 include/pfe_eth/pfe/cbus.h
 create mode 100644 include/pfe_eth/pfe/cbus/bmu.h
 create mode 100644 include/pfe_eth/pfe/cbus/class_csr.h
 create mode 100644 include/pfe_eth/pfe/cbus/emac.h
 create mode 100644 include/pfe_eth/pfe/cbus/gpi.h
 create mode 100644 include/pfe_eth/pfe/cbus/hif.h
 create mode 100644 include/pfe_eth/pfe/cbus/hif_nocpy.h
 create mode 100644 include/pfe_eth/pfe/cbus/tmu_csr.h
 create mode 100644 include/pfe_eth/pfe/cbus/util_csr.h
 create mode 100644 include/pfe_eth/pfe/pfe.h
 create mode 100644 include/pfe_eth/pfe_driver.h
 create mode 100644 include/pfe_eth/pfe_eth.h
 create mode 100644 include/pfe_eth/pfe_firmware.h

-- 
2.7.4

___
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Re: [U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization

[Calvin Johnson]

Hi York,

>-Original Message-
>From: york sun
>Sent: Wednesday, October 26, 2016 10:09 PM
>To: Calvin Johnson <calvin.john...@nxp.com>; Prabhakar Kushwaha 
><prabhakar.kushw...@nxp.com>; Pratiyush
>Srivastava <pratiyush.srivast...@nxp.com>; u-boot@lists.denx.de; Mingkai Hu 
><mingkai...@nxp.com>
>Cc: Hou Zhiqiang <zhiqiang@freescale.com>
>Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization
>
>On 10/24/2016 09:30 PM, Calvin Johnson wrote:
>
>>>>> I wonder why we don't see ECC errors before this patch. We have
>>>>> LS1043A boots on NAND, SD.
>>>>>
>>>>
>>>> OCRAM has a requirement of initializing before first time "read".
>>>> If user reads OCRAM before **initializing**; ECC error will come.  (u-boot 
>>>> is not handling this error for now).
>>>>
>>>> I can only guess the reason of not seeing this error as OCRAM never read 
>>>> before any write.
>>>> Even in case of Stack, data is first written and then read.
>>>>
>>>
>>> Is there a case you want to read from OCRAM before writing anything to it? 
>>> Why don't we need to do so for SPL or
>LSCH3?
>>
>> This issue will be seen ONLY in secure boot. It was reproduced on LS1043A 
>> also.
>>
>
>How about LSCH3? We have LS2080A secure boot.

I don't know about LS2080A. Prabhakar or Ruchika(copied) may be able to comment 
on this.

Regards
Calvin
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Re: [U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization

[Calvin Johnson]

Hi York,

>-Original Message-
>From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york sun
>Sent: Monday, October 24, 2016 9:45 PM
>To: Prabhakar Kushwaha ; Pratiyush Srivastava 
>; u-
>b...@lists.denx.de; Mingkai Hu 
>Cc: Hou Zhiqiang 
>Subject: Re: [U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization
>
>On 10/23/2016 06:59 AM, Prabhakar Kushwaha wrote:
>> Hi York,
>>
>>
>>> -Original Message-
>>> From: york sun
>>> Sent: Saturday, October 22, 2016 1:39 AM
>>> To: Prabhakar Kushwaha ; Pratiyush
>>> Srivastava ; u-boot@lists.denx.de;
>>> Mingkai Hu 
>>> Cc: Hou Zhiqiang 
>>> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization
>>>
>>> On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote:
 Hi Mingkai,

> -Original Message-
> From: Pratiyush Srivastava [mailto:pratiyush.srivast...@nxp.com]
> Sent: Wednesday, October 12, 2016 5:46 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Prabhakar Kushwaha
> ; Pratiyush Srivastava
> ; Hou Zhiqiang
>>> 
> Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization
>
> Clear the content to zero and the ECC error bit of OCRAM1/2.
>
> The OCRAM must be initialized to ZERO by the unit of 8-Byte before
> accessing it, or else it will generate ECC error. And the IBR has
> accessed the OCRAM before this initialization, so the ECC error
> status bit should to be cleared.
>
> Signed-off-by: Pratiyush Srivastava 
> Signed-off-by: Hou Zhiqiang 
> Signed-off-by: Prabhakar Kushwaha 
> ---

 This requirement is for both ls1043 and ls1088a.  was this patch
 taken care
>>> during ls1043a upstreaming
 If not, how it is being taken care for ls1043a.  Same approach can
 be used for
>>> ls1088a

>>>
>>> I wonder why we don't see ECC errors before this patch. We have
>>> LS1043A boots on NAND, SD.
>>>
>>
>> OCRAM has a requirement of initializing before first time "read".
>> If user reads OCRAM before **initializing**; ECC error will come.  (u-boot 
>> is not handling this error for now).
>>
>> I can only guess the reason of not seeing this error as OCRAM never read 
>> before any write.
>> Even in case of Stack, data is first written and then read.
>>
>
>Is there a case you want to read from OCRAM before writing anything to it? Why 
>don't we need to do so for SPL or LSCH3?

This issue will be seen ONLY in secure boot. It was reproduced on LS1043A also.

Regards
Calvin
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Re: [U-Boot] [Patch v2] fsl-layerscape: fdt: add IFC fixup if no IFC is avaliable in U-Boot

[Calvin Johnson]

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Scott Wood
> Sent: Tuesday, May 03, 2016 10:02 AM
> To: Qianyu Gong ; u-boot@lists.denx.de; york sun
> 
> Cc: Mingkai Hu 
> Subject: Re: [U-Boot] [Patch v2] fsl-layerscape: fdt: add IFC fixup if no IFC 
> is
> avaliable in U-Boot
> 
> On Thu, 2016-04-28 at 14:04 +0800, Gong Qianyu wrote:
> > IFC is considered as a required component in Layerscape platforms' Linux.
> 

I don't think IFC is considered as a required component on all SoCs. The 
LS1012A does not have IFC.

> What does this mean?
> 
> > But if IFC is not enabled in U-Boot on some boards, accessing IFC
> > memory space would cause kernel call trace. So disable IFC node in such
> cases.
> 
> That's the symptom, not the problem.  The problem is that the kernel is
> assuming that U-Boot has done certain initialization, such as the chipselect
> registers, and clearing SRAM (though Linux really should be doing the latter).
>  Why is U-Boot being configured without this?
> 
> -Scott
> 
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Calvin
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Calvin Johnson]

Hi Denis,


> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Wolfgang
> Denk
> Sent: Monday, February 08, 2016 5:53 PM
> To: Bakhvalov, Denis (Nokia - PL/Wroclaw) 
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] Problem with mounting a jffs2 partition on flash.
> 
> Dear Denis,
> 
> In message
> 
> you wrote:
> >
> 
> > Yes, I'm aware that jffs2 is quite old and ubifs is a successor of
> > jffs2, but the reason is that current Linux Kernel has no support for
> > UBI.
> 
> What do you mean by "current" here?  UBI/UBIFS support in U-Boot was
> actually adapted from the Linux kernel, so Linux support for UBI/UBIFS
> predates the U-Boot code by a long, long time.
> 
> Do you mean you are using a prehistoric Linux kernel version?
> 
> > I understand that it should have solution, but it requires recompiling
> > Linux kernel which is also time consuming.
> 
> Hm... just recompiling is only a matter of seconds (or, on a very slow system,
> minutes max).  I understand there are other concerns that you don't want to
> update?  Please be aware that there it is likely that there other 
> incompatibilities
> / bugs in such an ancient kernel...
> 
> > > What exactly are these "other problems" ?
> >
> > U-Boot launches, but after that it is hanging.
> > U-Boot 2016.01 (Feb 05 2016 - 14:15:47 +0100)
> >
> > CPU:   Altera SoCFPGA Platform
> > FPGA:  Altera Arria V, D5, version 0x0
> > BOOT:  QSPI Flash (3.0V)
> >Watchdog enabled
> > I2C:   ready
> > DRAM:
> >
> > I will try to tackle this problem also.
> > However, I must say that I don't have much experience with U-Boot, so
> > maybe I'm missing something obvious?
> 
> It appears it is hanging in the DRAM initialization phase.  This is a very 
> common
> issue.  Please make sure your memory configuration is correct.

I would also suggest you to enable DEBUG flag to get more information that 
helps debug your issues.

> 
> > Can you please share some examples of correct configuration for such
> > use case (jffs2 partition on NOR flash with SPI)?
> 
> You can deal with this later; first you need to have the system running at 
> all.
> You should focus on this first.
> 
> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Far
> back in the mists of ancient time, in the great and glorious days of the 
> former
> Galactic Empire, life was wild, rich  and  largely  tax
> free. - Douglas Adams, _The Hitchhiker's Guide to the Galaxy_
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Calvin
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Re: [U-Boot] [PATCH] armv8/ls2080ardb: Enable VID support

[Calvin Johnson]

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Prabhakar
> Kushwaha
> Sent: Friday, February 05, 2016 12:34 PM
> To: york sun ; Harninder Rai ;
> u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH] armv8/ls2080ardb: Enable VID support
> 
> > -Original Message-
> > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of
> > Prabhakar Kushwaha
> > Sent: Friday, February 05, 2016 6:49 AM
> > To: york sun ; Harninder Rai
> > ; u-boot@lists.denx.de
> > Subject: Re: [U-Boot] [PATCH] armv8/ls2080ardb: Enable VID support
> >
> >
> > > -Original Message-
> > > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york
> > > sun
> > > Sent: Thursday, February 04, 2016 10:15 PM
> > > To: Harninder Rai ; u-boot@lists.denx.de
> > > Subject: Re: [U-Boot] [PATCH] armv8/ls2080ardb: Enable VID support
> > >
> > > Rai,
> > >
> > > On 02/04/2016 06:25 AM, Rai Harninder wrote:
> > > > The fuse status register provides the values from on-chip voltage
> > > > ID efuses programmed at the factory. These values define the
> > > > voltage requirements for the chip. u-boot reads FUSESR and
> > > > translates the values into the appropriate commands to set the
> > > > voltage output value of an external voltage regulator.
> > >
> > > No need to repeat what VID feature is. Instead, please focus on what
> > > this patch does.
> > >
> > > >
> > > > Signed-off-by: Rai Harninder 
> > > > ---
> > > >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 
> > > >  board/freescale/common/vid.c   |   15 
> > > > ++-
> > > >  board/freescale/ls2080ardb/ls2080ardb.c|5 +
> > > >  include/configs/ls2080ardb.h   |   16 
> > > > 
> > > >  4 files changed, 39 insertions(+), 1 deletions(-)
> > > >
> > > > diff --git
> > > > a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > > > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > > > index 91f3ce8..4fd58ee 100644
> > > > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > > > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > > > @@ -146,6 +146,10 @@ struct ccsr_gur {
> > > > u8  res_008[0x20-0x8];
> > > > u32 gpporcr1;   /* General-purpose POR configuration */
> > > > u32 gpporcr2;   /* General-purpose POR configuration 2 
> > > > */
> > > > +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
> > > > +#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK  0x1F
> > > > +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  20
> > > > +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK   0x1F
> > > > u32 dcfg_fusesr;/* Fuse status register */
> > > > u32 gpporcr3;
> > > > u32 gpporcr4;
> > > > diff --git a/board/freescale/common/vid.c
> > > > b/board/freescale/common/vid.c index 1bd65a8..16ae177 100644
> > > > --- a/board/freescale/common/vid.c
> > > > +++ b/board/freescale/common/vid.c
> > > > @@ -10,6 +10,8 @@
> > > >  #include 
> > > >  #ifdef CONFIG_LS1043A

Also isn't it good to use CONFIG_FSL_LSCH2 instead of CONFIG_LS1043A?

> > > >  #include 
> > > > +#elif defined(CONFIG_FSL_LAYERSCAPE) #include
> > > > +
> > >
> > > It is not appropriate to use macro CONFIG_FSL_LAYERSCAPE here. It is
> > > defined for both LS1043 and LS2080.
> > >
> >
> > Oh...
> > Then LS2080 and LS2085 config needs to used. Also need to use LS2088A
> > and LS1088A.
> >
> > LS1043 is Chassis Gen2 and Other are Chassis Gen3 so different address etc.
> > How to avoid adding SoC config for each Chassis Gen3 SoC. We need to
> > define some config used across Gen3 SoCs.
> >
> 
> We do have such config CONFIG_FSL_LSCH3.
> 
> --prabhakar
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Re: [U-Boot] [PATCH] ls2085a: Correct the model & board name of RDB and QDS

[Calvin Johnson]

Hi Ashish,

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Ashish,
> Kumar
> Sent: Wednesday, January 20, 2016 12:33 PM
> To: prabhakar.khusw...@nxp.com; u-boot@lists.denx.de
> Subject: [U-Boot] [PATCH] ls2085a: Correct the model & board name of RDB
> and QDS
> 
>  * LS2085ARDB and LS2085AQDS host LS2080A and LS2085A,
> So update model and board name.
> 
> Signed-off-by: Ashish Kumar 
> ---
>  arch/arm/dts/fsl-ls2080a-qds.dts|2 +-
>  arch/arm/dts/fsl-ls2080a-rdb.dts|2 +-
>  board/freescale/ls2080aqds/ls2080aqds.c |3 +--
>  board/freescale/ls2080ardb/ls2080ardb.c |4 +---
>  4 files changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts 
> b/arch/arm/dts/fsl-ls2080a-qds.dts
> index 547ec27..7b1dae8 100644
> --- a/arch/arm/dts/fsl-ls2080a-qds.dts
> +++ b/arch/arm/dts/fsl-ls2080a-qds.dts
> @@ -11,7 +11,7 @@
>  #include "fsl-ls2080a.dtsi"
> 
>  / {
> - model = "Freescale Layerscape 2080a QDS Board";
> + model = "Freescale Layerscape 2085a QDS Board";
>   compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
> 
>   aliases {
> diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts 
> b/arch/arm/dts/fsl-ls2080a-rdb.dts
> index 1a1813b..71d1969 100644
> --- a/arch/arm/dts/fsl-ls2080a-rdb.dts
> +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts
> @@ -11,7 +11,7 @@
>  #include "fsl-ls2080a.dtsi"
> 
>  / {
> - model = "Freescale Layerscape 2080a RDB Board";
> + model = "Freescale Layerscape 2085a RDB Board";
>   compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
> 
>   aliases {
> diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
> b/board/freescale/ls2080aqds/ls2080aqds.c
> index aa256a2..fe20f3a 100644
> --- a/board/freescale/ls2080aqds/ls2080aqds.c
> +++ b/board/freescale/ls2080aqds/ls2080aqds.c
> @@ -61,8 +61,7 @@ int checkboard(void)
>   "100 separate SSCG"};
>   int clock;
> 
> - cpu_name(buf);
> - printf("Board: %s-QDS, ", buf);
> + printf("Board: LS2085A-QDS, ");

Isn't it good to change the file name to ls2085aqds.c?

> 
>   sw = QIXIS_READ(arch);
>   printf("Board Arch: V%d, ", sw >> 4);
> diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
> b/board/freescale/ls2080ardb/ls2080ardb.c
> index c63b639..ccf98c9 100644
> --- a/board/freescale/ls2080ardb/ls2080ardb.c
> +++ b/board/freescale/ls2080ardb/ls2080ardb.c
> @@ -54,10 +54,8 @@ unsigned long long get_qixis_addr(void)  int
> checkboard(void)  {
>   u8 sw;
> - char buf[15];
> 
> - cpu_name(buf);
> - printf("Board: %s-RDB, ", buf);
> + printf("Board: LS2085A-RDB, ");

And here file name change to ls1085rdb.c?

> 
>   sw = QIXIS_READ(arch);
>   printf("Board Arch: V%d, ", sw >> 4);
> --
> 1.7.6.GIT
> 
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Regards
Calvin
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Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot support

[Calvin Johnson]

Hi Qianyu,

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Qianyu
> Gong
> Sent: Thursday, January 14, 2016 9:57 AM
> To: Scott Wood ; u-boot@lists.denx.de
> Cc: b48...@freescale.com; Mingkai Hu ;
> wenbin.s...@freescale.com
> Subject: Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot support
> 
> 
> > -Original Message-
> > From: Scott Wood [mailto:o...@buserror.net]
> > Sent: Thursday, January 14, 2016 8:21 AM
> > To: Qianyu Gong ; u-boot@lists.denx.de
> > Cc: b07...@freescale.com; b48...@freescale.com;
> > wenbin.s...@freescale.com; Mingkai Hu 
> > Subject: Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot
> > support
> >
> > On Tue, 2016-01-12 at 03:14 +, Qianyu Gong wrote:
> > > > -Original Message-
> > > > From: Scott Wood [mailto:o...@buserror.net]
> > > > Sent: Tuesday, January 12, 2016 1:47 AM
> > > > To: Qianyu Gong ; u-boot@lists.denx.de
> > > > Cc: b07...@freescale.com; b48...@freescale.com;
> > > > wenbin.s...@freescale.com; Mingkai Hu 
> > > > Subject: Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI
> > > > boot support
> > > >
> > > > On Mon, 2016-01-11 at 10:17 +0800, Gong Qianyu wrote:
> > > > > diff --git a/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > b/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > index d6696ca..770b79f 100644
> > > > > --- a/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > +++ b/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > @@ -43,15 +43,19 @@ enum {
> > > > >
> > > > >  int checkboard(void)
> > > > >  {
> > > > > +#ifndef CONFIG_QSPI_BOOT
> > > > >   char buf[64];
> > > > >  #ifndef CONFIG_SD_BOOT
> > > > >   u8 sw;
> > > > >  #endif
> > > > > +#endif
> > > > >
> > > > >   puts("Board: LS1043AQDS, boot from ");
> > > > >
> > > > >  #ifdef CONFIG_SD_BOOT
> > > > >   puts("SD\n");
> > > > > +#elif defined(CONFIG_QSPI_BOOT)
> > > > > + puts("QSPI\n");
> > > > >  #else
> > > > >   sw = QIXIS_READ(brdcfg[0]);
> > > > >   sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@
> -68,12
> > > > +72,15
> > > > > @@ int checkboard(void)
> > > > >   printf("invalid setting of SW%u\n",
> QIXIS_LBMAP_SWITCH);
> > > > #endif
> > > > >
> > > > > +#ifndef CONFIG_QSPI_BOOT
> > > > > + /* For QSPI boot, here I2C is not ready yet. */
> > > > >   printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
> > > > >  QIXIS_READ(id), QIXIS_READ(arch));
> > > > >
> > > > >   printf("FPGA:  v%d (%s), build %d\n",
> > > > >  (int)QIXIS_READ(scver), qixis_read_tag(buf),
> > > > >  (int)qixis_read_minor());
> > > > > +#endif
> > > >

It will be useful, if the above FPGA prints are available for QSPI boot as well.

> > > > Why isn't i2c ready?  How is DDR inited without it?
> > > >
> > > > -Scott
> > >
> > > Hi Scott,
> > >
> > > The calling sequence in U-Boot is :
> > > checkboard() -> init_func_i2c() -> dram_init()
> > >
> > > So I2C is not ready in checkboard() but is ready for DDR initialization.
> >
> > Can you move the prints later in the boot sequence?
> >
> > In any case, the relevant variable is whether qixis uses i2c, not
> > whether you're booting from qspi (even if they are correlated).
> >
> > -Scott
> 
> Yes. Only with QSPI it needs I2C to access QIXIS.
> But if defining CONFIG_DISPLAY_BOARDINFO_LATE, the print layout will look
> really uncomfortable.. So we just comment out the FPGA prints for QSPI boot.
> 
> Regards,
> Qianyu

Thanks
Calvin
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Re: [U-Boot] UBIFS seeing corrupt blank pages when image flashed via u-boot

[Calvin Johnson]

Hi,

On Fri, Jan 3, 2014 at 6:29 PM, Artem Bityutskiy
artem.bityuts...@linux.intel.com wrote:

 Hi Pekon,

 On Fri, 2014-01-03 at 11:45 +, Gupta, Pekon wrote:
  *_Case-1_ Flashing UBIFS image from u-boot using 'nand write' utility*
 
  For a partially written erased-block..
  (a) 1st page is written with 'erase-header'
  (b) 2nd page is written with 'volume-header'
  (c) '3rd page' is written with 'some data'
  (d) '4th to last-page of block' should be left blank, but they are written 
  with 0xFF.
  As a effect of (d), the ECC calculated for (all 0xff data) is written to
  OOB area of all pages from 4th-page till last-page of the PEB.

 Yup.


If the 4th to last-page are left blank and not covered with ECC, what
will happen in case of bit flips on the blank pages? There was an
issue reported some time back.
http://lists.infradead.org/pipermail/linux-mtd/2012-January/039256.html

Does UBI/UBIFS take care of this now?

Thanks,
Calvin
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