Re: [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.

[Chee, Tien Fong]

On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Convert Macro #define configuration to Kconfig method. All FPGA
> > devices
> > enable configuration based on CONFIG_FPGA_ALTERA.
> > 
> > Signed-off-by: Tien Fong Chee 
> > ---
> >  drivers/fpga/Kconfig |5 -
> >  drivers/fpga/Makefile|3 +--
> >  include/altera.h |2 +-
> >  include/configs/socfpga_common.h |3 ---
> >  4 files changed, 6 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index a760944..fc4ea0d 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -2,12 +2,15 @@ menu "FPGA support"
> >  
> >  config FPGA
> >     bool
> > +   help
> > +     Enable FPGA driver build.
> Separate patch please , also this is not driver, but framework .
> There's
> not just drivers here IMO.
> 
ohh...okay, so you prefer i revert the changes, or better explanation
in separate patch? if for later,what is your suggestion? Thanks.
> > 
> >  config FPGA_ALTERA
> >     bool "Enable Altera FPGA drivers"
> > +   default y if TARGET_SOCFPGA_GEN5 && CMD_FPGA
> Should be selected by arch code, drop this.
> 
just for clarity, are you means defconfig == "selected by arch code"?
> > 
> >     select FPGA
> >     help
> > -     Say Y here to enable the Altera FPGA driver
> > +     Default Y here to enable the Altera FPGA driver
> Keep as is, it's up to user to decide.
> 
I found that all users enable it, so that is why i set this as default,
otherwise i have to add this into their defconfig one by one. Users who
don't want enable it, they can set "N" in their defconfig. What do you
think?
> > 
> >       This provides basic infrastructure to support Altera
> > FPGA devices.
> >       Enable Altera FPGA specific functions which includes
> > bitstream
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index 06f..84e7605 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -14,10 +14,9 @@ obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
> >  obj-$(CONFIG_FPGA_XILINX) += xilinx.o
> >  obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
> >  ifdef CONFIG_FPGA_ALTERA
> > -obj-y += altera.o
> > +obj-y += altera.o socfpga.o
> Now all the ancient systems which had the ancient Altera FPGAs will
> build-in the socfpga stuff too . That cannot work.
> 
Okay, i will revert the changes.
> > 
> >  obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
> >  obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
> >  obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
> >  obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
> > -obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
> >  endif
> > diff --git a/include/altera.h b/include/altera.h
> > index 48d3eb7..a627b37 100644
> > --- a/include/altera.h
> > +++ b/include/altera.h
> > @@ -109,7 +109,7 @@ typedef struct {
> >     Altera_post_fn post;
> >  } altera_board_specific_func;
> >  
> > -#ifdef CONFIG_FPGA_SOCFPGA
> > +#ifdef CONFIG_FPGA_ALTERA
> >  int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t
> > rbf_size);
> >  #endif
> >  
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index da7e4ad..1b79c03 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -107,9 +107,6 @@
> >   */
> >  #ifdef CONFIG_TARGET_SOCFPGA_GEN5
> >  #ifdef CONFIG_CMD_FPGA
> > -#define CONFIG_FPGA
> > -#define CONFIG_FPGA_ALTERA
> > -#define CONFIG_FPGA_SOCFPGA
> >  #define CONFIG_FPGA_COUNT  1
> >  #endif
> >  #endif
> > 
> 
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Re: [U-Boot] [PATCH] ARM: socfpga: boot0 hook: remove macro from boot0 header file

[Chee, Tien Fong]

On Rab, 2017-03-29 at 11:28 +0800, tien.fong.c...@intel.com wrote:
> From: "Chee, Tien Fong" <tien.fong.c...@intel.com>
> 
> Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole
> header file") miss out cleaning macro in this header file, and this
> has broken implementation of a boot header capability in socfpga
> SPL. Remove the macro in this file, and recovering it back
> to proper functioning.
> 
Please ignore this patch, i will send out another patch. Thanks.
> Fixes: ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole
> header file")
> 
> Signed-off-by: Chee, Tien Fong <tien.fong.c...@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/boot0.h | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> b/arch/arm/mach-socfpga/include/mach/boot0.h
> index aaada31..40f9d32 100644
> --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> @@ -8,7 +8,6 @@
>  #define __BOOT0_H
>  
>  #ifdef CONFIG_SPL_BUILD
> -#define ARM_SOC_BOOT0_HOOK   
> \
>   .balignl 64,0xf33db33f; 
>   \
>   
> \
>   .word   0x1337c0d3; /* SoCFPGA preloader
> validation word */\
> @@ -20,9 +19,6 @@
>   nop;
> \
>   nop;
> \
>   nop;
> -#else
> -#define ARM_SOC_BOOT0_HOOK
>  #endif
>  
> -
>  #endif /* __BOOT0_H */
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Re: [U-Boot] [PATCH] ARM: socfpga: Fix broken implementation and enhancing boot header

[Chee, Tien Fong]

On Sel, 2017-03-28 at 11:38 +0200, Marek Vasut wrote:
> On 03/28/2017 11:25 AM, tien.fong.c...@intel.com wrote:
> > 
> > From: "Chee, Tien Fong" <tien.fong.c...@intel.com>
> > 
> > Fixing the broken implementation caused by the patch
> > commit:ce62e57fc57177352a02b76dace0173bd13404b6, ARM: boot0 hook:
> See section 2) here [1] , in particular the part about referencing
> commits and the Fixes: tag .
> 
> [1] https://www.kernel.org/doc/html/latest/process/submitting-patches
> .html
> 
> > 
> > remove macro, include whole header file. This patch also enhances
> > boot header to contain more special data.
> This should be a separate patch then.
> 
okay. Thanks.
> > 
> > Signed-off-by: Chee, Tien Fong <tien.fong.c...@intel.com>
> > ---
> >  arch/arm/mach-socfpga/include/mach/boot0.h | 30 
> > --
> >  1 file changed, 16 insertions(+), 14 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > index aaada31..877866a 100644
> > --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > @@ -8,21 +8,23 @@
> >  #define __BOOT0_H
> >  
> >  #ifdef CONFIG_SPL_BUILD
> > -#define ARM_SOC_BOOT0_HOOK 
> > \
> > -   .balignl 64,0xf33db33f; 
> > \
> > -   
> > \
> > -   .word   0x1337c0d3; /* SoCFPGA preloader
> > validation word */  \
> > -   .word   0xc01df00d; /* Version, flags, length
> > */  \
> > -   .word   0xcafec0d3; /* Checksum, zero-pad */
> > \
> > -   nop;
> > \
> > -   
> > \
> > -   b reset;/* SoCFPGA jumps here */
> > \
> > -   nop;
> > \
> > -   nop;
> > \
> > -   nop;
> > -#else
> > -#define ARM_SOC_BOOT0_HOOK
> > +   .balignl 64,0xf33db33f;
> > +
> > +   /* Start of header offset */
> > +   .word   0x1337c0d3; /* SoCFPGA preloader validation
> > word(4B) */
> > +   .word   0xc01df00d; /* Header
> > length(2B),flags(1B),version(1B) */
> > +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
> > +   .word   0xcafec0d3; /* Program length(4B) */
> > +   .word   0xf00dcafe; /* Program entry
> > offset(4B),relative to  */
> > +   /* the start of program header */
> >  #endif
> > +   .word   0xfeedface; /* Simple checksum(2B),spare
> > offset(2B) */
> > +   nop;
> >  
> > +   b reset;/* SoCFPGA jumps here */
> > +   nop;
> > +   nop;
> > +   nop;
> > +#endif
> >  
> >  #endif /* __BOOT0_H */
> > 
> 
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Re: [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset

[Chee, Tien Fong]

On Sel, 2017-03-07 at 04:45 +0100, Marek Vasut wrote:
> On 03/06/2017 05:45 AM, Chee, Tien Fong wrote:
> > 
> > On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote:
> > > 
> > > On 03/03/2017 01:50 PM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.c...@intel.com>
> > > > 
> > > > This patch removes the unused passing parameter of
> > > > socfpga_bridges_reset
> > > > function in Arria10.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > > > Cc: Marek Vasut <ma...@denx.de>
> > > > Cc: Dinh Nguyen <dingu...@kernel.org>
> > > > Cc: Ching Liang See <chin.liang@intel.com>
> > > > Cc: Ley Foon <ley.foon@intel.com>
> > > > Cc: Westergreen Dalon <dalon.westergr...@intel.com>
> > > We do NOT have arria10 support in mainline, I am confused.
> > > Can you please sync with Ley when submitting patches ?
> > > 
> > > Thanks
> > > 
> > This series is working on top of [1] initial patchset which enables
> > the basic support for Arria 10 and other features.
> > https://www.mail-archive.com/u-boot@lists.denx.de/msg240053.html
> This patchset is still work-in-progress. Sending patches on top of it
> is 
> completely useless . Please work with Ley and integrate them or wait 
> until the initial patchset lands.
> 
Okay.
> > 
> > I just realized i forgot to +CC you guys in the cover letter,
> > https://www.mail-archive.com/u-boot@lists.denx.de/msg240829.html.
> > I am sorry to have you confused.
> [...]
> 
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Re: [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset

[Chee, Tien Fong]

On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote:
> On 03/03/2017 01:50 PM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> > 
> > This patch removes the unused passing parameter of
> > socfpga_bridges_reset
> > function in Arria10.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@kernel.org>
> > Cc: Ching Liang See <chin.liang@intel.com>
> > Cc: Ley Foon <ley.foon@intel.com>
> > Cc: Westergreen Dalon <dalon.westergr...@intel.com>
> We do NOT have arria10 support in mainline, I am confused.
> Can you please sync with Ley when submitting patches ?
> 
> Thanks
> 
This series is working on top of [1] initial patchset which enables 
the basic support for Arria 10 and other features.
https://www.mail-archive.com/u-boot@lists.denx.de/msg240053.html

I just realized i forgot to +CC you guys in the cover letter,
https://www.mail-archive.com/u-boot@lists.denx.de/msg240829.html.
I am sorry to have you confused.
> > 
> > ---
> >  arch/arm/mach-socfpga/include/mach/reset_manager.h |3 ---
> >  .../include/mach/reset_manager_arria10.h   |1 +
> >  .../mach-socfpga/include/mach/reset_manager_gen5.h |1 +
> >  arch/arm/mach-socfpga/reset_manager_arria10.c  |2 +-
> >  4 files changed, 3 insertions(+), 4 deletions(-)
> >  mode change 100755 => 100644 arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h
> >  mode change 100755 => 100644 arch/arm/mach-
> > socfpga/include/mach/reset_manager_gen5.h
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > index 64526b6..f5189e8 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > @@ -8,9 +8,6 @@
> >  #define_RESET_MANAGER_H_
> > 
> >  void reset_cpu(ulong addr);
> > -
> > -void socfpga_bridges_reset(int enable);
> > -
> >  void socfpga_per_reset(u32 reset, int set);
> >  void socfpga_per_reset_all(void);
> > 
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h
> > old mode 100755
> > new mode 100644
> > index 2668a86..954381c
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > @@ -16,6 +16,7 @@ void
> > reset_assert_fpga_connected_peripherals(void);
> >  void reset_deassert_osc1wd0(void);
> >  void reset_assert_uart(void);
> >  void reset_deassert_uart(void);
> > +void socfpga_bridges_reset(void);
> > 
> >  struct socfpga_reset_manager {
> >     u32 stat;
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-
> > socfpga/include/mach/reset_manager_gen5.h
> > old mode 100755
> > new mode 100644
> > index 028974a..da17f4c
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> > @@ -8,6 +8,7 @@
> >  #define_RESET_MANAGER_GEN5_H_
> > 
> >  void reset_deassert_peripherals_handoff(void);
> > +void socfpga_bridges_reset(int enable);
> > 
> >  struct socfpga_reset_manager {
> >     u32 status;
> > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > index 01156de..684c6be 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > @@ -355,7 +355,7 @@ void socfpga_bridges_reset(int enable)
> >     /* For SoCFPGA-VT, this is NOP. */
> >  }
> >  #else
> > -void socfpga_bridges_reset(int enable)
> > +void socfpga_bridges_reset(void)
> >  {
> >  /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
> > fpga2sdram) */
> >     /* set idle request to all bridges */
> > 
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Re: [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver

[Chee, Tien Fong]

On Jum, 2017-03-03 at 20:50 +0800, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.c...@intel.com>
> 
> This patchset adds FPGA driver to Intel Arria 10 SoC.
> 
> This series is working on top of [1] initial patchset which enables
> the basic
> support for Arria 10 and other features.
> 
> [1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg240053.html
> 
> Regards,
> Tien Fong
> 
> Tien Fong Chee (4):
>   arm: socfpga: Removing unused passing parameter of
> socfpga_bridges_reset
>   arm: socfpga: Restructure FPGA driver in the preparation to support
> A10.
>   arm: socfpga: Add Arria10 FPGA manager program assembly driver
>   arm: socfpga: Add FPGA driver support for Arria 10
> 
>  arch/arm/mach-socfpga/Makefile |3 +-
>  arch/arm/mach-socfpga/include/mach/fpga_manager.h  |   70 +--
>  .../include/mach/fpga_manager_arria10.h|  120 +
>  .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |   66 ++--
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |3 -
>  .../include/mach/reset_manager_arria10.h   |1 +
>  .../mach-socfpga/include/mach/reset_manager_gen5.h |1 +
>  arch/arm/mach-socfpga/lowlevel_init.S  |   48 ++
>  arch/arm/mach-socfpga/reset_manager_arria10.c  |2 +-
>  drivers/Makefile   |1 +
>  drivers/fpga/Makefile  |6 +-
>  drivers/fpga/socfpga.c |  272 +-
> -
>  drivers/fpga/socfpga_arria10.c |  565
> 
>  drivers/fpga/{socfpga.c => socfpga_gen5.c} |   33 +--
>  14 files changed, 792 insertions(+), 399 deletions(-)
>  create mode 100644 arch/arm/mach-
> socfpga/include/mach/fpga_manager_arria10.h
>  copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h =>
> fpga_manager_gen5.h} (85%)
>  mode change 100755 => 100644 arch/arm/mach-
> socfpga/include/mach/reset_manager_arria10.h
>  mode change 100755 => 100644 arch/arm/mach-
> socfpga/include/mach/reset_manager_gen5.h
>  create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S
>  create mode 100644 drivers/fpga/socfpga_arria10.c
>  copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (91%)
> 
+CC Marek, Dinh, LF, Dalon, CL ...
This is cover letter for this series patches https://www.mail-archive.c
om/u-boot@lists.denx.de/msg240843.html
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[U-Boot] [PATCH 4/4] arm: socfpga: Add FPGA driver support for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

Add FPGA driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Ley Foon 
Cc: Westergreen Dalon 
---
 arch/arm/mach-socfpga/Makefile |1 +
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |2 +
 .../include/mach/fpga_manager_arria10.h|  120 +
 drivers/Makefile   |1 +
 drivers/fpga/Makefile  |1 +
 drivers/fpga/socfpga_arria10.c |  565 
 6 files changed, 690 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 create mode 100644 drivers/fpga/socfpga_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 901bf91..d1ca3ee 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -18,6 +18,7 @@ obj-y += clock_manager_arria10.o
 obj-y  += misc_arria10.o
 obj-y  += pinmux_arria10.o
 obj-y  += reset_manager_arria10.o
+obj-y  += lowlevel_init.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index 76a9289..64e8344 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -12,6 +12,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 /* FPGA CD Ratio Value */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
new file mode 100644
index 000..a273be7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:BSD-3-Clause
+ */
+
+#ifndef _FPGA_MANAGER_ARRIA10_H_
+#define _FPGA_MANAGER_ARRIA10_H_
+
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  0x0001
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK 0x0002
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   0x0004
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK0x0008
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
0x0010
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK 0x0020
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
0x0040
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK 0x0080
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK  0x0100
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK   0x0200
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK0x0400
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK   0x0800
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK
0x1000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK0x2000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK  0x0001
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK  0x0002
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK  0x0004
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK   0x0100
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK0x0200
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK  0x1000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK
0x2000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB16
+
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK  0x0001
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK  0x0002
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK  0x0004
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK  0x0100
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK   0x0001
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK   0x0100
+
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK   0x0001
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK   0x0001
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK  0x0100
+
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK  0x0001
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK  0x0100
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK  0x0003

[U-Boot] [PATCH 3/4] arm: socfpga: Add Arria10 FPGA manager program assembly driver

[Chee Tien Fong]

From: Tien Fong Chee 

This patch adding the Arria10 FPGA manager program assembly driver
which can be used for feeding bitstream to configure FPGA.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Ley Foon 
Cc: Westergreen Dalon 
---
 arch/arm/mach-socfpga/lowlevel_init.S |   48 +
 1 files changed, 48 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S

diff --git a/arch/arm/mach-socfpga/lowlevel_init.S 
b/arch/arm/mach-socfpga/lowlevel_init.S
new file mode 100644
index 000..79e9d07
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+
+/*
+ * Write RBF data in burst form to FPGA Manager
+ * [r0] RBF binary source address
+ * [r1] FPGA Manager data address
+ * [r2] RBF data length
+ */
+
+ENTRY(fpgamgr_axi_write)
+   PUSH{r4-r11, lr}/* save registers per AAPCS */
+
+write_burst:
+   cmp r2,#32
+   beq write_burst_cont
+   bls write_word
+write_burst_cont:
+   ldmia   r0!, {r4-r11}
+   stmia   r1, {r4-r11}
+   subsr2, r2, #32
+   b   write_burst
+
+write_word:
+   cmp r2,#4
+   beq write_word_cont
+   bls write_byte
+write_word_cont:
+   ldmia   r0!, {r4}
+   stmia   r1, {r4}
+   subsr2, r2, #4
+   b   write_word
+
+write_byte:
+   cmp r2,#0
+   beq write_end
+   ldr r3, [r0]
+   str r3, [r1]
+write_end:
+   POP {r4-r11, pc}
+ENDPROC(fpgamgr_axi_write)
-- 
1.7.1

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[U-Boot] [PATCH 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10.

[Chee Tien Fong]

From: Tien Fong Chee 

Move the Gen5 specific code to gen5 files. No functional change.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Ley Foon 
Cc: Westergreen Dalon 
---
 arch/arm/mach-socfpga/Makefile |2 +-
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |   68 +
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |   66 +++---
 drivers/fpga/Makefile  |5 +-
 drivers/fpga/socfpga.c |  272 +---
 drivers/fpga/{socfpga.c => socfpga_gen5.c} |   33 +---
 6 files changed, 51 insertions(+), 395 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => 
fpga_manager_gen5.h} (85%)
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (91%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 7c7b471..901bf91 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,7 +9,6 @@
 
 obj-y  += board.o
 obj-y  += clock_manager.o
-obj-y  += fpga_manager.o
 obj-y  += misc.o
 obj-y  += reset_manager.o
 obj-y  += timer.o
@@ -28,6 +27,7 @@ obj-y += reset_manager_gen5.o
 obj-y  += scan_manager.o
 obj-y  += system_manager_gen5.o
 obj-y  += wrap_pll_config.o
+obj-y  += fpga_manager.o
 endif
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index a077e22..76a9289 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2017 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -10,58 +10,9 @@
 
 #include 
 
-struct socfpga_fpga_manager {
-   /* FPGA Manager Module */
-   u32 stat;   /* 0x00 */
-   u32 ctrl;
-   u32 dclkcnt;
-   u32 dclkstat;
-   u32 gpo;/* 0x10 */
-   u32 gpi;
-   u32 misci;  /* 0x18 */
-   u32 _pad_0x1c_0x82c[517];
-
-   /* Configuration Monitor (MON) Registers */
-   u32 gpio_inten; /* 0x830 */
-   u32 gpio_intmask;
-   u32 gpio_inttype_level;
-   u32 gpio_int_polarity;
-   u32 gpio_intstatus; /* 0x840 */
-   u32 gpio_raw_intstatus;
-   u32 _pad_0x848;
-   u32 gpio_porta_eoi;
-   u32 gpio_ext_porta; /* 0x850 */
-   u32 _pad_0x854_0x85c[3];
-   u32 gpio_1s_sync;   /* 0x860 */
-   u32 _pad_0x864_0x868[2];
-   u32 gpio_ver_id_code;
-   u32 gpio_config_reg2;   /* 0x870 */
-   u32 gpio_config_reg1;
-};
-
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB  3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK  0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK  0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK  0x2
-#define FPGAMGRREGS_CTRL_EN_MASK   0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB   6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF   0x0
-#define FPGAMGRREGS_MODE_RESETPHASE0x1
-#define FPGAMGRREGS_MODE_CFGPHASE  0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE  0x4
-#define FPGAMGRREGS_MODE_UNKNOWN   0x5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include 
+#endif
 
 /* FPGA CD Ratio Value */
 #define CDRATIO_x1 0x0
@@ -69,9 +20,12 @@ struct socfpga_fpga_manager {
 #define CDRATIO_x4 0x2
 #define CDRATIO_x8 0x3
 
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
-int fpgamgr_get_mode(void);
+#define FPGA_TIMEOUT_CNT   0x100
+
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
+int fpgamgr_dclkcnt_set(unsigned long cnt);
 
+#endif /* __ASSEMBLY__ */
 #endif /* _FPGA_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
similarity index 85%
copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
index a077e22..c03566e 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ 

[U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset

[Chee Tien Fong]

From: Tien Fong Chee 

This patch removes the unused passing parameter of socfpga_bridges_reset
function in Arria10.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Ley Foon 
Cc: Westergreen Dalon 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h |3 ---
 .../include/mach/reset_manager_arria10.h   |1 +
 .../mach-socfpga/include/mach/reset_manager_gen5.h |1 +
 arch/arm/mach-socfpga/reset_manager_arria10.c  |2 +-
 4 files changed, 3 insertions(+), 4 deletions(-)
 mode change 100755 => 100644 
arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
 mode change 100755 => 100644 
arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 64526b6..f5189e8 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -8,9 +8,6 @@
 #define_RESET_MANAGER_H_
 
 void reset_cpu(ulong addr);
-
-void socfpga_bridges_reset(int enable);
-
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
old mode 100755
new mode 100644
index 2668a86..954381c
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -16,6 +16,7 @@ void reset_assert_fpga_connected_peripherals(void);
 void reset_deassert_osc1wd0(void);
 void reset_assert_uart(void);
 void reset_deassert_uart(void);
+void socfpga_bridges_reset(void);
 
 struct socfpga_reset_manager {
u32 stat;
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
old mode 100755
new mode 100644
index 028974a..da17f4c
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -8,6 +8,7 @@
 #define_RESET_MANAGER_GEN5_H_
 
 void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_reset(int enable);
 
 struct socfpga_reset_manager {
u32 status;
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c 
b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 01156de..684c6be 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -355,7 +355,7 @@ void socfpga_bridges_reset(int enable)
/* For SoCFPGA-VT, this is NOP. */
 }
 #else
-void socfpga_bridges_reset(int enable)
+void socfpga_bridges_reset(void)
 {
 /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) */
/* set idle request to all bridges */
-- 
1.7.1

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[U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver

[Chee Tien Fong]

From: Tien Fong Chee 

This patchset adds FPGA driver to Intel Arria 10 SoC.

This series is working on top of [1] initial patchset which enables the basic
support for Arria 10 and other features.

[1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg240053.html

Regards,
Tien Fong

Tien Fong Chee (4):
  arm: socfpga: Removing unused passing parameter of
socfpga_bridges_reset
  arm: socfpga: Restructure FPGA driver in the preparation to support
A10.
  arm: socfpga: Add Arria10 FPGA manager program assembly driver
  arm: socfpga: Add FPGA driver support for Arria 10

 arch/arm/mach-socfpga/Makefile |3 +-
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |   70 +--
 .../include/mach/fpga_manager_arria10.h|  120 +
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |   66 ++--
 arch/arm/mach-socfpga/include/mach/reset_manager.h |3 -
 .../include/mach/reset_manager_arria10.h   |1 +
 .../mach-socfpga/include/mach/reset_manager_gen5.h |1 +
 arch/arm/mach-socfpga/lowlevel_init.S  |   48 ++
 arch/arm/mach-socfpga/reset_manager_arria10.c  |2 +-
 drivers/Makefile   |1 +
 drivers/fpga/Makefile  |6 +-
 drivers/fpga/socfpga.c |  272 +--
 drivers/fpga/socfpga_arria10.c |  565 
 drivers/fpga/{socfpga.c => socfpga_gen5.c} |   33 +--
 14 files changed, 792 insertions(+), 399 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => 
fpga_manager_gen5.h} (85%)
 mode change 100755 => 100644 
arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
 mode change 100755 => 100644 
arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
 create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S
 create mode 100644 drivers/fpga/socfpga_arria10.c
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (91%)

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Re: [U-Boot] [PATCH 14/20] arm: socfpga: add SPL support for Arria 10

[Chee, Tien Fong]

On Sab, 2017-02-25 at 22:43 +0100, Marek Vasut wrote:
> On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> > 
> > Add SPL support for Arria 10.
> > 
> > Signed-off-by: Tien Fong Chee 
> > Signed-off-by: Ley Foon Tan 
> > ---
> >  arch/arm/mach-socfpga/spl.c | 92
> > -
> >  1 file changed, 90 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > socfpga/spl.c
> > index fec4c7a..1299e67 100644
> > --- a/arch/arm/mach-socfpga/spl.c
> > +++ b/arch/arm/mach-socfpga/spl.c
> > @@ -19,37 +19,55 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#include 
> > +#endif
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +#define BOOTINFO_BSEL_SHIFT0
> Wasn't this defined in the misc support patch already ?
> 
> > 
> >  static struct pl310_regs *const pl310 =
> >     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> >  static struct scu_registers *scu_regs =
> >     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> >  static struct nic301_registers *nic301_regs =
> >     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > -static struct socfpga_system_manager *sysmgr_regs =
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#define BOOTINFO_BSEL_SHIFT12
> > +#endif
> > +
> > +static const struct socfpga_system_manager *sysmgr_regs =
> >     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >  
> >  u32 spl_boot_device(void)
> >  {
> >     const u32 bsel = readl(_regs->bootinfo);
> >  
> > -   switch (bsel & 0x7) {
> > +   switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) {
> >     case 0x1:   /* FPGA (HPS2FPGA Bridge) */
> >     return BOOT_DEVICE_RAM;
> >     case 0x2:   /* NAND Flash (1.8V) */
> >     case 0x3:   /* NAND Flash (3.0V) */
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >     socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
> > +#endif
> >     return BOOT_DEVICE_NAND;
> >     case 0x4:   /* SD/MMC External Transceiver (1.8V) */
> >     case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >     socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
> >     socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
> > +#endif
> >     return BOOT_DEVICE_MMC1;
> >     case 0x6:   /* QSPI Flash (1.8V) */
> >     case 0x7:   /* QSPI Flash (3.0V) */
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >     socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
> > +#endif
> This looks awful, you might want to split this function into
> A10-specific and Gen5 specific one(s) .
> 
#if defined(CONFIG_TARGET_SOCFPGA_GEN5) can be removed, Arria10 would
use the same implementation as gen5.
> > 
> >     return BOOT_DEVICE_SPI;
> >     default:
> >     printf("Invalid boot device (bsel=%08x)!\n",
> > bsel);
> > @@ -68,6 +86,7 @@ u32 spl_boot_mode(const u32 boot_device)
> >  }
> >  #endif
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  static void socfpga_nic301_slave_ns(void)
> >  {
> >     writel(0x1, _regs->lwhps2fpgaregs);
> > @@ -182,3 +201,72 @@ void board_init_f(ulong dummy)
> >     /* Configure simple malloc base pointer into RAM. */
> >     gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
> >  }
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#ifdef CONFIG_SPL_BOARD_INIT
> > +void spl_board_init(void)
> > +{
> > +   /* configuring the clock based on handoff */
> > +   cm_basic_init(gd->fdt_blob);
> > +   WATCHDOG_RESET();
> > +
> > +   config_dedicated_pins(gd->fdt_blob);
> > +   WATCHDOG_RESET();
> > +
> > +   /* Release UART from reset */
> > +   reset_deassert_uart();
> > +
> > +   /* enable console uart printing */
> > +   preloader_console_init();
> > +}
> > +#endif
> > +
> > +void board_init_f(ulong dummy)
> > +{
> > +   memset(__bss_start, 0, __bss_end - __bss_start);
> Is this really needed ? Should be done by common code already ...
> 
> > 
> > +   /*
> > +    * Configure Clock Manager to use intosc clock instead
> > external osc to
> > +    * ensure success watchdog operation. We do it as early as
> > possible.
> > +    */
> > +   cm_use_intosc();
> > +
> > +   watchdog_disable();
> > +
> > +   arch_early_init_r();
> > +
> > +#ifdef CONFIG_HW_WATCHDOG
> > +   /* release osc1 watchdog timer 0 from reset */
> > +   reset_deassert_osc1wd0();
> > +
> > +   /* reconfigure and enable the watchdog */
> > +   hw_watchdog_init();
> > +   WATCHDOG_RESET();
> > +#endif /* CONFIG_HW_WATCHDOG */
> > +
> > +#ifdef CONFIG_OF_CONTROL
> > +   /* We need to access to FDT as this stage */
> > +   /* FDT is at end of image */
> > +   gd->fdt_blob = (void *)(__bss_end);
> This looks like common code too ?
> 
> > 
> > +   /* Check whether we have a valid FDT or not. */
> > +   if (fdtdec_prepare_fdt()) {
> > + 

Re: [U-Boot] [PATCH v4 00/28] *** SUBJECT HERE ***

[Chee, Tien Fong]

On Sel, 2017-01-10 at 23:06 +0100, Marek Vasut wrote:
> On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> > 
> > *** BLURB HERE ***
> Please at least fill the blanks next time ... :)
> 
By the way, any comment on the rest of the patches?

Thanks :).
> > 
> > Tien Fong Chee (28):
> >   arm: socfpga: arria10: add additional i2c nodes for Arria10
> >   arm: socfpga: arria10: add sdram defines for Arria10
> >   arm: socfpga: arria10: add board files for the Arria10 SoCDK
> >   arm: socfpga: arria10: add system manager defines
> >   arm: socfpga: arria10: add misc functions for Arria10
> >   arm: socfpga: arria10: add socfpga_arria10_socdk config
> >   arm: socfpga: arria10: add socfpga_arria10_defconfig
> >   arm: socfpga: arria10: add config option build for arria10
> >   arm: socfpga: add define for bootinfo bsel bit shift
> >   arm: socfpga: arria10: add reset manager for Arria10
> >   arm: socfpga: wrap system manager functions for A5/C5 devices
> >   arm: socfpga: arria10: don't build GEN5 sdram for arria10
> >   arm: socfpga: arria10 fpga does not have bridges mapped
> >   arm: socfpga: arria10: remove board_init and s_init
> >   arm: socfpga: combine clrbits/setbits into a single clrsetbits
> >   arm: socfpga: add reset manager defines for Arria10
> >   arm: socfpga: arria10: update dwmac reset function to support
> > Arria10
> >   ARM:dts: Added device tree for socfpga arria10 development kit
> > sdmmc
> >   arm: socfpga: arria10: Enable SPL for Arria 10
> >   arm: socfpga: arria10: Added clock manager and pin mux compat
> > macro
> >   arm: socfpga: arria10: Added some hardware base address for Arria
> > 10
> >   arm: socfpga: arria10: Added support for Arria 10 socdk
> >   arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
> >   arm: socfpga: arria10: Added miscellaneous drivers for Arria 10
> >   arm: socfpga: arria10: Added drivers for Arria10 clock manager
> >   arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins
> > configuration
> >   arm: socfpga: arria10: Added Arria10 critical HW initialization
> > to spl
> >   arm: socfpga: arria10: Enable fpga driver build for SPL.
> > 
> >  arch/arm/dts/Makefile  |   3 +-
> >  arch/arm/dts/socfpga_arria10.dtsi  | 859
> > +++
> >  arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  30 +
> >  .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 479
> > +++
> >  arch/arm/mach-socfpga/Kconfig  |  10 +
> >  arch/arm/mach-socfpga/Makefile |  18 +-
> >  arch/arm/mach-socfpga/clock_manager.c  | 752 +++
> > -
> >  arch/arm/mach-socfpga/clock_manager_arria10.c  | 954
> > +
> >  .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
> >  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   8 +-
> >  arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
> >  arch/arm/mach-socfpga/include/mach/misc.h  |  32 +
> >  arch/arm/mach-socfpga/include/mach/pinmux.h|  17 +
> >  arch/arm/mach-socfpga/include/mach/reset_manager.h | 152 +++-
> >  arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 
> >  .../arm/mach-socfpga/include/mach/system_manager.h | 122 +++
> >  arch/arm/mach-socfpga/misc.c   | 367 +---
> >  arch/arm/mach-socfpga/misc_arria10.c   | 255 ++
> >  arch/arm/mach-socfpga/{misc.c => misc_gen5.c}  | 178 +---
> >  arch/arm/mach-socfpga/pinmux.c | 104 +++
> >  arch/arm/mach-socfpga/reset_manager.c  |  90 +-
> >  arch/arm/mach-socfpga/reset_manager_arria10.c  | 407 +
> >  .../{reset_manager.c => reset_manager_gen5.c}  |  82 +-
> >  arch/arm/mach-socfpga/spl.c|  79 +-
> >  arch/arm/mach-socfpga/system_manager.c |   6 +-
> >  board/altera/arria10-socdk/Kconfig |  18 +
> >  board/altera/arria10-socdk/Makefile|   7 +
> >  board/altera/arria10-socdk/socfpga.c   |   7 +
> >  configs/socfpga_arria10_defconfig  |  24 +
> >  drivers/Kconfig|   2 +
> >  drivers/Makefile   |   2 +-
> >  drivers/ddr/Kconfig|   1 +
> >  drivers/ddr/altera/Kconfig |   6 +
> >  drivers/fpga/socfpga.c

Re: [U-Boot] [PATCH v4 00/28] *** SUBJECT HERE ***

[Chee, Tien Fong]

On Sel, 2017-01-10 at 23:06 +0100, Marek Vasut wrote:
> On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> > 
> > *** BLURB HERE ***
> Please at least fill the blanks next time ... :)
> 
Oppssorry, i just realized i need to fill up the blanks here.
> > 
> > Tien Fong Chee (28):
> >   arm: socfpga: arria10: add additional i2c nodes for Arria10
> >   arm: socfpga: arria10: add sdram defines for Arria10
> >   arm: socfpga: arria10: add board files for the Arria10 SoCDK
> >   arm: socfpga: arria10: add system manager defines
> >   arm: socfpga: arria10: add misc functions for Arria10
> >   arm: socfpga: arria10: add socfpga_arria10_socdk config
> >   arm: socfpga: arria10: add socfpga_arria10_defconfig
> >   arm: socfpga: arria10: add config option build for arria10
> >   arm: socfpga: add define for bootinfo bsel bit shift
> >   arm: socfpga: arria10: add reset manager for Arria10
> >   arm: socfpga: wrap system manager functions for A5/C5 devices
> >   arm: socfpga: arria10: don't build GEN5 sdram for arria10
> >   arm: socfpga: arria10 fpga does not have bridges mapped
> >   arm: socfpga: arria10: remove board_init and s_init
> >   arm: socfpga: combine clrbits/setbits into a single clrsetbits
> >   arm: socfpga: add reset manager defines for Arria10
> >   arm: socfpga: arria10: update dwmac reset function to support
> > Arria10
> >   ARM:dts: Added device tree for socfpga arria10 development kit
> > sdmmc
> >   arm: socfpga: arria10: Enable SPL for Arria 10
> >   arm: socfpga: arria10: Added clock manager and pin mux compat
> > macro
> >   arm: socfpga: arria10: Added some hardware base address for Arria
> > 10
> >   arm: socfpga: arria10: Added support for Arria 10 socdk
> >   arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
> >   arm: socfpga: arria10: Added miscellaneous drivers for Arria 10
> >   arm: socfpga: arria10: Added drivers for Arria10 clock manager
> >   arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins
> > configuration
> >   arm: socfpga: arria10: Added Arria10 critical HW initialization
> > to spl
> >   arm: socfpga: arria10: Enable fpga driver build for SPL.
> > 
> >  arch/arm/dts/Makefile  |   3 +-
> >  arch/arm/dts/socfpga_arria10.dtsi  | 859
> > +++
> >  arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  30 +
> >  .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 479
> > +++
> >  arch/arm/mach-socfpga/Kconfig  |  10 +
> >  arch/arm/mach-socfpga/Makefile |  18 +-
> >  arch/arm/mach-socfpga/clock_manager.c  | 752 +++
> > -
> >  arch/arm/mach-socfpga/clock_manager_arria10.c  | 954
> > +
> >  .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
> >  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   8 +-
> >  arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
> >  arch/arm/mach-socfpga/include/mach/misc.h  |  32 +
> >  arch/arm/mach-socfpga/include/mach/pinmux.h|  17 +
> >  arch/arm/mach-socfpga/include/mach/reset_manager.h | 152 +++-
> >  arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 
> >  .../arm/mach-socfpga/include/mach/system_manager.h | 122 +++
> >  arch/arm/mach-socfpga/misc.c   | 367 +---
> >  arch/arm/mach-socfpga/misc_arria10.c   | 255 ++
> >  arch/arm/mach-socfpga/{misc.c => misc_gen5.c}  | 178 +---
> >  arch/arm/mach-socfpga/pinmux.c | 104 +++
> >  arch/arm/mach-socfpga/reset_manager.c  |  90 +-
> >  arch/arm/mach-socfpga/reset_manager_arria10.c  | 407 +
> >  .../{reset_manager.c => reset_manager_gen5.c}  |  82 +-
> >  arch/arm/mach-socfpga/spl.c|  79 +-
> >  arch/arm/mach-socfpga/system_manager.c |   6 +-
> >  board/altera/arria10-socdk/Kconfig |  18 +
> >  board/altera/arria10-socdk/Makefile|   7 +
> >  board/altera/arria10-socdk/socfpga.c   |   7 +
> >  configs/socfpga_arria10_defconfig  |  24 +
> >  drivers/Kconfig|   2 +
> >  drivers/Makefile   |   2 +-
> >  drivers/ddr/Kconfig|   1 +
> >  drivers/ddr/altera/Kconfig |   6 +
> >  drivers/fpga/socfpga.c

[U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/clock_manager.c  | 752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 954 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * 

[U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/clock_manager.c  | 752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 954 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * 

[U-Boot] [PATCH v4 27/28] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

[Chee Tien Fong]

From: Tien Fong Chee 

This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/spl.c | 79 +++--
 1 file changed, 76 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..d381904 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -19,37 +19,58 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define BOOTINFO_BSEL_SHIFT0
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define BOOTINFO_BSEL_SHIFT12
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(_regs->bootinfo);
 
-   switch (bsel & 0x7) {
+   switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
case 0x2:   /* NAND Flash (1.8V) */
case 0x3:   /* NAND Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
return BOOT_DEVICE_NAND;
case 0x4:   /* SD/MMC External Transceiver (1.8V) */
case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+#endif
return BOOT_DEVICE_MMC1;
case 0x6:   /* QSPI Flash (1.8V) */
case 0x7:   /* QSPI Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+#endif
return BOOT_DEVICE_SPI;
default:
printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -68,6 +89,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, _regs->lwhps2fpgaregs);
@@ -182,3 +204,54 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+   memset(__bss_start, 0, __bss_end - __bss_start);
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+   /* We need to access to FDT as this stage */
+   /* FDT is at end of image */
+   gd->fdt_blob = (void *)(__bss_end);
+   /* Check whether we have a valid FDT or not. */
+   if (fdtdec_prepare_fdt()) {
+   panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+   "doc/README.fdt-control");
+   }
+#endif /* CONFIG_OF_CONTROL */
+
+   /* Initialize the timer */
+   timer_init();
+
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   reset_deassert_uart();
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+#endif
-- 
2.2.0

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[U-Boot] [PATCH v4 28/28] arm: socfpga: arria10: Enable fpga driver build for SPL.

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa14..c15796b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)PINCTRL)+= pinctrl/
 obj-$(CONFIG_$(SPL_)RAM)   += ram/
 
 ifdef CONFIG_SPL_BUILD
-
+obj-$(CONFIG_FPGA) += fpga/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-- 
2.2.0

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[U-Boot] [PATCH v4 26/28] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/pinmux.h |  17 +
 arch/arm/mach-socfpga/pinmux.c  | 104 
 2 files changed, 121 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux.c

diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..ff54caa
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_PINMUX_H_
+#define_PINMUX_H_
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c
new file mode 100644
index 000..d45722f
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux.c
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+static int __do_pinctr_pins(const void *blob, int child, const char 
*node_name);
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name);
+
+static int __do_pinctr_pins(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", );
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins",
+   );
+   if (cell != NULL) {
+   debug("%p %d\n", cell, len);
+   for (;len > 0; len -= (2*sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   }
+   return 1;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return 2;
+
+   node_name = fdt_get_name(blob, child, );
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name)) {
+   __do_pinctr_pins(blob, child, node_name);
+   return(0);
+   }
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, );
+   }
+
+   return 1;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return 2;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return 3;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return 2;
+
+   return 0;
+}
-- 
2.2.0

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[U-Boot] [PATCH v4 22/28] arm: socfpga: arria10: Added support for Arria 10 socdk

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/system_manager.c  |  4 ++-
 drivers/fpga/socfpga.c  |  7 +++--
 include/configs/socfpga_arria10_socdk.h | 56 -
 include/configs/socfpga_common.h| 33 ---
 4 files changed, 71 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 9e1c3fd..e1f0082 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -11,8 +11,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index bfefafd..7fd922e 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
}
 
/* Prior programming the FPGA, all bridges need to be shut off */
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Disable all signals from hps peripheral controller to fpga */
writel(0, _regs->fpgaintfgrp_module);
+#endif
 
/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
index 577f60f..105c4c0 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2015 Altera Corporation 
+ *  Copyright (C) 2015-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0
  */
@@ -8,31 +8,20 @@
 #define __CONFIG_SOCFGPA_ARRIA10_H__
 
 #include 
+
 /* U-Boot Commands */
-#define CONFIG_SYS_NO_FLASH
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
 
-/*
- * Memory configurations
- */
-#define PHYS_SDRAM_1_SIZE  0x200
-
 /* Booting Linux */
-#define CONFIG_BOOTDELAY   3
 #define CONFIG_BOOTFILE"zImage"
 #define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
@@ -40,24 +29,30 @@
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /*
- * Display CPU and Board Info
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
+/*
+ * U-Boot console configurations
  */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DOS_PARTITION
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x8000
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9031
-
 #endif
 
+/*
+ * U-Boot environment configurations
+ */
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
-#define CONFIG_ENV_OFFSET  512/* just after the MBR */
 
 /*
  * arguments passed to the bootz command. The value of
@@ -89,6 +84,23 @@
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
"bootm ${loadaddr} - ${fdt_addr}\0"
 
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/*
+ * 

[U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/clock_manager.c  | 752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 954 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * 

[U-Boot] [PATCH v4 24/28] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile|   6 +-
 arch/arm/mach-socfpga/include/mach/misc.h |  32 ++
 arch/arm/mach-socfpga/misc.c  | 427 +-
 arch/arm/mach-socfpga/misc_arria10.c  | 255 +++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c} | 232 ++
 5 files changed, 337 insertions(+), 615 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (66%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b8fcf6e..1ab68be 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,9 +9,11 @@
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o 
\
+   clock_manager_arria10.o pinmux.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
-   reset_manager_gen5.o
+   reset_manager_gen5.o misc_gen5.o \
+   clock_manager_gen5.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..045268d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define_MISC_H_
+
+extern void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode);
+
+struct bsel{
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+extern void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 510aa1d..7fd5c0e 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,45 +7,33 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#include 
-#else
-#include 
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#else
-static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
-   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
-static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
-   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
-#endif
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bselbsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -84,219 +72,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id,
-const u32 phymode)
-{
-   

[U-Boot] [PATCH v4 23/28] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee Tien Fong]

From: Tien Fong Chee 

Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile |  16 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 155 ++--
 arch/arm/mach-socfpga/reset_manager.c  | 112 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 407 +
 .../{reset_manager.c => reset_manager_gen5.c}  |  94 ++---
 5 files changed, 570 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b8fcf6e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,21 +2,27 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2016 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+   reset_manager_gen5.o
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
+   wrap_pinmux_config.o wrap_sdram_config.o
+endif
 
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6225118..13f9731 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,15 +7,27 @@
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_
 
+/* Common function prototypes */
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
 void socfpga_bridges_reset(int enable);
-
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+void reset_deassert_peripherals_handoff(void);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+void reset_assert_uart(void);
+void reset_deassert_uart(void);
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -29,40 +41,40 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
-   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
-   u32 brg_mod_reset;
-   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
-   u32 coldmodrst;
-   u32 nrstmodrst;
-   u32 dbgmodrst;
-   u32 mpuwarmmask;
-   u32 per0warmmask;
-   u32 per1warmmask;
-   u32 brgwarmmask;
-   u32 syswarmmask;
-   u32 nrstwarmmask;
-   u32 l3warmmask;
-   u32 tststa;
-   u32 tstscratch;
-   u32 hdsktimeout;
-   u32 hmcintr;
-   u32 

[U-Boot] [PATCH v4 19/28] arm: socfpga: arria10: Enable SPL for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

This patch enables SPL build and implementation for Arria 10.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80c5992..0ed36cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+   select SUPPORT_SPL
select OF_CONTROL
-   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+   select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
-- 
2.2.0

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[U-Boot] [PATCH v4 18/28] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

[Chee Tien Fong]

From: Tien Fong Chee 

This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_arria10.dtsi  | 859 +
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 479 
 4 files changed, 1370 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3ee608b..024aa5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -137,7 +137,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_arria10_socdk_sdmmc.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
new file mode 100644
index 000..f63c4b4
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -0,0 +1,859 @@
+/*
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   ethernet2 = 
+   serial0 = 
+   serial1 = 
+   timer0 = 
+   timer1 = 
+   timer2 = 
+   timer3 = 
+   spi0 = 
+   spi1 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: intc@d000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <>;
+   ranges;
+
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   pdma: pdma@ffda1000 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda1000 0x1000>;
+   interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+<0 84 IRQ_TYPE_LEVEL_HIGH>,
+<0 85 IRQ_TYPE_LEVEL_HIGH>,
+<0 86 IRQ_TYPE_LEVEL_HIGH>,
+<0 87 IRQ_TYPE_LEVEL_HIGH>,
+<0 88 IRQ_TYPE_LEVEL_HIGH>,
+<0 89 IRQ_TYPE_LEVEL_HIGH>,
+<0 90 IRQ_TYPE_LEVEL_HIGH>,
+<0 91 IRQ_TYPE_LEVEL_HIGH>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clocks = <_main_clk>;
+   clock-names = "apb_pclk";
+   };
+   };
+
+   clkmgr@ffd04000 {
+   compatible = "altr,clk-mgr";
+   reg = <0xffd04000 0x1000>;
+   reg-names = 

[U-Boot] [PATCH v4 21/28] arm: socfpga: arria10: Added some hardware base address for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 902c321..2d66580 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -36,10 +36,13 @@
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
-- 
2.2.0

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[U-Boot] [PATCH v4 20/28] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee Tien Fong]

From: Tien Fong Chee 

These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/fdtdec.h | 8 
 lib/fdtdec.c | 8 
 2 files changed, 16 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..73e3a46 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,14 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_SUNXI_NAND,  /* SUNXI NAND controller */
+   COMPAT_ALTERA_SOCFPGA_CLK,  /* SoCFPGA Clock initialization */
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,   /* pinctrl-single */
+   COMPAT_ALTERA_SOCFPGA_H2F_BRG,  /* Arria10 hps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 lwhps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_F2H_BRG,  /* Arria10 fpga2hps bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR0,   /* Arria10 fpga2SDRAM0 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR1,   /* Arria10 fpga2SDRAM1 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR2,   /* Arria10 fpga2SDRAM2 bridge */
 
COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 81f47ef..ebe4a9a 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+   COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+   COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+   COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
2.2.0

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[U-Boot] [PATCH v4 17/28] arm: socfpga: arria10: update dwmac reset function to support Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.

Update the dwmac_deassert_reset function to support both GEN5 and Arria10
devices.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/system_manager.h |  4 +---
 arch/arm/mach-socfpga/misc.c| 14 ++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 9ca889a..831ba4a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -133,9 +133,7 @@ struct socfpga_system_manager {
u32  usb0_l3master;
u32  usb1_l3master;
u32  emac_global;
-   u32  emac0;
-   u32  emac1;
-   u32  emac2;
+   u32  emac[3];
u32  _pad_0x50_0x5f[4];
u32  fpgaintf_en_global;
u32  fpgaintf_en_0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c97caea..510aa1d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -21,7 +21,11 @@
 #include 
 #include 
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#else
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
} else if (of_reset_id == EMAC1_RESET) {
physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
reset = SOCFPGA_RESET(EMAC1);
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+#endif
} else {
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
return;
}
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* configure to PHY interface select choosed */
clrsetbits_le32(_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
phymode << physhift);
+#else
+   clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+#endif
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
2.2.0

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[U-Boot] [PATCH v4 16/28] arm: socfpga: add reset manager defines for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.

[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++
 1 file changed, 103 insertions(+)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h 
b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 000..7619ca2
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET  2
+#define SCUPER_RESET   3
+
+/* PER0MODRST */
+#define EMAC0_RESET32
+#define EMAC1_RESET33
+#define EMAC2_RESET34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET39
+#define EMAC0_OCP_RESET40
+#define EMAC1_OCP_RESET41
+#define EMAC2_OCP_RESET42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET47
+#define DMA_RESET  48
+#define SPIM0_RESET49
+#define SPIM1_RESET50
+#define SPIS0_RESET51
+#define SPIS1_RESET52
+#define DMA_OCP_RESET  53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET   56
+#define DMAIF1_RESET   57
+#define DMAIF2_RESET   58
+#define DMAIF3_RESET   59
+#define DMAIF4_RESET   60
+#define DMAIF5_RESET   61
+#define DMAIF6_RESET   62
+#define DMAIF7_RESET   63
+
+/* PER1MODRST */
+#define L4WD0_RESET64
+#define L4WD1_RESET65
+#define L4SYSTIMER0_RESET  66
+#define L4SYSTIMER1_RESET  67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET80
+#define UART1_RESET81
+/* 82-87 is reserved */
+#define GPIO0_RESET88
+#define GPIO1_RESET89
+#define GPIO2_RESET90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET   97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET99
+#define F2SSDRAM1_RESET100
+#define F2SSDRAM2_RESET101
+#define DDRSCH_RESET   102
+
+/* SYSMODRST*/
+#define ROM_RESET  128
+#define OCRAM_RESET129
+/* 130 is reserved */
+#define FPGAMGR_RESET  131
+#define S2F_RESET  132
+#define SYSDBG_RESET   133
+#define OCRAM_OCP_RESET134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET   160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET  163
+#define TIMESTAMPCOLD_RESET164
+#define TAPCOLD_RESET  165
+#define HMCCOLD_RESET  166
+#define IOMGRCOLD_RESET167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET192
+
+/* DBGMODRST */
+#define DBG_RESET  224
+#endif
-- 
2.2.0

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[U-Boot] [PATCH v4 14/28] arm: socfpga: arria10: remove board_init and s_init

[Chee Tien Fong]

From: Tien Fong Chee 

These functions are already in arch/arm/mach-socfpga/board.c

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 board/altera/arria10-socdk/socfpga.c | 17 -
 1 file changed, 17 deletions(-)

diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
index abedc22..8516633 100644
--- a/board/altera/arria10-socdk/socfpga.c
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -5,20 +5,3 @@
  */
 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void)
-{
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-   /* Address of boot parameters for ATAG (if ATAG is used) */
-   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-   return 0;
-}
-- 
2.2.0

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[U-Boot] [PATCH v4 15/28] arm: socfpga: combine clrbits/setbits into a single clrsetbits

[Chee Tien Fong]

From: Tien Fong Chee 

There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/misc.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 2645129..c97caea 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
return;
}
 
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
/* configure to PHY interface select choosed */
-   setbits_le32(_regs->emacgrp_ctrl,
-phymode << physhift);
+   clrsetbits_le32(_regs->emacgrp_ctrl,
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
+   phymode << physhift);
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
2.2.0

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[U-Boot] [PATCH v4 13/28] arm: socfpga: arria10 fpga does not have bridges mapped

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10 device, the bridges are not mapped through the interconnect.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/fpga/socfpga.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..bfefafd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset(1);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Unmap the bridges from NIC-301 */
writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
 
/* Initialize the FPGA Manager */
status = fpgamgr_program_init();
-- 
2.2.0

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[U-Boot] [PATCH v4 12/28] arm: socfpga: arria10: don't build GEN5 sdram for arria10

[Chee Tien Fong]

From: Tien Fong Chee 

The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/Kconfig  | 2 ++
 drivers/ddr/Kconfig  | 1 +
 drivers/ddr/altera/Kconfig   | 6 ++
 include/configs/socfpga_common.h | 5 -
 4 files changed, 9 insertions(+), 5 deletions(-)
 create mode 100644 drivers/ddr/Kconfig
 create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 0e5d97d..3e6bbac 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/ddr/fsl/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 000..b764add
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 000..9554da7
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,6 @@
+config ALTERA_SDRAM
+   bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
+   default y if TARGET_SOCFPGA_GEN5
+   help
+ This is for building the SDRAM controller for the Arria5/Cyclone5
+ devices.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 31f1338..bbbde1e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -77,11 +77,6 @@
 #define CONFIG_SYS_PL310_BASE  SOCFPGA_MPUL2_ADDRESS
 
 /*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
  * EPCS/EPCQx1 Serial Flash Controller
  */
 #ifdef CONFIG_ALTERA_SPI
-- 
2.2.0

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[U-Boot] [PATCH v4 09/28] arm: socfpga: add define for bootinfo bsel bit shift

[Chee Tien Fong]

From: Tien Fong Chee 

On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.

Suggested-by: Marek Vasut 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++
 arch/arm/mach-socfpga/misc.c| 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e688c50..9ca889a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -203,8 +203,10 @@ struct socfpga_system_manager {
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
 #else
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
 #endif
 
 #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c1e5969..2645129 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+   const u32 bsel = (readl(_regs->bootinfo) >>
+ SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-   const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
 #else
-   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
puts("CPU:   Altera SoCFPGA Arria 10\n");
 #endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
-- 
2.2.0

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[U-Boot] [PATCH v4 11/28] arm: socfpga: wrap system manager functions for A5/C5 devices

[Chee Tien Fong]

From: Tien Fong Chee 

The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/system_manager.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 75a65f3..9e1c3fd 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs =
  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void populate_sysmgr_fpgaintf_module(void)
 {
uint32_t handoff_val = 0;
@@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable)
clrbits_le32(_regs->romcodegrp_ctrl,
 SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
2.2.0

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[U-Boot] [PATCH v4 08/28] arm: socfpga: arria10: add config option build for arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/Kconfig  |  4 ++--
 arch/arm/mach-socfpga/Kconfig | 10 ++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0ed36cd..80c5992 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL
+   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
-   select SPL_OF_CONTROL
+   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
select DM
select DM_SPI_FLASH
select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6991af8..d9a5178 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+   bool
+
 config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_DENX_MCVEVK
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -86,6 +93,7 @@ endchoice
 
 config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -98,6 +106,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -111,6 +120,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
-- 
2.2.0

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[U-Boot] [PATCH v4 10/28] arm: socfpga: arria10: add reset manager for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++
 arch/arm/mach-socfpga/reset_manager.c  | 24 +++-
 2 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..6225118 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
+#else
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
+   u32 brg_mod_reset;
+   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -75,6 +113,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c 
b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..d0ff6c4 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base 
=
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
 void socfpga_per_reset(u32 reset, int set)
 {
const void *reg;
@@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
  */
 void 

[U-Boot] [PATCH v4 06/28] arm: socfpga: arria10: add socfpga_arria10_socdk config

[Chee Tien Fong]

From: Tien Fong Chee 

Add config for the Arria10 SoC Development Kit.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Acked-by: Marek Vasut 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/configs/socfpga_arria10_socdk.h | 94 +
 1 file changed, 94 insertions(+)
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 000..577f60f
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include 
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1_SIZE  0x200
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY   3
+#define CONFIG_BOOTFILE"zImage"
+#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR0x0100
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
+#define CONFIG_ENV_OFFSET  512/* just after the MBR */
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "verify=n\0" \
+   "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "bootimage=zImage\0" \
+   "fdt_addr=100\0" \
+   "fdtimage=socfpga.dtb\0" \
+   "fsloadcmd=ext2load\0" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "mmcroot=/dev/mmcblk0p2\0" \
+   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${mmcroot} rw rootwait;" \
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "mmcload=mmc rescan;" \
+   "load mmc 0:1 ${loadaddr} ${bootimage};" \
+   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+   "qspiroot=/dev/mtdblock0\0" \
+   "qspirootfstype=jffs2\0" \
+   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+   "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include 
+#endif /* __CONFIG_H */
-- 
2.2.0

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[U-Boot] [PATCH v4 07/28] arm: socfpga: arria10: add socfpga_arria10_defconfig

[Chee Tien Fong]

From: Tien Fong Chee 

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Acked-by: Marek Vasut 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 configs/socfpga_arria10_defconfig | 24 
 1 file changed, 24 insertions(+)
 create mode 100644 configs/socfpga_arria10_defconfig

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
new file mode 100644
index 000..755bb66
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
2.2.0

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[U-Boot] [PATCH v4 04/28] arm: socfpga: arria10: add system manager defines

[Chee Tien Fong]

From: Tien Fong Chee 

Add system manager defines for Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 .../arm/mach-socfpga/include/mach/system_manager.h | 122 +
 1 file changed, 122 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..e688c50 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable);
 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_system_manager {
/* System Manager Module */
u32 siliconid1; /* 0x00 */
@@ -115,6 +116,77 @@ struct socfpga_system_manager {
u32 _pad_0x734;
u32 spim0usefpga;   /* 0x738 */
 };
+#else /* Arria10 System Manager */
+struct socfpga_system_manager {
+   u32  siliconid1;
+   u32  siliconid2;
+   u32  wddbg;
+   u32  bootinfo;
+   u32  mpu_ctrl_l2_ecc;
+   u32  _pad_0x14_0x1f[3];
+   u32  dma;
+   u32  dma_periph;
+   u32  sdmmcgrp_ctrl;
+   u32  sdmmc_l3master;
+   u32  nand_bootstrap;
+   u32  nand_l3master;
+   u32  usb0_l3master;
+   u32  usb1_l3master;
+   u32  emac_global;
+   u32  emac0;
+   u32  emac1;
+   u32  emac2;
+   u32  _pad_0x50_0x5f[4];
+   u32  fpgaintf_en_global;
+   u32  fpgaintf_en_0;
+   u32  fpgaintf_en_1;
+   u32  fpgaintf_en_2;
+   u32  fpgaintf_en_3;
+   u32  _pad_0x74_0x7f[3];
+   u32  noc_addr_remap_value;
+   u32  noc_addr_remap_set;
+   u32  noc_addr_remap_clear;
+   u32  _pad_0x8c_0x8f;
+   u32  ecc_intmask_value;
+   u32  ecc_intmask_set;
+   u32  ecc_intmask_clr;
+   u32  ecc_intstatus_serr;
+   u32  ecc_intstatus_derr;
+   u32  mpu_status_l2_ecc;
+   u32  mpu_clear_l2_ecc;
+   u32  mpu_status_l1_parity;
+   u32  mpu_clear_l1_parity;
+   u32  mpu_set_l1_parity;
+   u32  _pad_0xb8_0xbf[2];
+   u32  noc_timeout;
+   u32  noc_idlereq_set;
+   u32  noc_idlereq_clr;
+   u32  noc_idlereq_value;
+   u32  noc_idleack;
+   u32  noc_idlestatus;
+   u32  fpga2soc_ctrl;
+   u32  _pad_0xdc_0xff[9];
+   u32  tsmc_tsel_0;
+   u32  tsmc_tsel_1;
+   u32  tsmc_tsel_2;
+   u32  tsmc_tsel_3;
+   u32  _pad_0x110_0x200[60];
+   u32  romhw_ctrl;
+   u32  romcode_ctrl;
+   u32  romcode_cpu1startaddr;
+   u32  romcode_initswstate;
+   u32  romcode_initswlastld;
+   u32  _pad_0x214_0x217;
+   u32  warmram_enable;
+   u32  warmram_datastart;
+   u32  warmram_length;
+   u32  warmram_execution;
+   u32  warmram_crc;
+   u32  _pad_0x22c_0x22f;
+   u32  isw_handoff[8];
+   u32  romcode_bootromswstate[8];
+};
+#endif
 
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1)
@@ -146,4 +218,54 @@ struct socfpga_system_manager {
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V   0x1
+#define VOLTAGE_SEL_2P5V   0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE  0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V   2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE  0
+#define WK_PU_ENABLE   1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT  PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT  PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT0x10
+#define PD_DRV_STRG_DEFAULT0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB0
+#define PD_SLW_RT_LSB  5
+#define PU_DRV_STRG_LSB8
+#define PU_SLW_RT_LSB  13
+#define WK_PU_LSB  16
+#define INPUT_BUF_LSB  17
+#define BIAS_TRIM_LSB  19
+#define VOLTAGE_SEL_LSB0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK   0x0010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK  0x0001
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK  0x0010
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK  0x0100

[U-Boot] [PATCH v4 03/28] arm: socfpga: arria10: add board files for the Arria10 SoCDK

[Chee Tien Fong]

From: Tien Fong Chee 

Add minimal support for the Arria10 SoCDK.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 board/altera/arria10-socdk/Kconfig   | 18 ++
 board/altera/arria10-socdk/Makefile  |  7 +++
 board/altera/arria10-socdk/socfpga.c | 24 
 3 files changed, 49 insertions(+)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig 
b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+   default "armv7"
+
+config SYS_BOARD
+   default "socfpga_arria10"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile 
b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000..abedc22
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+   /* Address of boot parameters for ATAG (if ATAG is used) */
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+   return 0;
+}
-- 
2.2.0

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[U-Boot] [PATCH v4 02/28] arm: socfpga: arria10: add sdram defines for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the structures for the SDRAM controller on Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 +
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
new file mode 100644
index 000..0403531
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SOCFPGA_SDRAM_A10_H_
+#define_SOCFPGA_SDRAM_A10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 caltiming4;
+   

[U-Boot] [PATCH v4 05/28] arm: socfpga: arria10: add misc functions for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/misc.c | 51 
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..c1e5969 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#else
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
@@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
+#else
+   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
+   puts("CPU:   Altera SoCFPGA Arria 10\n");
+#endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
return 0;
 }
@@ -338,6 +351,7 @@ int arch_cpu_init(void)
return 0;
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
@@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 
return 0;
 }
+#else
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+   /* Put OCRAM in non-secure */
+   writel(0x003f, _fw_ocram_base->region0);
+   writel(0x1, _fw_ocram_base->enable);
+
+   /* Put DDR in non-secure */
+   writel(0x, _fw_ddr_l3_base->hpsregion0addr);
+   writel(0x1, _fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+   initialize_security_policies();
+
+   /* Configure the L2 controller to make SDRAM start at 0 */
+   writel(0x1, >pl310_addr_filter_start);
+
+   /* assert reset to all except L4WD0 and L4TIMER0 */
+   socfpga_per_reset_all();
+
+   /* configuring the clock based on handoff */
+   /* TODO: Add call to cm_basic_init() */
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
+   return 0;
+}
+#endif
 
 U_BOOT_CMD(
bridge, 2, 1, do_bridge,
-- 
2.2.0

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[U-Boot] [PATCH v4 01/28] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add remaining 3 I2C base addresses for the Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Reviewed-by: Stefan Roese 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..902c321 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -29,6 +29,9 @@
 #define SOCFPGA_MPUL2_ADDRESS  0xf000
 #define SOCFPGA_I2C0_ADDRESS   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
-- 
2.2.0

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[U-Boot] [PATCH v4 00/28] *** SUBJECT HERE ***

[Chee Tien Fong]

From: Tien Fong Chee 

*** BLURB HERE ***

Tien Fong Chee (28):
  arm: socfpga: arria10: add additional i2c nodes for Arria10
  arm: socfpga: arria10: add sdram defines for Arria10
  arm: socfpga: arria10: add board files for the Arria10 SoCDK
  arm: socfpga: arria10: add system manager defines
  arm: socfpga: arria10: add misc functions for Arria10
  arm: socfpga: arria10: add socfpga_arria10_socdk config
  arm: socfpga: arria10: add socfpga_arria10_defconfig
  arm: socfpga: arria10: add config option build for arria10
  arm: socfpga: add define for bootinfo bsel bit shift
  arm: socfpga: arria10: add reset manager for Arria10
  arm: socfpga: wrap system manager functions for A5/C5 devices
  arm: socfpga: arria10: don't build GEN5 sdram for arria10
  arm: socfpga: arria10 fpga does not have bridges mapped
  arm: socfpga: arria10: remove board_init and s_init
  arm: socfpga: combine clrbits/setbits into a single clrsetbits
  arm: socfpga: add reset manager defines for Arria10
  arm: socfpga: arria10: update dwmac reset function to support Arria10
  ARM:dts: Added device tree for socfpga arria10 development kit sdmmc
  arm: socfpga: arria10: Enable SPL for Arria 10
  arm: socfpga: arria10: Added clock manager and pin mux compat macro
  arm: socfpga: arria10: Added some hardware base address for Arria 10
  arm: socfpga: arria10: Added support for Arria 10 socdk
  arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
  arm: socfpga: arria10: Added miscellaneous drivers for Arria 10
  arm: socfpga: arria10: Added drivers for Arria10 clock manager
  arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins
configuration
  arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
  arm: socfpga: arria10: Enable fpga driver build for SPL.

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_arria10.dtsi  | 859 +++
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 479 +++
 arch/arm/mach-socfpga/Kconfig  |  10 +
 arch/arm/mach-socfpga/Makefile |  18 +-
 arch/arm/mach-socfpga/clock_manager.c  | 752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 954 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   8 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
 arch/arm/mach-socfpga/include/mach/misc.h  |  32 +
 arch/arm/mach-socfpga/include/mach/pinmux.h|  17 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 152 +++-
 arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 
 .../arm/mach-socfpga/include/mach/system_manager.h | 122 +++
 arch/arm/mach-socfpga/misc.c   | 367 +---
 arch/arm/mach-socfpga/misc_arria10.c   | 255 ++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c}  | 178 +---
 arch/arm/mach-socfpga/pinmux.c | 104 +++
 arch/arm/mach-socfpga/reset_manager.c  |  90 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 407 +
 .../{reset_manager.c => reset_manager_gen5.c}  |  82 +-
 arch/arm/mach-socfpga/spl.c|  79 +-
 arch/arm/mach-socfpga/system_manager.c |   6 +-
 board/altera/arria10-socdk/Kconfig |  18 +
 board/altera/arria10-socdk/Makefile|   7 +
 board/altera/arria10-socdk/socfpga.c   |   7 +
 configs/socfpga_arria10_defconfig  |  24 +
 drivers/Kconfig|   2 +
 drivers/Makefile   |   2 +-
 drivers/ddr/Kconfig|   1 +
 drivers/ddr/altera/Kconfig |   6 +
 drivers/fpga/socfpga.c |   9 +-
 include/configs/socfpga_arria10_socdk.h| 106 +++
 include/configs/socfpga_common.h   |  38 +-
 include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 +++
 include/fdtdec.h   |   8 +
 lib/fdtdec.c   |   8 +
 39 files changed, 4937 insertions(+), 1382 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (73%)
 create mode 

Re: [U-Boot] [v4 18/29] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

[Chee, Tien Fong]

On Isn, 2017-01-09 at 08:47 -0600, Dinh Nguyen wrote:
> 
> On 01/09/2017 05:31 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> > 
> > Add base address header file for Stratix10 SoC
> > 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > Cc: Ley Foon Tan <lf...@altera.com>
> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   48
> > 
> >  1 files changed, 48 insertions(+), 0 deletions(-)
> >  create mode 100755 arch/arm/mach-
> > socfpga/include/mach/base_addr_s10.h
> While this is really nice to see, but can you separate this patch out
> from the Arria10 series. It's already confusing enough.
> 
> Dinh
Ahhthis was rebased from 01-arria10. Okay, i will remove this
patch.
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Re: [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee, Tien Fong]

On Isn, 2017-01-09 at 13:43 +0100, Marek Vasut wrote:
> On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> > 
> > Add remaining 3 I2C base addresses for the Arria10.
> > 
> > Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
> > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > Reviewed-by: Stefan Roese <s...@denx.de>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@kernel.org>
> > Cc: Chin Liang See <chin.liang@intel.com>
> > Cc: Tien Fong <skywind...@gmail.com>
> Please, just use git send-email to send the whole series. Don't drop
> the
> PATCH from the subject or anything. I am ignoring this series until
> it's
> sent properly.
> 
Ahhi catched what you means. I was used --subject-prefix when -v
was not working. Well, i would try again.
> > 
> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |3 +++
> >  1 files changed, 3 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > index a7056d4..902c321 100644
> > --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > @@ -29,6 +29,9 @@
> >  #define SOCFPGA_MPUL2_ADDRESS  0xf000
> >  #define SOCFPGA_I2C0_ADDRESS   0xffc02200
> >  #define SOCFPGA_I2C1_ADDRESS   0xffc02300
> > +#define SOCFPGA_I2C2_ADDRESS   0xffc02400
> > +#define SOCFPGA_I2C3_ADDRESS   0xffc02500
> > +#define SOCFPGA_I2C4_ADDRESS   0xffc02600
> >  
> >  #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
> >  #define SOCFPGA_UART0_ADDRESS  0xffc02000
> > 
> 
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Re: [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee, Tien Fong]

On Isn, 2017-01-09 at 10:54 -0600, Dinh Nguyen wrote:
> On Mon, Jan 9, 2017 at 6:43 AM, Marek Vasut <ma...@denx.de> wrote:
> > 
> > On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> > > 
> > > From: Tien Fong Chee <tien.fong.c...@intel.com>
> > > 
> > > Add remaining 3 I2C base addresses for the Arria10.
> > > 
> > > Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
> > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > > Reviewed-by: Stefan Roese <s...@denx.de>
> > > Cc: Marek Vasut <ma...@denx.de>
> > > Cc: Dinh Nguyen <dingu...@kernel.org>
> > > Cc: Chin Liang See <chin.liang@intel.com>
> > > Cc: Tien Fong <skywind...@gmail.com>
> > Please, just use git send-email to send the whole series. Don't
> > drop the
> > PATCH from the subject or anything. I am ignoring this series until
> > it's
> > sent properly.
> > 
Hi, i dind't drop any patch, this is rev4 with changes suggested from
Dinh which is merging the patch21 into patch7.

> Also, can I ask why the revision bump to v4? Please give reviewers
> time to
> review such a big change set before bumping the rev when most of the
> patches haven't been reviewed yet.
> 
> Dinh
Ohhwe thought that if reviewer has comment on any patch, some
reviewers might waiting next revision then only review.
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[U-Boot] [v4 29/29] arm: socfpga: arria10: Enable fpga driver build for SPL.

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/Makefile |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa14..c15796b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)PINCTRL)+= pinctrl/
 obj-$(CONFIG_$(SPL_)RAM)   += ram/
 
 ifdef CONFIG_SPL_BUILD
-
+obj-$(CONFIG_FPGA) += fpga/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-- 
1.7.7.4

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[U-Boot] [v4 28/29] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

[Chee Tien Fong]

From: Tien Fong Chee 

This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/spl.c |   79 +--
 1 files changed, 76 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..d381904 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -19,37 +19,58 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define BOOTINFO_BSEL_SHIFT0
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define BOOTINFO_BSEL_SHIFT12
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(_regs->bootinfo);
 
-   switch (bsel & 0x7) {
+   switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
case 0x2:   /* NAND Flash (1.8V) */
case 0x3:   /* NAND Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
return BOOT_DEVICE_NAND;
case 0x4:   /* SD/MMC External Transceiver (1.8V) */
case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+#endif
return BOOT_DEVICE_MMC1;
case 0x6:   /* QSPI Flash (1.8V) */
case 0x7:   /* QSPI Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+#endif
return BOOT_DEVICE_SPI;
default:
printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -68,6 +89,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, _regs->lwhps2fpgaregs);
@@ -182,3 +204,54 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+   memset(__bss_start, 0, __bss_end - __bss_start);
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+   /* We need to access to FDT as this stage */
+   /* FDT is at end of image */
+   gd->fdt_blob = (void *)(__bss_end);
+   /* Check whether we have a valid FDT or not. */
+   if (fdtdec_prepare_fdt()) {
+   panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+   "doc/README.fdt-control");
+   }
+#endif /* CONFIG_OF_CONTROL */
+
+   /* Initialize the timer */
+   timer_init();
+
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   reset_deassert_uart();
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+#endif
-- 
1.7.7.4

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[U-Boot] [v4 27/29] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/pinmux.h |   17 +
 arch/arm/mach-socfpga/pinmux.c  |  104 +++
 2 files changed, 121 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux.c

diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..ff54caa
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_PINMUX_H_
+#define_PINMUX_H_
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c
new file mode 100644
index 000..d45722f
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux.c
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+static int __do_pinctr_pins(const void *blob, int child, const char 
*node_name);
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name);
+
+static int __do_pinctr_pins(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", );
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins",
+   );
+   if (cell != NULL) {
+   debug("%p %d\n", cell, len);
+   for (;len > 0; len -= (2*sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   }
+   return 1;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return 2;
+
+   node_name = fdt_get_name(blob, child, );
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name)) {
+   __do_pinctr_pins(blob, child, node_name);
+   return(0);
+   }
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, );
+   }
+
+   return 1;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return 2;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return 3;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return 2;
+
+   return 0;
+}
-- 
1.7.7.4

___
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U-Boot@lists.denx.de
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[U-Boot] [v4 26/29] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/clock_manager.c  |  752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  |  954 
 .../{clock_manager.c => clock_manager_gen5.c}  |  240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * 

[U-Boot] [v4 25/29] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile|6 +-
 arch/arm/mach-socfpga/include/mach/misc.h |   32 ++
 arch/arm/mach-socfpga/misc.c  |  427 +
 arch/arm/mach-socfpga/misc_arria10.c  |  255 +++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c} |  232 ++
 5 files changed, 337 insertions(+), 615 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (66%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b8fcf6e..1ab68be 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,9 +9,11 @@
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o 
\
+   clock_manager_arria10.o pinmux.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
-   reset_manager_gen5.o
+   reset_manager_gen5.o misc_gen5.o \
+   clock_manager_gen5.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..045268d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define_MISC_H_
+
+extern void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode);
+
+struct bsel{
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+extern void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 510aa1d..7fd5c0e 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,45 +7,33 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#include 
-#else
-#include 
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#else
-static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
-   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
-static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
-   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
-#endif
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bselbsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -84,219 +72,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id,
-const u32 phymode)
-{
-   

[U-Boot] [v4 24/29] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee Tien Fong]

From: Tien Fong Chee 

Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile |   16 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  155 ++--
 arch/arm/mach-socfpga/reset_manager.c  |  112 +--
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  407 
 .../{reset_manager.c => reset_manager_gen5.c}  |   94 ++---
 5 files changed, 570 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b8fcf6e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,21 +2,27 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2016 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+   reset_manager_gen5.o
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
+   wrap_pinmux_config.o wrap_sdram_config.o
+endif
 
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6225118..13f9731 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,15 +7,27 @@
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_
 
+/* Common function prototypes */
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
 void socfpga_bridges_reset(int enable);
-
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+void reset_deassert_peripherals_handoff(void);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+void reset_assert_uart(void);
+void reset_deassert_uart(void);
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -29,40 +41,40 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
-   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
-   u32 brg_mod_reset;
-   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
-   u32 coldmodrst;
-   u32 nrstmodrst;
-   u32 dbgmodrst;
-   u32 mpuwarmmask;
-   u32 per0warmmask;
-   u32 per1warmmask;
-   u32 brgwarmmask;
-   u32 syswarmmask;
-   u32 nrstwarmmask;
-   u32 l3warmmask;
-   u32 tststa;
-   u32 tstscratch;
-   u32 hdsktimeout;
-   u32 hmcintr;
-   u32 

[U-Boot] [v4 23/29] arm: socfpga: arria10: Added support for Arria 10 socdk

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/system_manager.c  |4 ++-
 drivers/fpga/socfpga.c  |7 +++-
 include/configs/socfpga_arria10_socdk.h |   56 +++
 include/configs/socfpga_common.h|   33 --
 4 files changed, 71 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 9e1c3fd..e1f0082 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -11,8 +11,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index bfefafd..7fd922e 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
}
 
/* Prior programming the FPGA, all bridges need to be shut off */
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Disable all signals from hps peripheral controller to fpga */
writel(0, _regs->fpgaintfgrp_module);
+#endif
 
/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
index 577f60f..105c4c0 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2015 Altera Corporation 
+ *  Copyright (C) 2015-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0
  */
@@ -8,31 +8,20 @@
 #define __CONFIG_SOCFGPA_ARRIA10_H__
 
 #include 
+
 /* U-Boot Commands */
-#define CONFIG_SYS_NO_FLASH
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
 
-/*
- * Memory configurations
- */
-#define PHYS_SDRAM_1_SIZE  0x200
-
 /* Booting Linux */
-#define CONFIG_BOOTDELAY   3
 #define CONFIG_BOOTFILE"zImage"
 #define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
@@ -40,24 +29,30 @@
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /*
- * Display CPU and Board Info
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
+/*
+ * U-Boot console configurations
  */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DOS_PARTITION
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x8000
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9031
-
 #endif
 
+/*
+ * U-Boot environment configurations
+ */
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
-#define CONFIG_ENV_OFFSET  512/* just after the MBR */
 
 /*
  * arguments passed to the bootz command. The value of
@@ -89,6 +84,23 @@
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
"bootm ${loadaddr} - ${fdt_addr}\0"
 
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/*
+ 

[U-Boot] [v4 22/29] arm: socfpga: arria10: Added some hardware base address for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 902c321..2d66580 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -36,10 +36,13 @@
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
-- 
1.7.7.4

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[U-Boot] [v4 20/29] arm: socfpga: arria10: Enable SPL for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

This patch enables SPL build and implementation for Arria 10.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/Kconfig |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80c5992..0ed36cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+   select SUPPORT_SPL
select OF_CONTROL
-   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+   select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
-- 
1.7.7.4

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[U-Boot] [v4 21/29] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee Tien Fong]

From: Tien Fong Chee 

These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/fdtdec.h |8 
 lib/fdtdec.c |8 
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..73e3a46 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,14 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_SUNXI_NAND,  /* SUNXI NAND controller */
+   COMPAT_ALTERA_SOCFPGA_CLK,  /* SoCFPGA Clock initialization */
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,   /* pinctrl-single */
+   COMPAT_ALTERA_SOCFPGA_H2F_BRG,  /* Arria10 hps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 lwhps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_F2H_BRG,  /* Arria10 fpga2hps bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR0,   /* Arria10 fpga2SDRAM0 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR1,   /* Arria10 fpga2SDRAM1 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR2,   /* Arria10 fpga2SDRAM2 bridge */
 
COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 81f47ef..ebe4a9a 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+   COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+   COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+   COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
1.7.7.4

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[U-Boot] [v4 19/29] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

[Chee Tien Fong]

From: Tien Fong Chee 

This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/dts/Makefile  |3 +-
 arch/arm/dts/socfpga_arria10.dtsi  |  859 
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |   30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   |  479 +++
 4 files changed, 1370 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3ee608b..024aa5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -137,7 +137,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_arria10_socdk_sdmmc.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
new file mode 100644
index 000..f63c4b4
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -0,0 +1,859 @@
+/*
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   ethernet2 = 
+   serial0 = 
+   serial1 = 
+   timer0 = 
+   timer1 = 
+   timer2 = 
+   timer3 = 
+   spi0 = 
+   spi1 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: intc@d000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <>;
+   ranges;
+
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   pdma: pdma@ffda1000 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda1000 0x1000>;
+   interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+<0 84 IRQ_TYPE_LEVEL_HIGH>,
+<0 85 IRQ_TYPE_LEVEL_HIGH>,
+<0 86 IRQ_TYPE_LEVEL_HIGH>,
+<0 87 IRQ_TYPE_LEVEL_HIGH>,
+<0 88 IRQ_TYPE_LEVEL_HIGH>,
+<0 89 IRQ_TYPE_LEVEL_HIGH>,
+<0 90 IRQ_TYPE_LEVEL_HIGH>,
+<0 91 IRQ_TYPE_LEVEL_HIGH>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clocks = <_main_clk>;
+   clock-names = "apb_pclk";
+   };
+   };
+
+   clkmgr@ffd04000 {
+   compatible = "altr,clk-mgr";
+   reg = <0xffd04000 0x1000>;
+   reg-names = 

[U-Boot] [v4 18/29] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

[Chee Tien Fong]

From: Tien Fong Chee 

Add base address header file for Stratix10 SoC

Signed-off-by: Chin Liang See 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   48 
 1 files changed, 48 insertions(+), 0 deletions(-)
 create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100755
index 000..411518d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS   0xfa00
+#define SOCFPGA_EMAC0_ADDRESS  0xff80
+#define SOCFPGA_EMAC1_ADDRESS  0xff802000
+#define SOCFPGA_EMAC2_ADDRESS  0xff804000
+#define SOCFPGA_SDMMC_ADDRESS  0xff808000
+#define SOCFPGA_USB0_ADDRESS   0xffb0
+#define SOCFPGA_USB1_ADDRESS   0xffb4
+#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
+#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
+#define SOCFPGA_UART0_ADDRESS  0xffc02000
+#define SOCFPGA_UART1_ADDRESS  0xffc02100
+#define SOCFPGA_I2C0_ADDRESS   0xffc02800
+#define SOCFPGA_I2C1_ADDRESS   0xffc02900
+#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00300
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00400
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
+#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS  0xffe0
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
1.7.7.4

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[U-Boot] [v4 17/29] arm: socfpga: arria10: update dwmac reset function to support Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.

Update the dwmac_deassert_reset function to support both GEN5 and Arria10
devices.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 .../arm/mach-socfpga/include/mach/system_manager.h |4 +---
 arch/arm/mach-socfpga/misc.c   |   14 ++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 9ca889a..831ba4a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -133,9 +133,7 @@ struct socfpga_system_manager {
u32  usb0_l3master;
u32  usb1_l3master;
u32  emac_global;
-   u32  emac0;
-   u32  emac1;
-   u32  emac2;
+   u32  emac[3];
u32  _pad_0x50_0x5f[4];
u32  fpgaintf_en_global;
u32  fpgaintf_en_0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c97caea..510aa1d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -21,7 +21,11 @@
 #include 
 #include 
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#else
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
} else if (of_reset_id == EMAC1_RESET) {
physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
reset = SOCFPGA_RESET(EMAC1);
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+#endif
} else {
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
return;
}
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* configure to PHY interface select choosed */
clrsetbits_le32(_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
phymode << physhift);
+#else
+   clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+#endif
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
1.7.7.4

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[U-Boot] [v4 13/29] arm: socfpga: arria10 fpga does not have bridges mapped

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10 device, the bridges are not mapped through the interconnect.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/fpga/socfpga.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..bfefafd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset(1);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Unmap the bridges from NIC-301 */
writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
 
/* Initialize the FPGA Manager */
status = fpgamgr_program_init();
-- 
1.7.7.4

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[U-Boot] [v4 16/29] arm: socfpga: add reset manager defines for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.

[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h |  103 ++
 1 files changed, 103 insertions(+), 0 deletions(-)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h 
b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 000..7619ca2
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET  2
+#define SCUPER_RESET   3
+
+/* PER0MODRST */
+#define EMAC0_RESET32
+#define EMAC1_RESET33
+#define EMAC2_RESET34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET39
+#define EMAC0_OCP_RESET40
+#define EMAC1_OCP_RESET41
+#define EMAC2_OCP_RESET42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET47
+#define DMA_RESET  48
+#define SPIM0_RESET49
+#define SPIM1_RESET50
+#define SPIS0_RESET51
+#define SPIS1_RESET52
+#define DMA_OCP_RESET  53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET   56
+#define DMAIF1_RESET   57
+#define DMAIF2_RESET   58
+#define DMAIF3_RESET   59
+#define DMAIF4_RESET   60
+#define DMAIF5_RESET   61
+#define DMAIF6_RESET   62
+#define DMAIF7_RESET   63
+
+/* PER1MODRST */
+#define L4WD0_RESET64
+#define L4WD1_RESET65
+#define L4SYSTIMER0_RESET  66
+#define L4SYSTIMER1_RESET  67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET80
+#define UART1_RESET81
+/* 82-87 is reserved */
+#define GPIO0_RESET88
+#define GPIO1_RESET89
+#define GPIO2_RESET90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET   97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET99
+#define F2SSDRAM1_RESET100
+#define F2SSDRAM2_RESET101
+#define DDRSCH_RESET   102
+
+/* SYSMODRST*/
+#define ROM_RESET  128
+#define OCRAM_RESET129
+/* 130 is reserved */
+#define FPGAMGR_RESET  131
+#define S2F_RESET  132
+#define SYSDBG_RESET   133
+#define OCRAM_OCP_RESET134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET   160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET  163
+#define TIMESTAMPCOLD_RESET164
+#define TAPCOLD_RESET  165
+#define HMCCOLD_RESET  166
+#define IOMGRCOLD_RESET167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET192
+
+/* DBGMODRST */
+#define DBG_RESET  224
+#endif
-- 
1.7.7.4

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[U-Boot] [v4 14/29] arm: socfpga: arria10: remove board_init and s_init

[Chee Tien Fong]

From: Tien Fong Chee 

These functions are already in arch/arm/mach-socfpga/board.c

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 board/altera/arria10-socdk/socfpga.c |   17 -
 1 files changed, 0 insertions(+), 17 deletions(-)

diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
index abedc22..8516633 100644
--- a/board/altera/arria10-socdk/socfpga.c
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -5,20 +5,3 @@
  */
 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void)
-{
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-   /* Address of boot parameters for ATAG (if ATAG is used) */
-   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-   return 0;
-}
-- 
1.7.7.4

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[U-Boot] [v4 12/29] arm: socfpga: arria10: don't build GEN5 sdram for arria10

[Chee Tien Fong]

From: Tien Fong Chee 

The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/Kconfig  |2 ++
 drivers/ddr/Kconfig  |1 +
 drivers/ddr/altera/Kconfig   |6 ++
 include/configs/socfpga_common.h |5 -
 4 files changed, 9 insertions(+), 5 deletions(-)
 create mode 100644 drivers/ddr/Kconfig
 create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 0e5d97d..3e6bbac 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/ddr/fsl/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 000..b764add
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 000..9554da7
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,6 @@
+config ALTERA_SDRAM
+   bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
+   default y if TARGET_SOCFPGA_GEN5
+   help
+ This is for building the SDRAM controller for the Arria5/Cyclone5
+ devices.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 31f1338..bbbde1e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -77,11 +77,6 @@
 #define CONFIG_SYS_PL310_BASE  SOCFPGA_MPUL2_ADDRESS
 
 /*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
  * EPCS/EPCQx1 Serial Flash Controller
  */
 #ifdef CONFIG_ALTERA_SPI
-- 
1.7.7.4

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[U-Boot] [v4 15/29] arm: socfpga: combine clrbits/setbits into a single clrsetbits

[Chee Tien Fong]

From: Tien Fong Chee 

There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/misc.c |9 +++--
 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 2645129..c97caea 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
return;
}
 
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
/* configure to PHY interface select choosed */
-   setbits_le32(_regs->emacgrp_ctrl,
-phymode << physhift);
+   clrsetbits_le32(_regs->emacgrp_ctrl,
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
+   phymode << physhift);
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
1.7.7.4

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[U-Boot] [v4 10/29] arm: socfpga: arria10: add reset manager for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   65 
 arch/arm/mach-socfpga/reset_manager.c  |   24 +++-
 2 files changed, 88 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..6225118 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
+#else
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
+   u32 brg_mod_reset;
+   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -75,6 +113,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c 
b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..d0ff6c4 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base 
=
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
 void socfpga_per_reset(u32 reset, int set)
 {
const void *reg;
@@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
  */
 void 

[U-Boot] [v4 11/29] arm: socfpga: wrap system manager functions for A5/C5 devices

[Chee Tien Fong]

From: Tien Fong Chee 

The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/system_manager.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 75a65f3..9e1c3fd 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs =
  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void populate_sysmgr_fpgaintf_module(void)
 {
uint32_t handoff_val = 0;
@@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable)
clrbits_le32(_regs->romcodegrp_ctrl,
 SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
1.7.7.4

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[U-Boot] [v4 08/29] arm: socfpga: arria10: add config option build for arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/Kconfig  |4 ++--
 arch/arm/mach-socfpga/Kconfig |   10 ++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0ed36cd..80c5992 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL
+   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
-   select SPL_OF_CONTROL
+   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
select DM
select DM_SPI_FLASH
select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6991af8..d9a5178 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+   bool
+
 config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_DENX_MCVEVK
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -86,6 +93,7 @@ endchoice
 
 config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -98,6 +106,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -111,6 +120,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
-- 
1.7.7.4

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[U-Boot] [v4 09/29] arm: socfpga: add define for bootinfo bsel bit shift

[Chee Tien Fong]

From: Tien Fong Chee 

On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.

Suggested-by: Marek Vasut 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 .../arm/mach-socfpga/include/mach/system_manager.h |2 ++
 arch/arm/mach-socfpga/misc.c   |4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e688c50..9ca889a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -203,8 +203,10 @@ struct socfpga_system_manager {
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
 #else
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
 #endif
 
 #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c1e5969..2645129 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+   const u32 bsel = (readl(_regs->bootinfo) >>
+ SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-   const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
 #else
-   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
puts("CPU:   Altera SoCFPGA Arria 10\n");
 #endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
-- 
1.7.7.4

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[U-Boot] [v4 07/29] arm: socfpga: arria10: add socfpga_arria10_defconfig

[Chee Tien Fong]

From: Tien Fong Chee 

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Acked-by: Marek Vasut 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 configs/socfpga_arria10_defconfig |   24 
 1 files changed, 24 insertions(+), 0 deletions(-)
 create mode 100644 configs/socfpga_arria10_defconfig

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
new file mode 100644
index 000..755bb66
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
1.7.7.4

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[U-Boot] [v4 06/29] arm: socfpga: arria10: add socfpga_arria10_socdk config

[Chee Tien Fong]

From: Tien Fong Chee 

Add config for the Arria10 SoC Development Kit.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Acked-by: Marek Vasut 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/configs/socfpga_arria10_socdk.h |   94 +++
 1 files changed, 94 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 000..577f60f
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include 
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1_SIZE  0x200
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY   3
+#define CONFIG_BOOTFILE"zImage"
+#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR0x0100
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
+#define CONFIG_ENV_OFFSET  512/* just after the MBR */
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "verify=n\0" \
+   "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "bootimage=zImage\0" \
+   "fdt_addr=100\0" \
+   "fdtimage=socfpga.dtb\0" \
+   "fsloadcmd=ext2load\0" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "mmcroot=/dev/mmcblk0p2\0" \
+   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${mmcroot} rw rootwait;" \
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "mmcload=mmc rescan;" \
+   "load mmc 0:1 ${loadaddr} ${bootimage};" \
+   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+   "qspiroot=/dev/mtdblock0\0" \
+   "qspirootfstype=jffs2\0" \
+   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+   "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include 
+#endif /* __CONFIG_H */
-- 
1.7.7.4

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[U-Boot] [v4 05/29] arm: socfpga: arria10: add misc functions for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/misc.c |   51 ++
 1 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..c1e5969 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#else
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
@@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
+#else
+   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
+   puts("CPU:   Altera SoCFPGA Arria 10\n");
+#endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
return 0;
 }
@@ -338,6 +351,7 @@ int arch_cpu_init(void)
return 0;
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
@@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 
return 0;
 }
+#else
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+   /* Put OCRAM in non-secure */
+   writel(0x003f, _fw_ocram_base->region0);
+   writel(0x1, _fw_ocram_base->enable);
+
+   /* Put DDR in non-secure */
+   writel(0x, _fw_ddr_l3_base->hpsregion0addr);
+   writel(0x1, _fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+   initialize_security_policies();
+
+   /* Configure the L2 controller to make SDRAM start at 0 */
+   writel(0x1, >pl310_addr_filter_start);
+
+   /* assert reset to all except L4WD0 and L4TIMER0 */
+   socfpga_per_reset_all();
+
+   /* configuring the clock based on handoff */
+   /* TODO: Add call to cm_basic_init() */
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
+   return 0;
+}
+#endif
 
 U_BOOT_CMD(
bridge, 2, 1, do_bridge,
-- 
1.7.7.4

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[U-Boot] [v4 03/29] arm: socfpga: arria10: add board files for the Arria10 SoCDK

[Chee Tien Fong]

From: Tien Fong Chee 

Add minimal support for the Arria10 SoCDK.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 board/altera/arria10-socdk/Kconfig   |   18 ++
 board/altera/arria10-socdk/Makefile  |7 +++
 board/altera/arria10-socdk/socfpga.c |   24 
 3 files changed, 49 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig 
b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+   default "armv7"
+
+config SYS_BOARD
+   default "socfpga_arria10"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile 
b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000..abedc22
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+   /* Address of boot parameters for ATAG (if ATAG is used) */
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+   return 0;
+}
-- 
1.7.7.4

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[U-Boot] [v4 04/29] arm: socfpga: arria10: add system manager defines

[Chee Tien Fong]

From: Tien Fong Chee 

Add system manager defines for Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 .../arm/mach-socfpga/include/mach/system_manager.h |  122 
 1 files changed, 122 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..e688c50 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable);
 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_system_manager {
/* System Manager Module */
u32 siliconid1; /* 0x00 */
@@ -115,6 +116,77 @@ struct socfpga_system_manager {
u32 _pad_0x734;
u32 spim0usefpga;   /* 0x738 */
 };
+#else /* Arria10 System Manager */
+struct socfpga_system_manager {
+   u32  siliconid1;
+   u32  siliconid2;
+   u32  wddbg;
+   u32  bootinfo;
+   u32  mpu_ctrl_l2_ecc;
+   u32  _pad_0x14_0x1f[3];
+   u32  dma;
+   u32  dma_periph;
+   u32  sdmmcgrp_ctrl;
+   u32  sdmmc_l3master;
+   u32  nand_bootstrap;
+   u32  nand_l3master;
+   u32  usb0_l3master;
+   u32  usb1_l3master;
+   u32  emac_global;
+   u32  emac0;
+   u32  emac1;
+   u32  emac2;
+   u32  _pad_0x50_0x5f[4];
+   u32  fpgaintf_en_global;
+   u32  fpgaintf_en_0;
+   u32  fpgaintf_en_1;
+   u32  fpgaintf_en_2;
+   u32  fpgaintf_en_3;
+   u32  _pad_0x74_0x7f[3];
+   u32  noc_addr_remap_value;
+   u32  noc_addr_remap_set;
+   u32  noc_addr_remap_clear;
+   u32  _pad_0x8c_0x8f;
+   u32  ecc_intmask_value;
+   u32  ecc_intmask_set;
+   u32  ecc_intmask_clr;
+   u32  ecc_intstatus_serr;
+   u32  ecc_intstatus_derr;
+   u32  mpu_status_l2_ecc;
+   u32  mpu_clear_l2_ecc;
+   u32  mpu_status_l1_parity;
+   u32  mpu_clear_l1_parity;
+   u32  mpu_set_l1_parity;
+   u32  _pad_0xb8_0xbf[2];
+   u32  noc_timeout;
+   u32  noc_idlereq_set;
+   u32  noc_idlereq_clr;
+   u32  noc_idlereq_value;
+   u32  noc_idleack;
+   u32  noc_idlestatus;
+   u32  fpga2soc_ctrl;
+   u32  _pad_0xdc_0xff[9];
+   u32  tsmc_tsel_0;
+   u32  tsmc_tsel_1;
+   u32  tsmc_tsel_2;
+   u32  tsmc_tsel_3;
+   u32  _pad_0x110_0x200[60];
+   u32  romhw_ctrl;
+   u32  romcode_ctrl;
+   u32  romcode_cpu1startaddr;
+   u32  romcode_initswstate;
+   u32  romcode_initswlastld;
+   u32  _pad_0x214_0x217;
+   u32  warmram_enable;
+   u32  warmram_datastart;
+   u32  warmram_length;
+   u32  warmram_execution;
+   u32  warmram_crc;
+   u32  _pad_0x22c_0x22f;
+   u32  isw_handoff[8];
+   u32  romcode_bootromswstate[8];
+};
+#endif
 
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1)
@@ -146,4 +218,54 @@ struct socfpga_system_manager {
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V   0x1
+#define VOLTAGE_SEL_2P5V   0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE  0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V   2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE  0
+#define WK_PU_ENABLE   1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT  PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT  PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT0x10
+#define PD_DRV_STRG_DEFAULT0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB0
+#define PD_SLW_RT_LSB  5
+#define PU_DRV_STRG_LSB8
+#define PU_SLW_RT_LSB  13
+#define WK_PU_LSB  16
+#define INPUT_BUF_LSB  17
+#define BIAS_TRIM_LSB  19
+#define VOLTAGE_SEL_LSB0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK   0x0010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK  0x0001
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK  0x0010
+#define 

[U-Boot] [v4 02/29] arm: socfpga: arria10: add sdram defines for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the structures for the SDRAM controller on Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/sdram_a10.h |  380 
 1 files changed, 380 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
new file mode 100644
index 000..0403531
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SOCFPGA_SDRAM_A10_H_
+#define_SOCFPGA_SDRAM_A10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 

[U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add remaining 3 I2C base addresses for the Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Reviewed-by: Stefan Roese 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..902c321 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -29,6 +29,9 @@
 #define SOCFPGA_MPUL2_ADDRESS  0xf000
 #define SOCFPGA_I2C0_ADDRESS   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
-- 
1.7.7.4

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Re: [U-Boot] [v3 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee, Tien Fong]

On Jum, 2017-01-06 at 17:03 -0600, Dinh Nguyen wrote:
> 
> On 01/06/2017 05:19 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> > 
> > Drivers for reset manager is restructured such that common
> > functions,
> > gen5 drivers and Arria10 drivers are moved to reset_manager.c,
> > reset_manager_gen5.c and reset_manager_arria10.c respectively.
> > 
> In Linux, I was able to use the same reset manager driver to support 
> both gen5 and Arria10 devices, are you sure you can't do the same
> here?
> 
> Take a look at this commit:
> 
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commi
> /drivers/rese/resetsocfpga.c?id=27e44646dc0083c931b71bbb8e179aeb38010
> d31
> 
> My guess is that you can probably use the same driver but with
> different 
> macro defines.
> 
We have some prepocessing required before triggering the simple reset
assert/deassert on the right peripheral. Some new functions are created
for specific group reset purpose like all bridges reset based on
handoff. As per agreement between marek and CL, those functions merging
which require #ifdef arria10/gen5, then for the sake of clean code, it
is better putting them in different files based on device type.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@kernel.org>
> > Cc: Chin Liang See <chin.liang@intel.com>
> > Cc: Tien Fong <skywind...@gmail.com>
> > ---
> > Changes for V3
> > - no changes
> > Changes for V2
> > - Reverted license changes, removing extern and volatile
> > declaration
> > ---
> >  arch/arm/mach-socfpga/Makefile |   16 +-
> >  arch/arm/mach-socfpga/include/mach/reset_manager.h |  155 ++--
> >  arch/arm/mach-socfpga/reset_manager.c  |  112 +--
> >  arch/arm/mach-socfpga/reset_manager_arria10.c  |  407
> > 
> >  .../{reset_manager.c => reset_manager_gen5.c}  |   94 ++---
> >  5 files changed, 570 insertions(+), 214 deletions(-)
> >  create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
> >  copy arch/arm/mach-socfpga/{reset_manager.c =>
> > reset_manager_gen5.c} (58%)
> > 
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index 809cd47..b8fcf6e 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -2,21 +2,27 @@
> >  # (C) Copyright 2000-2003
> >  # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
> >  #
> > -# Copyright (C) 2012 Altera Corporation 
> > +# Copyright (C) 2012-2016 Altera Corporation 
> >  #
> >  # SPDX-License-Identifier: GPL-2.0+
> >  #
> > 
> >  obj-y  += misc.o timer.o reset_manager.o system_manager.o
> > clock_manager.o \
> >        fpga_manager.o board.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o
> > wrap_pll_config.o \
> > +   reset_manager_gen5.o
> > 
> > -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > +ifdef CONFIG_SPL_BUILD
> > +obj-y += spl.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o
> > wrap_iocsr_config.o \
> > +   wrap_pinmux_config.o
> > wrap_sdram_config.o
> > +endif
> > 
> > +ifdef CONFIG_TARGET_SOCFPGA_GEN5
> >  # QTS-generated config file wrappers
> > -obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o
> > wrap_pll_config.o
> > -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o
> > wrap_pinmux_config.o\
> > -      wrap_sdram_config.o
> >  CFLAGS_wrap_iocsr_config.o +=
> > -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_pinmux_config.o+=
> > -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_sdram_config.o +=
> > -I$(srctree)/board/$(BOARDDIR)
> > +endif
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > index 6225118..13f9731 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > @@ -1,5 +1,5 @@
> >  /*
> > - *  Copyright (C) 2012 Altera Corporation 
> > + *  Copyright (C) 2012-2016 Altera Corporation 
> >   *
> >   * SPDX-License-Identifier:GPL-2.0+
> &g

Re: [U-Boot] [v3 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Chee, Tien Fong]

On Jum, 2017-01-06 at 12:12 -0600, Dinh Nguyen wrote:
> 
> On 01/06/2017 05:19 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> > 
> > Enhanced defconfig file for Arria10 to enable SPL build and
> > supporting
> > device tree build for SDMMC.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@kernel.org>
> > Cc: Chin Liang See <chin.liang@intel.com>
> > Cc: Tien Fong <skywind...@gmail.com>
> > ---
> > Changes for V3
> > - no changes
> > Changes for V2
> > - Removed boot header info setup since it already fixed in mainline
> > ---
> You can probably just roll this patch together with the previous
> patch 
> for socfpga_arria10_defconfig "[v3 07/30] arm: socfpga: arria10: add
> socfpga_arria10_defconfig"
> 
> Dinh

Okay, noted.
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[U-Boot] [v3 30/30] arm: socfpga: arria10: Enable fpga driver build for SPL.

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- resolved build error of undefined some functions in fpga driver for SPL
  build
---
 drivers/Makefile |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa14..c15796b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)PINCTRL)+= pinctrl/
 obj-$(CONFIG_$(SPL_)RAM)   += ram/
 
 ifdef CONFIG_SPL_BUILD
-
+obj-$(CONFIG_FPGA) += fpga/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-- 
1.7.7.4

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[U-Boot] [v3 27/30] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Reverted license changes, removing extern and volatile declaration.
---
 arch/arm/mach-socfpga/clock_manager.c  |  752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  |  954 
 .../{clock_manager.c => clock_manager_gen5.c}  |  240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * 

[U-Boot] [v3 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

[Chee Tien Fong]

From: Tien Fong Chee 

This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- Created common spl_boot_device() for both gen5 and Arria10.
Changes for V2
- Release UART from reset before enalbing console, and reverting license
  changes.
---
 arch/arm/mach-socfpga/spl.c |   79 +--
 1 files changed, 76 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..d381904 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -19,37 +19,58 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define BOOTINFO_BSEL_SHIFT0
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define BOOTINFO_BSEL_SHIFT12
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(_regs->bootinfo);
 
-   switch (bsel & 0x7) {
+   switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
case 0x2:   /* NAND Flash (1.8V) */
case 0x3:   /* NAND Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
return BOOT_DEVICE_NAND;
case 0x4:   /* SD/MMC External Transceiver (1.8V) */
case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+#endif
return BOOT_DEVICE_MMC1;
case 0x6:   /* QSPI Flash (1.8V) */
case 0x7:   /* QSPI Flash (3.0V) */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+#endif
return BOOT_DEVICE_SPI;
default:
printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -68,6 +89,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, _regs->lwhps2fpgaregs);
@@ -182,3 +204,54 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+   memset(__bss_start, 0, __bss_end - __bss_start);
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+   /* We need to access to FDT as this stage */
+   /* FDT is at end of image */
+   gd->fdt_blob = (void *)(__bss_end);
+   /* Check whether we have a valid FDT or not. */
+   if (fdtdec_prepare_fdt()) {
+   panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+   "doc/README.fdt-control");
+   }
+#endif /* CONFIG_OF_CONTROL */
+
+   /* Initialize the timer */
+   timer_init();
+
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   reset_deassert_uart();
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+#endif
-- 
1.7.7.4

___

[U-Boot] [v3 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Removed extern declaration.
---
 arch/arm/mach-socfpga/include/mach/pinmux.h |   17 +
 arch/arm/mach-socfpga/pinmux.c  |  104 +++
 2 files changed, 121 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux.c

diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..ff54caa
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_PINMUX_H_
+#define_PINMUX_H_
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c
new file mode 100644
index 000..d45722f
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux.c
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+static int __do_pinctr_pins(const void *blob, int child, const char 
*node_name);
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name);
+
+static int __do_pinctr_pins(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", );
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins",
+   );
+   if (cell != NULL) {
+   debug("%p %d\n", cell, len);
+   for (;len > 0; len -= (2*sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   }
+   return 1;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return 2;
+
+   node_name = fdt_get_name(blob, child, );
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name)) {
+   __do_pinctr_pins(blob, child, node_name);
+   return(0);
+   }
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, );
+   }
+
+   return 1;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return 2;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return 3;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return 2;
+
+   return 0;
+}
-- 
1.7.7.4

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[U-Boot] [v3 24/30] arm: socfpga: arria10: Added support for Arria 10 socdk

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Separate patch, reuse socfpga_common.h
---
 arch/arm/mach-socfpga/system_manager.c  |4 ++-
 drivers/fpga/socfpga.c  |7 +++-
 include/configs/socfpga_arria10_socdk.h |   56 +++
 include/configs/socfpga_common.h|   33 --
 4 files changed, 71 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 9e1c3fd..e1f0082 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -11,8 +11,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index bfefafd..7fd922e 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
}
 
/* Prior programming the FPGA, all bridges need to be shut off */
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Disable all signals from hps peripheral controller to fpga */
writel(0, _regs->fpgaintfgrp_module);
+#endif
 
/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
index 577f60f..105c4c0 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2015 Altera Corporation 
+ *  Copyright (C) 2015-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0
  */
@@ -8,31 +8,20 @@
 #define __CONFIG_SOCFGPA_ARRIA10_H__
 
 #include 
+
 /* U-Boot Commands */
-#define CONFIG_SYS_NO_FLASH
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
 
-/*
- * Memory configurations
- */
-#define PHYS_SDRAM_1_SIZE  0x200
-
 /* Booting Linux */
-#define CONFIG_BOOTDELAY   3
 #define CONFIG_BOOTFILE"zImage"
 #define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
@@ -40,24 +29,30 @@
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /*
- * Display CPU and Board Info
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
+/*
+ * U-Boot console configurations
  */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DOS_PARTITION
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x8000
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9031
-
 #endif
 
+/*
+ * U-Boot environment configurations
+ */
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
-#define CONFIG_ENV_OFFSET  512/* just after the MBR */
 
 /*
  * arguments passed to the bootz command. The value of
@@ -89,6 +84,23 @@
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
"bootm ${loadaddr} - ${fdt_addr}\0"
 
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload 

[U-Boot] [v3 26/30] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Populating base address of UART based on handoff setting.
---
 arch/arm/mach-socfpga/Makefile|6 +-
 arch/arm/mach-socfpga/include/mach/misc.h |   32 ++
 arch/arm/mach-socfpga/misc.c  |  427 +
 arch/arm/mach-socfpga/misc_arria10.c  |  255 +++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c} |  232 ++
 5 files changed, 337 insertions(+), 615 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (66%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b8fcf6e..1ab68be 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,9 +9,11 @@
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o 
\
+   clock_manager_arria10.o pinmux.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
-   reset_manager_gen5.o
+   reset_manager_gen5.o misc_gen5.o \
+   clock_manager_gen5.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..045268d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define_MISC_H_
+
+extern void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode);
+
+struct bsel{
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+extern void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 510aa1d..7fd5c0e 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,45 +7,33 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#include 
-#else
-#include 
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#else
-static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
-   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
-static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
-   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
-#endif
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bselbsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -84,219 +72,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void 

[U-Boot] [v3 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for v3
- no changes
changes for v2
- Separate patch for adding some HW base address for Arria 10.
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 902c321..2d66580 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -36,10 +36,13 @@
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
-- 
1.7.7.4

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[U-Boot] [v3 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee Tien Fong]

From: Tien Fong Chee 

Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Reverted license changes, removing extern and volatile declaration
---
 arch/arm/mach-socfpga/Makefile |   16 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  155 ++--
 arch/arm/mach-socfpga/reset_manager.c  |  112 +--
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  407 
 .../{reset_manager.c => reset_manager_gen5.c}  |   94 ++---
 5 files changed, 570 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b8fcf6e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,21 +2,27 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2016 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+   reset_manager_gen5.o
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
+   wrap_pinmux_config.o wrap_sdram_config.o
+endif
 
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6225118..13f9731 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,15 +7,27 @@
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_
 
+/* Common function prototypes */
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
 void socfpga_bridges_reset(int enable);
-
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+void reset_deassert_peripherals_handoff(void);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+void reset_assert_uart(void);
+void reset_deassert_uart(void);
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -29,40 +41,40 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
-   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
-   u32 brg_mod_reset;
-   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
-   u32 coldmodrst;
-   u32 nrstmodrst;
-   u32 dbgmodrst;
-   u32 mpuwarmmask;
-   u32 per0warmmask;
-   u32 per1warmmask;
-   u32 brgwarmmask;
-   u32 syswarmmask;
-   u32 nrstwarmmask;
-   u32 l3warmmask;
-   

[U-Boot] [v3 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Chee Tien Fong]

From: Tien Fong Chee 

Enhanced defconfig file for Arria10 to enable SPL build and supporting
device tree build for SDMMC.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Removed boot header info setup since it already fixed in mainline
---
 configs/socfpga_arria10_defconfig |   18 +-
 1 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
index 422261b..755bb66 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
 CONFIG_TARGET_SOCFPGA_ARRIA10=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_DWAPB_GPIO=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
1.7.7.4

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[U-Boot] [v3 20/30] arm: socfpga: arria10: Enable SPL for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

This patch enables SPL build and implementation for Arria 10.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes.
Changes for V2
- Commit messages changed.
---
 arch/arm/Kconfig |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80c5992..0ed36cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+   select SUPPORT_SPL
select OF_CONTROL
-   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+   select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
-- 
1.7.7.4

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[U-Boot] [v3 19/30] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

[Chee Tien Fong]

From: Tien Fong Chee 

This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- modified the handoff.dtsi to board specific, and moving some chosen
  config to handoff.dtsi because these config would be generated by tool
---
 arch/arm/dts/Makefile  |3 +-
 arch/arm/dts/socfpga_arria10.dtsi  |  859 
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |   30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   |  479 +++
 4 files changed, 1370 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3ee608b..024aa5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -137,7 +137,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_arria10_socdk_sdmmc.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
new file mode 100644
index 000..f63c4b4
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -0,0 +1,859 @@
+/*
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   ethernet2 = 
+   serial0 = 
+   serial1 = 
+   timer0 = 
+   timer1 = 
+   timer2 = 
+   timer3 = 
+   spi0 = 
+   spi1 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: intc@d000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <>;
+   ranges;
+
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   pdma: pdma@ffda1000 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda1000 0x1000>;
+   interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+<0 84 IRQ_TYPE_LEVEL_HIGH>,
+<0 85 IRQ_TYPE_LEVEL_HIGH>,
+<0 86 IRQ_TYPE_LEVEL_HIGH>,
+<0 87 IRQ_TYPE_LEVEL_HIGH>,
+<0 88 IRQ_TYPE_LEVEL_HIGH>,
+<0 89 IRQ_TYPE_LEVEL_HIGH>,
+<0 90 IRQ_TYPE_LEVEL_HIGH>,
+<0 91 IRQ_TYPE_LEVEL_HIGH>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clocks = <_main_clk>;
+   clock-names = "apb_pclk";
+   };
+   };
+

[U-Boot] [v3 22/30] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee Tien Fong]

From: Tien Fong Chee 

These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V3
- no changes
Changes for V2
- Added only compat strings with matching drivers in this series patches
---
 include/fdtdec.h |8 
 lib/fdtdec.c |8 
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..73e3a46 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,14 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_SUNXI_NAND,  /* SUNXI NAND controller */
+   COMPAT_ALTERA_SOCFPGA_CLK,  /* SoCFPGA Clock initialization */
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,   /* pinctrl-single */
+   COMPAT_ALTERA_SOCFPGA_H2F_BRG,  /* Arria10 hps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 lwhps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_F2H_BRG,  /* Arria10 fpga2hps bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR0,   /* Arria10 fpga2SDRAM0 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR1,   /* Arria10 fpga2SDRAM1 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR2,   /* Arria10 fpga2SDRAM2 bridge */
 
COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 81f47ef..ebe4a9a 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+   COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+   COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+   COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
1.7.7.4

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[U-Boot] [v3 18/30] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

[Chee Tien Fong]

From: Tien Fong Chee 

Add base address header file for Stratix10 SoC

Signed-off-by: Chin Liang See 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   48 
 1 files changed, 48 insertions(+), 0 deletions(-)
 create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100755
index 000..411518d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS   0xfa00
+#define SOCFPGA_EMAC0_ADDRESS  0xff80
+#define SOCFPGA_EMAC1_ADDRESS  0xff802000
+#define SOCFPGA_EMAC2_ADDRESS  0xff804000
+#define SOCFPGA_SDMMC_ADDRESS  0xff808000
+#define SOCFPGA_USB0_ADDRESS   0xffb0
+#define SOCFPGA_USB1_ADDRESS   0xffb4
+#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
+#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
+#define SOCFPGA_UART0_ADDRESS  0xffc02000
+#define SOCFPGA_UART1_ADDRESS  0xffc02100
+#define SOCFPGA_I2C0_ADDRESS   0xffc02800
+#define SOCFPGA_I2C1_ADDRESS   0xffc02900
+#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00300
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00400
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
+#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS  0xffe0
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
1.7.7.4

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[U-Boot] [v3 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.

Update the dwmac_deassert_reset function to support both GEN5 and Arria10
devices.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 .../arm/mach-socfpga/include/mach/system_manager.h |4 +---
 arch/arm/mach-socfpga/misc.c   |   14 ++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 9ca889a..831ba4a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -133,9 +133,7 @@ struct socfpga_system_manager {
u32  usb0_l3master;
u32  usb1_l3master;
u32  emac_global;
-   u32  emac0;
-   u32  emac1;
-   u32  emac2;
+   u32  emac[3];
u32  _pad_0x50_0x5f[4];
u32  fpgaintf_en_global;
u32  fpgaintf_en_0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c97caea..510aa1d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -21,7 +21,11 @@
 #include 
 #include 
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#else
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
} else if (of_reset_id == EMAC1_RESET) {
physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
reset = SOCFPGA_RESET(EMAC1);
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+#endif
} else {
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
return;
}
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* configure to PHY interface select choosed */
clrsetbits_le32(_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
phymode << physhift);
+#else
+   clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+#endif
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
1.7.7.4

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[U-Boot] [v3 16/30] arm: socfpga: add reset manager defines for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.

[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h |  103 ++
 1 files changed, 103 insertions(+), 0 deletions(-)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h 
b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 000..7619ca2
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET  2
+#define SCUPER_RESET   3
+
+/* PER0MODRST */
+#define EMAC0_RESET32
+#define EMAC1_RESET33
+#define EMAC2_RESET34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET39
+#define EMAC0_OCP_RESET40
+#define EMAC1_OCP_RESET41
+#define EMAC2_OCP_RESET42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET47
+#define DMA_RESET  48
+#define SPIM0_RESET49
+#define SPIM1_RESET50
+#define SPIS0_RESET51
+#define SPIS1_RESET52
+#define DMA_OCP_RESET  53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET   56
+#define DMAIF1_RESET   57
+#define DMAIF2_RESET   58
+#define DMAIF3_RESET   59
+#define DMAIF4_RESET   60
+#define DMAIF5_RESET   61
+#define DMAIF6_RESET   62
+#define DMAIF7_RESET   63
+
+/* PER1MODRST */
+#define L4WD0_RESET64
+#define L4WD1_RESET65
+#define L4SYSTIMER0_RESET  66
+#define L4SYSTIMER1_RESET  67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET80
+#define UART1_RESET81
+/* 82-87 is reserved */
+#define GPIO0_RESET88
+#define GPIO1_RESET89
+#define GPIO2_RESET90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET   97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET99
+#define F2SSDRAM1_RESET100
+#define F2SSDRAM2_RESET101
+#define DDRSCH_RESET   102
+
+/* SYSMODRST*/
+#define ROM_RESET  128
+#define OCRAM_RESET129
+/* 130 is reserved */
+#define FPGAMGR_RESET  131
+#define S2F_RESET  132
+#define SYSDBG_RESET   133
+#define OCRAM_OCP_RESET134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET   160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET  163
+#define TIMESTAMPCOLD_RESET164
+#define TAPCOLD_RESET  165
+#define HMCCOLD_RESET  166
+#define IOMGRCOLD_RESET167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET192
+
+/* DBGMODRST */
+#define DBG_RESET  224
+#endif
-- 
1.7.7.4

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[U-Boot] [v3 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits

[Chee Tien Fong]

From: Tien Fong Chee 

There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/misc.c |9 +++--
 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 2645129..c97caea 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
return;
}
 
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
/* configure to PHY interface select choosed */
-   setbits_le32(_regs->emacgrp_ctrl,
-phymode << physhift);
+   clrsetbits_le32(_regs->emacgrp_ctrl,
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
+   phymode << physhift);
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
1.7.7.4

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[U-Boot] [v3 14/30] arm: socfpga: arria10: remove board_init and s_init

[Chee Tien Fong]

From: Tien Fong Chee 

These functions are already in arch/arm/mach-socfpga/board.c

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 board/altera/arria10-socdk/socfpga.c |   17 -
 1 files changed, 0 insertions(+), 17 deletions(-)

diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
index abedc22..8516633 100644
--- a/board/altera/arria10-socdk/socfpga.c
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -5,20 +5,3 @@
  */
 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void)
-{
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-   /* Address of boot parameters for ATAG (if ATAG is used) */
-   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-   return 0;
-}
-- 
1.7.7.4

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[U-Boot] [v3 13/30] arm: socfpga: arria10 fpga does not have bridges mapped

[Chee Tien Fong]

From: Tien Fong Chee 

On the Arria10 device, the bridges are not mapped through the interconnect.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/fpga/socfpga.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..bfefafd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset(1);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Unmap the bridges from NIC-301 */
writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
 
/* Initialize the FPGA Manager */
status = fpgamgr_program_init();
-- 
1.7.7.4

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[U-Boot] [v3 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices

[Chee Tien Fong]

From: Tien Fong Chee 

The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/system_manager.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 75a65f3..9e1c3fd 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs =
  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void populate_sysmgr_fpgaintf_module(void)
 {
uint32_t handoff_val = 0;
@@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable)
clrbits_le32(_regs->romcodegrp_ctrl,
 SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
1.7.7.4

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[U-Boot] [v3 10/30] arm: socfpga: arria10: add reset manager for Arria10

[Chee Tien Fong]

From: Tien Fong Chee 

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   65 
 arch/arm/mach-socfpga/reset_manager.c  |   24 +++-
 2 files changed, 88 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..6225118 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
+#else
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
+   u32 brg_mod_reset;
+   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -75,6 +113,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c 
b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..d0ff6c4 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base 
=
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
 void socfpga_per_reset(u32 reset, int set)
 {
const void *reg;
@@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
  */
 void 

[U-Boot] [v3 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10

[Chee Tien Fong]

From: Tien Fong Chee 

The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 drivers/Kconfig  |2 ++
 drivers/ddr/Kconfig  |1 +
 drivers/ddr/altera/Kconfig   |6 ++
 include/configs/socfpga_common.h |5 -
 4 files changed, 9 insertions(+), 5 deletions(-)
 create mode 100644 drivers/ddr/Kconfig
 create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 0e5d97d..3e6bbac 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/ddr/fsl/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 000..b764add
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 000..9554da7
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,6 @@
+config ALTERA_SDRAM
+   bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
+   default y if TARGET_SOCFPGA_GEN5
+   help
+ This is for building the SDRAM controller for the Arria5/Cyclone5
+ devices.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 31f1338..bbbde1e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -77,11 +77,6 @@
 #define CONFIG_SYS_PL310_BASE  SOCFPGA_MPUL2_ADDRESS
 
 /*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
  * EPCS/EPCQx1 Serial Flash Controller
  */
 #ifdef CONFIG_ALTERA_SPI
-- 
1.7.7.4

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