Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
On 10/4/2013 11:32 AM, Jagan Teki wrote: Couldn't find in master, can you provide the link atleast. I am sorry. Got confused with something else You are right. It seems this is not merged yet May be I have to take this and send a pull request. Meanwhile, can you try taking this patch from the mail itself Regards Vipin On Fri, Oct 4, 2013 at 9:40 AM, Vipin Kumarvipin.ku...@st.com wrote: On 10/4/2013 1:22 AM, Jagan Teki wrote: Any update on this. This should already be in u-boot mainline Regards Vipin On Wed, Jun 12, 2013 at 9:25 PM, Armando Visconti armando.visco...@st.com wrote: On 06/12/2013 05:29 PM, Jagan Teki wrote: On Wed, Jun 12, 2013 at 8:49 PM, Armando Visconti armando.visco...@st.com wrote: But if you prefer to be on safer side I think we need to re-do some checks on a spare 1340 board... OK, maybe it is better to re-check again. I need to find some time and a spare board... I'll let you know, Arm Do we have an config file available in master, i need to build at-least. Mmmh... currently in mainline there is only spear3xx config file, but there is no PL022 support there. In fact, to compile locally here I had to change it in this way, even if they cannot be used for testing (only compiling): diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h index 3cd56dc..03a046e 100644 --- a/include/configs/spear3xx_evb.h +++ b/include/configs/spear3xx_evb.h @@ -54,6 +54,11 @@ /* Ethernet driver configuration */ #define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_PL022_SPI1 +#define CONFIG_SYS_SPI_BASE 0xE010 +#define CONFIG_SYS_SPI_CLK 8300 +#define CONFIG_CMD_SPI 1 + #if defined(CONFIG_SPEAR310) #define CONFIG_MACB #define CONFIG_MACB0_PHY 0x01 I know that Vipin was going to add support of spear1340 in mainline. His patches are currently already submitted and partially acked but I'm not sure what is the status now... Vipin, can you update us? Rgds, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
On 10/4/2013 1:22 AM, Jagan Teki wrote: Any update on this. This should already be in u-boot mainline Regards Vipin On Wed, Jun 12, 2013 at 9:25 PM, Armando Visconti armando.visco...@st.com wrote: On 06/12/2013 05:29 PM, Jagan Teki wrote: On Wed, Jun 12, 2013 at 8:49 PM, Armando Visconti armando.visco...@st.com wrote: But if you prefer to be on safer side I think we need to re-do some checks on a spare 1340 board... OK, maybe it is better to re-check again. I need to find some time and a spare board... I'll let you know, Arm Do we have an config file available in master, i need to build at-least. Mmmh... currently in mainline there is only spear3xx config file, but there is no PL022 support there. In fact, to compile locally here I had to change it in this way, even if they cannot be used for testing (only compiling): diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h index 3cd56dc..03a046e 100644 --- a/include/configs/spear3xx_evb.h +++ b/include/configs/spear3xx_evb.h @@ -54,6 +54,11 @@ /* Ethernet driver configuration */ #define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_PL022_SPI1 +#define CONFIG_SYS_SPI_BASE 0xE010 +#define CONFIG_SYS_SPI_CLK 8300 +#define CONFIG_CMD_SPI 1 + #if defined(CONFIG_SPEAR310) #define CONFIG_MACB #define CONFIG_MACB0_PHY 0x01 I know that Vipin was going to add support of spear1340 in mainline. His patches are currently already submitted and partially acked but I'm not sure what is the status now... Vipin, can you update us? Rgds, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] drivers/net/designware - fix alignment of buffer descriptors
On 9/25/2013 8:57 PM, Alexey Brodkin wrote: It's important that buffer descriptors are aligned in accordance to GMAC data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes) for every bus width type. If buffer descriptor is improperly aligned GMAC discards lower bits of provided address and as a result reads from improper location that doesn't match expected fields. Commit ef76025a99247cdb8f927a2c9f15400678dfb599 net: Multiple updates/enhancements to designware.c introduced another structure member link_printed right before buffer descriptors while padding member was left untouched. This together with alignment of structure itself to 16-byte boundary forces buffer descriptoprs always to be 4-byte aligned that causes driver complete disfunction if GMAC bus width is 64 or 128-bit. I have also faced this problem before. May be a better solution is to place all the struct and buffer declarations at the very start of dw_eth_dev structure (off-course with a comment that these should not be moved). It may avoid the problem in later modifications Regards Vipin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers/net/designware - respect bus mode register contents on SW reset
On 9/25/2013 7:03 PM, Alexey Brodkin wrote: bus mode register contains lots of fields and some of them don't expect to be written with 0 (zero). So since we're only interested in resetting MAC (which is done with setting the least significant bit of this register with 0) I believe it's better to modify only 1 bit of the register. Signed-off-by: Alexey Brodkinabrod...@synopsys.com --- drivers/net/designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 46f6601..f11cb0b 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -112,7 +112,7 @@ static int mac_reset(struct eth_device *dev) ulong start; int timeout = CONFIG_MACRESET_TIMEOUT; - writel(DMAMAC_SRST,dma_p-busmode); + writel(readl(dma_p-busmode) | DMAMAC_SRST,dma_p-busmode); Acked-by: Vipin Kumar vipin.ku...@st.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation
On 7/1/2013 11:02 AM, Axel Lin wrote:
The questions raised here are valid and it forced me to re-read the
datasheet. For your convenience, I must tell you that the device is actually
pl061 from ARM, so the driver can also be named so.
The datasheet is here
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0190b/I1002697.html
Quoting from the datasheet
The GPIODATA register is the data register. In software control mode,
values written in the GPIODATA register are transferred onto the GPOUT pins
if the respective pins have been configured as outputs through the GPIODIR
register.
In order to write to GPIODATA, the corresponding bits in the mask, resulting
from the address bus, PADDR[9:2], must be HIGH. Otherwise the bit values
remain unchanged by the write.
Similarly, the values read from this register are determined for each bit,
by the mask bit derived from the address used to access the data register,
PADDR[9:2]. Bits that are 1 in the address mask cause the corresponding bits
in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective
pins are configured as output, or it returns the value on the corresponding
input GPIN bit when these are configured as inputs. All bits are cleared by
a reset.
After reading all this I am confused about numbering of the gpio's. I think
the numbering should be from 1 to 8 for a device. And this would mean that
we should write to *regs-datareg[1 (gpio - 1)]* instead of the present
code which is _regs-datareg[1 (gpio + 2)]_
Hi Vipin,
Hello Alex,
Thanks for the review and providing the datasheet information.
You mentioned that this is PL061.
So... I just checked the gpio-pl061 driver in linux kernel.
It's writing to _regs-datareg[1 (gpio + 2)]. and seems no bug
report for this.
Yes, I see it now. The difference is that we are using a writel and the
datareg is a u32 array.
And the gpio_get/set implementation in linux kernel has the same behavior as
this patch does:
( below is from linux/drivers/gpio/gpio-pl061.c )
static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
return !!readb(chip-base + (1 (offset + 2)));
}
static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
writeb(!!value offset, chip-base + (1 (offset + 2)));
}
BTW, it would be great if you have the hardware to test.
I am sorry about this. I have now moved to a different group and I have
no access to the hardware
Regards
Vipin
Regards,
Axel
.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation
On 6/30/2013 2:27 PM, Axel Lin wrote:
2013/6/30 Michael Trimarchimich...@amarulasolutions.com:
Hi
Il giorno 30/giu/2013 06:18, Axel Linaxel@ingics.com ha scritto:
2013/6/21 Michael Trimarchimich...@amarulasolutions.com:
On 06/21/2013 06:40 AM, Vipin Kumar wrote:
On 6/20/2013 7:26 PM, Axel Lin wrote:
2013/6/20 Marek Vasutma...@denx.de
Dear Axel Lin,
In current gpio_set_value() implementation, it always sets the gpio
control
bit no matter the value argument is 0 or 1. Thus the GPIOs never set
to
low. This patch fixes this bug.
Signed-off-by: Axel Linaxel@ingics.com
---
drivers/gpio/spear_gpio.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
index d3c728e..8878608 100644
--- a/drivers/gpio/spear_gpio.c
+++ b/drivers/gpio/spear_gpio.c
@@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
{
struct gpio_regs *regs = (struct gpio_regs
*)CONFIG_GPIO_BASE;
- writel(1 gpio,regs-gpiodata[DATA_REG_ADDR(gpio)]);
+ if (value)
+ writel(1
gpio,regs-gpiodata[DATA_REG_ADDR(gpio)]);
+ else
+ writel(0,regs-gpiodata[DATA_REG_ADDR(gpio)]);
How can this possibly work? Writing 0 to the whole bank will unset
all the
GPIOs, no ?
Because each GPIO is controlled by a register.
And only one bit will be set when set gpio to high.
So it's safe to write 0 for clearing the bit.
Note, the gpio_get_value() implementation also assumes there is only
one bit
will be set. ( If this is not true, both gpio_get_value() and
gpio_set_value()
need fix.)
Vipin, can you review this patch and confirm this behavior?
Yes this is right. and the code is fine
The problem is not in set one bit but in reset one bit. Can you check
the else path?
Hi,
I'm not the best person to answer this question because I don't have the
hardware and datasheet.
In the case only one bit is meaningful and the reset bits are 0,
it looks ok for me to write 0 for clearing the bit.
( note, each gpio pin is controlled by different register.)
This patch is acked and reviewed by Stefan Roese and Vipin Kumar.
I'm wondering if this patch is acceptable?
Or maybe a test-by can help to make this patch acceptable?
If each pin is controlled by a different register why you need to 1gpio in
set path?
Because the meaningful bit for different register is different.
And how it works for gpio 33?
SPEAR_GPIO_COUNT is 8, so this driver only allows setting gpio0 ~ gpio7.
Vipin, any chance to double check the datasheet and confirm if this patch is ok?
The questions raised here are valid and it forced me to re-read the
datasheet. For your convenience, I must tell you that the device is
actually pl061 from ARM, so the driver can also be named so.
The datasheet is here
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0190b/I1002697.html
Quoting from the datasheet
The GPIODATA register is the data register. In software control mode,
values written in the GPIODATA register are transferred onto the GPOUT
pins if the respective pins have been configured as outputs through the
GPIODIR register.
In order to write to GPIODATA, the corresponding bits in the mask,
resulting from the address bus, PADDR[9:2], must be HIGH. Otherwise the
bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each
bit, by the mask bit derived from the address used to access the data
register, PADDR[9:2]. Bits that are 1 in the address mask cause the
corresponding bits in GPIODATA to be read, and bits that are 0 in the
address mask cause the corresponding bits in GPIODATA to be read as 0,
regardless of their value.
A read from GPIODATA returns the last bit value written if the
respective pins are configured as output, or it returns the value on the
corresponding input GPIN bit when these are configured as inputs. All
bits are cleared by a reset.
After reading all this I am confused about numbering of the gpio's. I
think the numbering should be from 1 to 8 for a device. And this would
mean that we should write to *regs-datareg[1 (gpio - 1)]* instead
of the present code which is _regs-datareg[1 (gpio + 2)]_
Moreover, One GPIO device can control only 8 pins, so there is no
question of having GPIO33. In an SoC design, GPIO33 may actually map to
GPIO1 of device 4. I hope I am clear on this
Regards
Vipin
Regards,
Axel
.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation
On 6/20/2013 7:26 PM, Axel Lin wrote:
2013/6/20 Marek Vasutma...@denx.de
Dear Axel Lin,
In current gpio_set_value() implementation, it always sets the gpio control
bit no matter the value argument is 0 or 1. Thus the GPIOs never set to
low. This patch fixes this bug.
Signed-off-by: Axel Linaxel@ingics.com
---
drivers/gpio/spear_gpio.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
index d3c728e..8878608 100644
--- a/drivers/gpio/spear_gpio.c
+++ b/drivers/gpio/spear_gpio.c
@@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
{
struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
- writel(1 gpio,regs-gpiodata[DATA_REG_ADDR(gpio)]);
+ if (value)
+ writel(1 gpio,regs-gpiodata[DATA_REG_ADDR(gpio)]);
+ else
+ writel(0,regs-gpiodata[DATA_REG_ADDR(gpio)]);
How can this possibly work? Writing 0 to the whole bank will unset all the
GPIOs, no ?
Because each GPIO is controlled by a register.
And only one bit will be set when set gpio to high.
So it's safe to write 0 for clearing the bit.
Note, the gpio_get_value() implementation also assumes there is only one bit
will be set. ( If this is not true, both gpio_get_value() and gpio_set_value()
need fix.)
Vipin, can you review this patch and confirm this behavior?
Yes this is right. and the code is fine
Regards
Vipin
Thanks,
Axel
.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] gpio: Question about gpio_set_value() implementation in spear_gpio.c
On 6/19/2013 7:14 PM, Axel Lin wrote:
Current code looks strange because no matter the value argument is 0 or 1
it always calls
writel(1 gpio,regs-gpiodata[DATA_REG_ADDR(gpio)]);
And then gpio_get_value() always return 1.
I'm wondering if it needs to be fixed, something like below change:
diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
index d3c728e..8878608 100644
--- a/drivers/gpio/spear_gpio.c
+++ b/drivers/gpio/spear_gpio.c
@@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
{
struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
- writel(1 gpio,regs-gpiodata[DATA_REG_ADDR(gpio)]);
+ if (value)
+ writel(1 gpio,regs-gpiodata[DATA_REG_ADDR(gpio)]);
+ else
+ writel(0,regs-gpiodata[DATA_REG_ADDR(gpio)]);
Yes, this is the right way. It was a blunder. I am wondering no one ever
tried to set a ZERO on any GPIO..
Thanks for pointing out
Regards
Vipin
return 0;
}
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/7] usb: hub: Fix enumration timeout
On 3/27/2013 2:59 PM, Vivek Gautam wrote: Patch b6d7852c increases timeout for enumeration, taking worst case to be 10 sec. get_timer() api returns timestamp in micro-seconds, which is what we are checking in the do-while() loop in usb_hub_configure() (get_timer(start) CONFIG_SYS_HZ * 10). This should give us a required check for 10 seconds, and thereby we don't need to add additional mdelay of 100 microseconds in each cycle. Signed-off-by: Vivek Gautamgautam.vi...@samsung.com CC: Vipin Kumarvipin.ku...@st.com --- common/usb_hub.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/common/usb_hub.c b/common/usb_hub.c index 0677004..d77f98d 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -439,7 +439,6 @@ static int usb_hub_configure(struct usb_device *dev) (portstatus USB_PORT_STAT_CONNECTION)) break; - mdelay(100); } while (get_timer(start) CONFIG_SYS_HZ * 10); if (ret 0) With this change, we are continuously reading the uhb status. Although this is also OK, but I feel 100 ms delay is better Still, there is no harm even if this patch is added. So, Reviewed-by: Vipin Kumar vipin.ku...@st.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
On 3/1/2013 8:38 AM, Bo Shen wrote: Hi All, On 02/28/2013 08:59 PM, Albert ARIBAUD wrote: On Sun, 3 Feb 2013 12:19:26 +0100, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Vipin, On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumarvipin.ku...@st.com wrote: From: Shiraz Hashimshiraz.has...@st.com It is observed on SPEAr320S RMII#1 interface that on transmitting packets the MAC dma hangs randomly and constantly showing busy tx-go state. It comes out if this situation only when Transmission is disabled and enabled again. Since it happens randomly and u-boot doesn't require high performance we disable TE and re-enable it on each transmission. We also change number of transmit descriptor to 1 as we would not require more than it, further it would not alter GMAC notion of transmit descriptor start queue as it always point to same descriptor. Signed-off-by: Shiraz Hashimshiraz.has...@st.com --- drivers/net/macb.c | 38 ++ 1 file changed, 34 insertions(+), 4 deletions(-) Tested on Atmel EK board. It works. Tested-by: Bo Shen voice.s...@atmel.com BTW, would this be implemented as a workaround only for SPEAr320S? Yes, The idea was to implement this only for spear320s After your tested-by, I am thinking may be I can make a separate workaround config which can be enabled by any board using this peripheral. Is that OK? Regards Vipin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
On 2/28/2013 6:29 PM, Albert ARIBAUD wrote:
On Sun, 3 Feb 2013 12:19:26 +0100, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Vipin,
On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumarvipin.ku...@st.com
wrote:
From: Shiraz Hashimshiraz.has...@st.com
It is observed on SPEAr320S RMII#1 interface that on transmitting
packets the MAC dma hangs randomly and constantly showing busy tx-go
state.
It comes out if this situation only when Transmission is disabled and
enabled again.
Since it happens randomly and u-boot doesn't require high performance we
disable TE and re-enable it on each transmission. We also change number
of transmit descriptor to 1 as we would not require more than it, further
it would not alter GMAC notion of transmit descriptor start queue as it
always point to same descriptor.
Signed-off-by: Shiraz Hashimshiraz.has...@st.com
---
drivers/net/macb.c | 38 ++
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index ac25b52..17bad33 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -55,7 +55,7 @@
#define CONFIG_SYS_MACB_RX_BUFFER_SIZE4096
#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE
/ 128)
-#define CONFIG_SYS_MACB_TX_RING_SIZE 16
+#define CONFIG_SYS_MACB_TX_RING_SIZE 1
#define CONFIG_SYS_MACB_TX_TIMEOUT1000
#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 500
@@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void
*packet, int length)
macb-tx_ring[tx_head].ctrl = ctrl;
macb-tx_ring[tx_head].addr = paddr;
barrier();
- macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
+ /*
+* Due to issues on SPEAr320 RMII, disable TE first so that
+* controller can come out if it is hanged during transmission
+*/
+ macb_writel(macb, NCR, macb_readl(macb, NCR) ~MACB_BIT(TE));
+ macb_writel(macb, NCR, macb_readl(macb, NCR) |
+ MACB_BIT(TE) | MACB_BIT(TSTART));
/*
* I guess this is necessary because the networking core may
@@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
}
}
+static void macb_reset_hw(struct macb_device *bp)
+{
+ /* Make sure we have the write buffer for ourselves */
+ barrier();
+ /*
+* Disable RX and TX (XXX: Should we halt the transmission
+* more gracefully?) and we should not close the mdio port
+*/
+ macb_writel(bp, NCR, 0);
+
+ /* Clear the stats registers (XXX: Update stats first?) */
+ macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
+
+ /* keep the mdio port , otherwise other eth will not work */
+ macb_writel(bp, NCR, MACB_BIT(MPE));
+
+ /* Clear all status flags */
+ macb_writel(bp, TSR, ~0UL);
+ macb_writel(bp, RSR, ~0UL);
+
+ /* Disable all interrupts */
+ macb_writel(bp, IDR, ~0UL);
+ macb_readl(bp, ISR);
+}
+
static int macb_init(struct eth_device *netdev, bd_t *bd)
{
struct macb_device *macb = to_macb(netdev);
@@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
tsr = macb_readl(macb, TSR);
} while (tsr MACB_BIT(TGO));
- /* Disable TX and RX, and clear statistics */
- macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
+ macb_reset_hw(macb);
}
static int macb_write_hwaddr(struct eth_device *dev)
This patch did not reappear in later versions of the series, and no
other standalone patch seems to match it. Was it dropped?
Ping?
No, I have been busy with something. I would come back to the u-boot
development soon
Vipin
Amicalement,
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
On 3/1/2013 12:58 PM, Albert ARIBAUD wrote:
Hi Vipin,
On Fri, 1 Mar 2013 09:11:33 +0530, Vipin Kumarvipin.ku...@st.com
wrote:
On 2/28/2013 6:29 PM, Albert ARIBAUD wrote:
On Sun, 3 Feb 2013 12:19:26 +0100, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Vipin,
On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumarvipin.ku...@st.com
wrote:
From: Shiraz Hashimshiraz.has...@st.com
It is observed on SPEAr320S RMII#1 interface that on transmitting
packets the MAC dma hangs randomly and constantly showing busy tx-go
state.
It comes out if this situation only when Transmission is disabled and
enabled again.
Since it happens randomly and u-boot doesn't require high performance we
disable TE and re-enable it on each transmission. We also change number
of transmit descriptor to 1 as we would not require more than it, further
it would not alter GMAC notion of transmit descriptor start queue as it
always point to same descriptor.
Signed-off-by: Shiraz Hashimshiraz.has...@st.com
---
drivers/net/macb.c | 38 ++
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index ac25b52..17bad33 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -55,7 +55,7 @@
#define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE
/ 128)
-#define CONFIG_SYS_MACB_TX_RING_SIZE 16
+#define CONFIG_SYS_MACB_TX_RING_SIZE 1
#define CONFIG_SYS_MACB_TX_TIMEOUT 1000
#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 500
@@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void
*packet, int length)
macb-tx_ring[tx_head].ctrl = ctrl;
macb-tx_ring[tx_head].addr = paddr;
barrier();
- macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
+ /*
+* Due to issues on SPEAr320 RMII, disable TE first so that
+* controller can come out if it is hanged during transmission
+*/
+ macb_writel(macb, NCR, macb_readl(macb, NCR) ~MACB_BIT(TE));
+ macb_writel(macb, NCR, macb_readl(macb, NCR) |
+ MACB_BIT(TE) | MACB_BIT(TSTART));
/*
* I guess this is necessary because the networking core may
@@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
}
}
+static void macb_reset_hw(struct macb_device *bp)
+{
+ /* Make sure we have the write buffer for ourselves */
+ barrier();
+ /*
+* Disable RX and TX (XXX: Should we halt the transmission
+* more gracefully?) and we should not close the mdio port
+*/
+ macb_writel(bp, NCR, 0);
+
+ /* Clear the stats registers (XXX: Update stats first?) */
+ macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
+
+ /* keep the mdio port , otherwise other eth will not work */
+ macb_writel(bp, NCR, MACB_BIT(MPE));
+
+ /* Clear all status flags */
+ macb_writel(bp, TSR, ~0UL);
+ macb_writel(bp, RSR, ~0UL);
+
+ /* Disable all interrupts */
+ macb_writel(bp, IDR, ~0UL);
+ macb_readl(bp, ISR);
+}
+
static int macb_init(struct eth_device *netdev, bd_t *bd)
{
struct macb_device *macb = to_macb(netdev);
@@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
tsr = macb_readl(macb, TSR);
} while (tsr MACB_BIT(TGO));
- /* Disable TX and RX, and clear statistics */
- macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
+ macb_reset_hw(macb);
}
static int macb_write_hwaddr(struct eth_device *dev)
This patch did not reappear in later versions of the series, and no
other standalone patch seems to match it. Was it dropped?
Ping?
No, I have been busy with something. I would come back to the u-boot
development soon
Thanks. Following your discussion with Bo Shen, should I expect a new
version of this patch in the future, or does it stand as it is?
A new version
Vipin
Vipin
Amicalement,
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] imls: Add support to list images in NAND device
On 2/20/2013 6:45 AM, Scott Wood wrote:
On 12/17/2012 02:32:48 AM, Vipin Kumar wrote:
This patch adds support to list images in NAND flash through imls
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
Changes in v4
- Keep stdout dumps in one line
- Continue even after read errors for all the blocks
README | 3 +-
common/cmd_bootm.c | 167
-
2 files changed, 166 insertions(+), 4 deletions(-)
diff --git a/README b/README
index 2077c3b..46fd21d 100644
--- a/README
+++ b/README
@@ -831,7 +831,8 @@ The following options need to be configured:
CONFIG_CMD_I2C * I2C serial bus support
CONFIG_CMD_IDE * IDE harddisk support
CONFIG_CMD_IMIiminfo
- CONFIG_CMD_IMLS List all found images
+ CONFIG_CMD_IMLS List all images found in NOR
flash
+ CONFIG_CMD_IMLS_NAND List all images found in NAND
flash
CONFIG_CMD_IMMAP* IMMR dump support
CONFIG_CMD_IMPORTENV* import an environment
CONFIG_CMD_INI * import data from an ini file
into the env
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index d256ddf..938e500 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -80,9 +80,15 @@ static int image_info(unsigned long addr);
#includeflash.h
#includemtd/cfi_flash.h
extern flash_info_t flash_info[]; /* info for FLASH chips */
+#endif
+
+#if defined(CONFIG_CMD_IMLS) || defined(CONFIG_CMD_IMLS_NAND)
static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[]);
#endif
+#includelinux/err.h
+#includenand.h
+
#ifdef CONFIG_SILENT_CONSOLE
static void fixup_silent_linux(void);
#endif
@@ -1175,7 +1181,7 @@ U_BOOT_CMD(
/* imls - list all images found in flash */
/***/
#if defined(CONFIG_CMD_IMLS)
-static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
+static int do_imls_nor(void)
{
flash_info_t *info;
int i, j;
@@ -1224,6 +1230,161 @@ next_sector:;
}
next_bank:;
}
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_IMLS_NAND)
+static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev,
loff_t off,
+ size_t len)
+{
+ void *imgdata;
+ int ret;
+
+ imgdata = malloc(len);
+ if (!imgdata) {
+ printf(May be a Legacy Image at NAND device %d offset
%08llX:\n,
+ nand_dev, off);
+ printf( Low memory(cannot allocate memory for
image)\n);
+ return -ENOMEM;
+ }
So, it looks like any reasonably-sized kernel image is going to hit
this out-of-memory condition given how unreasonably small U-Boot malloc
heaps generally are.
Yes, that's right. And it is a pity
As a side note, running this showed U-Boot itself as may be a legacy
image... it seems that for some reason all the ppc arches start with
the uImage header, but otherwise aren't valid uImages.
This may be a legacy image print is when we have successfully copied
and validated the 64 byte mkimage header and are not able to allocate
the memory from heap for the image data. What it means is that although
the whole image might be a good Legacy image but we can not guarantee
because we have not yet validated the dcrc.
Thats why this print May be a legacy image
-Vipin
-Scott
.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] armv7/ltimer: Add support for local timer on armv7 cpus
On 2/3/2013 7:28 PM, Albert ARIBAUD wrote:
Hi Vipin,
On Thu, 6 Dec 2012 14:52:55 +0530, Vipin Kumarvipin.ku...@st.com
wrote:
Certain ARMV7 cpus eg. CortexA9 contains a local and a global timer within the
CPU core itself. This patch adds generic support for local timer.
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
arch/arm/cpu/armv7/Makefile | 11 ++-
arch/arm/cpu/armv7/ca9_ltimer.c | 152 ++
arch/arm/include/asm/ca9_ltimer.h | 40 ++
3 files changed, 199 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ca9_ltimer.c
create mode 100644 arch/arm/include/asm/ca9_ltimer.h
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..3ef01f6 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -27,15 +27,18 @@ LIB = $(obj)lib$(CPU).o
START := start.o
-COBJS += cache_v7.o
+COBJS-y+= cache_v7.o
-COBJS += cpu.o
-COBJS += syslib.o
+COBJS-y+= cpu.o
+COBJS-y+= syslib.o
+COBJS-$(CONFIG_ARMV7_CA9LTIMER) += ca9_ltimer.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
-SOBJS += lowlevel_init.o
+SOBJS-y+= lowlevel_init.o
endif
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/arm/cpu/armv7/ca9_ltimer.c b/arch/arm/cpu/armv7/ca9_ltimer.c
new file mode 100644
index 000..cbf1552
--- /dev/null
+++ b/arch/arm/cpu/armv7/ca9_ltimer.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/ca9_ltimer.h
+#includeasm/arch/hardware.h
+
+#define READ_TIMER() readl(ca9_timer_p-count)
+
+static struct ca9_timer_regs *const ca9_timer_p =
+ (struct ca9_timer_regs *)CONFIG_ARMV7_LTIMER_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd-tbl
+#define lastdecgd-lastinc
+#define tickshzgd-timer_rate_hz
+#define ticksper10usec gd-tbu
+
+int timer_init(void)
+{
+ u32 prescaler, timertickshz;
+ /*
+* Genrally, CortexA9 MPUs are operating from 500MHz to 1500MHz which
+* means that CA9 local timer clock would be in the range of 250 MHz to
+* 750MHz.
+* Try to find a prescaler which can perfectly divide the local timer
+* clock. Take prescaler as 200 if nothing is found
+*/
+ for (prescaler = 255; prescaler 1; prescaler--) {
+ if (CONFIG_ARMV7_LTMR_CLK ==
+ (CONFIG_ARMV7_LTMR_CLK / prescaler) * prescaler)
+ break;
+ }
+
+ if (prescaler == 1)
+ prescaler = 200;
+ timertickshz = CONFIG_ARMV7_LTMR_CLK / prescaler;
+ ticksper10usec = timertickshz / (100 * 1000);
+ tickshz = timertickshz / CONFIG_SYS_HZ;
+
+ /* disable timers */
+ writel(((prescaler - 1) 8) | AUTO_RELOAD,ca9_timer_p-control);
+
+ /* load value for free running */
+ writel(FREE_RUNNING,ca9_timer_p-load);
+
+ /* auto reload, start timer */
+ setbits_le32(ca9_timer_p-control, TIMER_ENABLE);
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return (get_timer_masked() / tickshz) - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong tmo;
+ ulong start = get_timer_masked();
+ ulong rndoff;
+
+ rndoff = (usec % 10) ? 1 : 0;
+ tmo = ((usec / 10) + rndoff) * ticksper10usec;
+
+ while ((ulong) (get_timer_masked() - start) tmo);
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER();
+
+ if (now= lastdec) {
+ /* normal mode */
+ timestamp += lastdec - now
Re: [U-Boot] [PATCH 1/2] drivers/net/designware, do an explicit memory access instead of implicit, re-written assignments to use readl() and writel(), all of this as preperation for making the driver
On 1/23/2013 12:25 PM, Albert ARIBAUD wrote: Hi Vipin, My first feeling is that the descriptors are allocated as Normal Cachabale memory and it would not help to access them using readl/writel Should the desciptors be allocated as non-cachable memory. If yes then how to do that in u-boot I suppose the rest of the code would be better reviewed if we know about this Vipin I would say that yes, descriptors are allocated in DRAM, so they are cacheable. And no, we don't need to allocate them non-cacheable, although in this case we need to use cache flush and invalidate calls. I would suggest doing so rather than allocating the descriptors non cacheable, because using non-cacheable memory makes the dependency between the driver and cache codes implicit (and thus more prone to improperly thought out changes in either code) and the memory usage more complex, while explicit cache operations make the relationship explicit. Yes, got it. Thanks Albert Frank, so in that case rather changing the code to use readl/writel, cache flush and invalidate operations need to be performed at appropriate places Regards Vipin One can always not cache descriptors if you one wants to, without this decision breaking driver functionality. Amicalement, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] make u-boot/drivers/net/designware cache supportive
On 1/22/2013 7:40 PM, Frank Dols wrote: Hello Vipin, As discussed, see included the patches to make your u-boot/drivers/net/designware Ethernet device driver cache support aware. You dont need to write u-boot/drivers in the patch subject. It is anyway implicit :) Vipin First patch is about: do an explicit memory access instead of implicit, I re-written assignments to use readl() and writel(). Second patch is about: making the driver able to work in a cached environment (do I$/D$ flush/invalidate where necessary). Frank Dols (2): drivers/net/designware, do an explicit memory access instead of implicit, re-written assignments to use readl() and writel(), all of this as preperation for making the driver able to work in a cached environment (I$D$ support). u-boot/drivers/net/designware with cache support. drivers/net/designware.c | 128 ++ drivers/net/designware.h |4 +- 2 files changed, 86 insertions(+), 46 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] drivers/net/designware, do an explicit memory access instead of implicit, re-written assignments to use readl() and writel(), all of this as preperation for making the driver
Provide a short patch title and a longer description in the patch
itself. that would be much more readable
On 1/22/2013 7:40 PM, Frank Dols wrote:
Signed-off-by: Frank Dolsfrank.d...@synopsys.com
---
drivers/net/designware.c | 108 +++---
drivers/net/designware.h |4 +-
2 files changed, 66 insertions(+), 46 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index bf21a08..2f235d5 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -44,29 +44,36 @@ static void tx_descs_init(struct eth_device *dev)
struct dmamacdescr *desc_p;
u32 idx;
+ txbuffs = (char *) unsigned long) txbuffs) +
+ CONFIG_SYS_CACHELINE_SIZE)
+ (~(CONFIG_SYS_CACHELINE_SIZE - 1)));
+
for (idx = 0; idx CONFIG_TX_DESCR_NUM; idx++) {
desc_p =desc_table_p[idx];
- desc_p-dmamac_addr =txbuffs[idx * CONFIG_ETH_BUFSIZE];
- desc_p-dmamac_next =desc_table_p[idx + 1];
+
+ writel((ulong)txbuffs[(idx * CONFIG_ETH_BUFSIZE)],
+ desc_p-dmamac_addr);
+ writel((ulong)desc_table_p[idx + 1],desc_p-dmamac_next);
My first feeling is that the descriptors are allocated as Normal
Cachabale memory and it would not help to access them using readl/writel
Should the desciptors be allocated as non-cachable memory. If yes then
how to do that in u-boot
I suppose the rest of the code would be better reviewed if we know about
this
Vipin
#if defined(CONFIG_DW_ALTDESCRIPTOR)
- desc_p-txrx_status= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
- DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
- DESC_TXSTS_TXCHECKINSCTRL | \
- DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
-
- desc_p-txrx_status |= DESC_TXSTS_TXCHAIN;
- desc_p-dmamac_cntl = 0;
- desc_p-txrx_status= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
+ writel(readl(desc_p-txrx_status) ~(DESC_TXSTS_TXINT |
+ DESC_TXSTS_TXLAST | DESC_TXSTS_TXFIRST |
+ DESC_TXSTS_TXCRCDIS | DESC_TXSTS_TXCHECKINSCTRL |
+ DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS),
+ desc_p-txrx_status);
+ writel(readl(desc_p-txrx_status) | DESC_TXSTS_TXCHAIN,
+ desc_p-txrx_status);
+ writel(0,desc_p-dmamac_cntl);
+ writel(readl(desc_p-txrx_status) ~(DESC_TXSTS_MSK |
+ DESC_TXSTS_OWNBYDMA),desc_p-txrx_status);
#else
- desc_p-dmamac_cntl = DESC_TXCTRL_TXCHAIN;
- desc_p-txrx_status = 0;
+ writel(DESC_TXCTRL_TXCHAIN,desc_p-dmamac_cntl);
+ writel(0,desc_p-txrx_status);
#endif
}
/* Correcting the last pointer of the chain */
- desc_p-dmamac_next =desc_table_p[0];
-
+ writel((ulong)desc_table_p[0],desc_p-dmamac_next);
writel((ulong)desc_table_p[0],dma_p-txdesclistaddr);
}
@@ -79,21 +86,23 @@ static void rx_descs_init(struct eth_device *dev)
struct dmamacdescr *desc_p;
u32 idx;
+ rxbuffs = (char *) unsigned long) rxbuffs) +
+ CONFIG_SYS_CACHELINE_SIZE)
+ (~(CONFIG_SYS_CACHELINE_SIZE - 1)));
+
for (idx = 0; idx CONFIG_RX_DESCR_NUM; idx++) {
desc_p =desc_table_p[idx];
- desc_p-dmamac_addr =rxbuffs[idx * CONFIG_ETH_BUFSIZE];
- desc_p-dmamac_next =desc_table_p[idx + 1];
- desc_p-dmamac_cntl =
- (MAC_MAX_FRAME_SZ DESC_RXCTRL_SIZE1MASK) | \
- DESC_RXCTRL_RXCHAIN;
-
- desc_p-txrx_status = DESC_RXSTS_OWNBYDMA;
+ writel((ulong)rxbuffs[idx * CONFIG_ETH_BUFSIZE],
+ desc_p-dmamac_addr);
+ writel((ulong)desc_table_p[idx + 1],desc_p-dmamac_next);
+ writel((MAC_MAX_FRAME_SZ DESC_RXCTRL_SIZE1MASK) |
+ DESC_RXCTRL_RXCHAIN,desc_p-dmamac_cntl);
+ writel(DESC_RXSTS_OWNBYDMA,desc_p-txrx_status);
}
/* Correcting the last pointer of the chain */
- desc_p-dmamac_next =desc_table_p[0];
-
+ writel((ulong)desc_table_p[0],desc_p-dmamac_next);
writel((ulong)desc_table_p[0],dma_p-rxdesclistaddr);
}
@@ -134,7 +143,7 @@ static int dw_write_hwaddr(struct eth_device *dev)
u32 macid_lo, macid_hi;
u8 *mac_id =dev-enetaddr[0];
- macid_lo = mac_id[0] + (mac_id[1] 8) + \
+ macid_lo = mac_id[0] + (mac_id[1] 8) +
(mac_id[2] 16) + (mac_id[3] 24);
macid_hi = mac_id[4] + (mac_id[5] 8);
@@ -198,7 +207,6 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
*/
writel(readl(dma_p-opmode) | RXSTART,dma_p-opmode);
Re: [U-Boot] [PATCH resend 2/2] arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P
On 12/7/2012 8:17 PM, Wolfgang Denk wrote: Dear Vipin Kumar, In message50c1b9a6.1020...@st.com you wrote: Can you please suggest what is the best way here. Wolfgang, Albert ? I don't like this patch at all. It introduces yet more architecture specific stuff to lib/board.c, while we actually should be working on coming up with a common version for all architectures. If you want to simplify code, then please not by making it worse in other places. I agree, but this code adds an option to pass boot params pointer to board descriptor. Just two lines above the intended change, there is a mach_type initialization based on the definition of CONFIG_MACH_TYPE. Moreover, the lib/board.c exists in arch/arm as of today which means that it can contain all the stuff common for arm boards If I am right, the patch should also be OK Vipin Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] imls: Add support to list images in NAND device
On 12/15/2012 12:29 AM, Scott Wood wrote:
On 12/14/2012 03:23:26 AM, Vipin Kumar wrote:
On 12/14/2012 3:22 AM, Scott Wood wrote:
On 12/13/2012 12:10:58 AM, Vipin Kumar wrote:
+ imgdata = malloc(read_size);
+ if (!imgdata) {
+ printf(Not able to list all
images \
+ (Low memory)\n);
Don't line-wrap error strings.
80 column ?
Error strings are an exception for the sake of greppability. From
Linux's Documentation/CodingStyle:
Statements longer than 80 columns will be broken into sensible
chunks, unless
exceeding 80 columns significantly increases readability and does
not hide
information. Descendants are always substantially shorter than
the
parent and
are placed substantially to the right. The same applies to
function
headers
with a long argument list. However, never break user-visible
strings
such as
printk messages, because that breaks the ability to grep for
them.
Yes, thanks for reminding. The error strings are more readable
already in v3. Please take a look
No, you're still breaking up strings (and you also have a totally
unnecessary backslash). If it's on one line in the output, it should
be on one line in the source.
Yes, got it. Please check v4. I will send it out soon
-Scott
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4] imls: Add support to list images in NAND device
This patch adds support to list images in NAND flash through imls
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
Changes in v4
- Keep stdout dumps in one line
- Continue even after read errors for all the blocks
README | 3 +-
common/cmd_bootm.c | 167 -
2 files changed, 166 insertions(+), 4 deletions(-)
diff --git a/README b/README
index 2077c3b..46fd21d 100644
--- a/README
+++ b/README
@@ -831,7 +831,8 @@ The following options need to be configured:
CONFIG_CMD_I2C * I2C serial bus support
CONFIG_CMD_IDE * IDE harddisk support
CONFIG_CMD_IMIiminfo
- CONFIG_CMD_IMLS List all found images
+ CONFIG_CMD_IMLS List all images found in NOR flash
+ CONFIG_CMD_IMLS_NAND List all images found in NAND flash
CONFIG_CMD_IMMAP* IMMR dump support
CONFIG_CMD_IMPORTENV* import an environment
CONFIG_CMD_INI * import data from an ini file into the
env
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index d256ddf..938e500 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -80,9 +80,15 @@ static int image_info(unsigned long addr);
#include flash.h
#include mtd/cfi_flash.h
extern flash_info_t flash_info[]; /* info for FLASH chips */
+#endif
+
+#if defined(CONFIG_CMD_IMLS) || defined(CONFIG_CMD_IMLS_NAND)
static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
+#include linux/err.h
+#include nand.h
+
#ifdef CONFIG_SILENT_CONSOLE
static void fixup_silent_linux(void);
#endif
@@ -1175,7 +1181,7 @@ U_BOOT_CMD(
/* imls - list all images found in flash */
/***/
#if defined(CONFIG_CMD_IMLS)
-static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_imls_nor(void)
{
flash_info_t *info;
int i, j;
@@ -1224,6 +1230,161 @@ next_sector:;
}
next_bank: ;
}
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_IMLS_NAND)
+static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
+ size_t len)
+{
+ void *imgdata;
+ int ret;
+
+ imgdata = malloc(len);
+ if (!imgdata) {
+ printf(May be a Legacy Image at NAND device %d offset
%08llX:\n,
+ nand_dev, off);
+ printf( Low memory(cannot allocate memory for image)\n);
+ return -ENOMEM;
+ }
+
+ ret = nand_read_skip_bad(nand, off, len,
+ imgdata);
+ if (ret 0 ret != -EUCLEAN) {
+ free(imgdata);
+ return ret;
+ }
+
+ if (!image_check_hcrc(imgdata)) {
+ free(imgdata);
+ return 0;
+ }
+
+ printf(Legacy Image at NAND device %d offset %08llX:\n,
+ nand_dev, off);
+ image_print_contents(imgdata);
+
+ puts( Verifying Checksum ... );
+ if (!image_check_dcrc(imgdata))
+ puts(Bad Data CRC\n);
+ else
+ puts(OK\n);
+
+ free(imgdata);
+
+ return 0;
+}
+
+static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
+ size_t len)
+{
+ void *imgdata;
+ int ret;
+
+ imgdata = malloc(len);
+ if (!imgdata) {
+ printf(May be a FIT Image at NAND device %d offset %08llX:\n,
+ nand_dev, off);
+ printf( Low memory(cannot allocate memory for image)\n);
+ return -ENOMEM;
+ }
+
+ ret = nand_read_skip_bad(nand, off, len,
+ imgdata);
+ if (ret 0 ret != -EUCLEAN) {
+ free(imgdata);
+ return ret;
+ }
+
+ if (!fit_check_format(imgdata)) {
+ free(imgdata);
+ return 0;
+ }
+
+ printf(FIT Image at NAND device %d offset %08llX:\n, nand_dev, off);
+
+ fit_print_contents(imgdata);
+ free(imgdata);
+
+ return 0;
+}
+
+static int do_imls_nand(void)
+{
+ nand_info_t *nand;
+ int nand_dev = nand_curr_device;
+ size_t len;
+ loff_t off;
+ u32 buffer[16];
+
+ if (nand_dev 0 || nand_dev = CONFIG_SYS_MAX_NAND_DEVICE) {
+ puts(\nNo NAND devices available\n);
+ return -ENODEV;
+ }
+
+ printf(\n);
+
+ for (nand_dev = 0; nand_dev CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
+ nand = nand_info[nand_dev];
+ if (!nand-name || !nand-size)
+ continue;
+
+ for (off = 0; off nand-size; off += nand-erasesize) {
+ const image_header_t *header;
+ int ret
[U-Boot] [PATCH] usb/host/ehci: Add support for EHCI on spear
Add EHCI support for spear boards
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-spear.c | 59 +++
2 files changed, 60 insertions(+)
create mode 100644 drivers/usb/host/ehci-spear.c
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 6c94794..9a6f982 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -54,6 +54,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+COBJS-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
new file mode 100644
index 000..f99bd1f
--- /dev/null
+++ b/drivers/usb/host/ehci-spear.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2010
+ * Armando Visconti, ST Micoelectronics, armando.visco...@st.com.
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include usb.h
+#include ehci.h
+#include asm/arch/hardware.h
+
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ *hccr = (struct ehci_hccr *)(CONFIG_SYS_UHC0_EHCI_BASE + 0x100);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr
+ + HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
+
+ debug(SPEAr-ehci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
+
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(int index)
+{
+ return 0;
+}
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] usbtty: adapt buffers for large packet support
From: Shiraz Hashim shiraz.has...@st.com
Increase buffer sizes at driver and tty level to accommodate kermit
large packet support.
Signed-off-by: Shiraz Hashim shiraz.has...@st.com
---
drivers/serial/usbtty.c | 2 +-
include/usbdevice.h | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index e47cb9a..148d1a6 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -63,7 +63,7 @@
/*
* Buffers to hold input and output data
*/
-#define USBTTY_BUFFER_SIZE 256
+#define USBTTY_BUFFER_SIZE 2048
static circbuf_t usbtty_input;
static circbuf_t usbtty_output;
diff --git a/include/usbdevice.h b/include/usbdevice.h
index 3edaf8b..7037efd 100644
--- a/include/usbdevice.h
+++ b/include/usbdevice.h
@@ -475,7 +475,9 @@ typedef struct urb_link {
* function driver to inform it that data has arrived.
*/
-#define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer
static data */
+/* in linux we'd malloc this, but in u-boot we prefer static data */
+#define URB_BUF_SIZE 512
+
struct urb {
struct usb_endpoint_instance *endpoint;
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] imls: Add support to list images in NAND device
On 12/18/2012 5:35 AM, Scott Wood wrote:
On 12/17/2012 02:22:40 AM, Vipin Kumar wrote:
On 12/14/2012 11:40 PM, Scott Wood wrote:
On 12/14/2012 03:32:04 AM, Vipin Kumar wrote:
+
+ switch (genimg_get_format(buffer)) {
+ case IMAGE_FORMAT_LEGACY:
+ header = (const image_header_t *)buffer;
+ len = image_get_image_size(header);
+
+ ret = nand_imls_legacyimage(nand,
nand_dev,
+ off, len);
+ if (ret 0 ret != -ENOMEM)
+ return ret;
+ break;
+#if defined(CONFIG_FIT)
+ case IMAGE_FORMAT_FIT:
+ len = fit_get_size(buffer);
+ ret = nand_imls_fitimage(nand, nand_dev,
+ off, len);
+ if (ret 0 ret != -ENOMEM)
+ return ret;
+ break;
+#endif
+ }
Do you really mean to return from the main imls function just because
one image has an error? By use return I meant return from the
subfunction.
This return only corresponds to the situation when there is an error
returned from nand read routine. In that case, I don't think there is
any use reading the NAND any further.
Just because one page has an uncorrectable error doesn't mean the
entire NAND is bad. Note that this is different from what you
currently do if you get an error on the initial read where you look for
a header.
Yes, I got your point.
I would now not announce the uncorrectable errors as they may hog the
whole stdout and still continue to work for the whole NAND device.
Please check the implementation in v4
I'd rather see errors be announced, with some reasonable limit on how
many (and a message indicating if further errors exist that were
suppressed).
Hmm, OK. I would do it this way in v5
-Scott
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] armv7/ltimer: Add support for local timer on armv7 cpus
On 12/16/2012 1:14 PM, Dennis Lan (dlan) wrote: Hi On Sat, Dec 15, 2012 at 6:20 AM, Wolfgang Denk w...@denx.de mailto:w...@denx.de wrote: Dear Vipin Kumar, In message 50caf0cb.1050...@st.com mailto:50caf0cb.1050...@st.com you wrote: ping again pong ;-) On 12/6/2012 2:52 PM, Vipin KUMAR wrote: Certain ARMV7 cpus eg. CortexA9 contains a local and a global timer within the CPU core itself. This patch adds generic support for local timer. What would be the use of such timer support? Is there any code that actually needs it, and why does it need anything beyond the existing timer support we have? Hi wolfgang: I think vipin here is trying to provide a generic timer support for ARMV7 architecture, which contains private(local) and global timer. It's general a good thing which means we can maximize the code usage.. Actually I was planing to test the code, but haven't find the time yet ;-) Hello Wolfgang Dennis is right. I am trying to provide the armv7 local timer support. Hi vipin: why you only support local timer(private)? shouldn't it different to support global timer too? Well, actually the local timer was used in the spear13xx support which is to be added later on. The global timer was not used and hence the driver was not needed (at least by us). but I agree that such a driver would be useful for a lot of people using armv7 cores and CPU timers The global timer support, even if it is added, would be added as a separate driver so this is infact complete in its own Regards Vipin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] imls: Add support to list images in NAND device
On 12/14/2012 3:29 AM, Scott Wood wrote:
On 12/13/2012 04:38:18 AM, Vipin Kumar wrote:
+ for (off = 0; off nand-size; off += nand-erasesize) {
+ const image_header_t *header;
+ int ret;
+
+ if (nand_block_isbad(nand, off))
+ continue;
+
+ len = sizeof(buffer);
+
+ ret = nand_read(nand, off, len, (u8 *)buffer);
+ if (ret 0 ret != -EUCLEAN)
+ continue;
Might want to make some noise if you get an uncorrectable error.
OK..
+
+ switch (genimg_get_format(buffer)) {
+ case IMAGE_FORMAT_LEGACY:
+ header = (const image_header_t *)buffer;
+ len = image_get_image_size(header);
+
+ ret = nand_imls_legacyimage(nand, nand_dev,
+ off, len);
+ if (ret 0 ret != -ENOMEM)
+ return ret;
+ break;
+#if defined(CONFIG_FIT)
+ case IMAGE_FORMAT_FIT:
+ len = fit_get_size(buffer);
+ ret = nand_imls_fitimage(nand, nand_dev,
+ off, len);
+ if (ret 0 ret != -ENOMEM)
+ return ret;
+ break;
+#endif
+ }
Do you really mean to return from the main imls function just because
one image has an error? By use return I meant return from the
subfunction.
I thought about it a little bit. How do you suggest
-Scott
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] usbh/ehci: Increase timeout for enumeration
On 12/13/2012 6:41 PM, Marek Vasut wrote: Dear Vipin Kumar, The current logic reads the port status just once after usb_hub_power_on and expects the portstatus and portchange to report the connection status immediately and correctly. Few pen drives are not able to report both of them immediately ie. those pens report the connection change but not the connected state after the first read. This opportunity once lost is gone for ever because the u-boot, unlike linux or any other OS, works in polling mode. This patch modifies the logic to read the port status continuously until the portstatus and portchange both report a connection change as well as a connected state or no connection change and no connection. This logic is placed in a timeout of 10 sec. At the end of it, the pen drive would have either reported a ONE or a ZERO in bit 1 of portstatus as well as portchange. It enhances the set of pen drives which can eventually be detected by u-boot Note: This 10 second timeout is based purely on several experiments done with the broken pen drives Signed-off-by: Vipin Kumarvipin.ku...@st.com Acked-by: Igor Grinberggrinb...@compulab.co.il Applied, tested. Thanks Thanks Marek Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] imls: Add support to list images in NAND device
On 12/14/2012 3:22 AM, Scott Wood wrote:
On 12/13/2012 12:10:58 AM, Vipin Kumar wrote:
Or better, just have one CONFIG_CMD_IMLS and have it operate on
whatever flash types are configured into U-Boot.
I didn't do it because until now the CONFIG_CMD_IMLS config is
tightly bound with flash only eg config_cmd_default.h enables
CONFIG_CMD_IMLS only when CONFIG_SYS_NO_FLASH is not defined. I
thought there might be other places as well
Still, it might be better to fix that than to build upon a
no-longer-accurate assumption.
OK, I would try that in v4
+#if defined(CONFIG_CMD_IMLS_NAND)
+static void do_imls_nand(void)
+{
+ nand_info_t *nand;
+ int nand_dev = nand_curr_device;
+ size_t read_size;
+ loff_t off;
+ u8 buffer[512];
Why 512?
Basically there are 2 image types supported as of today.
* Legacy: 64 byte header
* FIT: 512 byte header
After reading the first 512 bytes from each block of NAND, we try to
validate the header and only if the header validation is successful,
we malloc the space for the whole image and read the image into it
Do you really need 512 bytes for fdt_check_header() to work?
I have reduced it already to 64 bytes in v3
+ nand =nand_info[nand_dev];
+ if (!nand-name || !nand-size)
+ continue;
+
+ for (off = 0; off nand-size; off += nand-erasesize)
{
+ int ret;
+ void *imgdata;
+
+ if (nand_block_isbad(nand, off))
+ goto next_block;
+
+ read_size = sizeof(buffer);
+
+ ret = nand_read(nand, off,read_size, buffer);
+ if (ret 0 ret != -EUCLEAN)
+ goto next_block;
s/goto next_block/continue/
hmmm, OK.
I copied the original code ie for listing images from nor flash.
Should I also correct it !!
If you want to do that as a separate patch, that's fine -- but the code
is sufficiently different that I don't think there's a strong
consistency argument to be made.
Check if it is OK in v3
+ header = (const image_header_t *)buffer;
+
+ switch (genimg_get_format(buffer)) {
+ case IMAGE_FORMAT_LEGACY:
+ if (!image_check_hcrc(header))
+ goto next_block;
+
+ read_size =
image_get_image_size(header);
+
+ imgdata = malloc(read_size);
+ if (!imgdata) {
+ printf(Not able to list all
images \
+ (Low memory)\n);
Don't line-wrap error strings.
80 column ?
Error strings are an exception for the sake of greppability. From
Linux's Documentation/CodingStyle:
Statements longer than 80 columns will be broken into sensible
chunks, unless
exceeding 80 columns significantly increases readability and does
not hide
information. Descendants are always substantially shorter than the
parent and
are placed substantially to the right. The same applies to function
headers
with a long argument list. However, never break user-visible strings
such as
printk messages, because that breaks the ability to grep for them.
Yes, thanks for reminding. The error strings are more readable already
in v3. Please take a look
Why is the no-memory error message different for FIT versus legacy
images? I realize that at this point you don't know if it's a FIT
versus some other dtb, but why do you print the device and offset
here
but not in the legacy case? Why Low memory(cannot allocate memory
for
image) versus just (Low memory)?
Typo :(
I would give the following print for both
printf(May be a FIT Image at NAND \
device %d offset %08llX:\n,
nand_dev, off);
printf( Low memory(cannot allocate \
memory for image)\n);
It's a little more verbose than I'd have done, but OK. Can you put a
space between memory and (cannot, though?
Sure. I will do that in v4
-Vipin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] armv7/ltimer: Add support for local timer on armv7 cpus
ping again
On 12/6/2012 2:52 PM, Vipin KUMAR wrote:
Certain ARMV7 cpus eg. CortexA9 contains a local and a global timer within the
CPU core itself. This patch adds generic support for local timer.
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
arch/arm/cpu/armv7/Makefile | 11 ++-
arch/arm/cpu/armv7/ca9_ltimer.c | 152 ++
arch/arm/include/asm/ca9_ltimer.h | 40 ++
3 files changed, 199 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ca9_ltimer.c
create mode 100644 arch/arm/include/asm/ca9_ltimer.h
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..3ef01f6 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -27,15 +27,18 @@ LIB = $(obj)lib$(CPU).o
START := start.o
-COBJS += cache_v7.o
+COBJS-y+= cache_v7.o
-COBJS += cpu.o
-COBJS += syslib.o
+COBJS-y+= cpu.o
+COBJS-y+= syslib.o
+COBJS-$(CONFIG_ARMV7_CA9LTIMER) += ca9_ltimer.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
-SOBJS += lowlevel_init.o
+SOBJS-y+= lowlevel_init.o
endif
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/arm/cpu/armv7/ca9_ltimer.c b/arch/arm/cpu/armv7/ca9_ltimer.c
new file mode 100644
index 000..cbf1552
--- /dev/null
+++ b/arch/arm/cpu/armv7/ca9_ltimer.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/ca9_ltimer.h
+#includeasm/arch/hardware.h
+
+#define READ_TIMER() readl(ca9_timer_p-count)
+
+static struct ca9_timer_regs *const ca9_timer_p =
+ (struct ca9_timer_regs *)CONFIG_ARMV7_LTIMER_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd-tbl
+#define lastdecgd-lastinc
+#define tickshzgd-timer_rate_hz
+#define ticksper10usec gd-tbu
+
+int timer_init(void)
+{
+ u32 prescaler, timertickshz;
+ /*
+* Genrally, CortexA9 MPUs are operating from 500MHz to 1500MHz which
+* means that CA9 local timer clock would be in the range of 250 MHz to
+* 750MHz.
+* Try to find a prescaler which can perfectly divide the local timer
+* clock. Take prescaler as 200 if nothing is found
+*/
+ for (prescaler = 255; prescaler 1; prescaler--) {
+ if (CONFIG_ARMV7_LTMR_CLK ==
+ (CONFIG_ARMV7_LTMR_CLK / prescaler) * prescaler)
+ break;
+ }
+
+ if (prescaler == 1)
+ prescaler = 200;
+ timertickshz = CONFIG_ARMV7_LTMR_CLK / prescaler;
+ ticksper10usec = timertickshz / (100 * 1000);
+ tickshz = timertickshz / CONFIG_SYS_HZ;
+
+ /* disable timers */
+ writel(((prescaler - 1) 8) | AUTO_RELOAD,ca9_timer_p-control);
+
+ /* load value for free running */
+ writel(FREE_RUNNING,ca9_timer_p-load);
+
+ /* auto reload, start timer */
+ setbits_le32(ca9_timer_p-control, TIMER_ENABLE);
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return (get_timer_masked() / tickshz) - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong tmo;
+ ulong start = get_timer_masked();
+ ulong rndoff;
+
+ rndoff = (usec % 10) ? 1 : 0;
+ tmo = ((usec / 10) + rndoff) * ticksper10usec;
+
+ while ((ulong) (get_timer_masked() - start) tmo);
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER();
+
+ if (now= lastdec) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow
Re: [U-Boot] [PATCH v3] imls: Add support to list images in NAND device
+
+ switch (genimg_get_format(buffer)) {
+ case IMAGE_FORMAT_LEGACY:
+ header = (const image_header_t *)buffer;
+ len = image_get_image_size(header);
+
+ ret = nand_imls_legacyimage(nand,
nand_dev,
+ off, len);
+ if (ret 0 ret != -ENOMEM)
+ return ret;
+ break;
+#if defined(CONFIG_FIT)
+ case IMAGE_FORMAT_FIT:
+ len = fit_get_size(buffer);
+ ret = nand_imls_fitimage(nand, nand_dev,
+ off, len);
+ if (ret 0 ret != -ENOMEM)
+ return ret;
+ break;
+#endif
+ }
Do you really mean to return from the main imls function just because
one image has an error? By use return I meant return from the
subfunction.
This return only corresponds to the situation when there is an error
returned from nand read routine. In that case, I don't think there is
any use reading the NAND any further.
What do you think ?
-Scott
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] imls: Add support to list images in NAND device
This patch adds support to list images in NAND flash through imls
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
README | 3 +-
common/cmd_bootm.c | 166 -
2 files changed, 167 insertions(+), 2 deletions(-)
diff --git a/README b/README
index 2077c3b..46fd21d 100644
--- a/README
+++ b/README
@@ -831,7 +831,8 @@ The following options need to be configured:
CONFIG_CMD_I2C * I2C serial bus support
CONFIG_CMD_IDE * IDE harddisk support
CONFIG_CMD_IMIiminfo
- CONFIG_CMD_IMLS List all found images
+ CONFIG_CMD_IMLS List all images found in NOR flash
+ CONFIG_CMD_IMLS_NAND List all images found in NAND flash
CONFIG_CMD_IMMAP* IMMR dump support
CONFIG_CMD_IMPORTENV* import an environment
CONFIG_CMD_INI * import data from an ini file into the
env
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index d256ddf..e55becd 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -80,9 +80,15 @@ static int image_info(unsigned long addr);
#include flash.h
#include mtd/cfi_flash.h
extern flash_info_t flash_info[]; /* info for FLASH chips */
+#endif
+
+#if defined(CONFIG_CMD_IMLS) || defined(CONFIG_CMD_IMLS_NAND)
static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
+#include linux/err.h
+#include nand.h
+
#ifdef CONFIG_SILENT_CONSOLE
static void fixup_silent_linux(void);
#endif
@@ -1175,7 +1181,7 @@ U_BOOT_CMD(
/* imls - list all images found in flash */
/***/
#if defined(CONFIG_CMD_IMLS)
-static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_imls_nor(void)
{
flash_info_t *info;
int i, j;
@@ -1224,6 +1230,164 @@ next_sector:;
}
next_bank: ;
}
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_IMLS_NAND)
+static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
+ size_t len)
+{
+ void *imgdata;
+ int ret;
+
+ imgdata = malloc(len);
+ if (!imgdata) {
+ printf(May be a Legacy Image at NAND device %d \
+ offset %08llX:\n, nand_dev, off);
+ printf( Low memory(cannot allocate memory for image)\n);
+ return -ENOMEM;
+ }
+
+ ret = nand_read_skip_bad(nand, off, len,
+ imgdata);
+ if (ret 0 ret != -EUCLEAN) {
+ free(imgdata);
+ return ret;
+ }
+
+ if (!image_check_hcrc(imgdata)) {
+ free(imgdata);
+ return 0;
+ }
+
+ printf(Legacy Image at NAND device %d offset %08llX:\n,
+ nand_dev, off);
+ image_print_contents(imgdata);
+
+ puts( Verifying Checksum ... );
+ if (!image_check_dcrc(imgdata))
+ puts(Bad Data CRC\n);
+ else
+ puts(OK\n);
+
+ free(imgdata);
+
+ return 0;
+}
+
+static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
+ size_t len)
+{
+ void *imgdata;
+ int ret;
+
+ imgdata = malloc(len);
+ if (!imgdata) {
+ printf(May be a FIT Image at NAND device %d \
+ offset %08llX:\n, nand_dev, off);
+ printf( Low memory(cannot allocate memory for image)\n);
+ return -ENOMEM;
+ }
+
+ ret = nand_read_skip_bad(nand, off, len,
+ imgdata);
+ if (ret 0 ret != -EUCLEAN) {
+ free(imgdata);
+ return ret;
+ }
+
+ if (!fit_check_format(imgdata)) {
+ free(imgdata);
+ return 0;
+ }
+
+ printf(FIT Image at NAND device %d offset %08llX:\n, nand_dev, off);
+
+ fit_print_contents(imgdata);
+ free(imgdata);
+
+ return 0;
+}
+
+static int do_imls_nand(void)
+{
+ nand_info_t *nand;
+ int nand_dev = nand_curr_device;
+ size_t len;
+ loff_t off;
+ u32 buffer[16];
+
+ if (nand_dev 0 || nand_dev = CONFIG_SYS_MAX_NAND_DEVICE) {
+ puts(\nNo NAND devices available\n);
+ return -ENODEV;
+ }
+
+ printf(\n);
+
+ for (nand_dev = 0; nand_dev CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
+ nand = nand_info[nand_dev];
+ if (!nand-name || !nand-size)
+ continue;
+
+ for (off = 0; off nand-size; off += nand-erasesize) {
+ const image_header_t *header;
+ int ret;
+
+ if (nand_block_isbad(nand, off))
+ continue
[U-Boot] [PATCH v3] usbh/ehci: Increase timeout for enumeration
The current logic reads the port status just once after usb_hub_power_on and
expects the portstatus and portchange to report the connection status
immediately and correctly.
Few pen drives are not able to report both of them immediately ie. those pens
report the connection change but not the connected state after the first read.
This opportunity once lost is gone for ever because the u-boot, unlike linux or
any other OS, works in polling mode.
This patch modifies the logic to read the port status continuously until the
portstatus and portchange both report a connection change as well as a connected
state or no connection change and no connection. This logic is placed in a
timeout of 10 sec. At the end of it, the pen drive would have either reported a
ONE or a ZERO in bit 1 of portstatus as well as portchange.
It enhances the set of pen drives which can eventually be detected by u-boot
Note: This 10 second timeout is based purely on several experiments done with
the broken pen drives
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Igor Grinberg grinb...@compulab.co.il
---
Changes in v3
Added comment (in patch comment as well as code) for the reasons for choosing
10 seconds as timeout
common/usb_hub.c | 33 -
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index e4a1201..4d75b90 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -396,14 +396,37 @@ static int usb_hub_configure(struct usb_device *dev)
for (i = 0; i dev-maxchild; i++) {
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
+ int ret;
+ ulong start = get_timer(0);
+
+ /*
+* Wait for (whichever finishes first)
+* - A maximum of 10 seconds
+*This is a purely observational value driven by connecting
+*a few broken pen drives and taking the max * 1.5 approach
+* - connection_change and connection state to report same
+*state
+*/
+ do {
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret 0) {
+ USB_HUB_PRINTF(get_port_status failed\n);
+ break;
+ }
+
+ portstatus = le16_to_cpu(portsts-wPortStatus);
+ portchange = le16_to_cpu(portsts-wPortChange);
+
+ if ((portchange USB_PORT_STAT_C_CONNECTION) ==
+ (portstatus USB_PORT_STAT_CONNECTION))
+ break;
+
+ mdelay(100);
+ } while (get_timer(start) CONFIG_SYS_HZ * 10);
- if (usb_get_port_status(dev, i + 1, portsts) 0) {
- USB_HUB_PRINTF(get_port_status failed\n);
+ if (ret 0)
continue;
- }
- portstatus = le16_to_cpu(portsts-wPortStatus);
- portchange = le16_to_cpu(portsts-wPortChange);
USB_HUB_PRINTF(Port %d Status %X Change %X\n,
i + 1, portstatus, portchange);
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] spi/arm-pl022: Add support for ARM PL022 spi controller
From: Armando Visconti armando.visco...@st.com
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
Changes in v3
Added void to spi_init arguments
Used readl/writel in place of u16 accessors
Fix: Provided address of register in place of value to readl/writel IO
accessors
Tested with spear1340-evb
Stefan, I have not added your Acked-by because the patch has changed after you
acked it.
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 824d357..3a4e4b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..86d65ae
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __weak spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init(void
[U-Boot] [PATCH v2 1/2] net/designware: Do not select MIIPORT for RGMII interface
Do not select MIIPORT for RGMII interface
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
drivers/net/designware.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index bf21a08..46f6601 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -113,7 +113,9 @@ static int mac_reset(struct eth_device *dev)
int timeout = CONFIG_MACRESET_TIMEOUT;
writel(DMAMAC_SRST, dma_p-busmode);
- writel(MII_PORTSELECT, mac_p-conf);
+
+ if (priv-interface != PHY_INTERFACE_MODE_RGMII)
+ writel(MII_PORTSELECT, mac_p-conf);
start = get_timer(0);
while (get_timer(start) timeout) {
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] net/macb: Add arch specific routine to get mdio control
From: Shiraz Hashim shiraz.has...@st.com
SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently there is a fixed configuration in which only a
particular MAC can use the MDIO lines.
Call an arch specific function to take control of specific mdio lines at
runtime.
Signed-off-by: Shiraz Hashim shiraz.has...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
Changes in v2
Used __weak instead of __attribute__((weak...
Improve patch comment
drivers/net/macb.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 8bacbda..6b49f0e 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -163,6 +163,11 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
return MACB_BFEXT(DATA, frame);
}
+static void __weak arch_get_mdio_control(const char *name)
+{
+ return;
+}
+
#if defined(CONFIG_CMD_MII)
int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
@@ -173,6 +178,7 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8
reg, u16 *value)
if ( macb-phy_addr != phy_adr )
return -1;
+ arch_get_mdio_control(devname);
*value = macb_mdio_read(macb, reg);
return 0;
@@ -186,6 +192,7 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8
reg, u16 value)
if ( macb-phy_addr != phy_adr )
return -1;
+ arch_get_mdio_control(devname);
macb_mdio_write(macb, reg, value);
return 0;
@@ -377,6 +384,7 @@ static int macb_phy_init(struct macb_device *macb)
int media, speed, duplex;
int i;
+ arch_get_mdio_control(netdev-name);
#ifdef CONFIG_MACB_SEARCH_PHY
/* Auto-detect phy_addr */
if (!macb_phy_find(macb)) {
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] imls: Add support to list images in NAND device
imls does not list the images in NAND devices. This patch implements this
support for legacy type images.
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
Hello Scott,
There has been sometime since you reviewed the first version of this patch.
http://lists.denx.de/pipermail/u-boot/2012-November/139631.html
I am sorry for a late response on this. I was waiting for other comments if any
on the whole patch-set
Regards
Vipin
README | 3 +-
common/cmd_bootm.c | 133 -
2 files changed, 134 insertions(+), 2 deletions(-)
diff --git a/README b/README
index 2077c3b..ec5c31e 100644
--- a/README
+++ b/README
@@ -831,7 +831,8 @@ The following options need to be configured:
CONFIG_CMD_I2C * I2C serial bus support
CONFIG_CMD_IDE * IDE harddisk support
CONFIG_CMD_IMIiminfo
- CONFIG_CMD_IMLS List all found images
+ CONFIG_CMD_IMLS List all images found in flash
+ CONFIG_CMD_IMLS_NAND List all images found in NAND device
CONFIG_CMD_IMMAP* IMMR dump support
CONFIG_CMD_IMPORTENV* import an environment
CONFIG_CMD_INI * import data from an ini file into the
env
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index d256ddf..8ee562a 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -83,6 +83,9 @@ extern flash_info_t flash_info[]; /* info for FLASH chips */
static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
+#include linux/err.h
+#include nand.h
+
#ifdef CONFIG_SILENT_CONSOLE
static void fixup_silent_linux(void);
#endif
@@ -1175,7 +1178,7 @@ U_BOOT_CMD(
/* imls - list all images found in flash */
/***/
#if defined(CONFIG_CMD_IMLS)
-static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static void do_imls_flash(void)
{
flash_info_t *info;
int i, j;
@@ -1224,6 +1227,134 @@ next_sector:;
}
next_bank: ;
}
+}
+#endif
+
+#if defined(CONFIG_CMD_IMLS_NAND)
+static void do_imls_nand(void)
+{
+ nand_info_t *nand;
+ int nand_dev = nand_curr_device;
+ size_t read_size;
+ loff_t off;
+ u8 buffer[512];
+ const image_header_t *header = (const image_header_t *)buffer;
+
+ /* the following commands operate on the current device */
+ if (nand_dev 0 || nand_dev = CONFIG_SYS_MAX_NAND_DEVICE) {
+ puts(\nNo NAND devices available\n);
+ return;
+ }
+
+ printf(\n);
+
+ for (nand_dev = 0; nand_dev CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
+
+ nand = nand_info[nand_dev];
+ if (!nand-name || !nand-size)
+ continue;
+
+ for (off = 0; off nand-size; off += nand-erasesize) {
+ int ret;
+ void *imgdata;
+
+ if (nand_block_isbad(nand, off))
+ goto next_block;
+
+ read_size = sizeof(buffer);
+
+ ret = nand_read(nand, off, read_size, buffer);
+ if (ret 0 ret != -EUCLEAN)
+ goto next_block;
+
+ header = (const image_header_t *)buffer;
+
+ switch (genimg_get_format(buffer)) {
+ case IMAGE_FORMAT_LEGACY:
+ if (!image_check_hcrc(header))
+ goto next_block;
+
+ read_size = image_get_image_size(header);
+
+ imgdata = malloc(read_size);
+ if (!imgdata) {
+ printf(Not able to list all images \
+ (Low memory)\n);
+ goto next_block;
+ }
+
+ ret = nand_read_skip_bad(nand, off, read_size,
+ imgdata);
+ if (ret 0 ret != -EUCLEAN) {
+ free(imgdata);
+ goto next_block;
+ }
+
+ printf(Legacy Image at NAND device %d \
+ offset %08llX:\n, nand_dev, off);
+ image_print_contents(imgdata);
+
+ puts( Verifying Checksum ... );
+ if (!image_check_dcrc(imgdata))
+ puts(Bad Data CRC\n);
+ else
+ puts(OK\n
Re: [U-Boot] [PATCH v2] usbh/ehci: Increase timeout for enumeration
+ ulong start = get_timer(0);
+
+ do {
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret 0) {
+ USB_HUB_PRINTF(get_port_status failed\n);
+ break;
+ }
+
+ portstatus = le16_to_cpu(portsts-wPortStatus);
+ portchange = le16_to_cpu(portsts-wPortChange);
+
+ if ((portchange USB_PORT_STAT_C_CONNECTION) ==
+ (portstatus USB_PORT_STAT_CONNECTION))
I don't know if there is any corner case when the above check
will always fail and so it will always wait a maximal delay time.
Are those registers that identical, or can there be differences?
+ break;
+
+ mdelay(100);
+ } while (get_timer(start) CONFIG_SYS_HZ * 10);
Is there any justification for the CONFIG_SYS_HZ * 10?
I would be much more fine with this patch if there were any
(even just test based * 2) reason for that number.
Not really. Just a practical test.
Marek, can I have comments from you as well
Thanks
Vipin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] sdhci: Add sdhci support for spear devices
Stefan, Wolfgang,
Can you please add relevant people if not present already in this mail
Regards
Vipin
On 12/6/2012 12:14 PM, Vipin KUMAR wrote:
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
drivers/mmc/Makefile | 1 +
drivers/mmc/spear_sdhci.c | 44
2 files changed, 45 insertions(+)
create mode 100644 drivers/mmc/spear_sdhci.c
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index a1dd730..01dd61d 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -45,6 +45,7 @@ COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
COBJS-$(CONFIG_SDHCI) += sdhci.o
COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+COBJS-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
COBJS-$(CONFIG_DWMMC) += dw_mmc.o
diff --git a/drivers/mmc/spear_sdhci.c b/drivers/mmc/spear_sdhci.c
new file mode 100644
index 000..23f1f4b
--- /dev/null
+++ b/drivers/mmc/spear_sdhci.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#includecommon.h
+#includemalloc.h
+#includesdhci.h
+
+int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+{
+ struct sdhci_host *host = NULL;
+ host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+ if (!host) {
+ printf(sdhci host malloc fail!\n);
+ return 1;
+ }
+
+ host-name = sdhci;
+ host-ioaddr = (void *)regbase;
+ host-quirks = quirks;
+
+ if (quirks SDHCI_QUIRK_REG32_RW)
+ host-version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) 16;
+ else
+ host-version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+ add_sdhci(host, max_clk, min_clk);
+ return 0;
+}
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] spi/arm-pl022: Add support for ARM PL022 spi controller
Ping. Can I get a few Reviewed-by's :) On 12/6/2012 1:35 PM, Stefan Roese wrote: (Added Mike to Cc) On 12/06/2012 07:56 AM, Vipin Kumar wrote: From: Armando Viscontiarmando.visco...@st.com This patch adds the support for the ARM PL022 SPI controller for the standard variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO. Signed-off-by: Armando Viscontiarmando.visco...@st.com Signed-off-by: Vipin Kumarvipin.ku...@st.com --- Dear Wolfgang, Stefan, There seems to be no direct owner of spi framework. So, I am directing this patch to you IIRC, Mike Frysinger did a bit of SPI maintenance in the last years. Perhaps he can comment. Mike, still around? Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend 1/2] net/designware: Do not select MIIPORT for RGMII interface
ping
On 12/6/2012 12:40 PM, Vipin KUMAR wrote:
Do not select MIIPORT for RGMII interface
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
drivers/net/designware.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index bf21a08..46f6601 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -113,7 +113,9 @@ static int mac_reset(struct eth_device *dev)
int timeout = CONFIG_MACRESET_TIMEOUT;
writel(DMAMAC_SRST,dma_p-busmode);
- writel(MII_PORTSELECT,mac_p-conf);
+
+ if (priv-interface != PHY_INTERFACE_MODE_RGMII)
+ writel(MII_PORTSELECT,mac_p-conf);
start = get_timer(0);
while (get_timer(start) timeout) {
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] armv7/ltimer: Add support for local timer on armv7 cpus
ping
On 12/6/2012 2:52 PM, Vipin KUMAR wrote:
Certain ARMV7 cpus eg. CortexA9 contains a local and a global timer within the
CPU core itself. This patch adds generic support for local timer.
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
arch/arm/cpu/armv7/Makefile | 11 ++-
arch/arm/cpu/armv7/ca9_ltimer.c | 152 ++
arch/arm/include/asm/ca9_ltimer.h | 40 ++
3 files changed, 199 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ca9_ltimer.c
create mode 100644 arch/arm/include/asm/ca9_ltimer.h
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..3ef01f6 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -27,15 +27,18 @@ LIB = $(obj)lib$(CPU).o
START := start.o
-COBJS += cache_v7.o
+COBJS-y+= cache_v7.o
-COBJS += cpu.o
-COBJS += syslib.o
+COBJS-y+= cpu.o
+COBJS-y+= syslib.o
+COBJS-$(CONFIG_ARMV7_CA9LTIMER) += ca9_ltimer.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
-SOBJS += lowlevel_init.o
+SOBJS-y+= lowlevel_init.o
endif
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/arm/cpu/armv7/ca9_ltimer.c b/arch/arm/cpu/armv7/ca9_ltimer.c
new file mode 100644
index 000..cbf1552
--- /dev/null
+++ b/arch/arm/cpu/armv7/ca9_ltimer.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/ca9_ltimer.h
+#includeasm/arch/hardware.h
+
+#define READ_TIMER() readl(ca9_timer_p-count)
+
+static struct ca9_timer_regs *const ca9_timer_p =
+ (struct ca9_timer_regs *)CONFIG_ARMV7_LTIMER_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd-tbl
+#define lastdecgd-lastinc
+#define tickshzgd-timer_rate_hz
+#define ticksper10usec gd-tbu
+
+int timer_init(void)
+{
+ u32 prescaler, timertickshz;
+ /*
+* Genrally, CortexA9 MPUs are operating from 500MHz to 1500MHz which
+* means that CA9 local timer clock would be in the range of 250 MHz to
+* 750MHz.
+* Try to find a prescaler which can perfectly divide the local timer
+* clock. Take prescaler as 200 if nothing is found
+*/
+ for (prescaler = 255; prescaler 1; prescaler--) {
+ if (CONFIG_ARMV7_LTMR_CLK ==
+ (CONFIG_ARMV7_LTMR_CLK / prescaler) * prescaler)
+ break;
+ }
+
+ if (prescaler == 1)
+ prescaler = 200;
+ timertickshz = CONFIG_ARMV7_LTMR_CLK / prescaler;
+ ticksper10usec = timertickshz / (100 * 1000);
+ tickshz = timertickshz / CONFIG_SYS_HZ;
+
+ /* disable timers */
+ writel(((prescaler - 1) 8) | AUTO_RELOAD,ca9_timer_p-control);
+
+ /* load value for free running */
+ writel(FREE_RUNNING,ca9_timer_p-load);
+
+ /* auto reload, start timer */
+ setbits_le32(ca9_timer_p-control, TIMER_ENABLE);
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return (get_timer_masked() / tickshz) - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong tmo;
+ ulong start = get_timer_masked();
+ ulong rndoff;
+
+ rndoff = (usec % 10) ? 1 : 0;
+ tmo = ((usec / 10) + rndoff) * ticksper10usec;
+
+ while ((ulong) (get_timer_masked() - start) tmo);
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER();
+
+ if (now= lastdec) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow
Re: [U-Boot] [PATCH resend] spi/arm-pl022: Add support for ARM PL022 spi controller
On 12/12/2012 3:48 PM, Stefan Roese wrote:
On 12/06/2012 07:56 AM, Vipin Kumar wrote:
From: Armando Viscontiarmando.visco...@st.com
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Viscontiarmando.visco...@st.com
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
Dear Wolfgang, Stefan,
There seems to be no direct owner of spi framework. So, I am directing this
patch to you
A few comments below.
Regards
Vipin
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 308
2 files changed, 309 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 824d357..3a4e4b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..3ea769a
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#includecommon.h
+#includemalloc.h
+#includespi.h
+#includeasm/io.h
+#includeasm/arch/hardware.h
+
+/* SSP registers mapping */
+#define SSP_CR00x000
+#define SSP_CR10x004
+#define SSP_DR 0x008
+#define SSP_SR 0x00C
+#define SSP_CPSR 0x010
+#define SSP_IMSC 0x014
+#define SSP_RIS0x018
+#define SSP_MIS0x01C
+#define SSP_ICR0x020
+#define SSP_DMACR 0x024
+#define SSP_ITCR 0x080
+#define SSP_ITIP 0x084
+#define SSP_ITOP 0x088
+#define SSP_TDR0x08C
Please use C-structs instead to access the registers.
May be this patch is a ripped version from linux. That's why
Thanks. I will do this in v2
+#define SSP_PID0 0xFE0
+#define SSP_PID1 0xFE4
+#define SSP_PID2 0xFE8
+#define SSP_PID3 0xFEC
+
+#define SSP_CID0 0xFF0
+#define SSP_CID1 0xFF4
+#define SSP_CID2 0xFF8
+#define SSP_CID3 0xFFC
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+ __attribute__((weak, alias(__spi_cs_is_valid)));
+void spi_cs_activate(struct spi_slave *slave)
+ __attribute__((weak, alias(__spi_cs_activate)));
+void spi_cs_deactivate(struct spi_slave *slave)
+ __attribute__((weak, alias(__spi_cs_deactivate)));
__weak from linux/compiler.h
OK
+int __spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void
Re: [U-Boot] [PATCH resend 2/2] net/macb: Add arch specific routine to get mdio control
ping. one more :)
On 12/6/2012 12:40 PM, Vipin KUMAR wrote:
From: Shiraz Hashimshiraz.has...@st.com
SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently their is a fixed configuration in which only a
particular MAC can use the MDIO lines.
Call an arch specific function to take control of specific mdio lines at
runtime.
Signed-off-by: Shiraz Hashimshiraz.has...@st.com
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
drivers/net/macb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 8bacbda..45fbbd7 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -163,6 +163,13 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
return MACB_BFEXT(DATA, frame);
}
+static void __def_arch_get_mdio_control(const char *name)
+{
+ return;
+}
+int arch_get_mdio_control(const char *name)
+ __attribute__((weak, alias(__def_arch_get_mdio_control)));
+
#if defined(CONFIG_CMD_MII)
int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
@@ -173,6 +180,7 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8
reg, u16 *value)
if ( macb-phy_addr != phy_adr )
return -1;
+ arch_get_mdio_control(devname);
*value = macb_mdio_read(macb, reg);
return 0;
@@ -186,6 +194,7 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8
reg, u16 value)
if ( macb-phy_addr != phy_adr )
return -1;
+ arch_get_mdio_control(devname);
macb_mdio_write(macb, reg, value);
return 0;
@@ -377,6 +386,7 @@ static int macb_phy_init(struct macb_device *macb)
int media, speed, duplex;
int i;
+ arch_get_mdio_control(netdev-name);
#ifdef CONFIG_MACB_SEARCH_PHY
/* Auto-detect phy_addr */
if (!macb_phy_find(macb)) {
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend 2/2] net/macb: Add arch specific routine to get mdio control
On 12/12/2012 4:37 PM, Stefan Roese wrote:
On 12/06/2012 08:10 AM, Vipin Kumar wrote:
From: Shiraz Hashimshiraz.has...@st.com
SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently their is a fixed configuration in which only a
particular MAC can use the MDIO lines.
there is instead of their is
Thanks. I would change this in v2
Call an arch specific function to take control of specific mdio lines at
runtime.
Signed-off-by: Shiraz Hashimshiraz.has...@st.com
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
drivers/net/macb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 8bacbda..45fbbd7 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -163,6 +163,13 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
return MACB_BFEXT(DATA, frame);
}
+static void __def_arch_get_mdio_control(const char *name)
+{
+ return;
+}
+int arch_get_mdio_control(const char *name)
+ __attribute__((weak, alias(__def_arch_get_mdio_control)));
__weak from linux/compiler.h please
in v2
Otherwise:
Acked-by: Stefan Roeses...@denx.de
Thanks,
Stefan
Vipin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] spi/arm-pl022: Add support for ARM PL022 spi controller
On 12/12/2012 4:40 PM, Armando VISCONTI wrote: + +/* SSP registers mapping */ +#define SSP_CR0 0x000 +#define SSP_CR1 0x004 +#define SSP_DR 0x008 +#define SSP_SR 0x00C +#define SSP_CPSR 0x010 +#define SSP_IMSC 0x014 +#define SSP_RIS 0x018 +#define SSP_MIS 0x01C +#define SSP_ICR 0x020 +#define SSP_DMACR 0x024 +#define SSP_ITCR 0x080 +#define SSP_ITIP 0x084 +#define SSP_ITOP 0x088 +#define SSP_TDR 0x08C Please use C-structs instead to access the registers. May be this patch is a ripped version from linux. That's why Thanks. I will do this in v2 Yes, I took this part from the linux pl022 driver. Never understood which way (C-struct or defines) is preferable and why... U-boot uses the structure way(I do not exactly understand why) and the kernel code uses both ways I would change it to use the structure Rgds, Arm Vipin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] usbh/ehci: Increase timeout for enumeration
On 12/12/2012 5:10 PM, Igor Grinberg wrote:
On 12/12/12 11:54, Vipin Kumar wrote:
+ulong start = get_timer(0);
+
+do {
+ret = usb_get_port_status(dev, i + 1, portsts);
+if (ret 0) {
+USB_HUB_PRINTF(get_port_status failed\n);
+break;
+}
+
+portstatus = le16_to_cpu(portsts-wPortStatus);
+portchange = le16_to_cpu(portsts-wPortChange);
+
+if ((portchange USB_PORT_STAT_C_CONNECTION) ==
+(portstatus USB_PORT_STAT_CONNECTION))
I don't know if there is any corner case when the above check
will always fail and so it will always wait a maximal delay time.
Are those registers that identical, or can there be differences?
+break;
+
+mdelay(100);
+} while (get_timer(start) CONFIG_SYS_HZ * 10);
Is there any justification for the CONFIG_SYS_HZ * 10?
I would be much more fine with this patch if there were any
(even just test based * 2) reason for that number.
Not really. Just a practical test.
Ok. good. can we please have a comment saying that this value
is based on observations? Thanks!
You can add my ack along with the comment in v3.
Thanks for the patch!
Thanks Igor
Marek, I am waiting for your comments now, if any
-Vipin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] spi/arm-pl022: Add support for ARM PL022 spi controller
From: Armando Visconti armando.visco...@st.com
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 824d357..3a4e4b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..ba018b8
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __weak spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init()
+{
+ /* do nothing */
+}
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022), that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ struct pl022
Re: [U-Boot] [PATCH v2] imls: Add support to list images in NAND device
On 12/13/2012 1:54 AM, Wolfgang Denk wrote: Dear Vipin Kumar, In messagedba14c4ffef38a108f75342968bcd9ce2b75c4c7.1355303894.git.vipin.ku...@st.com you wrote: imls does not list the images in NAND devices. This patch implements this support for legacy type images. ... -static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static void do_imls_flash(void) Why is this void? Should we not return error codes? Or at least be able to? Yes, I agree. I would change this +static void do_imls_nand(void) Ditto. Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] imls: Add support to list images in NAND device
[...]
README | 3 +-
common/cmd_bootm.c | 133
-
2 files changed, 134 insertions(+), 2 deletions(-)
diff --git a/README b/README
index 2077c3b..ec5c31e 100644
--- a/README
+++ b/README
@@ -831,7 +831,8 @@ The following options need to be configured:
CONFIG_CMD_I2C * I2C serial bus support
CONFIG_CMD_IDE * IDE harddisk support
CONFIG_CMD_IMIiminfo
- CONFIG_CMD_IMLS List all found images
+ CONFIG_CMD_IMLS List all images found in flash
+ CONFIG_CMD_IMLS_NAND List all images found in NAND
device
s/in flash/in NOR flash/
s/in NAND device/in NAND flash/
OK
Or better, just have one CONFIG_CMD_IMLS and have it operate on
whatever flash types are configured into U-Boot.
I didn't do it because until now the CONFIG_CMD_IMLS config is tightly
bound with flash only eg config_cmd_default.h enables CONFIG_CMD_IMLS
only when CONFIG_SYS_NO_FLASH is not defined. I thought there might be
other places as well
CONFIG_CMD_IMMAP* IMMR dump support
CONFIG_CMD_IMPORTENV* import an environment
CONFIG_CMD_INI * import data from an ini file
into the env
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index d256ddf..8ee562a 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -83,6 +83,9 @@ extern flash_info_t flash_info[]; /* info for FLASH
chips */
static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[]);
#endif
+#includelinux/err.h
+#includenand.h
+
#ifdef CONFIG_SILENT_CONSOLE
static void fixup_silent_linux(void);
#endif
@@ -1175,7 +1178,7 @@ U_BOOT_CMD(
/* imls - list all images found in flash */
/***/
#if defined(CONFIG_CMD_IMLS)
-static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
+static void do_imls_flash(void)
s/flash/nor/
OK
{
flash_info_t *info;
int i, j;
@@ -1224,6 +1227,134 @@ next_sector:;
}
next_bank:;
}
+}
+#endif
+
+#if defined(CONFIG_CMD_IMLS_NAND)
+static void do_imls_nand(void)
+{
+ nand_info_t *nand;
+ int nand_dev = nand_curr_device;
+ size_t read_size;
+ loff_t off;
+ u8 buffer[512];
Why 512?
Basically there are 2 image types supported as of today.
* Legacy: 64 byte header
* FIT: 512 byte header
After reading the first 512 bytes from each block of NAND, we try to
validate the header and only if the header validation is successful, we
malloc the space for the whole image and read the image into it
+ const image_header_t *header = (const image_header_t *)buffer;
+
+ /* the following commands operate on the current device */
+ if (nand_dev 0 || nand_dev= CONFIG_SYS_MAX_NAND_DEVICE) {
+ puts(\nNo NAND devices available\n);
+ return;
+ }
following commands, plural?
I think its a copy paste error
And this command seems to operate on all devices, not just the current
one.
Yes, that's why a copy paste
+
+ printf(\n);
+
+ for (nand_dev = 0; nand_dev CONFIG_SYS_MAX_NAND_DEVICE;
nand_dev++) {
+
Don't put a blank line inside braces at the beginning/end of blocks.
OK
+ nand =nand_info[nand_dev];
+ if (!nand-name || !nand-size)
+ continue;
+
+ for (off = 0; off nand-size; off += nand-erasesize)
{
+ int ret;
+ void *imgdata;
+
+ if (nand_block_isbad(nand, off))
+ goto next_block;
+
+ read_size = sizeof(buffer);
+
+ ret = nand_read(nand, off,read_size, buffer);
+ if (ret 0 ret != -EUCLEAN)
+ goto next_block;
s/goto next_block/continue/
hmmm, OK.
I copied the original code ie for listing images from nor flash.
Should I also correct it !!
+ header = (const image_header_t *)buffer;
+
+ switch (genimg_get_format(buffer)) {
+ case IMAGE_FORMAT_LEGACY:
+ if (!image_check_hcrc(header))
+ goto next_block;
+
+ read_size =
image_get_image_size(header);
+
+ imgdata = malloc(read_size);
+ if (!imgdata) {
+ printf(Not able to list all
images \
+ (Low memory)\n);
Don't line-wrap error strings.
80 column ?
+ goto next_block;
+ }
+
+ ret =
Re: [U-Boot] [PATCH v2] usbh/ehci: Increase timeout for enumeration
On 12/12/2012 4:55 PM, Marek Vasut wrote:
Dear Vipin Kumar,
+ ulong start = get_timer(0);
+
+ do {
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret 0) {
+ USB_HUB_PRINTF(get_port_status failed\n);
+ break;
+ }
+
+ portstatus = le16_to_cpu(portsts-wPortStatus);
+ portchange = le16_to_cpu(portsts-wPortChange);
+
+ if ((portchange USB_PORT_STAT_C_CONNECTION) ==
+ (portstatus USB_PORT_STAT_CONNECTION))
I don't know if there is any corner case when the above check
will always fail and so it will always wait a maximal delay time.
Are those registers that identical, or can there be differences?
+ break;
+
+ mdelay(100);
+ } while (get_timer(start) CONFIG_SYS_HZ * 10);
Is there any justification for the CONFIG_SYS_HZ * 10?
I would be much more fine with this patch if there were any
(even just test based * 2) reason for that number.
Not really. Just a practical test.
Marek, can I have comments from you as well
Sorry, I'm really busy these days. I went through it and I see Igor still has
some comment. Just fix that one and I'm good.
Thanks marek, I would send a v3 soon
Best regards,
Marek Vasut
.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] usbh/ehci: Increase timeout for enumeration
The current logic reads the port status just once after usb_hub_power_on and
expects the portstatus and portchange to report the connection status
immediately and correctly.
Few pen drives are not able to report both of them immediately ie. those pens
report the connection change but not the connected state after the first read.
This opportunity once lost is gone for ever because the u-boot, unlike linux or
any other OS, works in polling mode.
This patch modifies the logic to read the port status continuously until the
portstatus and portchange both report a connection change as well as a connected
state or no connection change and no connection. This logic is placed in a
timeout of 10 sec. At the end of it, the pen drive would have either reported a
ONE or a ZERO in bit 1 of portstatus as well as portchange.
It enhances the set of pen drives which can eventually be detected by u-boot
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
Hello Marek, Igor,
I found another way to handle it. Please let me know if it is OK from the USB
stack poit of view. The fact is that a few pens do not report a connected status
in portstatus while they report a connection change in portchange after a
usb_hub_power_on.
In this patch, I have tried to compare the connection bit from portstatus and
portchange for a timeout of 10 seconds. The situation is asumed to be stable
once both of them report the same. This seems to have increased the set of pens
supported by u-boot without any apparent side effect
Please let me know if this is OK from your side
Regards
Vipin
common/usb_hub.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index e4a1201..3a66b0e 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -396,14 +396,29 @@ static int usb_hub_configure(struct usb_device *dev)
for (i = 0; i dev-maxchild; i++) {
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
+ int ret;
+ ulong start = get_timer(0);
+
+ do {
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret 0) {
+ USB_HUB_PRINTF(get_port_status failed\n);
+ break;
+ }
+
+ portstatus = le16_to_cpu(portsts-wPortStatus);
+ portchange = le16_to_cpu(portsts-wPortChange);
+
+ if ((portchange USB_PORT_STAT_C_CONNECTION) ==
+ (portstatus USB_PORT_STAT_CONNECTION))
+ break;
+
+ mdelay(100);
+ } while (get_timer(start) CONFIG_SYS_HZ * 10);
- if (usb_get_port_status(dev, i + 1, portsts) 0) {
- USB_HUB_PRINTF(get_port_status failed\n);
+ if (ret 0)
continue;
- }
- portstatus = le16_to_cpu(portsts-wPortStatus);
- portchange = le16_to_cpu(portsts-wPortChange);
USB_HUB_PRINTF(Port %d Status %X Change %X\n,
i + 1, portstatus, portchange);
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] misc/crypto: Add support for C3
On 12/6/2012 5:26 PM, Stefan Roese wrote:
On 12/06/2012 10:15 AM, Vipin Kumar wrote:
C3 is a cryptographic controller which is used by the SPL when DDR ECC support
is enabled.
Basically, the DDR ECC feature requires the initialization of ECC values before
the DDR can actually be used. To accomplish this, the complete on board DDR is
initialized with zeroes. This initialization can be done using
* CPU
* CPU (with Dcache enabled)
* C3
The current SPL code uses C3 because the initialization using the CPU is slow
and we do not have enough memory in SPL to initialize page tables required to
enable MMU and Dcache
Signed-off-by: Vipin Kumarvipin.ku...@st.com
Reviewed-by: Shiraz Hashimshiraz.has...@st.com
---
drivers/misc/Makefile | 1 +
drivers/misc/c3.c | 122 ++
include/c3.h | 63 ++
I'm not so sure about the name of this driver and its location in
drivers/misc. Is C3 a generic crypto IP name? On which devices/SoC's
is it currently implemented? Perhaps the name should be a little less
It is an ST peripheral and is used in spear SoCs and could be used in
other ST SoCs
generic, e.g. spear-c3 or st-crypto-c3...?
hmm, ok. I can rename it to st-crypto-c3
And if this driver only supports this memory fill operation for some
ST SoC (SPEAr?), then its perhaps better located in arch/arm/ right now.
Not sure.
You mean arch/arm/cpu/armv7/spear13xx/ ?
Is the drivers/misc a special place. Why not here ?
Still some review comments below.
3 files changed, 186 insertions(+)
create mode 100644 drivers/misc/c3.c
create mode 100644 include/c3.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 9fac190..3ef8177 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libmisc.o
COBJS-$(CONFIG_ALI152X) += ali512x.o
+COBJS-$(CONFIG_C3) += c3.o
COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
diff --git a/drivers/misc/c3.c b/drivers/misc/c3.c
new file mode 100644
index 000..5f1eaee
--- /dev/null
+++ b/drivers/misc/c3.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2012
+ * ST Micoelectronics Pvt. Ltd.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#includecommon.h
+#includec3.h
+#includeerrno.h
+#includeasm/io.h
+#includeasm/arch/hardware.h
+
+static unsigned long c3_mem_xlate(void *addr)
+{
+
Remove empty line.
+ if (((ulong)addr C3_INT_MEM_BASE_ADDR) || \
The \ is not necessary, or?
+ ((ulong)addr= (C3_INT_MEM_BASE_ADDR + C3_INT_MEM_SIZE)))
+ return (ulong)addr;
+
+ return (unsigned long)addr - C3_INT_MEM_BASE_ADDR +
+ C3_LOCAL_MEM_ADDR;
+}
+
+int c3_init(void)
+{
+ if (readl(C3_ID0_SCR) != C3_ID0_DEF_RDY_VAL)
+ writel(C3_ID0_SCR_RST, C3_ID0_SCR);
Please use structs to access the SoC registers, see below (.h).
+
+ if (readl(C3_MOVE_CHANNEL_ID) == C3_MOVE_CHANNEL_ID_VAL)
+ return -EINVAL;
+
+ writel(C3_HIF_MCR_ENB_INT_MEM, C3_HIF_MCR);
+ writel(C3_LOCAL_MEM_ADDR, C3_HIF_MBAR);
+
+ return 0;
+}
+
+static int c3_run(void *prog_start)
+{
+ writel(c3_mem_xlate(prog_start), C3_ID0_IP);
+
+ while ((readl(C3_ID0_SCR) C3_ID0_STATE_MASK) == C3_ID0_STATE_RUN)
+ ;
+
+ if ((readl(C3_ID0_SCR) C3_ID0_STATE_MASK) != C3_ID0_STATE_IDLE) {
+ /* If not back to idle an error occured */
+ writel(C3_ID0_SCR_RST, C3_ID0_SCR);
+
+ /* Set internal access to run c3 programs */
+ writel(C3_HIF_MCR_ENB_INT_MEM, C3_HIF_MCR);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int c3_move(void *dest, void *src, int cnt, int optype, int opdata)
+{
+ unsigned long *c3_prog;
+ int ret = 0;
+
+ /* 3.b Prepare program */
+ c3_prog = (unsigned long *)C3_INT_MEM_BASE_ADDR;
+
+ /* 3.b.i. Mov init */
+ c3_prog[0] = C3_CMD_MOVE_INIT;
+ c3_prog[1] = opdata;
+
+ /* 3.b.ii. Mov data */
+ c3_prog[2] = C3_CMD_MOVE_DATA + cnt + optype;
+ c3_prog[3
Re: [U-Boot] [PATCH resend 2/2] arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P
On 12/6/2012 4:56 PM, Stefan Roese wrote:
On 12/06/2012 10:56 AM, Vipin Kumar wrote:
snip
+#ifdef CONFIG_BOOT_PARAMS_P
+ /* Boot params passed to Linux */
+ gd-bd-bi_boot_params = CONFIG_BOOT_PARAMS_P;
+#endif
Again an ugly #ifdef. Why not something like this instead:
Define a default earlier in the code (is 0x100 the best default?):
#ifndef CONFIG_BOOT_PARAMS_P
#define CONFIG_BOOT_PARAMS_P0x100
#endif
then here just:
/* Boot params passed to Linux */
gd-bd-bi_boot_params = CONFIG_BOOT_PARAMS_P;
This would mean that I am forcing the boot params at 0x100 for all
boards. Is that the right thing to do
Off-course, all of them might already be initializing
gd-bd-bi_boot_params on their own
Yes. Before or after this initialization? Will the board_init code
overwrite this one here?
board_init would overwrite it as it is called after relocation from
board_init_r while this routine is called even before relocation
But I also think this could be confusing. The generic way to implement
this would be to remove *all* local board specific assignments of
gd-bd-bi_boot_params and define CONFIG_BOOT_PARAMS_P in their board
config header. But this will be quite intrusive and could be error-prone.
Yes, that is what I also thought..
Originally, I based my patch on the CONFIG_MACH_TYPE handling. If it is
defined the board need not initialize gd-bd-bi_arch_number
Can you please suggest what is the best way here. Wolfgang, Albert ?
without the #ifdef.
+
addr_sp -= sizeof (gd_t);
id = (gd_t *) addr_sp;
debug(Reserving %zu Bytes for Global Data at: %08lx\n,
@@ -468,6 +473,13 @@ void board_init_f(ulong bootflag)
static char *failed = *** failed ***\n;
#endif
+static int __def_board_init(bd_t *bis)
+{
+ return -1;
Is -1 a good value to return as default board_init()?
The return value is not checked as of today
Then I suggest to use 0.
OK. Accepted
Thanks,
Stefan
.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend 1/2] u-boot/spl: Add u-boot-spl.img to u-boot targets
On 12/6/2012 5:38 PM, Stefan Roese wrote: On 12/06/2012 10:29 AM, Vipin Kumar wrote: Signed-off-by: Vipin Kumarvipin.ku...@st.com Is this new build target really needed? Please take a look at the recently added/renamed targets (e.g. u-boot-with-spl.bin or u-boot-img.bin). Hmm, this is an mkimage version of spl binary. This mkimage header is detected by the BootROM in spear devices for loading and booting the SPL binary If this does not fit, then please add a short description about this new build target and which SoC's need it and why. You mean add a short description in commit log or in README ? Vipin Thanks, STefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] usbh/ehci: Increase timeout for enumeration
On 12/7/2012 3:48 PM, Igor Grinberg wrote:
On 12/07/12 12:03, Igor Grinberg wrote:
On 12/07/12 10:58, Vipin Kumar wrote:
The current logic reads the port status just once after usb_hub_power_on and
expects the portstatus and portchange to report the connection status
immediately and correctly.
Few pen drives are not able to report both of them immediately ie. those pens
report the connection change but not the connected state after the first read.
This opportunity once lost is gone for ever because the u-boot, unlike linux or
any other OS, works in polling mode.
This patch modifies the logic to read the port status continuously until the
portstatus and portchange both report a connection change as well as a connected
state or no connection change and no connection. This logic is placed in a
timeout of 10 sec. At the end of it, the pen drive would have either reported a
ONE or a ZERO in bit 1 of portstatus as well as portchange.
It enhances the set of pen drives which can eventually be detected by u-boot
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
Hello Marek, Igor,
I found another way to handle it. Please let me know if it is OK from the USB
stack poit of view. The fact is that a few pens do not report a connected status
in portstatus while they report a connection change in portchange after a
usb_hub_power_on.
In this patch, I have tried to compare the connection bit from portstatus and
portchange for a timeout of 10 seconds. The situation is asumed to be stable
once both of them report the same. This seems to have increased the set of pens
supported by u-boot without any apparent side effect
Please let me know if this is OK from your side
Basically, this one looks fine, although I have two minor concerns below.
Regards
Vipin
common/usb_hub.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index e4a1201..3a66b0e 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -396,14 +396,29 @@ static int usb_hub_configure(struct usb_device *dev)
for (i = 0; i dev-maxchild; i++) {
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
+ int ret;
+ ulong start = get_timer(0);
+
+ do {
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret 0) {
+ USB_HUB_PRINTF(get_port_status failed\n);
+ break;
+ }
+
+ portstatus = le16_to_cpu(portsts-wPortStatus);
+ portchange = le16_to_cpu(portsts-wPortChange);
+
+ if ((portchange USB_PORT_STAT_C_CONNECTION) ==
+ (portstatus USB_PORT_STAT_CONNECTION))
I don't know if there is any corner case when the above check
will always fail and so it will always wait a maximal delay time.
Are those registers that identical, or can there be differences?
Never mind, my mistake, USB_PORT_STAT_C_CONNECTION and USB_PORT_STAT_CONNECTION
are the same bit in the register.
+ break;
+
+ mdelay(100);
+ } while (get_timer(start) CONFIG_SYS_HZ * 10);
Is there any justification for the CONFIG_SYS_HZ * 10?
I would be much more fine with this patch if there were any
(even just test based * 2) reason for that number.
Once you address this one, feel free to add:
Acked-by: Igor Grinberggrinb...@compulab.co.il
Thanks Igor, let me wait for Marek's comments also
- if (usb_get_port_status(dev, i + 1, portsts) 0) {
- USB_HUB_PRINTF(get_port_status failed\n);
+ if (ret 0)
continue;
- }
- portstatus = le16_to_cpu(portsts-wPortStatus);
- portchange = le16_to_cpu(portsts-wPortChange);
USB_HUB_PRINTF(Port %d Status %X Change %X\n,
i + 1, portstatus, portchange);
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend 1/2] u-boot/spl: Add u-boot-spl.img to u-boot targets
On 12/7/2012 4:14 PM, Stefan Roese wrote: On 12/07/2012 10:47 AM, Vipin Kumar wrote: On 12/6/2012 5:38 PM, Stefan Roese wrote: On 12/06/2012 10:29 AM, Vipin Kumar wrote: Signed-off-by: Vipin Kumarvipin.ku...@st.com Is this new build target really needed? Please take a look at the recently added/renamed targets (e.g. u-boot-with-spl.bin or u-boot-img.bin). Hmm, this is an mkimage version of spl binary. This mkimage header is detected by the BootROM in spear devices for loading and booting the SPL binary Yes, I remember this from the SPEAr600. I introduced a new build target for this: u-boot.spr. Take a look at the commit: Yes, I remember 94aebe6cc3111c7c9e3cd1311cc9793d01cc3ded Makefile: Add u-boot.spr build target (SPEAr) On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. Both images are created using mkimage (crc etc), so that the ROM bootloader can check its integrity. Padding needs to be done to the SPL image (with mkimage header) and not the binary. Otherwise the resulting image which is loaded/copied by the ROM bootloader to SRAM doesn't fit. The resulting image containing both U-Boot images is called u-boot.spr. Or does your patch only introduce the mkimage SPL image version? Yes, it introduces only mkimage SPL image version. This is necessary for a few booting options where we absolutely require a different SPL binary with an mkimage header Then please consolidate this with the u-boot.spr build target. You mean u-boot.spr can use this u-boot-spl.img. Yes, I will do that in v2 Thanks, Stefan . Vipin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend 1/7] mtd/st_smi: Clear error flags while initiating a fresh write
On 12/6/2012 1:07 PM, Stefan Roese wrote: On 12/06/2012 07:21 AM, Vipin Kumar wrote: SMI controller reports an error when the code tries to write on the flash area with Write Enable command not issued or the bank has come out of the write mode. This error is reported even with a fresh write once the ERF1 or ERF2 is set. Clear these flags while initiating a fresh write Signed-off-by: Vipin Kumarvipin.ku...@st.com --- drivers/mtd/st_smi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 7507e5d..fad4420 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -392,6 +392,8 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, return -1; } + writel(readl(smicntl-smi_sr) ~(ERF1 | ERF2),smicntl-smi_sr); Better use: clrbits_le32(smicntl-smi_sr, ERF1 | ERF2) Thanks.. I would use it and send a v2 Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend 0/7] mtd/st_smi: Add fixes for smi driver
On 12/6/2012 1:05 PM, Stefan Roese wrote: Hi Vipin, On 12/06/2012 07:21 AM, Vipin Kumar wrote: Hello, This patch-set adds simple fixes for smi driver used in spear devices. Modifications include - Add MTD support for smi driver - Write to flash in a tight loop - Alphabetically sort the list of devices - Avoid issuing multiple write enable commands PS: Wolfgang, Stefan, I am directing these to you as there is no direct maintainer of mtd in u-boot. I can add these in my pull-request once you review these patches Since I'm the CFI (NOR parallel) flash custodian, I can take these patches through my repository as well. If there is a dependency with some of your platforms patches, then the patches can go through your ST repo as well, after successful review. These patches do not have any dependency with the platform patches and they can go with your repository as well. Let me know if you plan to add these through your repo Vipin Reviewing in a minute... Thanks, Stefan . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend 7/7] mtd/st_smi: Add mtd support for smi
On 12/6/2012 1:32 PM, Stefan Roese wrote:
On 12/06/2012 07:21 AM, Vipin Kumar wrote:
This patch adds mtd device support for smi devices
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
drivers/mtd/st_smi.c | 167 ++-
1 file changed, 165 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 0e529a4..4d1a6bd 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -24,6 +24,7 @@
#includecommon.h
#includeflash.h
#includelinux/err.h
+#includelinux/mtd/mtd.h
#includelinux/mtd/st_smi.h
#includeasm/io.h
@@ -37,6 +38,14 @@ static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] =
CONFIG_SYS_FLASH_ADDR_BASE;
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+#if defined(CONFIG_MTD_DEVICE)
+/* MTD interface for SMI devices */
+static struct mtd_info smi_mtd_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static char smi_mtd_names[CONFIG_SYS_MAX_FLASH_BANKS][16];
+
+static int smi_mtd_init(void);
+#endif
+
/* data structure to maintain flash ids from different vendors */
struct flash_device {
char *name;
@@ -482,7 +491,9 @@ unsigned long flash_init(void)
{
unsigned long size = 0;
int i, j;
-
+#if defined(CONFIG_MTD_DEVICE)
+ int error;
+#endif
Hmm, I don't like all those new #ifdef's. Can't we instead add a dummy
smi_mtd_init() functions for the non-MTD version? Something like:
#if defined(CONFIG_MTD_DEVICE)
/* MTD interface for SMI devices */
static struct mtd_info smi_mtd_info[CONFIG_SYS_MAX_FLASH_BANKS];
static char smi_mtd_names[CONFIG_SYS_MAX_FLASH_BANKS][16];
static int smi_mtd_init(void);
#else
static int smi_mtd_init(void)
{
return 0;
}
#endif
What do you think?
I agree. That would be more readable. I would send out a v2
Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/7] mtd/st_smi: Add fixes for smi driver
Modifications in v2 (Review comments incorporation) - Use setbits_le32 and clrbits_le32 whereever applicable in patch-set - Define smi_mtd_init() routine irrespective of CONFIG_MTD_DEVICE Modifications in v1 - Add MTD support for smi driver - Write to flash in a tight loop - Alphabetically sort the list of devices - Avoid issuing multiple write enable commands Armando Visconti (1): mtd/st_smi: Add support for Micron N25Q128 Flash Vipin Kumar (6): mtd/st_smi: Clear error flags while initiating a fresh write mtd/st_smi: Rearrange the supported devices in alphabetical order mtd/st_smi: Avoid issuing multiple WE commands mtd/st_smi: Write to flash in a tight loop mtd/st_smi: Use page sizes respective to flash mtd/st_smi: Add mtd support for smi drivers/mtd/st_smi.c | 260 ++--- include/linux/mtd/st_smi.h | 1 - 2 files changed, 223 insertions(+), 38 deletions(-) -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/7] mtd/st_smi: Clear error flags while initiating a fresh write
SMI controller reports an error when the code tries to write on the flash area with Write Enable command not issued or the bank has come out of the write mode. This error is reported even with a fresh write once the ERF1 or ERF2 is set. Clear these flags while initiating a fresh write Signed-off-by: Vipin Kumar vipin.ku...@st.com --- drivers/mtd/st_smi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 7507e5d..63b10fc 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -392,6 +392,8 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, return -1; } + clrbits_le32(smicntl-smi_sr, ERF1 | ERF2); + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) return -EBUSY; -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/7] mtd/st_smi: Rearrange the supported devices in alphabetical order
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
drivers/mtd/st_smi.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 63b10fc..30bfa3f 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -62,24 +62,24 @@ struct flash_device {
* Currently the erase_cmd field is not used in this driver.
*/
static struct flash_device flash_devices[] = {
- FLASH_ID(st m25p16 , 0xd8, 0x00152020, 0x100, 0x1, 0x20),
- FLASH_ID(st m25p32 , 0xd8, 0x00162020, 0x100, 0x1, 0x40),
- FLASH_ID(st m25p64 , 0xd8, 0x00172020, 0x100, 0x1, 0x80),
- FLASH_ID(st m25p128, 0xd8, 0x00182020, 0x100, 0x4, 0x100),
+ FLASH_ID(sp s25fl004 , 0xd8, 0x00120201, 0x100, 0x1, 0x8),
+ FLASH_ID(sp s25fl008 , 0xd8, 0x00130201, 0x100, 0x1, 0x10),
+ FLASH_ID(sp s25fl016 , 0xd8, 0x00140201, 0x100, 0x1, 0x20),
+ FLASH_ID(sp s25fl032 , 0xd8, 0x00150201, 0x100, 0x1, 0x40),
+ FLASH_ID(sp s25fl064 , 0xd8, 0x00160201, 0x100, 0x1, 0x80),
FLASH_ID(st m25p05 , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x1),
FLASH_ID(st m25p10 , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x2),
+ FLASH_ID(st m25p16 , 0xd8, 0x00152020, 0x100, 0x1, 0x20),
FLASH_ID(st m25p20 , 0xd8, 0x00122020, 0x100, 0x1, 0x4),
+ FLASH_ID(st m25p32 , 0xd8, 0x00162020, 0x100, 0x1, 0x40),
FLASH_ID(st m25p40 , 0xd8, 0x00132020, 0x100, 0x1, 0x8),
+ FLASH_ID(st m25p64 , 0xd8, 0x00172020, 0x100, 0x1, 0x80),
FLASH_ID(st m25p80 , 0xd8, 0x00142020, 0x100, 0x1, 0x10),
+ FLASH_ID(st m25p128, 0xd8, 0x00182020, 0x100, 0x4, 0x100),
FLASH_ID(st m45pe10, 0xd8, 0x00114020, 0x100, 0x1, 0x2),
FLASH_ID(st m45pe20, 0xd8, 0x00124020, 0x100, 0x1, 0x4),
FLASH_ID(st m45pe40, 0xd8, 0x00134020, 0x100, 0x1, 0x8),
FLASH_ID(st m45pe80, 0xd8, 0x00144020, 0x100, 0x1, 0x10),
- FLASH_ID(sp s25fl004 , 0xd8, 0x00120201, 0x100, 0x1, 0x8),
- FLASH_ID(sp s25fl008 , 0xd8, 0x00130201, 0x100, 0x1, 0x10),
- FLASH_ID(sp s25fl016 , 0xd8, 0x00140201, 0x100, 0x1, 0x20),
- FLASH_ID(sp s25fl032 , 0xd8, 0x00150201, 0x100, 0x1, 0x40),
- FLASH_ID(sp s25fl064 , 0xd8, 0x00160201, 0x100, 0x1, 0x80),
FLASH_ID(mac 25l512, 0xd8, 0x001020C2, 0x010, 0x1, 0x1),
FLASH_ID(mac 25l1005 , 0xd8, 0x001120C2, 0x010, 0x1, 0x2),
FLASH_ID(mac 25l2005 , 0xd8, 0x001220C2, 0x010, 0x1, 0x4),
@@ -91,7 +91,7 @@ static struct flash_device flash_devices[] = {
FLASH_ID(mac 25l3205 , 0xd8, 0x001620C2, 0x100, 0x1, 0x40),
FLASH_ID(mac 25l3205a , 0xd8, 0x001620C2, 0x100, 0x1, 0x40),
FLASH_ID(mac 25l6405 , 0xd8, 0x001720C2, 0x100, 0x1, 0x80),
- FLASH_ID(wbd w25q128 , 0xd8, 0x001840EF, 0x100, 0x1, 0x100),
+ FLASH_ID(wbd w25q128 , 0xd8, 0x001840EF, 0x100, 0x1, 0x100),
};
/*
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/7] mtd/st_smi: Add support for Micron N25Q128 Flash
From: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Signed-off-by: Armando Visconti armando.visco...@st.com
Acked-by: Stefan Roese s...@denx.de
---
drivers/mtd/st_smi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 30bfa3f..99b9576 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -91,6 +91,7 @@ static struct flash_device flash_devices[] = {
FLASH_ID(mac 25l3205 , 0xd8, 0x001620C2, 0x100, 0x1, 0x40),
FLASH_ID(mac 25l3205a , 0xd8, 0x001620C2, 0x100, 0x1, 0x40),
FLASH_ID(mac 25l6405 , 0xd8, 0x001720C2, 0x100, 0x1, 0x80),
+ FLASH_ID(mcr n25q128 , 0xd8, 0x0018BA20, 0x100, 0x1, 0x100),
FLASH_ID(wbd w25q128 , 0xd8, 0x001840EF, 0x100, 0x1, 0x100),
};
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/7] mtd/st_smi: Avoid issuing multiple WE commands
At the start of an smi_write, if the destination address is page aligned, the
Write Enable command is getting issued twice. This patch fixes it by keeping a
flag.
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
drivers/mtd/st_smi.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 99b9576..6c3e594 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -374,7 +374,7 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
u8 *src_addr8 = (u8 *)src_addr;
u8 *dst_addr8 = (u8 *)dst_addr;
int banknum;
- int i;
+ int i, issue_we;
switch (bank_addr) {
case SMIBANK0_BASE:
@@ -394,19 +394,16 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
}
clrbits_le32(smicntl-smi_sr, ERF1 | ERF2);
-
- if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
- return -EBUSY;
+ issue_we = 1;
/* Set SMI in Hardware Mode */
writel(readl(smicntl-smi_cr1) ~SW_MODE, smicntl-smi_cr1);
- if (smi_write_enable(banknum))
- return -EIO;
-
/* Perform the write command */
for (i = 0; i length; i += 4) {
- if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
+ if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
+ issue_we = 0;
+
if (smi_wait_till_ready(banknum,
CONFIG_SYS_FLASH_WRITE_TOUT))
return -EBUSY;
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/7] mtd/st_smi: Write to flash in a tight loop
The write loop is checking for dest_addr alignment with page size. This
sometimes leads to smi controller coming out of write mode and eventually the
next write failing with ERF1 being set.
To avoid this, write to flash in a tight loop and write bytewise to also support
not word aligned data bytes to be written. Additionally, enable burst mode
before this loop so that the controller does not deselect the chip if the
transfer is finished.
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/mtd/st_smi.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 6c3e594..5f67807 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -368,13 +368,11 @@ static int smi_sector_erase(flash_info_t *info, unsigned
int sector)
*
* Write to SMI flash
*/
-static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
+static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
unsigned int length, ulong bank_addr)
{
- u8 *src_addr8 = (u8 *)src_addr;
- u8 *dst_addr8 = (u8 *)dst_addr;
int banknum;
- int i, issue_we;
+ int issue_we;
switch (bank_addr) {
case SMIBANK0_BASE:
@@ -400,7 +398,10 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
writel(readl(smicntl-smi_cr1) ~SW_MODE, smicntl-smi_cr1);
/* Perform the write command */
- for (i = 0; i length; i += 4) {
+ while (length) {
+ int k;
+ unsigned int wlen = min(SFLASH_PAGE_SIZE, length);
+
if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
issue_we = 0;
@@ -412,19 +413,14 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
return -EIO;
}
- if (length 4) {
- int k;
+ setbits_le32(smicntl-smi_cr1, WB_MODE);
- /*
-* Handle special case, where length 4 (redundant env)
-*/
- for (k = 0; k length; k++)
- *dst_addr8++ = *src_addr8++;
- } else {
- /* Normal 32bit write */
+ for (k = 0; k wlen; k++)
*dst_addr++ = *src_addr++;
- }
+ clrbits_le32(smicntl-smi_cr1, WB_MODE);
+
+ length -= wlen;
if ((readl(smicntl-smi_sr) (ERF1 | ERF2)))
return -EIO;
}
@@ -448,8 +444,8 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
*/
int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
{
- return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
-length, info-start[0]);
+ return smi_write(src, (unsigned char *)dest_addr, length,
+ info-start[0]);
}
/*
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 7/7] mtd/st_smi: Add mtd support for smi
This patch adds mtd device support for smi devices
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/mtd/st_smi.c | 167 ++-
1 file changed, 166 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 0ed6c0d..c4780c3 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -24,6 +24,7 @@
#include common.h
#include flash.h
#include linux/err.h
+#include linux/mtd/mtd.h
#include linux/mtd/st_smi.h
#include asm/io.h
@@ -37,6 +38,14 @@ static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] =
CONFIG_SYS_FLASH_ADDR_BASE;
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+#if defined(CONFIG_MTD_DEVICE)
+/* MTD interface for SMI devices */
+static struct mtd_info smi_mtd_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static char smi_mtd_names[CONFIG_SYS_MAX_FLASH_BANKS][16];
+#endif
+
+static int smi_mtd_init(void);
+
/* data structure to maintain flash ids from different vendors */
struct flash_device {
char *name;
@@ -482,6 +491,7 @@ unsigned long flash_init(void)
{
unsigned long size = 0;
int i, j;
+ int error;
smi_init();
@@ -498,6 +508,10 @@ unsigned long flash_init(void)
}
+ error = smi_mtd_init();
+ if (error 0)
+ return 0;
+
return size;
}
@@ -599,4 +613,155 @@ int flash_erase(flash_info_t *info, int s_first, int
s_last)
puts( done\n);
return rcode;
}
-#endif
+
+#if defined(CONFIG_MTD_DEVICE)
+static int smi_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ flash_info_t *fi = mtd-priv;
+ size_t a_start = fi-start[0] + instr-addr;
+ size_t a_end = a_start + instr-len;
+ int s_first = -1;
+ int s_last = -1;
+ int error, sect;
+
+ for (sect = 0; sect fi-sector_count; sect++) {
+ if (a_start == fi-start[sect])
+ s_first = sect;
+
+ if (sect fi-sector_count - 1) {
+ if (a_end == fi-start[sect + 1]) {
+ s_last = sect;
+ break;
+ }
+ } else {
+ s_last = sect;
+ break;
+ }
+ }
+
+ if (s_first = 0 s_first = s_last) {
+ instr-state = MTD_ERASING;
+
+ error = flash_erase(fi, s_first, s_last);
+ if (error) {
+ instr-state = MTD_ERASE_FAILED;
+ return -EIO;
+ }
+
+ instr-state = MTD_ERASE_DONE;
+ mtd_erase_callback(instr);
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int smi_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ flash_info_t *fi = mtd-priv;
+ u_char *f = (u_char *)(fi-start[0]) + from;
+
+ memcpy(buf, f, len);
+ *retlen = len;
+
+ return 0;
+}
+
+static int smi_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ flash_info_t *fi = mtd-priv;
+ u_long t = fi-start[0] + to;
+ int error;
+
+ error = write_buff(fi, (u_char *)buf, t, len);
+ if (!error) {
+ *retlen = len;
+ return 0;
+ }
+
+ return -EIO;
+}
+
+static void smi_mtd_sync(struct mtd_info *mtd)
+{
+ /*
+* This function should wait until all pending operations
+* finish. However this driver is fully synchronous, so
+* this function returns immediately
+*/
+}
+
+static int smi_mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ flash_info_t *fi = mtd-priv;
+
+ flash_protect(FLAG_PROTECT_SET, fi-start[0] + ofs,
+ fi-start[0] + ofs + len - 1, fi);
+ return 0;
+}
+
+static int smi_mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ flash_info_t *fi = mtd-priv;
+
+ flash_protect(FLAG_PROTECT_CLEAR, fi-start[0] + ofs,
+ fi-start[0] + ofs + len - 1, fi);
+ return 0;
+}
+
+static int smi_mtd_init(void)
+{
+ struct flash_device *flash_device_p;
+ struct mtd_info *mtd;
+ flash_info_t *fi;
+ int i;
+
+ for (i = 0; i CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ fi = flash_info[i];
+
+ if (!fi-size)
+ continue;
+
+ flash_device_p = get_flash_device(fi-flash_id);
+ if (!flash_device_p)
+ return -EIO;
+
+ mtd = smi_mtd_info[i];
+
+ memset(mtd, 0, sizeof(struct mtd_info));
+
+ /* Uniform erase sizes for all sectors */
+ mtd-numeraseregions = 0;
+ mtd-erasesize = flash_device_p-sectorsize;
+
+ sprintf(smi_mtd_names[i], nor%d, i
[U-Boot] [PATCH v2 6/7] mtd/st_smi: Use page sizes respective to flash
The page size is a flash dependent property and the driver was using a macro in
place of page size. This patch uses the proper page size wrt the flash device
connected on board
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
drivers/mtd/st_smi.c | 41 +
include/linux/mtd/st_smi.h | 1 -
2 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 5f67807..0ed6c0d 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -96,6 +96,25 @@ static struct flash_device flash_devices[] = {
};
/*
+ * get_flash_device - Return flash_device pointer for a particular device id
+ * @id: Device id
+ *
+ * Return flash_device pointer for a particular device id
+ */
+static struct flash_device *get_flash_device(u32 id)
+{
+ struct flash_device *flash_dev_p = flash_devices[0];
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(flash_devices); i++, flash_dev_p++) {
+ if (flash_dev_p-device_id == id)
+ return flash_dev_p;
+ }
+
+ return NULL;
+}
+
+/*
* smi_wait_xfer_finish - Wait until TFF is set in status register
* @timeout:timeout in milliseconds
*
@@ -361,20 +380,27 @@ static int smi_sector_erase(flash_info_t *info, unsigned
int sector)
/*
* smi_write - Write to SMI flash
+ * @info: flash info structure
* @src_addr: source buffer
* @dst_addr: destination buffer
* @length: length to write in bytes
- * @bank: bank base address
*
* Write to SMI flash
*/
-static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
-unsigned int length, ulong bank_addr)
+static int smi_write(flash_info_t *info, unsigned char *src_addr,
+ unsigned char *dst_addr, unsigned int length)
{
+ struct flash_device *flash_device_p = get_flash_device(info-flash_id);
+ u32 page_size;
int banknum;
int issue_we;
- switch (bank_addr) {
+ if (!flash_device_p)
+ return -EIO;
+
+ page_size = flash_device_p-pagesize;
+
+ switch (info-start[0]) {
case SMIBANK0_BASE:
banknum = BANK0;
break;
@@ -400,9 +426,9 @@ static int smi_write(unsigned char *src_addr, unsigned char
*dst_addr,
/* Perform the write command */
while (length) {
int k;
- unsigned int wlen = min(SFLASH_PAGE_SIZE, length);
+ unsigned int wlen = min(page_size, length);
- if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
+ if (issue_we || (((ulong)(dst_addr) % page_size) == 0)) {
issue_we = 0;
if (smi_wait_till_ready(banknum,
@@ -444,8 +470,7 @@ static int smi_write(unsigned char *src_addr, unsigned char
*dst_addr,
*/
int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
{
- return smi_write(src, (unsigned char *)dest_addr, length,
- info-start[0]);
+ return smi_write(info, src, (unsigned char *)dest_addr, length);
}
/*
diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h
index 04f81ea..5837493 100644
--- a/include/linux/mtd/st_smi.h
+++ b/include/linux/mtd/st_smi.h
@@ -108,7 +108,6 @@ struct flash_dev {
ushort sector_count;
};
-#define SFLASH_PAGE_SIZE 0x100 /* flash page size */
#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */
#define WMODE_TOUT 15 /* write enable timeout(in ms) */
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend 0/7] mtd/st_smi: Add fixes for smi driver
On 12/6/2012 2:02 PM, Stefan Roese wrote: On 12/06/2012 09:19 AM, Vipin Kumar wrote: Since I'm the CFI (NOR parallel) flash custodian, I can take these patches through my repository as well. If there is a dependency with some of your platforms patches, then the patches can go through your ST repo as well, after successful review. These patches do not have any dependency with the platform patches and they can go with your repository as well. Let me know if you plan to add these through your repo Please push them to your repository after final review. OK Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] usbh/ehci: Increase timeout for enumeration
On 12/6/2012 1:06 PM, Igor Grinberg wrote: On 12/06/12 08:58, Vipin Kumar wrote: On 12/6/2012 12:17 PM, Igor Grinberg wrote: On 12/06/12 08:30, Vipin Kumar wrote: Few pen drives take longer than usual for enumeration. The u-boot unlike linux does not depend on interrupts and works in polling and timeout mode. This patch increases this timeout to increase the set of usb sticks that can be enumerated by u-boot Signed-off-by: Vipin Kumarvipin.ku...@st.com --- common/usb_hub.c | 27 ++- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/common/usb_hub.c b/common/usb_hub.c index e4a1201..24de9b7 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -393,17 +393,34 @@ static int usb_hub_configure(struct usb_device *dev) : no ); usb_hub_power_on(hub); +mdelay(1500); a 1.5 seconds? This looks like a huge overkill... Even for broken usb sticks... Yes, but we are not talking about performance in u-boot. And since we are working in a polling mode, we only have 1 chance to detect the pen-drive Of course we _do care_ about performance and 1.5 seconds is huge and not justified impact. OK Where is this value come from? Any real justification? Or just: lets make it huge... A bit of both. In routine usb_hub_power_on, we wait for max(pgood_delay, 100) ms for power to be stable. The pgood_delay can go max upto 512. This is because max u8 can carry is 255 and pgood_delay is usb_hub_power_on * 2 A few pens request the maximum possible delay and are not stable even after this. The new added delay is for power to be stable but I agree that this value is more experimental and I do not have a real written justification Also, as I understand from your commit message, this is needed only for broken pens... Yes Why should all others suffer? If this is really needed, I think you can do better then this. For example instead of waiting 1.5 seconds no meter what each time, make it a busy/wait loop (like you do below) and expire after a timeout. The problem is that I do not know what to wait on in that case. Can you point me to something Regards Vipin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/7] mtd/st_smi: Add fixes for smi driver
Hello Stefan, As you can see, I have added your Acked-by to patches 2, 3, 4, 6 The reset are still pending. If you can quickly close them, I can send a pull-request for these patches Thanks for a fast review Regards Vipin On 12/6/2012 2:17 PM, Vipin KUMAR wrote: Modifications in v2 (Review comments incorporation) - Use setbits_le32 and clrbits_le32 whereever applicable in patch-set - Define smi_mtd_init() routine irrespective of CONFIG_MTD_DEVICE Modifications in v1 - Add MTD support for smi driver - Write to flash in a tight loop - Alphabetically sort the list of devices - Avoid issuing multiple write enable commands Armando Visconti (1): mtd/st_smi: Add support for Micron N25Q128 Flash Vipin Kumar (6): mtd/st_smi: Clear error flags while initiating a fresh write mtd/st_smi: Rearrange the supported devices in alphabetical order mtd/st_smi: Avoid issuing multiple WE commands mtd/st_smi: Write to flash in a tight loop mtd/st_smi: Use page sizes respective to flash mtd/st_smi: Add mtd support for smi drivers/mtd/st_smi.c | 260 ++--- include/linux/mtd/st_smi.h | 1 - 2 files changed, 223 insertions(+), 38 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend] armv7/ltimer: Add support for local timer on armv7 cpus
Certain ARMV7 cpus eg. CortexA9 contains a local and a global timer within the
CPU core itself. This patch adds generic support for local timer.
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
arch/arm/cpu/armv7/Makefile | 11 ++-
arch/arm/cpu/armv7/ca9_ltimer.c | 152 ++
arch/arm/include/asm/ca9_ltimer.h | 40 ++
3 files changed, 199 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ca9_ltimer.c
create mode 100644 arch/arm/include/asm/ca9_ltimer.h
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..3ef01f6 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -27,15 +27,18 @@ LIB = $(obj)lib$(CPU).o
START := start.o
-COBJS += cache_v7.o
+COBJS-y+= cache_v7.o
-COBJS += cpu.o
-COBJS += syslib.o
+COBJS-y+= cpu.o
+COBJS-y+= syslib.o
+COBJS-$(CONFIG_ARMV7_CA9LTIMER) += ca9_ltimer.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
-SOBJS += lowlevel_init.o
+SOBJS-y+= lowlevel_init.o
endif
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/arm/cpu/armv7/ca9_ltimer.c b/arch/arm/cpu/armv7/ca9_ltimer.c
new file mode 100644
index 000..cbf1552
--- /dev/null
+++ b/arch/arm/cpu/armv7/ca9_ltimer.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/ca9_ltimer.h
+#include asm/arch/hardware.h
+
+#define READ_TIMER() readl(ca9_timer_p-count)
+
+static struct ca9_timer_regs *const ca9_timer_p =
+ (struct ca9_timer_regs *)CONFIG_ARMV7_LTIMER_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd-tbl
+#define lastdecgd-lastinc
+#define tickshzgd-timer_rate_hz
+#define ticksper10usec gd-tbu
+
+int timer_init(void)
+{
+ u32 prescaler, timertickshz;
+ /*
+* Genrally, CortexA9 MPUs are operating from 500MHz to 1500MHz which
+* means that CA9 local timer clock would be in the range of 250 MHz to
+* 750MHz.
+* Try to find a prescaler which can perfectly divide the local timer
+* clock. Take prescaler as 200 if nothing is found
+*/
+ for (prescaler = 255; prescaler 1; prescaler--) {
+ if (CONFIG_ARMV7_LTMR_CLK ==
+ (CONFIG_ARMV7_LTMR_CLK / prescaler) * prescaler)
+ break;
+ }
+
+ if (prescaler == 1)
+ prescaler = 200;
+ timertickshz = CONFIG_ARMV7_LTMR_CLK / prescaler;
+ ticksper10usec = timertickshz / (100 * 1000);
+ tickshz = timertickshz / CONFIG_SYS_HZ;
+
+ /* disable timers */
+ writel(((prescaler - 1) 8) | AUTO_RELOAD, ca9_timer_p-control);
+
+ /* load value for free running */
+ writel(FREE_RUNNING, ca9_timer_p-load);
+
+ /* auto reload, start timer */
+ setbits_le32(ca9_timer_p-control, TIMER_ENABLE);
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return (get_timer_masked() / tickshz) - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong tmo;
+ ulong start = get_timer_masked();
+ ulong rndoff;
+
+ rndoff = (usec % 10) ? 1 : 0;
+ tmo = ((usec / 10) + rndoff) * ticksper10usec;
+
+ while ((ulong) (get_timer_masked() - start) tmo);
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER();
+
+ if (now = lastdec) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + FREE_RUNNING - now
[U-Boot] [PATCH resend 1/2] u-boot/spl: Add u-boot-spl.img to u-boot targets
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
Makefile | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Makefile b/Makefile
index 8a04727..7f416f4 100644
--- a/Makefile
+++ b/Makefile
@@ -499,6 +499,13 @@ $(obj)u-boot.sb: $(obj)u-boot.bin
$(obj)spl/u-boot-spl.bin
elftosb -zdf $(ELFTOSB_TARGET-y) -c
$(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
-o $(obj)u-boot.sb
+$(obj)spl/u-boot-spl.img: $(obj)spl/u-boot-spl.bin
+ $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) \
+ -n $(shell sed -n -e 's/.*U_BOOT_SPL_VERSION//p'
$(VERSION_FILE) | \
+ sed -e 's/[ ]*$$/ for $(BOARD) board/') \
+ -d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img
+
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
# Both images are created using mkimage (crc etc), so that the ROM
# bootloader can check its integrity. Padding needs to be done to the
@@ -707,6 +714,9 @@ $(VERSION_FILE):
$(U_BOOT_VERSION) $${localvers} ; \
printf '#define U_BOOT_VERSION U-Boot %s%s\n' \
$(U_BOOT_VERSION) $${localvers} ; \
+ printf '#define U_BOOT_SPL_VERSION %s %s%s\n' \
+ $(if
$(CONFIG_SPL_IMAGENAME),$(CONFIG_SPL_IMAGENAME),U-Boot SPL) \
+ $(U_BOOT_VERSION) $${localvers} ; \
) $@.tmp
@( printf '#define CC_VERSION_STRING %s\n' \
'$(shell $(CC) --version | head -n 1)' ) $@.tmp
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 2/2] arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P
A lot of ARM boards are using board_init routine just to initialize boot_params
variable in the global data structure.
This patch lets the board config files to define a CONFIG_BOOT_PARAMS_P option
which is assigned to gd-bd-bi_boot_params automatically
Consequently, many board_init routines would not be required in the respective
board directories and a weak definition becomes necessary before their removal
from the code.
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
README | 6 ++
arch/arm/lib/board.c | 12
2 files changed, 18 insertions(+)
diff --git a/README b/README
index 037513a..2077c3b 100644
--- a/README
+++ b/README
@@ -550,6 +550,12 @@ The following options need to be configured:
in a single configuration file and the machine type is
runtime discoverable, do not have to use this setting.
+ CONFIG_BOOT_PARAMS_P[relevant for ARM only]
+
+ This config option can provide a way to initialize
+ bi_boot_params from the u-boot infrastructure itself. The
+ board still has the option to override it in board_init routine
+
- vxWorks boot parameters:
bootvx constructs a valid bootline using the following
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 92cad9a..fa161b8 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -399,6 +399,11 @@ void board_init_f(ulong bootflag)
gd-bd-bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
#endif
+#ifdef CONFIG_BOOT_PARAMS_P
+ /* Boot params passed to Linux */
+ gd-bd-bi_boot_params = CONFIG_BOOT_PARAMS_P;
+#endif
+
addr_sp -= sizeof (gd_t);
id = (gd_t *) addr_sp;
debug(Reserving %zu Bytes for Global Data at: %08lx\n,
@@ -468,6 +473,13 @@ void board_init_f(ulong bootflag)
static char *failed = *** failed ***\n;
#endif
+static int __def_board_init(bd_t *bis)
+{
+ return -1;
+}
+
+int board_init(void) __attribute__((weak, alias(__def_board_init)));
+
/*
*
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend] misc/crypto: Add support for C3
C3 is a cryptographic controller which is used by the SPL when DDR ECC support
is enabled.
Basically, the DDR ECC feature requires the initialization of ECC values before
the DDR can actually be used. To accomplish this, the complete on board DDR is
initialized with zeroes. This initialization can be done using
* CPU
* CPU (with Dcache enabled)
* C3
The current SPL code uses C3 because the initialization using the CPU is slow
and we do not have enough memory in SPL to initialize page tables required to
enable MMU and Dcache
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Reviewed-by: Shiraz Hashim shiraz.has...@st.com
---
drivers/misc/Makefile | 1 +
drivers/misc/c3.c | 122 ++
include/c3.h | 63 ++
3 files changed, 186 insertions(+)
create mode 100644 drivers/misc/c3.c
create mode 100644 include/c3.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 9fac190..3ef8177 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libmisc.o
COBJS-$(CONFIG_ALI152X) += ali512x.o
+COBJS-$(CONFIG_C3) += c3.o
COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
diff --git a/drivers/misc/c3.c b/drivers/misc/c3.c
new file mode 100644
index 000..5f1eaee
--- /dev/null
+++ b/drivers/misc/c3.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2012
+ * ST Micoelectronics Pvt. Ltd.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include c3.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+static unsigned long c3_mem_xlate(void *addr)
+{
+
+ if (((ulong)addr C3_INT_MEM_BASE_ADDR) || \
+ ((ulong)addr = (C3_INT_MEM_BASE_ADDR + C3_INT_MEM_SIZE)))
+ return (ulong)addr;
+
+ return (unsigned long)addr - C3_INT_MEM_BASE_ADDR +
+ C3_LOCAL_MEM_ADDR;
+}
+
+int c3_init(void)
+{
+ if (readl(C3_ID0_SCR) != C3_ID0_DEF_RDY_VAL)
+ writel(C3_ID0_SCR_RST, C3_ID0_SCR);
+
+ if (readl(C3_MOVE_CHANNEL_ID) == C3_MOVE_CHANNEL_ID_VAL)
+ return -EINVAL;
+
+ writel(C3_HIF_MCR_ENB_INT_MEM, C3_HIF_MCR);
+ writel(C3_LOCAL_MEM_ADDR, C3_HIF_MBAR);
+
+ return 0;
+}
+
+static int c3_run(void *prog_start)
+{
+ writel(c3_mem_xlate(prog_start), C3_ID0_IP);
+
+ while ((readl(C3_ID0_SCR) C3_ID0_STATE_MASK) == C3_ID0_STATE_RUN)
+ ;
+
+ if ((readl(C3_ID0_SCR) C3_ID0_STATE_MASK) != C3_ID0_STATE_IDLE) {
+ /* If not back to idle an error occured */
+ writel(C3_ID0_SCR_RST, C3_ID0_SCR);
+
+ /* Set internal access to run c3 programs */
+ writel(C3_HIF_MCR_ENB_INT_MEM, C3_HIF_MCR);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int c3_move(void *dest, void *src, int cnt, int optype, int opdata)
+{
+ unsigned long *c3_prog;
+ int ret = 0;
+
+ /* 3.b Prepare program */
+ c3_prog = (unsigned long *)C3_INT_MEM_BASE_ADDR;
+
+ /* 3.b.i. Mov init */
+ c3_prog[0] = C3_CMD_MOVE_INIT;
+ c3_prog[1] = opdata;
+
+ /* 3.b.ii. Mov data */
+ c3_prog[2] = C3_CMD_MOVE_DATA + cnt + optype;
+ c3_prog[3] = c3_mem_xlate(src);
+ c3_prog[4] = c3_mem_xlate(dest);
+
+ /* 3.b.iii. Stop */
+ c3_prog[5] = C3_CMD_STOP;
+
+ /* 4. Execute and wait */
+ ret = c3_run(c3_prog);
+
+ return ret;
+}
+
+void *c3_memset(void *s, int c, size_t count)
+{
+#define DATA_SIZE (1024*4)
+ u32 data = C3_INT_MEM_BASE_ADDR + 0x100;
+ u32 size;
+ size_t cur = 0;
+
+ writel(0x100, C3_HIF_MAAR);
+ writel(c, C3_HIF_MADR);
+
+ for (size = 4; size DATA_SIZE; size = 1)
+ c3_move((void *)(data + size), (void *)data, size,
+ C3_MOVE_AND, 0x);
+
+ while (cur count) {
+ c3_move(s + cur, (void *)data, DATA_SIZE,
+ C3_MOVE_AND, 0x);
+ cur += DATA_SIZE;
+ }
+
+ return s;
+}
diff --git a/include/c3.h b/include
Re: [U-Boot] [PATCH resend 2/2] arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P
On 12/6/2012 3:14 PM, Stefan Roese wrote:
On 12/06/2012 10:29 AM, Vipin Kumar wrote:
A lot of ARM boards are using board_init routine just to initialize boot_params
variable in the global data structure.
This patch lets the board config files to define a CONFIG_BOOT_PARAMS_P option
which is assigned to gd-bd-bi_boot_params automatically
Consequently, many board_init routines would not be required in the respective
board directories and a weak definition becomes necessary before their removal
from the code.
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
README | 6 ++
arch/arm/lib/board.c | 12
2 files changed, 18 insertions(+)
diff --git a/README b/README
index 037513a..2077c3b 100644
--- a/README
+++ b/README
@@ -550,6 +550,12 @@ The following options need to be configured:
in a single configuration file and the machine type is
runtime discoverable, do not have to use this setting.
+ CONFIG_BOOT_PARAMS_P[relevant for ARM only]
+
+ This config option can provide a way to initialize
+ bi_boot_params from the u-boot infrastructure itself. The
+ board still has the option to override it in board_init routine
+
- vxWorks boot parameters:
bootvx constructs a valid bootline using the following
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 92cad9a..fa161b8 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -399,6 +399,11 @@ void board_init_f(ulong bootflag)
gd-bd-bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
#endif
+#ifdef CONFIG_BOOT_PARAMS_P
+ /* Boot params passed to Linux */
+ gd-bd-bi_boot_params = CONFIG_BOOT_PARAMS_P;
+#endif
Again an ugly #ifdef. Why not something like this instead:
Define a default earlier in the code (is 0x100 the best default?):
#ifndef CONFIG_BOOT_PARAMS_P
#define CONFIG_BOOT_PARAMS_P0x100
#endif
then here just:
/* Boot params passed to Linux */
gd-bd-bi_boot_params = CONFIG_BOOT_PARAMS_P;
This would mean that I am forcing the boot params at 0x100 for all
boards. Is that the right thing to do
Off-course, all of them might already be initializing
gd-bd-bi_boot_params on their own
without the #ifdef.
+
addr_sp -= sizeof (gd_t);
id = (gd_t *) addr_sp;
debug(Reserving %zu Bytes for Global Data at: %08lx\n,
@@ -468,6 +473,13 @@ void board_init_f(ulong bootflag)
static char *failed = *** failed ***\n;
#endif
+static int __def_board_init(bd_t *bis)
+{
+ return -1;
Is -1 a good value to return as default board_init()?
The return value is not checked as of today
+}
+
+int board_init(void) __attribute__((weak, alias(__def_board_init)));
+
Use __weak from inlcude/linux/compiler.h instead:
int __weak board_init(bd_t *bis)
...
OK, I would do that in v2
Vipin
Thanks,
Stefan
.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsmc: Skip BBT scan for bad block management
On 12/7/2012 12:57 AM, Scott Wood wrote: On 12/06/2012 01:21:28 AM, Vipin Kumar wrote: This patch forces to read the bad block marker from location 0 in large page nand devices and location 5 in small page devices. Signed-off-by: Vipin Kumarvipin.ku...@st.com Reviewed-by: Shiraz Hashimshiraz.has...@st.com --- drivers/mtd/nand/fsmc_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 7a61d88..bce4298 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -433,7 +433,7 @@ int fsmc_nand_init(struct nand_chip *nand) writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, fsmc_regs_p-attrib); - nand-options = 0; + nand-options = NAND_SKIP_BBTSCAN; #if defined(CONFIG_SYS_FSMC_NAND_16BIT) nand-options |= NAND_BUSWIDTH_16; #endif I don't think this will change the bad block marker behavior -- just whether you use a BBT. Why do you need this? Why not NAND_USE_FLASH_BBT instead? It's because the BootROM which is fused in the device itself (ie non-modifiable) is going to read the bad block markers from the oob area. Which means that anything written via u-boot is non-readable if it uses flash bbt -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/7] mtd/st_smi: Add fixes for smi driver
On 12/6/2012 5:12 PM, Stefan Roese wrote: Hi Vipin, On 12/06/2012 10:05 AM, Vipin Kumar wrote: As you can see, I have added your Acked-by to patches 2, 3, 4, 6 The reset are still pending. If you can quickly close them, I can send a pull-request for these patches I'm fine with all patches now. But please wait still a few days for further review comments before sending a pull-request. Sure. Thanks Vipin Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 1/7] mtd/st_smi: Clear error flags while initiating a fresh write
SMI controller reports an error when the code tries to write on the flash area with Write Enable command not issued or the bank has come out of the write mode. This error is reported even with a fresh write once the ERF1 or ERF2 is set. Clear these flags while initiating a fresh write Signed-off-by: Vipin Kumar vipin.ku...@st.com --- drivers/mtd/st_smi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 7507e5d..fad4420 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -392,6 +392,8 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, return -1; } + writel(readl(smicntl-smi_sr) ~(ERF1 | ERF2), smicntl-smi_sr); + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) return -EBUSY; -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 0/7] mtd/st_smi: Add fixes for smi driver
Hello, This patch-set adds simple fixes for smi driver used in spear devices. Modifications include - Add MTD support for smi driver - Write to flash in a tight loop - Alphabetically sort the list of devices - Avoid issuing multiple write enable commands PS: Wolfgang, Stefan, I am directing these to you as there is no direct maintainer of mtd in u-boot. I can add these in my pull-request once you review these patches Thanks in advance Vipin Armando Visconti (1): mtd/st_smi: Add support for Micron N25Q128 Flash Vipin Kumar (6): mtd/st_smi: Clear error flags while initiating a fresh write mtd/st_smi: Rearrange the supported devices in alphabetical order mtd/st_smi: Avoid issuing multiple WE commands mtd/st_smi: Write to flash in a tight loop mtd/st_smi: Use page sizes respective to flash mtd/st_smi: Add mtd support for smi drivers/mtd/st_smi.c | 260 ++--- include/linux/mtd/st_smi.h | 1 - 2 files changed, 222 insertions(+), 39 deletions(-) -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 2/7] mtd/st_smi: Rearrange the supported devices in alphabetical order
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/mtd/st_smi.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index fad4420..c3e35c0 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -62,24 +62,24 @@ struct flash_device {
* Currently the erase_cmd field is not used in this driver.
*/
static struct flash_device flash_devices[] = {
- FLASH_ID(st m25p16 , 0xd8, 0x00152020, 0x100, 0x1, 0x20),
- FLASH_ID(st m25p32 , 0xd8, 0x00162020, 0x100, 0x1, 0x40),
- FLASH_ID(st m25p64 , 0xd8, 0x00172020, 0x100, 0x1, 0x80),
- FLASH_ID(st m25p128, 0xd8, 0x00182020, 0x100, 0x4, 0x100),
+ FLASH_ID(sp s25fl004 , 0xd8, 0x00120201, 0x100, 0x1, 0x8),
+ FLASH_ID(sp s25fl008 , 0xd8, 0x00130201, 0x100, 0x1, 0x10),
+ FLASH_ID(sp s25fl016 , 0xd8, 0x00140201, 0x100, 0x1, 0x20),
+ FLASH_ID(sp s25fl032 , 0xd8, 0x00150201, 0x100, 0x1, 0x40),
+ FLASH_ID(sp s25fl064 , 0xd8, 0x00160201, 0x100, 0x1, 0x80),
FLASH_ID(st m25p05 , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x1),
FLASH_ID(st m25p10 , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x2),
+ FLASH_ID(st m25p16 , 0xd8, 0x00152020, 0x100, 0x1, 0x20),
FLASH_ID(st m25p20 , 0xd8, 0x00122020, 0x100, 0x1, 0x4),
+ FLASH_ID(st m25p32 , 0xd8, 0x00162020, 0x100, 0x1, 0x40),
FLASH_ID(st m25p40 , 0xd8, 0x00132020, 0x100, 0x1, 0x8),
+ FLASH_ID(st m25p64 , 0xd8, 0x00172020, 0x100, 0x1, 0x80),
FLASH_ID(st m25p80 , 0xd8, 0x00142020, 0x100, 0x1, 0x10),
+ FLASH_ID(st m25p128, 0xd8, 0x00182020, 0x100, 0x4, 0x100),
FLASH_ID(st m45pe10, 0xd8, 0x00114020, 0x100, 0x1, 0x2),
FLASH_ID(st m45pe20, 0xd8, 0x00124020, 0x100, 0x1, 0x4),
FLASH_ID(st m45pe40, 0xd8, 0x00134020, 0x100, 0x1, 0x8),
FLASH_ID(st m45pe80, 0xd8, 0x00144020, 0x100, 0x1, 0x10),
- FLASH_ID(sp s25fl004 , 0xd8, 0x00120201, 0x100, 0x1, 0x8),
- FLASH_ID(sp s25fl008 , 0xd8, 0x00130201, 0x100, 0x1, 0x10),
- FLASH_ID(sp s25fl016 , 0xd8, 0x00140201, 0x100, 0x1, 0x20),
- FLASH_ID(sp s25fl032 , 0xd8, 0x00150201, 0x100, 0x1, 0x40),
- FLASH_ID(sp s25fl064 , 0xd8, 0x00160201, 0x100, 0x1, 0x80),
FLASH_ID(mac 25l512, 0xd8, 0x001020C2, 0x010, 0x1, 0x1),
FLASH_ID(mac 25l1005 , 0xd8, 0x001120C2, 0x010, 0x1, 0x2),
FLASH_ID(mac 25l2005 , 0xd8, 0x001220C2, 0x010, 0x1, 0x4),
@@ -91,7 +91,7 @@ static struct flash_device flash_devices[] = {
FLASH_ID(mac 25l3205 , 0xd8, 0x001620C2, 0x100, 0x1, 0x40),
FLASH_ID(mac 25l3205a , 0xd8, 0x001620C2, 0x100, 0x1, 0x40),
FLASH_ID(mac 25l6405 , 0xd8, 0x001720C2, 0x100, 0x1, 0x80),
- FLASH_ID(wbd w25q128 , 0xd8, 0x001840EF, 0x100, 0x1, 0x100),
+ FLASH_ID(wbd w25q128 , 0xd8, 0x001840EF, 0x100, 0x1, 0x100),
};
/*
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 3/7] mtd/st_smi: Add support for Micron N25Q128 Flash
From: Armando Visconti armando.visco...@st.com
Signed-off-by: Armando Visconti armando.visco...@st.com
---
drivers/mtd/st_smi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index c3e35c0..a46b273 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -91,6 +91,7 @@ static struct flash_device flash_devices[] = {
FLASH_ID(mac 25l3205 , 0xd8, 0x001620C2, 0x100, 0x1, 0x40),
FLASH_ID(mac 25l3205a , 0xd8, 0x001620C2, 0x100, 0x1, 0x40),
FLASH_ID(mac 25l6405 , 0xd8, 0x001720C2, 0x100, 0x1, 0x80),
+ FLASH_ID(mcr n25q128 , 0xd8, 0x0018BA20, 0x100, 0x1, 0x100),
FLASH_ID(wbd w25q128 , 0xd8, 0x001840EF, 0x100, 0x1, 0x100),
};
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 4/7] mtd/st_smi: Avoid issuing multiple WE commands
At the start of an smi_write, if the destination address is page aligned, the
Write Enable command is getting issued twice. This patch fixes it by keeping a
flag.
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/mtd/st_smi.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index a46b273..a84802a 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -374,7 +374,7 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
u8 *src_addr8 = (u8 *)src_addr;
u8 *dst_addr8 = (u8 *)dst_addr;
int banknum;
- int i;
+ int i, issue_we;
switch (bank_addr) {
case SMIBANK0_BASE:
@@ -394,19 +394,16 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
}
writel(readl(smicntl-smi_sr) ~(ERF1 | ERF2), smicntl-smi_sr);
-
- if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
- return -EBUSY;
+ issue_we = 1;
/* Set SMI in Hardware Mode */
writel(readl(smicntl-smi_cr1) ~SW_MODE, smicntl-smi_cr1);
- if (smi_write_enable(banknum))
- return -EIO;
-
/* Perform the write command */
for (i = 0; i length; i += 4) {
- if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
+ if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
+ issue_we = 0;
+
if (smi_wait_till_ready(banknum,
CONFIG_SYS_FLASH_WRITE_TOUT))
return -EBUSY;
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 5/7] mtd/st_smi: Write to flash in a tight loop
The write loop is checking for dest_addr alignment with page size. This
sometimes leads to smi controller coming out of write mode and eventually the
next write failing with ERF1 being set.
To avoid this, write to flash in a tight loop and write bytewise to also support
not word aligned data bytes to be written. Additionally, enable burst mode
before this loop so that the controller does not deselect the chip if the
transfer is finished.
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/mtd/st_smi.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index a84802a..998bacb 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -368,13 +368,11 @@ static int smi_sector_erase(flash_info_t *info, unsigned
int sector)
*
* Write to SMI flash
*/
-static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
+static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
unsigned int length, ulong bank_addr)
{
- u8 *src_addr8 = (u8 *)src_addr;
- u8 *dst_addr8 = (u8 *)dst_addr;
int banknum;
- int i, issue_we;
+ int issue_we;
switch (bank_addr) {
case SMIBANK0_BASE:
@@ -400,7 +398,10 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
writel(readl(smicntl-smi_cr1) ~SW_MODE, smicntl-smi_cr1);
/* Perform the write command */
- for (i = 0; i length; i += 4) {
+ while (length) {
+ int k;
+ unsigned int wlen = min(SFLASH_PAGE_SIZE, length);
+
if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
issue_we = 0;
@@ -412,19 +413,14 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
return -EIO;
}
- if (length 4) {
- int k;
+ writel(readl(smicntl-smi_cr1) | WB_MODE, smicntl-smi_cr1);
- /*
-* Handle special case, where length 4 (redundant env)
-*/
- for (k = 0; k length; k++)
- *dst_addr8++ = *src_addr8++;
- } else {
- /* Normal 32bit write */
+ for (k = 0; k wlen; k++)
*dst_addr++ = *src_addr++;
- }
+ writel(readl(smicntl-smi_cr1) ~WB_MODE, smicntl-smi_cr1);
+
+ length -= wlen;
if ((readl(smicntl-smi_sr) (ERF1 | ERF2)))
return -EIO;
}
@@ -448,8 +444,8 @@ static int smi_write(unsigned int *src_addr, unsigned int
*dst_addr,
*/
int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
{
- return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
-length, info-start[0]);
+ return smi_write(src, (unsigned char *)dest_addr, length,
+ info-start[0]);
}
/*
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 6/7] mtd/st_smi: Use page sizes respective to flash
The page size is a flash dependent property and the driver was using a macro in
place of page size. This patch uses the proper page size wrt the flash device
connected on board
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/mtd/st_smi.c | 41 +
include/linux/mtd/st_smi.h | 1 -
2 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 998bacb..0e529a4 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -96,6 +96,25 @@ static struct flash_device flash_devices[] = {
};
/*
+ * get_flash_device - Return flash_device pointer for a particular device id
+ * @id: Device id
+ *
+ * Return flash_device pointer for a particular device id
+ */
+static struct flash_device *get_flash_device(u32 id)
+{
+ struct flash_device *flash_dev_p = flash_devices[0];
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(flash_devices); i++, flash_dev_p++) {
+ if (flash_dev_p-device_id == id)
+ return flash_dev_p;
+ }
+
+ return NULL;
+}
+
+/*
* smi_wait_xfer_finish - Wait until TFF is set in status register
* @timeout:timeout in milliseconds
*
@@ -361,20 +380,27 @@ static int smi_sector_erase(flash_info_t *info, unsigned
int sector)
/*
* smi_write - Write to SMI flash
+ * @info: flash info structure
* @src_addr: source buffer
* @dst_addr: destination buffer
* @length: length to write in bytes
- * @bank: bank base address
*
* Write to SMI flash
*/
-static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
-unsigned int length, ulong bank_addr)
+static int smi_write(flash_info_t *info, unsigned char *src_addr,
+ unsigned char *dst_addr, unsigned int length)
{
+ struct flash_device *flash_device_p = get_flash_device(info-flash_id);
+ u32 page_size;
int banknum;
int issue_we;
- switch (bank_addr) {
+ if (!flash_device_p)
+ return -EIO;
+
+ page_size = flash_device_p-pagesize;
+
+ switch (info-start[0]) {
case SMIBANK0_BASE:
banknum = BANK0;
break;
@@ -400,9 +426,9 @@ static int smi_write(unsigned char *src_addr, unsigned char
*dst_addr,
/* Perform the write command */
while (length) {
int k;
- unsigned int wlen = min(SFLASH_PAGE_SIZE, length);
+ unsigned int wlen = min(page_size, length);
- if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
+ if (issue_we || (((ulong)(dst_addr) % page_size) == 0)) {
issue_we = 0;
if (smi_wait_till_ready(banknum,
@@ -444,8 +470,7 @@ static int smi_write(unsigned char *src_addr, unsigned char
*dst_addr,
*/
int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
{
- return smi_write(src, (unsigned char *)dest_addr, length,
- info-start[0]);
+ return smi_write(info, src, (unsigned char *)dest_addr, length);
}
/*
diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h
index 04f81ea..5837493 100644
--- a/include/linux/mtd/st_smi.h
+++ b/include/linux/mtd/st_smi.h
@@ -108,7 +108,6 @@ struct flash_dev {
ushort sector_count;
};
-#define SFLASH_PAGE_SIZE 0x100 /* flash page size */
#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */
#define WMODE_TOUT 15 /* write enable timeout(in ms) */
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 7/7] mtd/st_smi: Add mtd support for smi
This patch adds mtd device support for smi devices
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/mtd/st_smi.c | 167 ++-
1 file changed, 165 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 0e529a4..4d1a6bd 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -24,6 +24,7 @@
#include common.h
#include flash.h
#include linux/err.h
+#include linux/mtd/mtd.h
#include linux/mtd/st_smi.h
#include asm/io.h
@@ -37,6 +38,14 @@ static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] =
CONFIG_SYS_FLASH_ADDR_BASE;
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+#if defined(CONFIG_MTD_DEVICE)
+/* MTD interface for SMI devices */
+static struct mtd_info smi_mtd_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static char smi_mtd_names[CONFIG_SYS_MAX_FLASH_BANKS][16];
+
+static int smi_mtd_init(void);
+#endif
+
/* data structure to maintain flash ids from different vendors */
struct flash_device {
char *name;
@@ -482,7 +491,9 @@ unsigned long flash_init(void)
{
unsigned long size = 0;
int i, j;
-
+#if defined(CONFIG_MTD_DEVICE)
+ int error;
+#endif
smi_init();
for (i = 0; i CONFIG_SYS_MAX_FLASH_BANKS; i++) {
@@ -498,6 +509,12 @@ unsigned long flash_init(void)
}
+#if defined(CONFIG_MTD_DEVICE)
+ error = smi_mtd_init();
+ if (error 0)
+ return 0;
+#endif
+
return size;
}
@@ -599,4 +616,150 @@ int flash_erase(flash_info_t *info, int s_first, int
s_last)
puts( done\n);
return rcode;
}
-#endif
+
+#if defined(CONFIG_MTD_DEVICE)
+static int smi_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ flash_info_t *fi = mtd-priv;
+ size_t a_start = fi-start[0] + instr-addr;
+ size_t a_end = a_start + instr-len;
+ int s_first = -1;
+ int s_last = -1;
+ int error, sect;
+
+ for (sect = 0; sect fi-sector_count; sect++) {
+ if (a_start == fi-start[sect])
+ s_first = sect;
+
+ if (sect fi-sector_count - 1) {
+ if (a_end == fi-start[sect + 1]) {
+ s_last = sect;
+ break;
+ }
+ } else {
+ s_last = sect;
+ break;
+ }
+ }
+
+ if (s_first = 0 s_first = s_last) {
+ instr-state = MTD_ERASING;
+
+ error = flash_erase(fi, s_first, s_last);
+ if (error) {
+ instr-state = MTD_ERASE_FAILED;
+ return -EIO;
+ }
+
+ instr-state = MTD_ERASE_DONE;
+ mtd_erase_callback(instr);
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int smi_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ flash_info_t *fi = mtd-priv;
+ u_char *f = (u_char *)(fi-start[0]) + from;
+
+ memcpy(buf, f, len);
+ *retlen = len;
+
+ return 0;
+}
+
+static int smi_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ flash_info_t *fi = mtd-priv;
+ u_long t = fi-start[0] + to;
+ int error;
+
+ error = write_buff(fi, (u_char *)buf, t, len);
+ if (!error) {
+ *retlen = len;
+ return 0;
+ }
+
+ return -EIO;
+}
+
+static void smi_mtd_sync(struct mtd_info *mtd)
+{
+ /*
+* This function should wait until all pending operations
+* finish. However this driver is fully synchronous, so
+* this function returns immediately
+*/
+}
+
+static int smi_mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ flash_info_t *fi = mtd-priv;
+
+ flash_protect(FLAG_PROTECT_SET, fi-start[0] + ofs,
+ fi-start[0] + ofs + len - 1, fi);
+ return 0;
+}
+
+static int smi_mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ flash_info_t *fi = mtd-priv;
+
+ flash_protect(FLAG_PROTECT_CLEAR, fi-start[0] + ofs,
+ fi-start[0] + ofs + len - 1, fi);
+ return 0;
+}
+
+static int smi_mtd_init(void)
+{
+ struct flash_device *flash_device_p;
+ struct mtd_info *mtd;
+ flash_info_t *fi;
+ int i;
+
+ for (i = 0; i CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ fi = flash_info[i];
+
+ if (!fi-size)
+ continue;
+
+ flash_device_p = get_flash_device(fi-flash_id);
+ if (!flash_device_p)
+ return -EIO;
+
+ mtd = smi_mtd_info[i];
+
+ memset(mtd, 0, sizeof(struct mtd_info));
+
+ /* Uniform erase sizes for all sectors */
+ mtd
[U-Boot] [PATCH resend] usbh/ehci: Increase timeout for enumeration
Few pen drives take longer than usual for enumeration. The u-boot unlike linux
does not depend on interrupts and works in polling and timeout mode.
This patch increases this timeout to increase the set of usb sticks that can be
enumerated by u-boot
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
common/usb_hub.c | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index e4a1201..24de9b7 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -393,17 +393,34 @@ static int usb_hub_configure(struct usb_device *dev)
: no );
usb_hub_power_on(hub);
+ mdelay(1500);
+
for (i = 0; i dev-maxchild; i++) {
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
+ int ret;
+ ulong start = get_timer(0);
+
+ do {
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret 0) {
+ USB_HUB_PRINTF(get_port_status failed\n);
+ break;
+ }
+
+ portstatus = le16_to_cpu(portsts-wPortStatus);
+ portchange = le16_to_cpu(portsts-wPortChange);
+
+ if ((portchange USB_PORT_STAT_C_CONNECTION)
+ (portstatus USB_PORT_STAT_CONNECTION))
+ break;
- if (usb_get_port_status(dev, i + 1, portsts) 0) {
- USB_HUB_PRINTF(get_port_status failed\n);
+ mdelay(100);
+ } while (get_timer(start) CONFIG_SYS_HZ * 10);
+
+ if (ret 0)
continue;
- }
- portstatus = le16_to_cpu(portsts-wPortStatus);
- portchange = le16_to_cpu(portsts-wPortChange);
USB_HUB_PRINTF(Port %d Status %X Change %X\n,
i + 1, portstatus, portchange);
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend] sdhci: Add sdhci support for spear devices
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/mmc/Makefile | 1 +
drivers/mmc/spear_sdhci.c | 44
2 files changed, 45 insertions(+)
create mode 100644 drivers/mmc/spear_sdhci.c
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index a1dd730..01dd61d 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -45,6 +45,7 @@ COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
COBJS-$(CONFIG_SDHCI) += sdhci.o
COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+COBJS-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
COBJS-$(CONFIG_DWMMC) += dw_mmc.o
diff --git a/drivers/mmc/spear_sdhci.c b/drivers/mmc/spear_sdhci.c
new file mode 100644
index 000..23f1f4b
--- /dev/null
+++ b/drivers/mmc/spear_sdhci.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include sdhci.h
+
+int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+{
+ struct sdhci_host *host = NULL;
+ host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+ if (!host) {
+ printf(sdhci host malloc fail!\n);
+ return 1;
+ }
+
+ host-name = sdhci;
+ host-ioaddr = (void *)regbase;
+ host-quirks = quirks;
+
+ if (quirks SDHCI_QUIRK_REG32_RW)
+ host-version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) 16;
+ else
+ host-version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+ add_sdhci(host, max_clk, min_clk);
+ return 0;
+}
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend] spi/arm-pl022: Add support for ARM PL022 spi controller
From: Armando Visconti armando.visco...@st.com
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
Dear Wolfgang, Stefan,
There seems to be no direct owner of spi framework. So, I am directing this
patch to you
Regards
Vipin
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 308
2 files changed, 309 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 824d357..3a4e4b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..3ea769a
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+#define SSP_CR00x000
+#define SSP_CR10x004
+#define SSP_DR 0x008
+#define SSP_SR 0x00C
+#define SSP_CPSR 0x010
+#define SSP_IMSC 0x014
+#define SSP_RIS0x018
+#define SSP_MIS0x01C
+#define SSP_ICR0x020
+#define SSP_DMACR 0x024
+#define SSP_ITCR 0x080
+#define SSP_ITIP 0x084
+#define SSP_ITOP 0x088
+#define SSP_TDR0x08C
+
+#define SSP_PID0 0xFE0
+#define SSP_PID1 0xFE4
+#define SSP_PID2 0xFE8
+#define SSP_PID3 0xFEC
+
+#define SSP_CID0 0xFF0
+#define SSP_CID1 0xFF4
+#define SSP_CID2 0xFF8
+#define SSP_CID3 0xFFC
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+ __attribute__((weak, alias(__spi_cs_is_valid)));
+void spi_cs_activate(struct spi_slave *slave)
+ __attribute__((weak, alias(__spi_cs_activate)));
+void spi_cs_deactivate(struct spi_slave *slave)
+ __attribute__((weak, alias(__spi_cs_deactivate)));
+
+int __spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init()
+{
+ /* do nothing */
+}
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022), that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO
Re: [U-Boot] [PATCH resend] usbh/ehci: Increase timeout for enumeration
On 12/6/2012 12:17 PM, Igor Grinberg wrote:
On 12/06/12 08:30, Vipin Kumar wrote:
Few pen drives take longer than usual for enumeration. The u-boot unlike linux
does not depend on interrupts and works in polling and timeout mode.
This patch increases this timeout to increase the set of usb sticks that can be
enumerated by u-boot
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
common/usb_hub.c | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index e4a1201..24de9b7 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -393,17 +393,34 @@ static int usb_hub_configure(struct usb_device *dev)
: no );
usb_hub_power_on(hub);
+ mdelay(1500);
a 1.5 seconds? This looks like a huge overkill...
Even for broken usb sticks...
Yes, but we are not talking about performance in u-boot. And since we
are working in a polling mode, we only have 1 chance to detect the pen-drive
+
for (i = 0; i dev-maxchild; i++) {
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
+ int ret;
+ ulong start = get_timer(0);
+
+ do {
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret 0) {
+ USB_HUB_PRINTF(get_port_status failed\n);
+ break;
+ }
+
+ portstatus = le16_to_cpu(portsts-wPortStatus);
+ portchange = le16_to_cpu(portsts-wPortChange);
+
+ if ((portchange USB_PORT_STAT_C_CONNECTION)
+ (portstatus USB_PORT_STAT_CONNECTION))
+ break;
- if (usb_get_port_status(dev, i + 1, portsts) 0) {
- USB_HUB_PRINTF(get_port_status failed\n);
+ mdelay(100);
+ } while (get_timer(start) CONFIG_SYS_HZ * 10);
+
+ if (ret 0)
continue;
- }
- portstatus = le16_to_cpu(portsts-wPortStatus);
- portchange = le16_to_cpu(portsts-wPortChange);
USB_HUB_PRINTF(Port %d Status %X Change %X\n,
i + 1, portstatus, portchange);
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 1/2] net/designware: Do not select MIIPORT for RGMII interface
Do not select MIIPORT for RGMII interface
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/net/designware.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index bf21a08..46f6601 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -113,7 +113,9 @@ static int mac_reset(struct eth_device *dev)
int timeout = CONFIG_MACRESET_TIMEOUT;
writel(DMAMAC_SRST, dma_p-busmode);
- writel(MII_PORTSELECT, mac_p-conf);
+
+ if (priv-interface != PHY_INTERFACE_MODE_RGMII)
+ writel(MII_PORTSELECT, mac_p-conf);
start = get_timer(0);
while (get_timer(start) timeout) {
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH resend 2/2] net/macb: Add arch specific routine to get mdio control
From: Shiraz Hashim shiraz.has...@st.com
SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently their is a fixed configuration in which only a
particular MAC can use the MDIO lines.
Call an arch specific function to take control of specific mdio lines at
runtime.
Signed-off-by: Shiraz Hashim shiraz.has...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
drivers/net/macb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 8bacbda..45fbbd7 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -163,6 +163,13 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
return MACB_BFEXT(DATA, frame);
}
+static void __def_arch_get_mdio_control(const char *name)
+{
+ return;
+}
+int arch_get_mdio_control(const char *name)
+ __attribute__((weak, alias(__def_arch_get_mdio_control)));
+
#if defined(CONFIG_CMD_MII)
int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
@@ -173,6 +180,7 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8
reg, u16 *value)
if ( macb-phy_addr != phy_adr )
return -1;
+ arch_get_mdio_control(devname);
*value = macb_mdio_read(macb, reg);
return 0;
@@ -186,6 +194,7 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8
reg, u16 value)
if ( macb-phy_addr != phy_adr )
return -1;
+ arch_get_mdio_control(devname);
macb_mdio_write(macb, reg, value);
return 0;
@@ -377,6 +386,7 @@ static int macb_phy_init(struct macb_device *macb)
int media, speed, duplex;
int i;
+ arch_get_mdio_control(netdev-name);
#ifdef CONFIG_MACB_SEARCH_PHY
/* Auto-detect phy_addr */
if (!macb_phy_find(macb)) {
--
1.8.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] fsmc: Skip BBT scan for bad block management
This patch forces to read the bad block marker from location 0 in large page nand devices and location 5 in small page devices. Signed-off-by: Vipin Kumar vipin.ku...@st.com Reviewed-by: Shiraz Hashim shiraz.has...@st.com --- drivers/mtd/nand/fsmc_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 7a61d88..bce4298 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -433,7 +433,7 @@ int fsmc_nand_init(struct nand_chip *nand) writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, fsmc_regs_p-attrib); - nand-options = 0; + nand-options = NAND_SKIP_BBTSCAN; #if defined(CONFIG_SYS_FSMC_NAND_16BIT) nand-options |= NAND_BUSWIDTH_16; #endif -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/46] Enhance spear support
On 11/30/2012 6:04 PM, Wolfgang Denk wrote: Dear Armando Visconti, In message50b89534.6040...@st.com you wrote: Not sure what are next steps for this patchset. Is someone going to review it, or part of it? Or is Vipin expected to do something on the repository assigned to him (maybe he already did)? Vipin volunteered as custodian, so the next step should be that he performs a final review, applies the patches to his repo, and sends a pullr equest to Albert. Yes, I am preparing the repository and I am going to send a pull request very soon Thanks Vipin Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/46] Enhance spear support
Hello u-boot team, Can you please provide some comments on this patch-set Please consider this for inclusion Regards Vipin On 11/2/2012 11:09 PM, Vipin KUMAR wrote: This patchset is split in several pieces - Drivers: This is essentially a few new drivers and fixes in already exiasting drivers - Enhancement: This series enhances the already existing spear support - spear13xx: This is a totally new suppoort for spear13xx architecture Armando Visconti (2): mtd/st_smi: Add support for Micron N25Q128 Flash spi/arm-pl022: Add support for ARM PL022 spi controller Pratyush Anand (1): usb/gadget/designware_otg: Add support for designware otg Shiraz Hashim (3): usbtty: adapt buffers for large packet support net/macb: Add arch specific routine to get mdio control net/macb: workaround for transmission hang issue Vipin Kumar (40): mtd/st_smi: Clear error flags while initiating a fresh write mtd/st_smi: Avoid issuing multiple WE commands mtd/st_smi: Write to flash in a tight loop mtd/st_smi: Use page sizes respective to flash usbh/ehci: Increase timeout for enumeration sdhci: Add sdhci support for spear devices net/designware: Do not select MIIPORT for RGMII interface usb/host/ehci: Add support for EHCI on spear misc/crypto: Add support for C3 armv7/ltimer: Add support for local timer on armv7 cpus imls: Add support to list images in NAND device u-boot/spl: Add u-boot-spl.img to u-boot targets arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P SPEAr: Remove extra spear board configurations spear/configs: Split config files hierarchically into plat, arch, soc and board spear/include: Clean up the spear include files spear/board: Cleanup spear related board files spear: Append MISC_ as prefix to misc register bitmasks spear: Read ethaddr from I2C memory spear: Cleanup SoC area spear/spl: Cleanup spear SPL spear: Add POST memory support spear: Enable ehci support spear3xx: FIX: Enable access to memory for spear310 and spear320 spear: Add cache support spear3xx: Add pinmux support spear320plc: Correct the MACB interface spear/configs: Modify several configurations spear320: Add support for SD/MMC spear320-hmi: Add support for hmi machine spear6xx/spear3xx: Add support to boot via NAND device spear/spl: Add support to boot from Parallel NOR device spear300evb: Add SPL support spear1340: Add support for spear1340 SoC spear1310: Add support for spear1310 SoC spear1340evb: Add support for evb machine spear1310evb: Add support for evb machine spear1340lcad: Add support for LCAD machine spear1340evb: Add SPL support spear1310evb: Add SPL support MAINTAINERS|4 + Makefile | 10 + README |6 + arch/arm/cpu/arm926ejs/spear/Makefile | 26 +- arch/arm/cpu/arm926ejs/spear/cache.c | 32 + arch/arm/cpu/arm926ejs/spear/cpu.c | 93 +- arch/arm/cpu/arm926ejs/spear/emi.c | 80 ++ arch/arm/cpu/arm926ejs/spear/reset.c |2 +- arch/arm/cpu/arm926ejs/spear/spear300.c| 140 +++ arch/arm/cpu/arm926ejs/spear/spear310.c| 162 +++ arch/arm/cpu/arm926ejs/spear/spear320.c| 860 arch/arm/cpu/arm926ejs/spear/spear3xx.c| 130 +++ arch/arm/cpu/arm926ejs/spear/spear600.c| 236 - arch/arm/cpu/arm926ejs/spear/spear6xx.c| 43 + arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c| 171 arch/arm/cpu/arm926ejs/spear/spl-spear600.c| 98 ++ arch/arm/cpu/arm926ejs/spear/spl.c | 181 +--- arch/arm/cpu/arm926ejs/spear/spl_boot.c| 206 +++- arch/arm/cpu/arm926ejs/spear/spl_nand.c| 121 +++ arch/arm/cpu/arm926ejs/spear/start.S | 58 +- arch/arm/cpu/arm926ejs/spear/timer.c |8 +- arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds| 65 +- arch/arm/cpu/armv7/Makefile| 17 +- arch/arm/cpu/armv7/ca9_ltimer.c| 154 +++ arch/arm/cpu/armv7/spear13xx/Makefile | 71 ++ arch/arm/cpu/armv7/spear13xx/reset.c | 47 + arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c| 860 arch/arm/cpu/armv7/spear13xx/spear1310.c | 205 arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c| 439 arch/arm/cpu/armv7/spear13xx/spear1340.c | 270 + arch/arm/cpu/armv7/spear13xx/spear13xx.c | 62 ++ arch/arm/cpu/armv7/spear13xx/spl-boot.c| 76 ++ arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c | 239 + arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c| 229 + arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c | 608
Re: [U-Boot] [PATCH 00/46] Enhance spear support
On 11/11/2012 1:20 PM, Wolfgang Denk wrote: Dear Stefan, In message509f4194.9070...@denx.de you wrote: Vipin, please send your public ssh key to Wolfgang so that we can create the new spear U-Boot git repository for you. Hello Wolfgang Will this be only SPEAr, or should we expect other chips fromSTM to go Yes, it will only be for spear as of now though it, too (so a more generic name like u-boot-stm would be better) ? The ssh key is as below ssh-rsa B3NzaC1yc2EBIwAAAQEA4FSMngFagc4TFNX5JoxxTmLe9oqUZcaILgs6OH8T2kOpxykq4tL30xzKPdTW5w++UT+N7GYJLaYvv0gaGg9d/GbunhBrHexBar8aYwz71uHQzOJ1Gpx4otbE1vZ5TOlOqecBGMTYXzHBRDdCCDWwwKgkLm6Q2ZlEXeo64q2RZ7iOCoWAUjHoXcNnNKtKI4D+JIVeONxCYYehbktPGznajpzXMHuOBS7wEXBj4U1ekv2YUI316b485KjYoufALeICoGQq3OCqxVH8FxgV1HfzVer1fimHYPjaHSAPRyDiNqxLj/s/ToBKuW+3UX+gM2ef9x0TXXGhoeXozXTxlyQyaw== vipink@DLH10018 Best Regards Vipin Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/46] Enhance spear support
On 11/7/2012 7:40 PM, Stefan Roese wrote: Hi Vipin, On 11/02/2012 06:39 PM, Vipin Kumar wrote: This patchset is split in several pieces - Drivers: This is essentially a few new drivers and fixes in already exiasting drivers - Enhancement: This series enhances the already existing spear support - spear13xx: This is a totally new suppoort for spear13xx architecture Thanks for all these patches. This is a massive patch-set. I'll try to review at least some of them later this week. Please be patient. But this amount of patches does raise a question that I discussed a time ago. If you continue to work on upstream U-Boot, which we greatly appreciate, then its perhaps better to create/add an SPEAr U-Boot custodian responsible for the SPEAr related patches. Reviewing, collecting patches and pushing them to Alberts ARM repository. This would take a bit of work from Albert, since without such an custodian all those SPEAr patches would fall into his area. What do you guys think? Albert, what are your thoughts on this? Vipin, would you volunteer to eventually become this SPEAr U-Boot custodian? Or someone else? Yes, I can volunteer to be the SPEAr U-Boot custodian.. Regards Vipin Just my thought, comments welcome! Thanks, Stefan DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/46] Enhance spear support
On 11/7/2012 7:40 PM, Stefan Roese wrote: Hi Vipin, On 11/02/2012 06:39 PM, Vipin Kumar wrote: This patchset is split in several pieces - Drivers: This is essentially a few new drivers and fixes in already exiasting drivers - Enhancement: This series enhances the already existing spear support - spear13xx: This is a totally new suppoort for spear13xx architecture Thanks for all these patches. This is a massive patch-set. I'll try to review at least some of them later this week. Please be patient. But this amount of patches does raise a question that I discussed a time ago. If you continue to work on upstream U-Boot, which we greatly appreciate, then its perhaps better to create/add an SPEAr U-Boot custodian responsible for the SPEAr related patches. Reviewing, collecting patches and pushing them to Alberts ARM repository. This would take a bit of work from Albert, since without such an custodian all those SPEAr patches would fall into his area. What do you guys think? Albert, what are your thoughts on this? Vipin, would you volunteer to eventually become this SPEAr U-Boot custodian? Or someone else? Yes, I volunteer to be the SPEAr U-Boot custodian.. Regards Vipin Just my thought, comments welcome! Thanks, Stefan DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Drivers PATCH 17/19] imls: Add support to list images in NAND device
On 11/7/2012 5:00 AM, Scott Wood wrote:
On 11/02/2012 12:40:02 PM, Vipin Kumar wrote:
imls does not list the images in NAND devices. This patch implements this
support for legacy type images.
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
common/cmd_bootm.c | 98
++
1 file changed, 98 insertions(+)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 83fa5d7..ca3c430 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -62,6 +62,11 @@
#include linux/lzo.h
#endif /* CONFIG_LZO */
+#if defined(CONFIG_CMD_NAND)
+#include linux/err.h
+#include nand.h
+#endif
You shouldn't need to ifdef-protect header files.
OK. I would correct this in v2
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_BOOTM_LEN
@@ -1221,6 +1226,99 @@ next_sector: ;
next_bank: ;
}
+#if defined(CONFIG_CMD_NAND)
+ printf(\n);
+ nand_info_t *nand;
+ image_header_t image_header;
+ image_header_t *header = image_header;
+ int nand_dev = nand_curr_device;
+ unsigned long img_size;
+ size_t hdr_size, read_len;
+ loff_t off;
+ unsigned int crc;
+ u_char *data;
+
+ /* the following commands operate on the current device */
+ if (nand_dev 0 || nand_dev = CONFIG_SYS_MAX_NAND_DEVICE) {
+ puts(\nNo NAND devices available\n);
+ return 0;
+ }
Please move the NAND and NOR code into their own functions.
You mean I can separate the NOR list images code in one routine and NAND
in another?
+
+ for (nand_dev = 0; nand_dev CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
+
+ nand = nand_info[nand_dev];
+ if ((!nand-name) || (!nand-size))
+ continue;
Redundant parentheses.
Accepted
+ data = malloc(nand-writesize);
+ if (!data) {
+ puts(No memory available to list NAND images\n);
+ return 0;
+ }
+
+ for (off = 0; off nand-size; off += nand-erasesize) {
+ int ret;
+
+ if (nand_block_isbad(nand, off))
+ continue;
+
+ hdr_size = sizeof(image_header_t);
+ ret = nand_read(nand, off, hdr_size, (u_char *)header);
+ if (ret 0 ret != -EUCLEAN)
+ continue;
I guess you don't use nand_read_skip_bad() because you don't want to
allocate a buffer for the whole image... How about moving this code to
nand_util.c? That would at least allow some refactoring rather than
duplication.
+ if (!image_check_hcrc(header))
+ continue;
+
+ printf(Legacy Image at NAND device %d offset %08lX:\n,
+ nand_dev, (ulong)off);
+ image_print_contents(header);
Shouldn't you check for FIT images as well?
Yes. I was a bit reluctant because I don't know about that format.
OK, I would try to add it in v2
+ puts( Verifying Checksum ... );
+ crc = 0;
+ img_size = ntohl(header-ih_size);
+ img_size += hdr_size;
+
+ while (img_size 0) {
+ int blockoff = 0;
+
+ while (nand_block_isbad(nand, off)) {
+ off += nand-erasesize;
+ if (off = nand-size)
+ goto out;
+ }
+
+ do {
+ read_len = min(img_size,
+ nand-writesize);
+ ret = nand_read(nand, off + blockoff,
+ read_len, data);
+ if (ret 0 ret != -EUCLEAN)
+ break;
+
+ crc = crc32(crc, data + hdr_size,
+ read_len - hdr_size);
+ img_size -= read_len;
+ blockoff += read_len;
+ hdr_size = 0;
+ } while (img_size
+ (blockoff nand-erasesize));
+
+ off += nand-erasesize;
+ if (off = nand-size)
+ goto out;
+ }
+ off -= nand-erasesize;
+out:
+ if (crc != ntohl(header-ih_dcrc))
+ puts( Bad Data CRC\n);
+ else
+ puts(OK\n);
+ }
Please refactor this into separate functions to improve readability.
Maybe put a nand_crc_skip_bad() function into nand_util.c?
OK, I would give it a try. Please wait for v2
-Scott
btw, thanks for the review
How about other patches, Albert, Wolfgang ?
Regards
Vipin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [SPEAr Fixes PATCH 02/11] spear/configs: Split config files hierarchically into plat, arch, soc and board
The spear configuration files are split into spear6xx_evb.h and spear3xx_evb.h
with the common configurations placed in spear-common.h.
This split of configuration is not very conducive to increasing number of boards
within each architecture. With number of boards supported by spear3xx_evb.h
going up to 4, managing those boards becomes a tedious task.
This patch tries to re-split the spear configuration files hierarchically into
board files (spear600-evb.h, spear300-evb.h ...)
soc files (spear600.h, spear300.h ...)
arch files (spear6xx.h, spear3xx.h)
platform file (spear.h)
board configuration file would define the driver enabler which is required for
that respective board and would also define all board related configurations.
All other generic configurations would be defined by respective config files
(either spear3xx.h or spear300.h/spear310.h etc)
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 12 +-
arch/arm/cpu/arm926ejs/spear/spl.c | 8 +-
arch/arm/cpu/arm926ejs/spear/timer.c | 4 +-
arch/arm/include/asm/arch-spear/spr_misc.h | 4 +-
include/configs/spear-common.h | 251 -
include/configs/spear.h| 193 +++
include/configs/spear300-evb.h | 99 ++
include/configs/{spear6xx_evb.h = spear300.h} | 45 ++---
include/configs/spear310-evb.h | 130 +
include/configs/spear310.h | 76
include/configs/spear320-evb.h | 128 +
include/configs/spear320.h | 66 +++
include/configs/spear3xx.h | 50 +
include/configs/spear3xx_evb.h | 173 -
include/configs/spear600-evb.h | 99 ++
include/configs/spear600.h | 58 ++
include/configs/x600.h | 2 +-
17 files changed, 928 insertions(+), 470 deletions(-)
delete mode 100644 include/configs/spear-common.h
create mode 100644 include/configs/spear.h
create mode 100644 include/configs/spear300-evb.h
rename include/configs/{spear6xx_evb.h = spear300.h} (54%)
create mode 100644 include/configs/spear310-evb.h
create mode 100644 include/configs/spear310.h
create mode 100644 include/configs/spear320-evb.h
create mode 100644 include/configs/spear320.h
create mode 100644 include/configs/spear3xx.h
delete mode 100644 include/configs/spear3xx_evb.h
create mode 100644 include/configs/spear600-evb.h
create mode 100644 include/configs/spear600.h
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c
b/arch/arm/cpu/arm926ejs/spear/cpu.c
index e299de3..7f29514 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -34,9 +34,9 @@ int arch_cpu_init(void)
periph1_clken = readl(misc_p-periph1_clken);
-#if defined(CONFIG_SPEAR3XX)
+#if defined(CONFIG_ARCH_SPEAR3XX)
periph1_clken |= MISC_GPT2ENB;
-#elif defined(CONFIG_SPEAR600)
+#elif defined(CONFIG_SOC_SPEAR600)
periph1_clken |= MISC_GPT3ENB;
#endif
@@ -71,13 +71,13 @@ int arch_cpu_init(void)
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
-#ifdef CONFIG_SPEAR300
+#ifdef CONFIG_SOC_SPEAR300
printf(CPU: SPEAr300\n);
-#elif defined(CONFIG_SPEAR310)
+#elif defined(CONFIG_SOC_SPEAR310)
printf(CPU: SPEAr310\n);
-#elif defined(CONFIG_SPEAR320)
+#elif defined(CONFIG_SOC_SPEAR320)
printf(CPU: SPEAr320\n);
-#elif defined(CONFIG_SPEAR600)
+#elif defined(CONFIG_SOC_SPEAR600)
printf(CPU: SPEAr600\n);
#else
#error CPU not supported in spear platform
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c
b/arch/arm/cpu/arm926ejs/spear/spl.c
index 48e6efb..77fe3a9 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -203,7 +203,7 @@ static void sys_init(void)
*/
int get_socrev(void)
{
-#if defined(CONFIG_SPEAR600)
+#if defined(CONFIG_SOC_SPEAR600)
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 soc_id = readl(misc_p-soc_core_id);
u32 pri_socid = (soc_id SOC_PRI_SHFT) 0xFF;
@@ -219,11 +219,11 @@ int get_socrev(void)
return SOC_SPEAR600_BA;
else
return SOC_SPEAR_NA;
-#elif defined(CONFIG_SPEAR300)
+#elif defined(CONFIG_SOC_SPEAR300)
return SOC_SPEAR300;
-#elif defined(CONFIG_SPEAR310)
+#elif defined(CONFIG_SOC_SPEAR310)
return SOC_SPEAR310;
-#elif defined(CONFIG_SPEAR320)
+#elif defined(CONFIG_SOC_SPEAR320)
return SOC_SPEAR320;
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c
b/arch/arm/cpu/arm926ejs/spear/timer.c
index 1dc7860..25a4f62 100644
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -46,10 +46,10 @@ int timer_init(void)
u32 synth;
/* Prescaler setting */
-#if defined
[U-Boot] [SPEAr Fixes PATCH 05/11] spear: Append MISC_ as prefix to misc register bitmasks
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 4 ++--
arch/arm/cpu/arm926ejs/spear/spear600.c | 22 +-
arch/arm/include/asm/arch-spear/misc.h | 10 --
3 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c
b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 1301608..311f31b 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -44,8 +44,8 @@ int arch_cpu_init(void)
periph1_clken |= MISC_UART0ENB;
periph_clk_cfg = readl(misc_p-periph_clk_cfg);
- periph_clk_cfg = ~CONFIG_SPEAR_UARTCLKMSK;
- periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+ periph_clk_cfg = ~MISC_UARTCLKMSK;
+ periph_clk_cfg |= MISC_UART48M;
writel(periph_clk_cfg, misc_p-periph_clk_cfg);
#endif
#if defined(CONFIG_DESIGNWARE_ETH)
diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c
b/arch/arm/cpu/arm926ejs/spear/spear600.c
index f4ec10a..bd8cb7a 100644
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ b/arch/arm/cpu/arm926ejs/spear/spear600.c
@@ -138,8 +138,9 @@ void soc_init(void)
*/
static u32 read_bootstrap(void)
{
- return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) CONFIG_SPEAR_BOOTSTRAPSHFT)
-CONFIG_SPEAR_BOOTSTRAPMASK;
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ return readl(misc_p-auto_cfg_reg) MISC_BOOTSTRAPMASK;
}
int snor_boot_selected(void)
@@ -148,16 +149,13 @@ int snor_boot_selected(void)
if (SNOR_BOOT_SUPPORTED) {
/* Check whether SNOR boot is selected */
- if ((bootstrap CONFIG_SPEAR_ONLYSNORBOOT) ==
- CONFIG_SPEAR_ONLYSNORBOOT)
+ if ((bootstrap MISC_ONLYSNORBOOT) == MISC_ONLYSNORBOOT)
return TRUE;
- if ((bootstrap CONFIG_SPEAR_NORNANDBOOT) ==
- CONFIG_SPEAR_NORNAND8BOOT)
+ if ((bootstrap MISC_NORNANDBOOT) == MISC_NORNAND8BOOT)
return TRUE;
- if ((bootstrap CONFIG_SPEAR_NORNANDBOOT) ==
- CONFIG_SPEAR_NORNAND16BOOT)
+ if ((bootstrap MISC_NORNANDBOOT) == MISC_NORNAND16BOOT)
return TRUE;
}
@@ -170,12 +168,10 @@ int nand_boot_selected(void)
if (NAND_BOOT_SUPPORTED) {
/* Check whether NAND boot is selected */
- if ((bootstrap CONFIG_SPEAR_NORNANDBOOT) ==
- CONFIG_SPEAR_NORNAND8BOOT)
+ if ((bootstrap MISC_NORNANDBOOT) == MISC_NORNAND8BOOT)
return TRUE;
- if ((bootstrap CONFIG_SPEAR_NORNANDBOOT) ==
- CONFIG_SPEAR_NORNAND16BOOT)
+ if ((bootstrap MISC_NORNANDBOOT) == MISC_NORNAND16BOOT)
return TRUE;
}
@@ -194,7 +190,7 @@ int usb_boot_selected(void)
if (USB_BOOT_SUPPORTED) {
/* Check whether USB boot is selected */
- if (!(bootstrap CONFIG_SPEAR_USBBOOT))
+ if (!(bootstrap MISC_USBBOOT))
return TRUE;
}
diff --git a/arch/arm/include/asm/arch-spear/misc.h
b/arch/arm/include/asm/arch-spear/misc.h
index 89f7964..2696203 100644
--- a/arch/arm/include/asm/arch-spear/misc.h
+++ b/arch/arm/include/asm/arch-spear/misc.h
@@ -137,12 +137,18 @@ struct misc_regs {
#define MISC_SOCCFG30 0x000C
#define MISC_SOCCFG31 0x000D
#define MISC_NANDDIS 0x0002
+#define MISC_BOOTSTRAPMASK 0x000B
+#define MISC_ONLYSNORBOOT 0x000A
+#define MISC_NORNANDBOOT 0x000B
+#define MISC_NORNAND8BOOT 0x0008
+#define MISC_NORNAND16BOOT 0x0009
+#define MISC_USBBOOT 0x0008
/* PERIPH_CLK_CFG value */
#define MISC_GPT3SYNTH 0x0400
#define MISC_GPT4SYNTH 0x0800
-#define CONFIG_SPEAR_UART48M 0
-#define CONFIG_SPEAR_UARTCLKMSK(0x1 4)
+#define MISC_UART48M 0x
+#define MISC_UARTCLKMSK0x0010
/* PRSC_CLK_CFG value */
/*
--
1.7.11.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [SPEAr Fixes PATCH 04/11] spear/board: Cleanup spear related board files
This patch targets to cleanup the board area for spear. The modifications in
this patch include
- Move spear board files to board/st/spear/
- Place specific init routines in respective macro
Place board_nand_init and board_eth_init in respective CONFIG_CMD_ macros
- Remove initialization of bi_arch_number
bi_arch_number gets initialized via CONFIG_MACH_TYPE through the uboot
framework itself obviating the need of this code
- Remove misc_init_r routine
- Remove routine dram_init_banksize
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
board/spear/common/Makefile| 50 --
board/spear/spear300/Makefile | 45 ---
board/spear/spear320/Makefile | 45 ---
board/spear/x600/Makefile | 47
board/{spear/spear600 = st/spear}/Makefile| 16 ++-
.../spear310/Makefile = st/spear/config.mk} | 27 ++--
.../spear300/spear300.c = st/spear/spear300evb.c} | 12 +++---
.../spear310/spear310.c = st/spear/spear310evb.c} | 12 +++---
.../spear320/spear320.c = st/spear/spear320plc.c} | 11 +++--
.../spear600/spear600.c = st/spear/spear600evb.c} | 13 +++---
.../common/spr_misc.c = st/spear/spear_common.c} | 34 ++-
.../spear/spear_lowlevel_init.S} | 0
board/{spear/x600 = st/spear}/x600.c | 0
board/{spear/x600/fpga.c = st/spear/x600fpga.c} | 0
board/{spear/x600/fpga.h = st/spear/x600fpga.h} | 0
boards.cfg | 28 ++--
16 files changed, 61 insertions(+), 279 deletions(-)
delete mode 100644 board/spear/common/Makefile
delete mode 100644 board/spear/spear300/Makefile
delete mode 100644 board/spear/spear320/Makefile
delete mode 100644 board/spear/x600/Makefile
rename board/{spear/spear600 = st/spear}/Makefile (76%)
rename board/{spear/spear310/Makefile = st/spear/config.mk} (56%)
rename board/{spear/spear300/spear300.c = st/spear/spear300evb.c} (94%)
rename board/{spear/spear310/spear310.c = st/spear/spear310evb.c} (95%)
rename board/{spear/spear320/spear320.c = st/spear/spear320plc.c} (95%)
rename board/{spear/spear600/spear600.c = st/spear/spear600evb.c} (94%)
rename board/{spear/common/spr_misc.c = st/spear/spear_common.c} (89%)
rename board/{spear/common/spr_lowlevel_init.S =
st/spear/spear_lowlevel_init.S} (100%)
rename board/{spear/x600 = st/spear}/x600.c (100%)
rename board/{spear/x600/fpga.c = st/spear/x600fpga.c} (100%)
rename board/{spear/x600/fpga.h = st/spear/x600fpga.h} (100%)
diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile
deleted file mode 100644
index 5c66c3f..000
--- a/board/spear/common/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
-endif
-
-LIB= $(obj)lib$(VENDOR).o
-
-ifndef CONFIG_SPL_BUILD
-COBJS := spr_misc.o
-SOBJS := spr_lowlevel_init.o
-endif
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB):$(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#
diff --git a/board/spear/spear300/Makefile b/board/spear/spear300/Makefile
deleted file mode 100644
index aa10749..000
--- a/board/spear/spear300/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later
