[PATCH v2] configs: ls1028aqds: add lpuart config

[Yuantian Tang]

Add lpuart config to enable lpuart feature.

Signed-off-by: Vabhav Sharma 
Signed-off-by: Yuantian Tang .
---
v2:
- fix buildman compiling warnings
 board/freescale/ls1028a/MAINTAINERS |  1 +
 configs/ls1028aqds_tfa_lpuart_defconfig | 88 +
 2 files changed, 89 insertions(+)
 create mode 100644 configs/ls1028aqds_tfa_lpuart_defconfig

diff --git a/board/freescale/ls1028a/MAINTAINERS 
b/board/freescale/ls1028a/MAINTAINERS
index 2c28825..5b7a8db 100644
--- a/board/freescale/ls1028a/MAINTAINERS
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -8,6 +8,7 @@ F:  board/freescale/ls1028a/
 F: include/configs/ls1028a_common.h
 F: include/configs/ls1028aqds.h
 F: configs/ls1028aqds_tfa_defconfig
+F: configs/ls1028aqds_tfa_lpuart_defconfig
 
 LS1028ARDB BOARD
 M: Sudhanshu Gupta 
diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig 
b/configs/ls1028aqds_tfa_lpuart_defconfig
new file mode 100644
index 000..417f292
--- /dev/null
+++ b/configs/ls1028aqds_tfa_lpuart_defconfig
@@ -0,0 +1,88 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028AQDS=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x4
+CONFIG_ENV_OFFSET=0x50
+CONFIG_DM_GPIO=y
+CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 
earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x200 default_hugepagesz=2m 
hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x2050
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_E1000=y
+CONFIG_FSL_ENETC=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-- 
2.9.5

[PATCH v3] armv8: ls1046ardb: update the WRLVL_START to accommodate more DIMM

[Yuantian Tang]

The WRLVL_START values are optimized for old DDR MTA18ASF1G72AZ.
Update DDR struct to set new WRLVL_START values so that the new DIMM
MTA18ADF2G72AZ get optimized and the old DIMM still works.

Signed-off-by: Yuantian Tang 
---
v3:
- fix typo
 board/freescale/ls1046ardb/ddr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h
index 3b4d44d465..05baef232a 100644
--- a/board/freescale/ls1046ardb/ddr.h
+++ b/board/freescale/ls1046ardb/ddr.h
@@ -32,7 +32,7 @@ static const struct board_specific_parameters udimm0[] = {
{2,  1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2,  1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2,  1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
-   {2,  2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},
+   {2,  2300, 0, 8, 7, 0x08090A0E, 0x1011120C,},
{}
 };
 
-- 
2.17.1

[PATCH v2] armv8: ls1046ardb: update the WRLVL_START to accomadate more DIMM

[Yuantian Tang]

The WRLVL_START values are optimized for old DDR MTA18ASF1G72AZ.
Update DDR struct to set new WRLVL_START values so that the new DIMM
MTA18ADF2G72AZ get optimized and the old DIMM still works.

Signed-off-by: Yuantian Tang 
---
v2:
- refine the commit message
 board/freescale/ls1046ardb/ddr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h
index 3b4d44d465..05baef232a 100644
--- a/board/freescale/ls1046ardb/ddr.h
+++ b/board/freescale/ls1046ardb/ddr.h
@@ -32,7 +32,7 @@ static const struct board_specific_parameters udimm0[] = {
{2,  1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2,  1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2,  1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
-   {2,  2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},
+   {2,  2300, 0, 8, 7, 0x08090A0E, 0x1011120C,},
{}
 };
 
-- 
2.17.1

[PATCH 2/2] arm64: ls1046a: remove fdt_high environment variable

[Yuantian Tang]

Setting fdt_high and initrd_high to 0x leads to
various difficulty to resolve bugs.
Remove them and use bootm_size instead to safely contain a kernel,
device tree and initrd for relocation.

Signed-off-by: Yuantian Tang 
---
 include/configs/ls1046a_common.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 3944f87794..978df3c947 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -217,8 +217,7 @@
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
"ramdisk_addr=0x80\0"   \
"ramdisk_size=0x200\0"  \
-   "fdt_high=0x\0" \
-   "initrd_high=0x\0"  \
+   "bootm_size=0x1000\0"   \
"fdt_addr=0x64f0\0" \
"kernel_addr=0x6500\0"  \
"scriptaddr=0x8000\0"   \
-- 
2.17.1

[PATCH 1/2] arm64: ls1028a: remove fdt_high environment variable

[Yuantian Tang]

Setting fdt_high and initrd_high to 0x leads to
various difficulty to resolve bugs.
Remove them and use bootm_size instead to safely contain a kernel,
device tree and initrd for relocation.

Signed-off-by: Yuantian Tang 
---
 include/configs/ls1028a_common.h | 3 +--
 include/configs/ls1028aqds.h | 2 --
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 05b8cf00ee..1c7680c234 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -79,8 +79,7 @@
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
"ramdisk_addr=0x80\0"   \
"ramdisk_size=0x200\0"  \
-   "fdt_high=0x\0" \
-   "initrd_high=0x\0"  \
+   "bootm_size=0x1000\0"   \
"fdt_addr=0x00f0\0" \
"kernel_addr=0x0100\0"  \
"scriptaddr=0x8000\0"   \
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index 982df07bb0..fca0a3af19 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -90,8 +90,6 @@
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"ramdisk_addr=0x80\0" \
"ramdisk_size=0x200\0" \
-   "fdt_high=0x\0" \
-   "initrd_high=0x\0" \
"fdt_addr=0x00f0\0" \
"kernel_addr=0x0100\0" \
"scriptaddr=0x8000\0" \
-- 
2.17.1

[U-Boot] [PATCH v3] armv8: ls1028a: Add environment variables to facilitate the boot

[Yuantian Tang]

Add some environment variables to facilitate the auto boot.

Signed-off-by: Yuantian Tang 
---
v3:
- rebase to the latest code
 include/configs/ls1028a_common.h | 28 +---
 1 file changed, 25 insertions(+), 3 deletions(-)

diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 0db86396e9..022981bfa3 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -67,6 +67,7 @@
 
 #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
+   func(MMC, mmc, 1) \
func(USB, usb, 0)
 #include 
 
@@ -127,25 +128,46 @@
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};"\
"source ${scriptaddr}\0"  \
-   "sd_bootcmd=echo Trying load from SD ..;"   \
+   "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
+   "sf probe 0:0 && sf read $load_addr " \
+   "$kernel_start $kernel_size ; env exists secureboot &&" \
+   "sf read $kernelheader_addr_r $kernelheader_start " \
+   "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+   " bootm $load_addr#$board\0" \
+   "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
+   "sf probe 0:0 && sf read $load_addr 0x94 0x3 " \
+   "&& hdp load $load_addr 0x2000\0"   \
+   "sd_bootcmd=echo Trying load from SD ...;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && "   \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0" \
+   "sd_hdploadcmd=echo Trying load HDP firmware from SD..;"\
+   "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
+   "&& hdp load $load_addr 0x2000\0"   \
"emmc_bootcmd=echo Trying load from EMMC ..;"   \
"mmcinfo; mmc dev 1; mmc read $load_addr "  \
"$kernel_addr_sd $kernel_size_sd && "   \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
-   "bootm $load_addr#$board\0"
+   "bootm $load_addr#$board\0" \
+   "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;"  \
+   "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 "   \
+   "&& hdp load $load_addr 0x2000\0"
 
 #undef CONFIG_BOOTCOMMAND
 
+#define XSPI_NOR_BOOTCOMMAND   \
+   "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
+   "env exists secureboot && esbc_halt;;"
 #define SD_BOOTCOMMAND \
-   "run distro_bootcmd;run sd_bootcmd; " \
+   "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
+   "env exists secureboot && esbc_halt;"
+#define SD2_BOOTCOMMAND\
+   "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
"env exists secureboot && esbc_halt;"
 
 /* Monitor Command Prompt */
-- 
2.17.1

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[U-Boot] [PATCH v2] armv8: ls1028a: disable multimedia feature when not supported

[Yuantian Tang]

ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a.
Both ls1027a and ls1017a personalities are lower functionality version
which doesn't support the multimedia subsystems, like LCD, GPU.

To disable multimedia feature on non-multimedia version, set the status
property to disabled in dts nodes.

Signed-off-by: Tang Yuantian 
---
v2:
- use micro to replace hardcoded number

 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 23 +++
 .../arm/include/asm/arch-fsl-layerscape/soc.h |  3 +++
 2 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 19917b207a..e993209593 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -401,6 +401,26 @@ void fdt_fixup_remove_jr(void *blob)
 }
 #endif
 
+#ifdef CONFIG_ARCH_LS1028A
+static void fdt_disable_multimedia(void *blob, unsigned int svr)
+{
+   int off;
+
+   if (IS_MULTIMEDIA_EN(svr))
+   return;
+
+   /* Disable eDP/LCD node */
+   off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
+   if (off != -FDT_ERR_NOTFOUND)
+   fdt_status_disabled(blob, off);
+
+   /* Disable GPU node */
+   off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
+   if (off != -FDT_ERR_NOTFOUND)
+   fdt_status_disabled(blob, off);
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -462,4 +482,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
fdt_fixup_msi(blob);
 #endif
+#ifdef CONFIG_ARCH_LS1028A
+   fdt_disable_multimedia(blob, svr);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 234440b5fe..485ea66591 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -112,6 +112,9 @@ enum boot_src get_boot_src(void);
 #ifdef CONFIG_ARCH_LX2160A
 #define IS_C_PROCESSOR(svr)(!((svr >> 12) & 0x1))
 #endif
+#ifdef CONFIG_ARCH_LS1028A
+#define IS_MULTIMEDIA_EN(svr)  (!((svr >> 10) & 0x1))
+#endif
 #define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
 #define SVR_DEV(svr)   ((svr) >> 8)
-- 
2.17.1

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[U-Boot] [PATCH] armv8: ls1028a: disable multimedia feature when not supported

[Yuantian Tang]

Ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a.
Both ls1027a and ls1017a personalities are lower functionality version
which doesn't support the multimedia subsystems, like LCD, GPU.

To disable multimedia feature on non-multimedia version, set the status
property to disabled in dts nodes.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 19917b207a..ef0e2095a6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -401,6 +401,24 @@ void fdt_fixup_remove_jr(void *blob)
 }
 #endif
 
+static void fdt_disable_multimedia(void *blob, unsigned int svr)
+{
+   int off;
+
+   if (!((svr >> 10) & 0x1))
+   return;
+
+   /* Disable eDP/LCD node */
+   off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
+   if (off != -FDT_ERR_NOTFOUND)
+   fdt_status_disabled(blob, off);
+
+   /* Disable GPU node */
+   off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
+   if (off != -FDT_ERR_NOTFOUND)
+   fdt_status_disabled(blob, off);
+}
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -462,4 +480,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
fdt_fixup_msi(blob);
 #endif
+#ifdef CONFIG_ARCH_LS1028A
+   fdt_disable_multimedia(blob, svr);
+#endif
 }
-- 
2.17.1

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[U-Boot] [PATCH v2] armv8: ls1028a: add more personalities support

[Yuantian Tang]

Add LS1027A, LS1018A and LS1017A  personalities support to
LS1028A processor soc family.

LS1028A processor is the prime personality of LS1028A soc family.
LS1027A processor is a lower funtionality version of QorIQ LS1028A
which does not support the multimedia subsystems, such as LCD
controller, GPU, and eDP PHY.
The QorIQ LS1018A and LS1017A are low power versions of the QorIQ
LS1028A and LS1027A processors, respectively which integrate single
64-bit Arm A72 core.

Signed-off-by: Tang Yuantian 
---
v2:
- refine description
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 +++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 3e2a24fe80..dee96afe2d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -58,6 +58,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+   CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
+   CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
+   CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h

--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -83,6 +83,9 @@ enum boot_src get_boot_src(void);
 /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
 #define SVR_LS1043A_P230x879202
 #define SVR_LS1023A_P230x87920A
+#define SVR_LS1017A0x870B24
+#define SVR_LS1018A0x870B20
+#define SVR_LS1027A0x870B04
 #define SVR_LS1028A0x870B00
 #define SVR_LS1046A0x870700
 #define SVR_LS1026A0x870708
-- 
2.17.1

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[U-Boot] [PATCH] armv8: ls1028a: add more personalities support

[Yuantian Tang]

Add LS1027A, LS1018A and LS1017A  personalities support to
LS1028A processor soc family.

LS1028A processor is the prime personality of LS1028A soc family.
LS1027A processor is a lower funtionality version of QorIQ LS1028A
which does not support the multimedia subsystems, such as LCD
controller, GPU, and eDP PHY.
The QorIQ LS1018A and LS1017A are low power versions of the QorIQ
LS1028A and LS1027A processors, respectively which integrate single
64-bit Arm A72 core.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 +++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 3e2a24fe80..dee96afe2d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -58,6 +58,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+   CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
+   CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
+   CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h

--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -83,6 +83,9 @@ enum boot_src get_boot_src(void);
 /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
 #define SVR_LS1043A_P230x879202
 #define SVR_LS1023A_P230x87920A
+#define SVR_LS1017A0x870B24
+#define SVR_LS1018A0x870B20
+#define SVR_LS1027A0x870B04
 #define SVR_LS1028A0x870B00
 #define SVR_LS1046A0x870700
 #define SVR_LS1026A0x870708
-- 
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[U-Boot] [PATCH] armv8: ls1028a: add more personalities support

[Yuantian Tang]

Add three more personalities support to LS1028A processor soc family.

LS1028A processor is the prime personality of LS1028A soc family.
LS1027A processor is a lower funtionality version of QorIQ LS1028A
which does not support the multimedia subsystems, such as LCD
controller, GPU, and eDP PHY.
The QorIQ LS1018A and LS1017A are low power versions of the QorIQ
LS1028A and LS1027A processors, respectively which integrate single
64-bit Arm A72 core.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 +++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 3e2a24fe80..dee96afe2d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -58,6 +58,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+   CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
+   CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
+   CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 8d6541cb94..8bbf342d90 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -83,6 +83,9 @@ enum boot_src get_boot_src(void);
 /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
 #define SVR_LS1043A_P230x879202
 #define SVR_LS1023A_P230x87920A
+#define SVR_LS1017A0x870B24
+#define SVR_LS1018A0x870B20
+#define SVR_LS1027A0x870B04
 #define SVR_LS1028A0x870B00
 #define SVR_LS1046A0x870700
 #define SVR_LS1026A0x870708
-- 
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[U-Boot] [PATCH v2] armv8: ls1028a: select BOARD_LATE_INIT config

[Yuantian Tang]

Select BOARD_LATE_INIT for ls1028ardb and ls1028aqds targets
so that late init work can be done

Signed-off-by: Yuantian Tang 
---
v2:
- refine commit message
 arch/arm/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 958d048971..8b6a68367e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1207,6 +1207,7 @@ config TARGET_LS1028AQDS
select ARCH_LS1028A
select ARM64
select ARMV8_MULTIENTRY
+   select BOARD_LATE_INIT
help
  Support for Freescale LS1028AQDS platform
  The LS1028A Development System (QDS) is a high-performance
@@ -1218,6 +1219,7 @@ config TARGET_LS1028ARDB
select ARCH_LS1028A
select ARM64
select ARMV8_MULTIENTRY
+   select BOARD_LATE_INIT
help
  Support for Freescale LS1028ARDB platform
  The LS1028A Development System (RDB) is a high-performance
-- 
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[U-Boot] [PATCH] armv8: ls1028a: add BOARD_LATE_INIT config

[Yuantian Tang]

Add CONFIG_BOARD_LATE_INIT config so that
many late init work can be done.

Signed-off-by: Yuantian Tang 
---
 arch/arm/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 958d048971..8b6a68367e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1207,6 +1207,7 @@ config TARGET_LS1028AQDS
select ARCH_LS1028A
select ARM64
select ARMV8_MULTIENTRY
+   select BOARD_LATE_INIT
help
  Support for Freescale LS1028AQDS platform
  The LS1028A Development System (QDS) is a high-performance
@@ -1218,6 +1219,7 @@ config TARGET_LS1028ARDB
select ARCH_LS1028A
select ARM64
select ARMV8_MULTIENTRY
+   select BOARD_LATE_INIT
help
  Support for Freescale LS1028ARDB platform
  The LS1028A Development System (RDB) is a high-performance
-- 
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[U-Boot] [PATCH v2] armv8: ls1028a: Add environment variables to facilitate the boot

[Yuantian Tang]

Add some environment variables to facilitate the auto boot.

Signed-off-by: Yuantian Tang 
---
v2:
- merge with its dependent patch
 include/configs/ls1028a_common.h | 28 +---
 1 file changed, 25 insertions(+), 3 deletions(-)

diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 0db86396e9..022981bfa3 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -67,6 +67,7 @@
 
 #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
+   func(MMC, mmc, 1) \
func(USB, usb, 0)
 #include 
 
@@ -127,25 +128,46 @@
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};"\
"source ${scriptaddr}\0"  \
-   "sd_bootcmd=echo Trying load from SD ..;"   \
+   "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
+   "sf probe 0:0 && sf read $load_addr " \
+   "$kernel_start $kernel_size ; env exists secureboot &&" \
+   "sf read $kernelheader_addr_r $kernelheader_start " \
+   "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+   " bootm $load_addr#$board\0" \
+   "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
+   "sf probe 0:0 && sf read $load_addr 0x94 0x3 " \
+   "&& hdp load $load_addr 0x2000\0"   \
+   "sd_bootcmd=echo Trying load from SD ...;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && "   \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0" \
+   "sd_hdploadcmd=echo Trying load HDP firmware from SD..;"\
+   "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
+   "&& hdp load $load_addr 0x2000\0"   \
"emmc_bootcmd=echo Trying load from EMMC ..;"   \
"mmcinfo; mmc dev 1; mmc read $load_addr "  \
"$kernel_addr_sd $kernel_size_sd && "   \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
-   "bootm $load_addr#$board\0"
+   "bootm $load_addr#$board\0" \
+   "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;"  \
+   "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 "   \
+   "&& hdp load $load_addr 0x2000\0"
 
 #undef CONFIG_BOOTCOMMAND
 
+#define XSPI_NOR_BOOTCOMMAND   \
+   "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
+   "env exists secureboot && esbc_halt;;"
 #define SD_BOOTCOMMAND \
-   "run distro_bootcmd;run sd_bootcmd; " \
+   "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
+   "env exists secureboot && esbc_halt;"
+#define SD2_BOOTCOMMAND\
+   "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
"env exists secureboot && esbc_halt;"
 
 /* Monitor Command Prompt */
-- 
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[U-Boot] [PATCH v2] common: qixis: make the qixis compatible with new soc

[Yuantian Tang]

This driver needs modification to work with new soc,
like ls1028, since bitmap of RCFG is changed to
RESV[7:5] LIVE[4] WDEN[3] RESV[2:1] GO[0]
   000  1   000  0

Also the RCW location is moved to only dutcfg0.
RESV[7:4] RCWSRC[3:0]
      configurable

Following commands are functional now
qixis_reset
qixis_reset sd
qixis_reset qspi
qixis_reset emmc

Signed-off-by: Ashish Kumar 
Signed-off-by: Yuantian Tang 
---
v2:
- refine the description
 board/freescale/common/qixis.c | 45 +-
 1 file changed, 33 insertions(+), 12 deletions(-)

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 2c4c4ae108..716c93b2c2 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -21,6 +21,13 @@
 #define QIXIS_LBMAP_BRDCFG_REG 0x00
 #endif
 
+#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#endif
+#ifndef QIXIS_RCFG_CTL_RECONFIG_START
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
@@ -159,11 +166,13 @@ static void qixis_reset(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
 }
 
+#ifdef QIXIS_LBMAP_ALTBANK
 static void qixis_bank_reset(void)
 {
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 }
+#endif
 
 static void __maybe_unused set_lbmap(int lbmap)
 {
@@ -176,12 +185,16 @@ static void __maybe_unused set_lbmap(int lbmap)
 
 static void __maybe_unused set_rcw_src(int rcw_src)
 {
+#ifdef CONFIG_NXP_LSCH3_2
+   QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff));
+#else
u8 reg;
 
reg = QIXIS_READ(dutcfg[1]);
reg = (reg & ~1) | (rcw_src & 1);
QIXIS_WRITE(dutcfg[1], reg);
QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
+#endif
 }
 
 static void qixis_dump_regs(void)
@@ -227,16 +240,20 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, 
int argc, char * const ar
set_lbmap(QIXIS_LBMAP_DFLTBANK);
qixis_reset();
} else if (strcmp(argv[1], "altbank") == 0) {
+#ifdef QIXIS_LBMAP_ALTBANK
set_lbmap(QIXIS_LBMAP_ALTBANK);
qixis_bank_reset();
+#else
+   printf("No Altbank!\n");
+#endif
} else if (strcmp(argv[1], "nand") == 0) {
 #ifdef QIXIS_LBMAP_NAND
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_NAND);
set_rcw_src(QIXIS_RCW_SRC_NAND);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
printf("Not implemented\n");
 #endif
@@ -250,8 +267,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const ar
set_lbmap(QIXIS_LBMAP_SD);
set_rcw_src(QIXIS_RCW_SRC_SD);
 #endif
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
printf("Not implemented\n");
 #endif
@@ -261,8 +278,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_IFC);
set_rcw_src(QIXIS_RCW_SRC_IFC);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
printf("Not implemented\n");
 #endif
@@ -272,8 +289,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_EMMC);
set_rcw_src(QIXIS_RCW_SRC_EMMC);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
printf("Not implemented\n");
 #endif
@@ -283,8 +300,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD_QSPI);
set_rcw_src(QIXIS_RCW_SRC_SD);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+   QI

[U-Boot] [PATCH] armv8: ls1028a: Add environment variables to facilitate the boot

[Yuantian Tang]

Add some environment variables to facilitate the auto boot.

Signed-off-by: Yuantian Tang 
---
 include/configs/ls1028a_common.h | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index aeb2c7251a..4f64c9fdb7 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -67,6 +67,7 @@
 
 #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
+   func(MMC, mmc, 1) \
func(USB, usb, 0)
 #include 
 
@@ -127,12 +128,14 @@
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};"\
"source ${scriptaddr}\0"  \
-   "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
+   "qspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
"sf probe 0:0 && sf read $load_addr " \
"$kernel_start $kernel_size ; env exists secureboot &&" \
"sf read $kernelheader_addr_r $kernelheader_start " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
" bootm $load_addr#$board\0" \
+   "qspi_hdploadcmd=echo Trying load HDP firmware from flexspi..;" \
+   "hdp load 0x2090 0x2000\0"  \
"sd_bootcmd=echo Trying load from SD ...;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && "   \
@@ -165,6 +168,9 @@
 #define SD_BOOTCOMMAND \
"run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
"env exists secureboot && esbc_halt;"
+#define SD2_BOOTCOMMAND\
+   "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
+   "env exists secureboot && esbc_halt;"
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE  512 /* Console I/O Buffer Size */
-- 
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[U-Boot] [PATCH] common: qixis: make the qixis compatible with new soc

[Yuantian Tang]

This driver needs modification to work with new soc,
like ls1028, since bitmap of RCFG is changed to
RESV[7:5] LIVE[4] WDEN[3] RESV[2:1] GO[0]
   000  1   000  0

Also the RCW location is moved to only dutcfg0.
RESV[7:4] RCWSRC[3:0]
      configurable

Following commands should be functional now
qixis_reset
qixis_reset sd
qixis_reset qspi
qixis_reset emmc

Signed-off-by: Ashish Kumar 
Signed-off-by: Yuantian Tang 
---
 board/freescale/common/qixis.c | 45 +-
 1 file changed, 33 insertions(+), 12 deletions(-)

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 2c4c4ae108..716c93b2c2 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -21,6 +21,13 @@
 #define QIXIS_LBMAP_BRDCFG_REG 0x00
 #endif
 
+#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#endif
+#ifndef QIXIS_RCFG_CTL_RECONFIG_START
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
@@ -159,11 +166,13 @@ static void qixis_reset(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
 }
 
+#ifdef QIXIS_LBMAP_ALTBANK
 static void qixis_bank_reset(void)
 {
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 }
+#endif
 
 static void __maybe_unused set_lbmap(int lbmap)
 {
@@ -176,12 +185,16 @@ static void __maybe_unused set_lbmap(int lbmap)
 
 static void __maybe_unused set_rcw_src(int rcw_src)
 {
+#ifdef CONFIG_NXP_LSCH3_2
+   QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff));
+#else
u8 reg;
 
reg = QIXIS_READ(dutcfg[1]);
reg = (reg & ~1) | (rcw_src & 1);
QIXIS_WRITE(dutcfg[1], reg);
QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
+#endif
 }
 
 static void qixis_dump_regs(void)
@@ -227,16 +240,20 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, 
int argc, char * const ar
set_lbmap(QIXIS_LBMAP_DFLTBANK);
qixis_reset();
} else if (strcmp(argv[1], "altbank") == 0) {
+#ifdef QIXIS_LBMAP_ALTBANK
set_lbmap(QIXIS_LBMAP_ALTBANK);
qixis_bank_reset();
+#else
+   printf("No Altbank!\n");
+#endif
} else if (strcmp(argv[1], "nand") == 0) {
 #ifdef QIXIS_LBMAP_NAND
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_NAND);
set_rcw_src(QIXIS_RCW_SRC_NAND);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
printf("Not implemented\n");
 #endif
@@ -250,8 +267,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const ar
set_lbmap(QIXIS_LBMAP_SD);
set_rcw_src(QIXIS_RCW_SRC_SD);
 #endif
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
printf("Not implemented\n");
 #endif
@@ -261,8 +278,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_IFC);
set_rcw_src(QIXIS_RCW_SRC_IFC);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
printf("Not implemented\n");
 #endif
@@ -272,8 +289,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_EMMC);
set_rcw_src(QIXIS_RCW_SRC_EMMC);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+   QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
printf("Not implemented\n");
 #endif
@@ -283,8 +300,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD_QSPI);
set_rcw_src(QIXIS_RCW_SRC_SD);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+   QI

[U-Boot] [PATCH] armv8: ls1028a: Add secure boot defconfig

[Yuantian Tang]

Add secure boot defconfig for ls1028aqds and ls1028ardb boards.

Signed-off-by: Yuantian Tang 
---
 configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 62 
 configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 62 
 include/configs/ls1028a_common.h |  4 ++
 3 files changed, 128 insertions(+)
 create mode 100644 configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1028ardb_tfa_SECURE_BOOT_defconfig

diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig 
b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
new file mode 100644
index 00..7cd2f59d7b
--- /dev/null
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028AQDS=y
+CONFIG_SECURE_BOOT=y
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_TFABOOT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 
earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x200 default_hugepagesz=2m 
hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig 
b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
new file mode 100644
index 00..3432f90087
--- /dev/null
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028ARDB=y
+CONFIG_SECURE_BOOT=y
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_TFABOOT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 
earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x200 default_hugepagesz=2m 
hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 9531548184..aeb2c7251a 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -215,4 +215,8 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
 
+#ifdef CONFIG_SECURE_BOOT
+#include 
+#endif
+
 #endif /* __L1028A_COMMON_H */
-- 
2.17.1

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[U-Boot] [PATCH v2] armv8: ls1028ardb: Add sd and emmc related environments

[Yuantian Tang]

Add SD, EMMC and xspi environments to faciliate the boot.

Signed-off-by: Yuantian Tang 
---
v2:
- rebase to latest code
 include/configs/ls1028a_common.h | 24 +---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 0db86396e9..9531548184 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -127,25 +127,43 @@
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};"\
"source ${scriptaddr}\0"  \
-   "sd_bootcmd=echo Trying load from SD ..;"   \
+   "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
+   "sf probe 0:0 && sf read $load_addr " \
+   "$kernel_start $kernel_size ; env exists secureboot &&" \
+   "sf read $kernelheader_addr_r $kernelheader_start " \
+   "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+   " bootm $load_addr#$board\0" \
+   "sd_bootcmd=echo Trying load from SD ...;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && "   \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0" \
+   "xspi_hdploadcmd=echo Trying load HDP firmware from 
FlexSPI...;" \
+   "sf probe 0:0 && sf read $load_addr 0x94 0x3 " \
+   "&& hdp load $load_addr 0x2000\0"   \
+   "sd_hdploadcmd=echo Trying load HDP firmware from SD..;"\
+   "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
+   "&& hdp load $load_addr 0x2000\0"   \
"emmc_bootcmd=echo Trying load from EMMC ..;"   \
"mmcinfo; mmc dev 1; mmc read $load_addr "  \
"$kernel_addr_sd $kernel_size_sd && "   \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
-   "bootm $load_addr#$board\0"
+   "bootm $load_addr#$board\0" \
+   "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;"  \
+   "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 "   \
+   "&& hdp load $load_addr 0x2000\0"
 
 #undef CONFIG_BOOTCOMMAND
 
+#define XSPI_NOR_BOOTCOMMAND   \
+   "run qspi_hdploadcmd; run distro_bootcmd; run qspi_bootcmd; " \
+   "env exists secureboot && esbc_halt;;"
 #define SD_BOOTCOMMAND \
-   "run distro_bootcmd;run sd_bootcmd; " \
+   "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
"env exists secureboot && esbc_halt;"
 
 /* Monitor Command Prompt */
-- 
2.17.1

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[U-Boot] [PATCH] armv8: ls1028ardb: Add sd and emmc related environments

[Yuantian Tang]

Add SD and EMMC environments to faciliate the boot.

Signed-off-by: Yuantian Tang 
---
 include/configs/ls1028a_common.h | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 10f2e88bfd..9531548184 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -127,15 +127,24 @@
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};"\
"source ${scriptaddr}\0"  \
-   "sd_bootcmd=echo Trying load from SD ..;"   \
+   "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
+   "sf probe 0:0 && sf read $load_addr " \
+   "$kernel_start $kernel_size ; env exists secureboot &&" \
+   "sf read $kernelheader_addr_r $kernelheader_start " \
+   "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+   " bootm $load_addr#$board\0" \
+   "sd_bootcmd=echo Trying load from SD ...;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && "   \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0" \
-   "sd_hdploadcmd=echo Trying load HDP firmware from SD..;"  \
-   "mmcinfo;mmc read $load_addr 0x4800 0x200 " \
+   "xspi_hdploadcmd=echo Trying load HDP firmware from 
FlexSPI...;" \
+   "sf probe 0:0 && sf read $load_addr 0x94 0x3 " \
+   "&& hdp load $load_addr 0x2000\0"   \
+   "sd_hdploadcmd=echo Trying load HDP firmware from SD..;"\
+   "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
"&& hdp load $load_addr 0x2000\0"   \
"emmc_bootcmd=echo Trying load from EMMC ..;"   \
"mmcinfo; mmc dev 1; mmc read $load_addr "  \
@@ -145,7 +154,7 @@
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0" \
"emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;"  \
-   "mmc dev 1;mmcinfo;mmc read $load_addr 0x4800 0x200 "   \
+   "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 "   \
"&& hdp load $load_addr 0x2000\0"
 
 #undef CONFIG_BOOTCOMMAND
-- 
2.17.1

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[U-Boot] [PATCH 3/3 v3] armv8: ls1028aqds: Add support of LS1028AQDS

[Yuantian Tang]

LS1028AQDS Development System is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.

Signed-off-by: Sudhanshu Gupta 
Signed-off-by: Rai Harninder 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Bhaskar Upadhaya 
Signed-off-by: Tang yuantian 
---
v3:
-- fix some issues
 arch/arm/Kconfig|  11 +++
 arch/arm/cpu/armv8/Kconfig  |   2 +-
 arch/arm/dts/fsl-ls1028a-qds.dts|  88 +++
 board/freescale/ls1028a/Kconfig |  39 +
 board/freescale/ls1028a/MAINTAINERS |  11 +++
 board/freescale/ls1028a/README  |  85 ++
 board/freescale/ls1028a/ls1028a.c   |  38 
 configs/ls1028aqds_tfa_defconfig|  61 +
 include/configs/ls1028aqds.h| 167 
 9 files changed, 501 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1028a-qds.dts
 create mode 100644 configs/ls1028aqds_tfa_defconfig
 create mode 100644 include/configs/ls1028aqds.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aaaf36a..7741ea2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1203,6 +1203,17 @@ config TARGET_LS1012AFRDM
  development platform that supports the QorIQ LS1012A
  Layerscape Architecture processor.
 
+config TARGET_LS1028AQDS
+   bool "Support ls1028aqds"
+   select ARCH_LS1028A
+   select ARM64
+   select ARMV8_MULTIENTRY
+   help
+ Support for Freescale LS1028AQDS platform
+ The LS1028A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1028A
+ Layerscape Architecture processor.
+
 config TARGET_LS1028ARDB
bool "Support ls1028ardb"
select ARCH_LS1028A
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index a4fa63b..3e9d47a 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -104,7 +104,7 @@ config PSCI_RESET
   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
   !TARGET_LS1012AFRWY && \
-  !TARGET_LS1028ARDB && \
+  !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts
new file mode 100644
index 000..46a0419
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028AQDS device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+   model = "NXP Layerscape 1028a QDS Board";
+   compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig
index bbfd4dd..ca22c92 100644
--- a/board/freescale/ls1028a/Kconfig
+++ b/board/freescale/ls1028a/Kconfig
@@ -1,3 +1,42 @@
+if TARGET_LS1028AQDS
+
+config SYS_BOARD
+   default "ls1028a"
+
+config SYS_VENDOR
+   default "freescale"
+
+config SYS_SOC
+   default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+   default "ls1028aqds"
+
+config EMMC_BOOT
+   bool "Support for booting from EMMC"
+   default n
+
+config SYS_TEXT_BASE
+   default 0x9600 if SD_BOOT || EMMC_BOOT
+   default 0x8200 if TFABOOT
+   default 0x2010
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+   hex "PPA Firmware Addr"
+   default 0x2040 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+   default 0x40 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+   hex "PPA header Addr"
+   default 0x2060 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
+
 if TARGET_LS1028ARDB
 
 config SYS_BOARD
diff --git a/board/freescale/ls1028a/MAINTAINERS 
b/board/freescale/ls1028a/MAINTAINERS
index 135454c..6f1a95e 100644
--- a/board/freescale/ls1028a/MAINTAINERS
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -1,3 +1,14 @@
+LS1028AQDS BOARD
+M: Sudhanshu Gupta 
+M: Rai 

[U-Boot] [PATCH 2/3 v3] armv8: ls1028ardb: Add support for LS1028ARDB platform

[Yuantian Tang]

LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluatoin
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Sudhanshu Gupta 
Signed-off-by: Rai Harninder 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Bhaskar Upadhaya 
Signed-off-by: Tang Yuantian 
---
v3:
- remove ddr fixed initialization
 arch/arm/Kconfig|  12 +++
 arch/arm/cpu/armv8/Kconfig  |   1 +
 arch/arm/dts/fsl-ls1028a-rdb.dts|  88 +++
 board/freescale/ls1028a/Kconfig |  26 +
 board/freescale/ls1028a/MAINTAINERS |  10 ++
 board/freescale/ls1028a/Makefile|   8 ++
 board/freescale/ls1028a/README  |  79 ++
 board/freescale/ls1028a/ddr.c   |  20 
 board/freescale/ls1028a/ls1028a.c   | 193 +
 configs/ls1028ardb_tfa_defconfig|  61 +++
 include/configs/ls1028a_common.h| 209 
 include/configs/ls1028ardb.h|  77 +
 12 files changed, 784 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1028a-rdb.dts
 create mode 100644 board/freescale/ls1028a/Kconfig
 create mode 100644 board/freescale/ls1028a/MAINTAINERS
 create mode 100644 board/freescale/ls1028a/Makefile
 create mode 100644 board/freescale/ls1028a/README
 create mode 100644 board/freescale/ls1028a/ddr.c
 create mode 100644 board/freescale/ls1028a/ls1028a.c
 create mode 100644 configs/ls1028ardb_tfa_defconfig
 create mode 100644 include/configs/ls1028a_common.h
 create mode 100644 include/configs/ls1028ardb.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f42ecce..aaaf36a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1203,6 +1203,17 @@ config TARGET_LS1012AFRDM
  development platform that supports the QorIQ LS1012A
  Layerscape Architecture processor.
 
+config TARGET_LS1028ARDB
+   bool "Support ls1028ardb"
+   select ARCH_LS1028A
+   select ARM64
+   select ARMV8_MULTIENTRY
+   help
+ Support for Freescale LS1028ARDB platform
+ The LS1028A Development System (RDB) is a high-performance
+ development platform that supports the QorIQ LS1028A
+ Layerscape Architecture processor.
+
 config TARGET_LS1088ARDB
bool "Support ls1088ardb"
select ARCH_LS1088A
@@ -1585,6 +1596,7 @@ source "board/freescale/ls2080a/Kconfig"
 source "board/freescale/ls2080aqds/Kconfig"
 source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1088a/Kconfig"
+source "board/freescale/ls1028a/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index f053603..a4fa63b 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -104,6 +104,7 @@ config PSCI_RESET
   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
   !TARGET_LS1012AFRWY && \
+  !TARGET_LS1028ARDB && \
   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
new file mode 100644
index 000..932cfa2
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028ARDB device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+   model = "NXP Layerscape 1028a RDB Board";
+   compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig
new file mode 100644
index 000..bbfd4dd
--- /dev/null
+++ b/board/freescale/ls1028a/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_LS1028ARDB
+
+config SYS_BOARD
+   default "ls1028a"
+
+config SYS_VENDOR
+   default "freescale"
+
+config SYS_SOC
+   default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+   default "ls1028ardb"
+
+config EMMC_BOOT
+   bool "Support for booting from EMMC"
+   default n
+
+config SYS_TEXT_BASE
+   default 0x9600 

[U-Boot] [PATCH 1/3 v3] armv8: ls1028a: Add NXP LS1028A SoC support

[Yuantian Tang]

Ls1028a Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
 ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.

Signed-off-by: Sudhanshu Gupta 
Signed-off-by: Rai Harninder 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Bhaskar Upadhaya 
Signed-off-by: Tang Yuantian 
---
v3:
-- fix some issues
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  39 ++-
 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|   3 +
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   |  51 
 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c |  73 ++
 arch/arm/dts/fsl-ls1028a.dtsi  | 280 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  61 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |   9 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   1 +
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h  |   2 +-
 10 files changed, 521 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
 create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f48481f..8ecd095 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -20,6 +20,40 @@ config ARCH_LS1012A
select SYS_I2C_MXC_I2C2
imply PANIC_HANG
 
+config ARCH_LS1028A
+   bool
+   select ARMV8_SET_SMPEN
+   select FSL_LSCH3
+   select NXP_LSCH3_2
+   select SYS_FSL_HAS_CCI400
+   select SYS_FSL_SRDS_1
+   select SYS_HAS_SERDES
+   select SYS_FSL_DDR
+   select SYS_FSL_DDR_LE
+   select SYS_FSL_DDR_VER_50
+   select SYS_FSL_HAS_DDR3
+   select SYS_FSL_HAS_DDR4
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_5
+   select SYS_FSL_SEC_LE
+   select FSL_TZASC_1
+   select ARCH_EARLY_INIT_R
+   select BOARD_EARLY_INIT_F
+   select SYS_I2C_MXC
+   select SYS_I2C_MXC_I2C1
+   select SYS_I2C_MXC_I2C2
+   select SYS_I2C_MXC_I2C3
+   select SYS_I2C_MXC_I2C4
+   select SYS_I2C_MXC_I2C5
+   select SYS_I2C_MXC_I2C6
+   select SYS_I2C_MXC_I2C7
+   select SYS_I2C_MXC_I2C8
+   select SYS_FSL_ERRATUM_A009007
+   select SYS_FSL_ERRATUM_A008514 if !TFABOOT
+   select SYS_FSL_ERRATUM_A009663 if !TFABOOT
+   select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+   imply PANIC_HANG
+
 config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
@@ -244,6 +278,7 @@ config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
depends on PCIE_LAYERSCAPE
default "fsl,ls1012a-pcie" if ARCH_LS1012A
+   default "fsl,ls1028a-pcie" if ARCH_LS1028A
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
@@ -343,6 +378,7 @@ config SYS_FSL_ERRATUM_A010539
 
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
+   default 2 if ARCH_LS1028A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
@@ -377,7 +413,7 @@ config QSPI_AHB_INIT
 config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
-   default 0x309 if ARCH_LS1088A
+   default 0x309 if ARCH_LS1088A || ARCH_LS1028A
default 0x18 if FSL_LSCH2
help
  Offset for CCI400 base
@@ -446,6 +482,7 @@ config CLUSTER_CLK_FREQ
 
 config SYS_FSL_PCLK_DIV
int "Platform clock divider"
+   default 1 if ARCH_LS1028A
default 1 if ARCH_LS1043A
default 1 if ARCH_LS1046A
default 1 if ARCH_LS1088A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index e9bc987..a8d3cf9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -48,3 +48,7 @@ endif
 ifneq ($(CONFIG_ARCH_LS1088A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
 endif
+
+ifneq ($(CONFIG_ARCH_LS1028A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b..c258f2e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -58,6 +58,7 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+   CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
@@ -246,11 +247,13 @@ static 

[U-Boot] [PATCH 2/3 v2] armv8: ls1028ardb: Add support for LS1028ARDB platform

[Yuantian Tang]

From: Tang Yuantian 

LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluatoin
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Sudhanshu Gupta 
Signed-off-by: Rai Harninder 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Bhaskar Upadhaya 
Signed-off-by: Tang Yuantian 
---
v2:
- fix many issues
 arch/arm/Kconfig|  12 ++
 arch/arm/cpu/armv8/Kconfig  |   1 +
 arch/arm/dts/fsl-ls1028a-rdb.dts|  92 
 arch/arm/dts/fsl-ls1028a.dtsi   |   2 +-
 board/freescale/ls1028a/Kconfig |  38 +
 board/freescale/ls1028a/MAINTAINERS |  10 ++
 board/freescale/ls1028a/Makefile|   8 +
 board/freescale/ls1028a/README  |  79 ++
 board/freescale/ls1028a/ddr.c   | 284 
 board/freescale/ls1028a/ddr.h   |  46 ++
 board/freescale/ls1028a/ls1028a.c   | 194 
 configs/ls1028ardb_tfa_defconfig|  61 
 include/configs/ls1028a_common.h| 243 ++
 include/configs/ls1028ardb.h|  82 +++
 14 files changed, 1151 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1028a-rdb.dts
 create mode 100644 board/freescale/ls1028a/Kconfig
 create mode 100644 board/freescale/ls1028a/MAINTAINERS
 create mode 100644 board/freescale/ls1028a/Makefile
 create mode 100644 board/freescale/ls1028a/README
 create mode 100644 board/freescale/ls1028a/ddr.c
 create mode 100644 board/freescale/ls1028a/ddr.h
 create mode 100644 board/freescale/ls1028a/ls1028a.c
 create mode 100644 configs/ls1028ardb_tfa_defconfig
 create mode 100644 include/configs/ls1028a_common.h
 create mode 100644 include/configs/ls1028ardb.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f42ecce..aaaf36a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1203,6 +1203,17 @@ config TARGET_LS1012AFRDM
  development platform that supports the QorIQ LS1012A
  Layerscape Architecture processor.
 
+config TARGET_LS1028ARDB
+   bool "Support ls1028ardb"
+   select ARCH_LS1028A
+   select ARM64
+   select ARMV8_MULTIENTRY
+   help
+ Support for Freescale LS1028ARDB platform
+ The LS1028A Development System (RDB) is a high-performance
+ development platform that supports the QorIQ LS1028A
+ Layerscape Architecture processor.
+
 config TARGET_LS1088ARDB
bool "Support ls1088ardb"
select ARCH_LS1088A
@@ -1585,6 +1596,7 @@ source "board/freescale/ls2080a/Kconfig"
 source "board/freescale/ls2080aqds/Kconfig"
 source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1088a/Kconfig"
+source "board/freescale/ls1028a/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index f053603..a4fa63b 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -104,6 +104,7 @@ config PSCI_RESET
   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
   !TARGET_LS1012AFRWY && \
+  !TARGET_LS1028ARDB && \
   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
new file mode 100644
index 000..e86ba06
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028ARDB device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+   model = "NXP Layerscape 1028a RDB Board";
+   compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index a38c8ce..31e1aef 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -276,5 +276,5 @@
interrupts = <0 133 4>;
clocks = < 4 1>;
status = "disabled";
- };
+   };
 };
diff 

[U-Boot] [PATCH 3/3 v2] armv8: ls1028aqds: Add support of LS1028AQDS

[Yuantian Tang]

From: Tang Yuantian 

LS1028AQDS Development System is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.

Signed-off-by: Sudhanshu Gupta 
Signed-off-by: Rai Harninder 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Bhaskar Upadhaya 
Signed-off-by: Tang yuantian 
---
v2:
- fix many issues
 arch/arm/Kconfig|  11 +++
 arch/arm/cpu/armv8/Kconfig  |   2 +-
 arch/arm/dts/fsl-ls1028a-qds.dts|  92 +++
 board/freescale/ls1028a/Kconfig |  39 
 board/freescale/ls1028a/MAINTAINERS |  11 +++
 board/freescale/ls1028a/README  |  85 +
 board/freescale/ls1028a/ls1028a.c   |  38 
 configs/ls1028aqds_tfa_defconfig|  61 +
 include/configs/ls1028aqds.h| 176 
 9 files changed, 514 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1028a-qds.dts
 create mode 100644 configs/ls1028aqds_tfa_defconfig
 create mode 100644 include/configs/ls1028aqds.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aaaf36a..7741ea2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1203,6 +1203,17 @@ config TARGET_LS1012AFRDM
  development platform that supports the QorIQ LS1012A
  Layerscape Architecture processor.
 
+config TARGET_LS1028AQDS
+   bool "Support ls1028aqds"
+   select ARCH_LS1028A
+   select ARM64
+   select ARMV8_MULTIENTRY
+   help
+ Support for Freescale LS1028AQDS platform
+ The LS1028A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1028A
+ Layerscape Architecture processor.
+
 config TARGET_LS1028ARDB
bool "Support ls1028ardb"
select ARCH_LS1028A
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index a4fa63b..3e9d47a 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -104,7 +104,7 @@ config PSCI_RESET
   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
   !TARGET_LS1012AFRWY && \
-  !TARGET_LS1028ARDB && \
+  !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts
new file mode 100644
index 000..ee8a0c2
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds.dts
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028AQDS device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+   model = "NXP Layerscape 1028a QDS Board";
+   compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig
index f4733c2..f8c2fe8 100644
--- a/board/freescale/ls1028a/Kconfig
+++ b/board/freescale/ls1028a/Kconfig
@@ -1,3 +1,42 @@
+if TARGET_LS1028AQDS
+
+config SYS_BOARD
+   default "ls1028a"
+
+config SYS_VENDOR
+   default "freescale"
+
+config SYS_SOC
+   default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+   default "ls1028aqds"
+
+config EMMC_BOOT
+   bool "Support for booting from EMMC"
+   default n
+
+config SYS_TEXT_BASE
+   default 0x9600 if SD_BOOT || EMMC_BOOT
+   default 0x8200 if TFABOOT
+   default 0x2010
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+   hex "PPA Firmware Addr"
+   default 0x2040 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+   default 0x40 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+   hex "PPA header Addr"
+   default 0x2060 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
+
 if TARGET_LS1028ARDB
 
 config SYS_BOARD
diff --git a/board/freescale/ls1028a/MAINTAINERS 
b/board/freescale/ls1028a/MAINTAINERS
index 135454c..6f1a95e 100644
--- a/board/freescale/ls1028a/MAINTAINERS
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -1,3 +1,14 @@

[U-Boot] [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support

[Yuantian Tang]

LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with a
GPU and LCD controller, as well as TSN-enabled Ethernet ports and a
TSN-enabled switch with four external ports.
The high performance Cortex-A72 cores, performing above 16,000 CoreMarks,
combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0
and Octal/Quad SPI interfaces provide capabilities for a number of
industrial and embedded applications. The device provides excellent
integration with the new Time-Sensitive Networking standards and enables
a number of TSN applications

Features Summary
* Two 32/64-bit Arm v8 Cortex-A72 CPUs
* Cache coherent interconnect fabric (CCI-400)
* 32-bit DDR3L/DDR4 SDRAM memory controller with ECC support
* LCD controller and DisplayPort/eDP interface
* Graphics processing unit
* TSN-capable Ethernet Switch with four external ports
* Ethernet Controller (ENETC) with TSN functionality
* Four SerDes lanes with two PLLs for high-speed peripheral interfaces
* Additional peripheral interfaces
* Two high-speed USB 3.0 controllers
* Two eSDHC controllers
* Two controller area network (FlexCAN) modules
* supporting flexible datarate (FD)
* Three serial peripheral interface (SPI) controllers
* Flexible SPI interface (FlexSPI) controller
* Eight I2C controllers
* Six LPUARTs
* 16550-compliant DUART
* General Purpose IO (GPIO)
* Eight FlexTimers/PWM controllers
* Six asynchronous audio interface (SAI)
* Support for hardware virtualization and partitioning enforcement
* QorIQ platform's trust architecture 3.0
* Queue direct memory access controller (qDMA)
* Enhanced direct memory access controller (eDMA)
* Global programmable interrupt controller (GIC)
* Arm generic timer
* Thermal Monitor Unit (TMU)

Signed-off-by: Sudhanshu Gupta 
Signed-off-by: Rai Harninder 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Bhaskar Upadhaya 
Signed-off-by: Tang Yuantian 
---
v2:
- fix many issues
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  39 ++-
 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|   3 +
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   |  51 
 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c |  88 +++
 arch/arm/dts/fsl-ls1028a.dtsi  | 280 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  61 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |  16 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |   9 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   1 +
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h  |   2 +-
 11 files changed, 552 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
 create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f48481f..8ecd095 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -20,6 +20,40 @@ config ARCH_LS1012A
select SYS_I2C_MXC_I2C2
imply PANIC_HANG
 
+config ARCH_LS1028A
+   bool
+   select ARMV8_SET_SMPEN
+   select FSL_LSCH3
+   select NXP_LSCH3_2
+   select SYS_FSL_HAS_CCI400
+   select SYS_FSL_SRDS_1
+   select SYS_HAS_SERDES
+   select SYS_FSL_DDR
+   select SYS_FSL_DDR_LE
+   select SYS_FSL_DDR_VER_50
+   select SYS_FSL_HAS_DDR3
+   select SYS_FSL_HAS_DDR4
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_5
+   select SYS_FSL_SEC_LE
+   select FSL_TZASC_1
+   select ARCH_EARLY_INIT_R
+   select BOARD_EARLY_INIT_F
+   select SYS_I2C_MXC
+   select SYS_I2C_MXC_I2C1
+   select SYS_I2C_MXC_I2C2
+   select SYS_I2C_MXC_I2C3
+   select SYS_I2C_MXC_I2C4
+   select SYS_I2C_MXC_I2C5
+   select SYS_I2C_MXC_I2C6
+   select SYS_I2C_MXC_I2C7
+   select SYS_I2C_MXC_I2C8
+   select SYS_FSL_ERRATUM_A009007
+   select SYS_FSL_ERRATUM_A008514 if !TFABOOT
+   select SYS_FSL_ERRATUM_A009663 if !TFABOOT
+   select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+   imply PANIC_HANG
+
 config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
@@ -244,6 +278,7 @@ config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
depends on PCIE_LAYERSCAPE
default "fsl,ls1012a-pcie" if ARCH_LS1012A
+   default "fsl,ls1028a-pcie" if ARCH_LS1028A
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
@@ -343,6 +378,7 @@ config SYS_FSL_ERRATUM_A010539
 
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
+   default 2 if ARCH_LS1028A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
@@ -377,7 

[U-Boot] [PATCH 1/2] arm64: ls1046a: Add sata distro boot support

[Yuantian Tang]

Sata is equipped on ls1046a and can be a boot source.
Add sata boot support as a option if available.

Signed-off-by: Tang Yuantian 
---
 include/configs/ls1046a_common.h |   13 +
 include/configs/ls1046aqds.h |   10 --
 include/configs/ls1046ardb.h |   12 
 3 files changed, 13 insertions(+), 22 deletions(-)

diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index e208f7d..309bfd8 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -145,6 +145,18 @@
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 
+/* SATA */
+#ifndef SPL_NO_SATA
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATAAHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+   CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
 /* Command line configuration */
 
 /* MMC */
@@ -201,6 +213,7 @@
 #include 
 #ifndef CONFIG_SPL_BUILD
 #define BOOT_TARGET_DEVICES(func) \
+   func(SCSI, scsi, 0) \
func(MMC, mmc, 0) \
func(USB, usb, 0)
 #include 
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index c3b0f4d..456f61a 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -136,9 +136,6 @@ unsigned long get_board_ddr_clk(void);
 #define CFG_LPUART_EN  0x2
 #endif
 
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
@@ -148,13 +145,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
 
-#define CONFIG_SYS_SATAAHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
-#define CONFIG_SYS_SCSI_MAX_LUN1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-   CONFIG_SYS_SCSI_MAX_LUN)
-
 /*
  * IFC Definitions
  */
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 784894f..f4f4fd7 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -209,18 +209,6 @@
 #endif
 #endif
 
-/* SATA */
-#ifndef SPL_NO_SATA
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATAAHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
-#define CONFIG_SYS_SCSI_MAX_LUN1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-   CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
 #ifndef SPL_NO_MISC
 #undef CONFIG_BOOTCOMMAND
 #if defined(CONFIG_QSPI_BOOT)
-- 
1.7.1

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[U-Boot] [PATCH 2/2] arm64: ls1012a: Add sata distro boot support

[Yuantian Tang]

Sata is equipped on ls1012a and can be a boot source.
Add sata boot support as a option if available.

Signed-off-by: Tang Yuantian 
---
 include/configs/ls1012a_common.h |   11 +++
 include/configs/ls1012aqds.h |   10 --
 include/configs/ls1012ardb.h |9 -
 3 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index db920bc..c57c08e 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -69,6 +69,16 @@
 #define CONFIG_ENV_SECT_SIZE   0x4
 #endif
 
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATAAHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+   CONFIG_SYS_SCSI_MAX_LUN)
+
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
@@ -90,6 +100,7 @@
 #include 
 #ifndef CONFIG_SPL_BUILD
 #define BOOT_TARGET_DEVICES(func) \
+   func(SCSI, scsi, 0) \
func(MMC, mmc, 0) \
func(USB, usb, 0)
 #include 
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index af5f37c..47d863a 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -124,16 +124,6 @@
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATAAHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
-#define CONFIG_SYS_SCSI_MAX_LUN1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-   CONFIG_SYS_SCSI_MAX_LUN)
-
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 
 #define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index ab139b0..438b5a6 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -46,15 +46,6 @@
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATAAHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
-#define CONFIG_SYS_SCSI_MAX_LUN1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-   CONFIG_SYS_SCSI_MAX_LUN)
 
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 
-- 
1.7.1

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[U-Boot] [PATCH v2] armv8: layerscape: sata: refine port register configuration

[Yuantian Tang]

Sata registers PP2C and PP3C are used to control the configuration
of the PHY control OOB timing for the COMINIT/COMWAKE parameters
respectively.
Calculate those parameters from port clock frequency. Overwrite those
registers with calculated values to get better OOB timing.

Signed-off-by: Tang Yuantian 
---
v2:
- refine the commit message and title

 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 6 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 497a4b541d..b52653929c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -328,6 +328,8 @@ int sata_init(void)
 #ifdef CONFIG_SYS_SATA2
ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 #endif
@@ -335,6 +337,8 @@ int sata_init(void)
 #ifdef CONFIG_SYS_SATA1
ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
@@ -355,6 +359,8 @@ int sata_init(void)
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5..664d847e9c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -88,6 +88,8 @@ struct cpu_type {
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
+#define AHCI_PORT_PHY2_CFG 0x28184d1f
+#define AHCI_PORT_PHY3_CFG 0x0e081509
 #define AHCI_PORT_TRANS_CFG0x0829
 #define AHCI_PORT_AXICC_CFG0x3fff
 
-- 
2.14.1

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[U-Boot] [PATCH] armv8: layerscape: refine port register configuration

[Yuantian Tang]

These PP2C and PP3C registers control the configuration of the PHY
control OOB timing for the COMINIT/COMWAKE parameters respectively
for sata port. Overwrite default values with calculated ones to get
better OOB timing.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 6 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 497a4b541d..b52653929c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -328,6 +328,8 @@ int sata_init(void)
 #ifdef CONFIG_SYS_SATA2
ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 #endif
@@ -335,6 +337,8 @@ int sata_init(void)
 #ifdef CONFIG_SYS_SATA1
ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
@@ -355,6 +359,8 @@ int sata_init(void)
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5..664d847e9c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -88,6 +88,8 @@ struct cpu_type {
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
+#define AHCI_PORT_PHY2_CFG 0x28184d1f
+#define AHCI_PORT_PHY3_CFG 0x0e081509
 #define AHCI_PORT_TRANS_CFG0x0829
 #define AHCI_PORT_AXICC_CFG0x3fff
 
-- 
2.14.1

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[U-Boot] [PATCH v3] arm: psci: make psci usable on single core socs

[Yuantian Tang]

PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.

Signed-off-by: Chenhui Zhao 
Signed-off-by: Tang Yuantian 
---
v3:
- replace printf with debug
v2:
- refine the title and commit message
 arch/arm/cpu/armv8/cpu-dt.c   | 13 +++---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   | 35 ---
 arch/arm/cpu/armv8/sec_firmware.c |  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/mp.h |  4 +++
 arch/arm/include/asm/armv8/sec_firmware.h |  7 ++
 5 files changed, 31 insertions(+), 30 deletions(-)

diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 5156a15..e3c8aa2 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -7,25 +7,19 @@
 #include 
 #include 
 #include 
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
-#endif
 
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 int psci_update_dt(void *fdt)
 {
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
-
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
 * If the PSCI in SEC Firmware didn't work, avoid to update the
 * device node of PSCI. But still return 0 instead of an error
 * number to support detecting PSCI dynamically and then switching
 * the SMP boot method between PSCI and spin-table.
 */
-   if (sec_firmware_support_psci_version() == 0x)
+   if (sec_firmware_support_psci_version() == PSCI_INVALID_VER)
return 0;
-#endif
fdt_psci(fdt);
 
 #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE)
@@ -34,7 +28,6 @@ int psci_update_dt(void *fdt)
__secure_end - __secure_start);
 #endif
 
-#endif
-#endif
return 0;
 }
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c24f3f1..bb02960 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -15,18 +15,14 @@
 #include 
 #include 
 #include 
-#ifdef CONFIG_MP
 #include 
-#endif
 #include 
 #include 
 #include 
 #ifdef CONFIG_FSL_ESDHC
 #include 
 #endif
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
-#endif
 #ifdef CONFIG_SYS_FSL_DDR
 #include 
 #endif
@@ -475,13 +471,19 @@ int cpu_eth_init(bd_t *bis)
return error;
 }
 
-int arch_early_init_r(void)
+static inline int check_psci(void)
 {
-#ifdef CONFIG_MP
-   int rv = 1;
-   u32 psci_ver = 0x;
-#endif
+   unsigned int psci_ver;
 
+   psci_ver = sec_firmware_support_psci_version();
+   if (psci_ver == PSCI_INVALID_VER)
+   return 1;
+
+   return 0;
+}
+
+int arch_early_init_r(void)
+{
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
u32 svr_dev_id;
/*
@@ -495,18 +497,13 @@ int arch_early_init_r(void)
 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
erratum_a009942_check_cpo();
 #endif
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
-   defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
-   /* Check the psci version to determine if the psci is supported */
-   psci_ver = sec_firmware_support_psci_version();
-#endif
-   if (psci_ver == 0x) {
-   rv = fsl_layerscape_wake_seconday_cores();
-   if (rv)
+   if (check_psci()) {
+   debug("PSCI: PSCI does not exist.\n");
+
+   /* if PSCI does not exist, boot secondary cores here */
+   if (fsl_layerscape_wake_seconday_cores())
printf("Did not wake secondary cores\n");
}
-#endif
 
 #ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
diff --git a/arch/arm/cpu/armv8/sec_firmware.c 
b/arch/arm/cpu/armv8/sec_firmware.c
index ec9cf40..4afa3ad 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -227,7 +227,7 @@ unsigned int sec_firmware_support_psci_version(void)
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING)
return _sec_firmware_support_psci_version();
 
-   return 0x;
+   return PSCI_INVALID_VER;
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h 
b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
index d0832b5..fd3f851 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -31,7 +31,11 @@ extern u64 __spin_table[];
 extern u64 __real_cntfrq;
 extern u64 *secondary_boot_code;
 extern size_t __secondary_boot_code_size;
+#ifdef CONFIG_MP
 int fsl_layerscape_wake_seconday_cores(void);
+#else
+static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
+#endif
 void *get_spin_tbl_addr(void);
 phys_addr_t determine_mp_bootpg(void);
 void 

[U-Boot] [PATCH v2] arm: psci: make psci usable on single core socs

[Yuantian Tang]

PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.

Signed-off-by: Chenhui Zhao 
Signed-off-by: Tang Yuantian 
---
v2:
- refine the title and commit message

 arch/arm/cpu/armv8/cpu-dt.c   | 13 +++---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   | 35 ---
 arch/arm/cpu/armv8/sec_firmware.c |  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/mp.h |  4 +++
 arch/arm/include/asm/armv8/sec_firmware.h |  7 ++
 5 files changed, 31 insertions(+), 30 deletions(-)

diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 5156a15..e3c8aa2 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -7,25 +7,19 @@
 #include 
 #include 
 #include 
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
-#endif
 
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 int psci_update_dt(void *fdt)
 {
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
-
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
 * If the PSCI in SEC Firmware didn't work, avoid to update the
 * device node of PSCI. But still return 0 instead of an error
 * number to support detecting PSCI dynamically and then switching
 * the SMP boot method between PSCI and spin-table.
 */
-   if (sec_firmware_support_psci_version() == 0x)
+   if (sec_firmware_support_psci_version() == PSCI_INVALID_VER)
return 0;
-#endif
fdt_psci(fdt);
 
 #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE)
@@ -34,7 +28,6 @@ int psci_update_dt(void *fdt)
__secure_end - __secure_start);
 #endif
 
-#endif
-#endif
return 0;
 }
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ea6c090..ccddd49 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -14,18 +14,14 @@
 #include 
 #include 
 #include 
-#ifdef CONFIG_MP
 #include 
-#endif
 #include 
 #include 
 #include 
 #ifdef CONFIG_FSL_ESDHC
 #include 
 #endif
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
-#endif
 #ifdef CONFIG_SYS_FSL_DDR
 #include 
 #endif
@@ -474,13 +470,19 @@ int cpu_eth_init(bd_t *bis)
return error;
 }
 
-int arch_early_init_r(void)
+static inline int check_psci(void)
 {
-#ifdef CONFIG_MP
-   int rv = 1;
-   u32 psci_ver = 0x;
-#endif
+   unsigned int psci_ver;
 
+   psci_ver = sec_firmware_support_psci_version();
+   if (psci_ver == PSCI_INVALID_VER)
+   return 1;
+
+   return 0;
+}
+
+int arch_early_init_r(void)
+{
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
u32 svr_dev_id;
/*
@@ -494,18 +496,13 @@ int arch_early_init_r(void)
 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
erratum_a009942_check_cpo();
 #endif
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
-   defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
-   /* Check the psci version to determine if the psci is supported */
-   psci_ver = sec_firmware_support_psci_version();
-#endif
-   if (psci_ver == 0x) {
-   rv = fsl_layerscape_wake_seconday_cores();
-   if (rv)
+   if (check_psci()) {
+   printf("PSCI: PSCI does not exist.\n");
+
+   /* if PSCI does not exist, boot secondary cores here */
+   if (fsl_layerscape_wake_seconday_cores())
printf("Did not wake secondary cores\n");
}
-#endif
 
 #ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
diff --git a/arch/arm/cpu/armv8/sec_firmware.c 
b/arch/arm/cpu/armv8/sec_firmware.c
index ec9cf40..4afa3ad 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -227,7 +227,7 @@ unsigned int sec_firmware_support_psci_version(void)
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING)
return _sec_firmware_support_psci_version();
 
-   return 0x;
+   return PSCI_INVALID_VER;
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h 
b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
index d0832b5..fd3f851 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -31,7 +31,11 @@ extern u64 __spin_table[];
 extern u64 __real_cntfrq;
 extern u64 *secondary_boot_code;
 extern size_t __secondary_boot_code_size;
+#ifdef CONFIG_MP
 int fsl_layerscape_wake_seconday_cores(void);
+#else
+static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
+#endif
 void *get_spin_tbl_addr(void);
 phys_addr_t determine_mp_bootpg(void);
 void secondary_boot_func(void);
diff --git 

[U-Boot] [PATCH] armv8: ls1046aqds: added ppa support

[Yuantian Tang]

PPA is used on ls1046aqds to support sleep, hotplug feature.
Add PPA support to enable them.

Signed-off-by: Tang Yuantian 
---
 board/freescale/ls1046aqds/ls1046aqds.c |  5 +
 include/configs/ls1046aqds.h| 11 +++
 2 files changed, 16 insertions(+)

diff --git a/board/freescale/ls1046aqds/ls1046aqds.c 
b/board/freescale/ls1046aqds/ls1046aqds.c
index af3f70a..470e61a 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "../common/vid.h"
 #include "../common/qixis.h"
@@ -265,6 +266,10 @@ int board_init(void)
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
 
+#ifdef CONFIG_FSL_LS_PPA
+   ppa_init();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 4b3b21e..f8f74aa 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -9,6 +9,17 @@
 
 #include "ls1046a_common.h"
 
+#if defined(CONFIG_FSL_LS_PPA)
+#define CONFIG_ARMV8_PSCI
+#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#define SEC_FIRMWARE_ERET_ADDR_REVERT
+
+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
+#defineCONFIG_SYS_LS_PPA_FW_ADDR   0x6050
+#endif
+#endif
+
 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE   0x8200
 #elif defined(CONFIG_QSPI_BOOT)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] armv8: ls1046aqds: enable ppa in default config

[Yuantian Tang]

Signed-off-by: Tang Yuantian 
---
 configs/ls1046aqds_defconfig | 1 +
 configs/ls1046aqds_lpuart_defconfig  | 1 +
 configs/ls1046aqds_nand_defconfig| 1 +
 configs/ls1046aqds_qspi_defconfig| 1 +
 configs/ls1046aqds_sdcard_ifc_defconfig  | 1 +
 configs/ls1046aqds_sdcard_qspi_defconfig | 1 +
 6 files changed, 6 insertions(+)

diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index d6b8af2..cb0f164 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -35,3 +35,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_FSL_LS_PPA=y
diff --git a/configs/ls1046aqds_lpuart_defconfig 
b/configs/ls1046aqds_lpuart_defconfig
index 20136a4..b481d90 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -31,3 +31,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_FSL_LS_PPA=y
diff --git a/configs/ls1046aqds_nand_defconfig 
b/configs/ls1046aqds_nand_defconfig
index b23861c..c4e9c90 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -40,3 +40,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_FSL_LS_PPA=y
diff --git a/configs/ls1046aqds_qspi_defconfig 
b/configs/ls1046aqds_qspi_defconfig
index 45782be..0bbee81 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -37,3 +37,4 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_FSL_LS_PPA=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig 
b/configs/ls1046aqds_sdcard_ifc_defconfig
index 3df92b2..c5ff822 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -41,3 +41,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_FSL_LS_PPA=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig 
b/configs/ls1046aqds_sdcard_qspi_defconfig
index 998d2cf..34950ee 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -42,3 +42,4 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_FSL_LS_PPA=y
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v5] arm: Add sata support on Layerscape ARMv8 board

[Yuantian Tang]

Hi York,

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Tuesday, December 08, 2015 12:27 AM
> To: Tang Yuantian-B29983 
> Cc: u-boot@lists.denx.de; si...@writeme.com
> Subject: Re: [PATCH v5] arm: Add sata support on Layerscape ARMv8 board
> 
> 
> 
> On 12/06/2015 07:09 PM, Tang Yuantian-B29983 wrote:
> > Hi York,
> >
> > Please see explanation inline.
> >
> >> -Original Message-
> >> From: York Sun [mailto:york...@freescale.com]
> >> Sent: Saturday, December 05, 2015 1:25 AM
> >> To: Tang Yuantian-B29983 
> >> Cc: u-boot@lists.denx.de; si...@writeme.com
> >> Subject: Re: [PATCH v5] arm: Add sata support on Layerscape ARMv8
> >> board
> >>
> >>
> >>
> >> On 12/03/2015 06:47 PM, Tang Yuantian-B29983 wrote:
> >>> Hi York,
> >>>
> >>> Please see my explanation inline.
> >>>
>  -Original Message-
>  From: York Sun [mailto:york...@freescale.com]
>  Sent: Friday, December 04, 2015 12:27 AM
>  To: Tang Yuantian-B29983 
>  Cc: u-boot@lists.denx.de; si...@writeme.com
>  Subject: Re: [PATCH v5] arm: Add sata support on Layerscape ARMv8
>  board
> 
> 
> 
>  On 12/01/2015 07:27 PM, yuantian.t...@freescale.com wrote:
> > From: Tang Yuantian 
> >
> > Freescale ARM-based Layerscape contains a SATA controller which
> > comply with the serial ATA 3.0 specification and the AHCI 1.3
> >> specification.
> > This patch adds SATA feature on ls2080aqds, ls2080ardb and
> > ls1043aqds boards.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> > v5:
> > - re-organize the code
> > v4:
> > - rebase to lastest git tree
> > - add another ARMv8 platform which is ls1043aqds
> > v3:
> > - rename ls2085a to ls2080a
> > - rebase to the latest git tree
> > - replace the magic number with micro variable
> > v2:
> > - rebase to the latest git tree
> >
> >  arch/arm/cpu/armv8/fsl-layerscape/soc.c| 43
>  ++
> >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  4 ++
> >  arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31
>  
> >  include/configs/ls1043aqds.h   | 17 +
> >  include/configs/ls2080aqds.h   | 18 +
> >  include/configs/ls2080ardb.h   | 18 +
> >  6 files changed, 131 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 8896b70..574ffc4 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -6,6 +6,8 @@
> >
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
> > erratum_a009203();
> >  }
> >
> 
>  Yuantian,
> 
>  Please help me understand below.
> 
> > +#ifdef CONFIG_SCSI_AHCI_PLAT
> > +int sata_init(void)
> > +{
> > +   struct ccsr_ahci __iomem *ccsr_ahci;
> > +
> > +   ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
> > +   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > +   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> 
>  You didn't set pp2c or pp3c. Is it because the default values are
>  OK or something else?
> 
> >>> Those settings of registers vary from soc to soc. If the default
> >>> value will be
> >> used if the register is not updated explicitly.
> >>
> >> If you put the macros for each SoC, you probably can use one function for
> all.
> >> You only want to keep them separated if they have not much in common.
> >>
> > I was trying to use one function for all, but I found separating them is
> better.
> > Take ls1043a and ls2080a as an example, ls2080a has two controllers, while
> ls1043a has one.
> > Ls2080a has two registers that need to be updated while ls1043a has four.
> > A lot of #ifdef are needed if we unify them, not mention that in the future,
> changing one of the platforms' register will affect the other.
> > Maybe I am not thinking it through.  If you can give me more detail that
> viable, I can give a try.
> 
> Yuantian,
> 
> I was thinking to set all registers, including those with default values. Then
> you can use one function for both. My understand is LS1043 and LS2080 has
> different default value. It will be easier to update the macros if you need
> different values, than changing the functions. If we have a new SoC in the
> same family, you don't have to add another function.
> 
> Try it to see if you still have to separate them.
> 
I didn't see any 

Re: [U-Boot] [PATCH v5] arm: Add sata support on Layerscape ARMv8 board

[Yuantian Tang]

Hi York,

Please see explanation inline.

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Saturday, December 05, 2015 1:25 AM
> To: Tang Yuantian-B29983 
> Cc: u-boot@lists.denx.de; si...@writeme.com
> Subject: Re: [PATCH v5] arm: Add sata support on Layerscape ARMv8 board
> 
> 
> 
> On 12/03/2015 06:47 PM, Tang Yuantian-B29983 wrote:
> > Hi York,
> >
> > Please see my explanation inline.
> >
> >> -Original Message-
> >> From: York Sun [mailto:york...@freescale.com]
> >> Sent: Friday, December 04, 2015 12:27 AM
> >> To: Tang Yuantian-B29983 
> >> Cc: u-boot@lists.denx.de; si...@writeme.com
> >> Subject: Re: [PATCH v5] arm: Add sata support on Layerscape ARMv8
> >> board
> >>
> >>
> >>
> >> On 12/01/2015 07:27 PM, yuantian.t...@freescale.com wrote:
> >>> From: Tang Yuantian 
> >>>
> >>> Freescale ARM-based Layerscape contains a SATA controller which
> >>> comply with the serial ATA 3.0 specification and the AHCI 1.3
> specification.
> >>> This patch adds SATA feature on ls2080aqds, ls2080ardb and
> >>> ls1043aqds boards.
> >>>
> >>> Signed-off-by: Tang Yuantian 
> >>> ---
> >>> v5:
> >>>   - re-organize the code
> >>> v4:
> >>>   - rebase to lastest git tree
> >>>   - add another ARMv8 platform which is ls1043aqds
> >>> v3:
> >>>   - rename ls2085a to ls2080a
> >>>   - rebase to the latest git tree
> >>>   - replace the magic number with micro variable
> >>> v2:
> >>>   - rebase to the latest git tree
> >>>
> >>>  arch/arm/cpu/armv8/fsl-layerscape/soc.c| 43
> >> ++
> >>>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  4 ++
> >>>  arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31
> >> 
> >>>  include/configs/ls1043aqds.h   | 17 +
> >>>  include/configs/ls2080aqds.h   | 18 +
> >>>  include/configs/ls2080ardb.h   | 18 +
> >>>  6 files changed, 131 insertions(+)
> >>>
> >>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> index 8896b70..574ffc4 100644
> >>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> @@ -6,6 +6,8 @@
> >>>
> >>>  #include 
> >>>  #include 
> >>> +#include 
> >>> +#include 
> >>>  #include 
> >>>  #include 
> >>>  #include 
> >>> @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
> >>>   erratum_a009203();
> >>>  }
> >>>
> >>
> >> Yuantian,
> >>
> >> Please help me understand below.
> >>
> >>> +#ifdef CONFIG_SCSI_AHCI_PLAT
> >>> +int sata_init(void)
> >>> +{
> >>> + struct ccsr_ahci __iomem *ccsr_ahci;
> >>> +
> >>> + ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
> >>> + out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> >>> + out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> >>
> >> You didn't set pp2c or pp3c. Is it because the default values are OK
> >> or something else?
> >>
> > Those settings of registers vary from soc to soc. If the default value will 
> > be
> used if the register is not updated explicitly.
> 
> If you put the macros for each SoC, you probably can use one function for all.
> You only want to keep them separated if they have not much in common.
> 
I was trying to use one function for all, but I found separating them is better.
Take ls1043a and ls2080a as an example, ls2080a has two controllers, while 
ls1043a has one.
Ls2080a has two registers that need to be updated while ls1043a has four.
A lot of #ifdef are needed if we unify them, not mention that in the future, 
changing one of the platforms' register will affect the other.
Maybe I am not thinking it through.  If you can give me more detail that 
viable, I can give a try.

> > Speaking of this, I got new information from validation team about giving a
> new value to PTC register.
> > So please hold this patch for a while, I will update it in next version.
> >
> >>> +
> >>> + ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
> >>> + out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> >>> + out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> >>> +
> >>> + ahci_init((void __iomem *)CONFIG_SYS_SATA1);
> >>
> >> You only call ahci_init() here but not above. Is SATA2 active?
> >>
> > AHCI SATA driver only supports one SATA port. On ls2080a we have two
> ports, so we have to choice one. In this case I choice the first one which is
> SATA1.
> 
> This should be put into comment, or README if you have one.
This phenomenon is not LS platform specific, that's uboot's issue which needs 
another patch to fix.
I think uboot know that and choice to not fix it because for uboot supporting 
two sata port is not that significant.
It is just like that uboot doesn't support local sata and PCIe sata 
simutaniously.

If a comment is needed, it would be better to put it in our own README (in this 
case, ls2080a) document. 

Regards,
Yuantian
> 
> York

Re: [U-Boot] [PATCH v5] arm: Add sata support on Layerscape ARMv8 board

[Yuantian Tang]

Hi Sinan,

> -Original Message-
> From: Sinan Akman [mailto:si...@writeme.com]
> Sent: Monday, December 07, 2015 2:04 PM
> To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>; Sun York-R58495
> <york...@freescale.com>
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v5] arm: Add sata support on Layerscape
> ARMv8 board
> 
> 
>Hi Yuantian
> 
> On 06/12/15 10:09 PM, Yuantian Tang wrote:
> > Hi York,
> >
> > Please see explanation inline.
> > [...]
> > I was trying to use one function for all, but I found separating them is
> better.
> > Take ls1043a and ls2080a as an example, ls2080a has two controllers, while
> ls1043a has one.
> > Ls2080a has two registers that need to be updated while ls1043a has four.
> > A lot of #ifdef are needed if we unify them, not mention that in the future,
> changing one of the platforms' register will affect the other.
> 
> You might want to take into consideration that in the near future we will 
> be
> moving this to dm. In that respect having all that in one file already will
> probably make things much easier. If you consider this, perhaps you will have
> a different view.
> 
They are in the same file but different functions.

> > Maybe I am not thinking it through.  If you can give me more detail that
> viable, I can give a try.
> >
> >> [...]
> >> ports, so we have to choice one. In this case I choice the first one
> >> which is SATA1.
> >>
> >> This should be put into comment, or README if you have one.
> > This phenomenon is not LS platform specific, that's uboot's issue which
> needs another patch to fix.
> > I think uboot know that and choice to not fix it because for uboot
> supporting two sata port is not that significant.
> 
>Again, with dm and reading all the hardware properties from device tree
> will also change this. If both device nodes are enabled we will have to
> support both as long as there is no hardware limitation. So I think there is 
> no
> reason why having both SATA and PCIe would not be significant. It is just that
> the current implementation has this limitation and there is already some
> timeline for removing these limitations.
> 
I am not seeing what we are arguing here? 
Are we talking about if this limitation is important?
Please point out what's wrong with this patch.

Regards,
Yuantian

>Regards
>Sinan Akman
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Re: [U-Boot] [PATCH v5] arm: Add sata support on Layerscape ARMv8 board

[Yuantian Tang]

Hi York,

Please see my explanation inline.

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Friday, December 04, 2015 12:27 AM
> To: Tang Yuantian-B29983 
> Cc: u-boot@lists.denx.de; si...@writeme.com
> Subject: Re: [PATCH v5] arm: Add sata support on Layerscape ARMv8 board
> 
> 
> 
> On 12/01/2015 07:27 PM, yuantian.t...@freescale.com wrote:
> > From: Tang Yuantian 
> >
> > Freescale ARM-based Layerscape contains a SATA controller which comply
> > with the serial ATA 3.0 specification and the AHCI 1.3 specification.
> > This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds
> > boards.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> > v5:
> > - re-organize the code
> > v4:
> > - rebase to lastest git tree
> > - add another ARMv8 platform which is ls1043aqds
> > v3:
> > - rename ls2085a to ls2080a
> > - rebase to the latest git tree
> > - replace the magic number with micro variable
> > v2:
> > - rebase to the latest git tree
> >
> >  arch/arm/cpu/armv8/fsl-layerscape/soc.c| 43
> ++
> >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  4 ++
> >  arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31
> 
> >  include/configs/ls1043aqds.h   | 17 +
> >  include/configs/ls2080aqds.h   | 18 +
> >  include/configs/ls2080ardb.h   | 18 +
> >  6 files changed, 131 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 8896b70..574ffc4 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -6,6 +6,8 @@
> >
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
> > erratum_a009203();
> >  }
> >
> 
> Yuantian,
> 
> Please help me understand below.
> 
> > +#ifdef CONFIG_SCSI_AHCI_PLAT
> > +int sata_init(void)
> > +{
> > +   struct ccsr_ahci __iomem *ccsr_ahci;
> > +
> > +   ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
> > +   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > +   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> 
> You didn't set pp2c or pp3c. Is it because the default values are OK or
> something else?
> 
Those settings of registers vary from soc to soc. If the default value will be 
used if the register is not updated explicitly.
Speaking of this, I got new information from validation team about giving a new 
value to PTC register.
So please hold this patch for a while, I will update it in next version. 

> > +
> > +   ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
> > +   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > +   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> > +
> > +   ahci_init((void __iomem *)CONFIG_SYS_SATA1);
> 
> You only call ahci_init() here but not above. Is SATA2 active?
> 
AHCI SATA driver only supports one SATA port. On ls2080a we have two ports, so 
we have to choice one. In this case I choice the first one which is SATA1.

Regards,
Yuantian

> 
> > +   scsi_scan(0);
> > +
> > +   return 0;
> > +}
> > +#endif
> > +
> >  #elif defined(CONFIG_LS1043A)
> > +#ifdef CONFIG_SCSI_AHCI_PLAT
> > +int sata_init(void)
> > +{
> > +   struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
> > +
> > +   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > +   out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
> > +   out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
> > +   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> > +
> > +   ahci_init((void __iomem *)CONFIG_SYS_SATA);
> > +   scsi_scan(0);
> > +
> > +   return 0;
> > +}
> > +#endif
> > +
> 
> York

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Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board

[Yuantian Tang]

OK, thanks.
I will rework this patch.

Regards,
Yuantian

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Wednesday, December 02, 2015 12:59 AM
> To: si...@writeme.com; Tang Yuantian-B29983
> 
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
> ARMv8 board
> 
> 
> 
> On 12/01/2015 08:54 AM, Sinan Akman wrote:
> >
> >Hi York
> >
> > On 01/12/15 11:44 AM, York Sun wrote:
> >> Sinan,
> >>
> >> Thanks for your review.
> >>
> >> Yuantian,
> >>
> >> You are right about putting things together. We have some macros in
> >> wrong places, including config.h. If you can, please try to move them
> >> into proper files, such as immap_lsch3.h. Enabling SATA should be
> >> done at board level because it depends on the board to have physical
> connection.
> >
> >Just to make this clear one final time, I am not against enabling
> > SATA at the board level but my suggestion is to define the SATA
> > register values (which is *not* board dependent) in the soc specific
> > header file, then at the board level if SATA is not enabled we don't
> > use it, if it is enabled we use it and use the same register values
> > across all boards with this SoC. That's all.
> >
> 
> Agreed.
> 
> York

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Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board

[Yuantian Tang]

Hi Sinan Akman,

Please see my explanation inline.

> -Original Message-
> From: Sinan Akman [mailto:si...@writeme.com]
> Sent: Tuesday, December 01, 2015 3:24 PM
> To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>; Sun York-R58495
> <york...@freescale.com>
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
> ARMv8 board
> 
> 
>    Hi Yuan
> 
> On 01/12/15 01:41 AM, Yuantian Tang wrote:
> > Hi Sinan Akman,
> >
> >> -Original Message-
> >> From: Sinan Akman [mailto:si...@writeme.com]
> >> Sent: Tuesday, December 01, 2015 2:29 PM
> >> To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>; Sun
> >> York-R58495 <york...@freescale.com>
> >> Cc: u-boot@lists.denx.de
> >> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
> >> ARMv8 board
> >>
> >>
> >> Hi Yuan
> >>
> >> On 01/12/15 01:16 AM, Yuantian Tang wrote:
> >>> Hi Sinan Akman,
> >>>
> >>> Please see my explanation inline.
> >>>
> >>>> -Original Message-
> >>>> From: Sinan Akman [mailto:si...@writeme.com]
> >>>> Sent: Tuesday, December 01, 2015 1:28 AM
> >>>> To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>; Sun
> >>>> York-R58495 <york...@freescale.com>
> >>>> Cc: u-boot@lists.denx.de
> >>>> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on
> >>>> Layerscape
> >>>> ARMv8 board
> >>>>
> >>>>
> >>>>  Hi Yuan
> >>>>
> >>>> On 30/11/15 02:44 AM, yuantian.t...@freescale.com wrote:
> >>>>> From: Tang Yuantian <yuantian.t...@freescale.com>
> >>>>>
> >>>>> Freescale ARM-based Layerscape contains a SATA controller which
> >>>>> comply with the serial ATA 3.0 specification and the AHCI 1.3
> >> specification.
> >>>>> This patch adds SATA feature on ls2080aqds, ls2080ardb and
> >>>>> ls1043aqds boards.
> >>>>>
> >>>>> Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com>
> >>>>> ---
> >>>>> v4:
> >>>>> - rebase to lastest git tree
> >>>>> - add another ARMv8 platform which is ls1043aqds
> >>>>> v3:
> >>>>> - rename ls2085a to ls2080a
> >>>>> - rebase to the latest git tree
> >>>>> - replace the magic number with micro variable
> >>>>> v2:
> >>>>> - rebase to the latest git tree
> >>>>>
> >>>>> arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 43
> >>>> +++
> >>>>> arch/arm/include/asm/arch-fsl-layerscape/config.h | 18
> ++
> >>>>> arch/arm/include/asm/arch-fsl-layerscape/soc.h| 31
> >>>> 
> >>>>> include/configs/ls1043aqds.h  | 17 +
> >>>>> 4 files changed, 109 insertions(+)
> >>>>>
> >>>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>>> index 8896b70..574ffc4 100644
> >>>>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>>> @@ -6,6 +6,8 @@
> >>>>>
> >>>>> #include 
> >>>>> #include 
> >>>>> +#include 
> >>>>> +#include 
> >>>>> #include 
> >>>>> #include 
> >>>>> #include 
> >>>>> @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
> >>>>> erratum_a009203();
> >>>>> }
> >>>>>
> >>>>> +#ifdef CONFIG_SCSI_AHCI_PLAT
> >>>>> +int sata_init(void)
> >>>>> +{
> >>>>> +   struct ccsr_ahci __iomem *ccsr_ahci;
> >>>>> +
> >>>>> +   ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
> >>>>> +   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> >>>>> +   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> >>>>> +
> >>>>

Re: [U-Boot] [PATCH v3] arm: ls2080a: Add sata support on qds and rdb board

[Yuantian Tang]

I have sent the newer version of this patch: 
http://patchwork.ozlabs.org/patch/549883/

Please have a review.

Regards,
Yuantian

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Tuesday, December 01, 2015 3:41 AM
> To: Tang Yuantian-B29983 
> Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579
> ; Wang Huan-B18965
> 
> Subject: Re: [PATCH v3] arm: ls2080a: Add sata support on qds and rdb board
> 
> 
> 
> On 10/23/2015 12:16 AM, Tang Yuantian wrote:
> > Freescale ARM-based Layerscape LS2080A contain a SATA controller which
> > comply with the serial ATA 3.0 specification and the AHCI 1.3
> > specification.
> > This patch adds SATA feature on ls2080aqds and ls2080ardb boards.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> > depends on patches:
> > http://patchwork.ozlabs.org/patch/530576/
> > armv8: LS2080A: Rename LS2085A to reflect LS2080A
> > http://patchwork.ozlabs.org/patch/530575/
> > armv8: ls2085a: Add support of LS2085A SoC
> > v3:
> > - rename ls2085a to ls2080a
> > - rebase to the latest git tree
> > - replace the magic number with micro variable
> > v2:
> > - rebase to the latest git tree
> >
> 
> Yuantian,
> 
> The dependency patches have been updated and merged. Please rebase
> your patch and test on the new base git://git.denx.de/u-boot-fsl-qoriq.git
> master.
> 
> Thanks.
> 
> York

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Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board

[Yuantian Tang]

Hi Sinan Akman,

Please see my explanation inline.

> -Original Message-
> From: Sinan Akman [mailto:si...@writeme.com]
> Sent: Tuesday, December 01, 2015 1:28 AM
> To: Tang Yuantian-B29983 ; Sun York-R58495
> 
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
> ARMv8 board
> 
> 
>Hi Yuan
> 
> On 30/11/15 02:44 AM, yuantian.t...@freescale.com wrote:
> > From: Tang Yuantian 
> >
> > Freescale ARM-based Layerscape contains a SATA controller which comply
> > with the serial ATA 3.0 specification and the AHCI 1.3 specification.
> > This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds
> > boards.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> > v4:
> > - rebase to lastest git tree
> > - add another ARMv8 platform which is ls1043aqds
> > v3:
> > - rename ls2085a to ls2080a
> > - rebase to the latest git tree
> > - replace the magic number with micro variable
> > v2:
> > - rebase to the latest git tree
> >
> >   arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 43
> +++
> >   arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++
> >   arch/arm/include/asm/arch-fsl-layerscape/soc.h| 31
> 
> >   include/configs/ls1043aqds.h  | 17 +
> >   4 files changed, 109 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 8896b70..574ffc4 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -6,6 +6,8 @@
> >
> >   #include 
> >   #include 
> > +#include 
> > +#include 
> >   #include 
> >   #include 
> >   #include 
> > @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
> > erratum_a009203();
> >   }
> >
> > +#ifdef CONFIG_SCSI_AHCI_PLAT
> > +int sata_init(void)
> > +{
> > +   struct ccsr_ahci __iomem *ccsr_ahci;
> > +
> > +   ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
> > +   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > +   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> > +
> > +   ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
> > +   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > +   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> > +
> > +   ahci_init((void __iomem *)CONFIG_SYS_SATA1);
> > +   scsi_scan(0);
> > +
> > +   return 0;
> > +}
> > +#endif
> > +
> >   #elif defined(CONFIG_LS1043A)
> > +#ifdef CONFIG_SCSI_AHCI_PLAT
> > +int sata_init(void)
> > +{
> > +   struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
> > +
> > +   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > +   out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
> > +   out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
> > +   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> > +
> > +   ahci_init((void __iomem *)CONFIG_SYS_SATA);
> > +   scsi_scan(0);
> > +
> > +   return 0;
> > +}
> > +#endif
> > +
> >   void fsl_lsch2_early_init_f(void)
> >   {
> > struct ccsr_cci400 *cci = (struct ccsr_cci400
> > *)CONFIG_SYS_CCI400_ADDR; @@ -141,6 +180,10 @@ void
> fsl_lsch2_early_init_f(void)
> >   #ifdef CONFIG_BOARD_LATE_INIT
> >   int board_late_init(void)
> >   {
> > +#ifdef CONFIG_SCSI_AHCI_PLAT
> > +   sata_init();
> > +#endif
> > +
> > return 0;
> >   }
> >   #endif
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > index b5a2d28..be3acc3 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > @@ -54,6 +54,24 @@
> >
> >   #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
> >
> > +/* SATA */
> > +#define CONFIG_LIBATA
> > +#define CONFIG_SCSI_AHCI
> > +#define CONFIG_SCSI_AHCI_PLAT
> > +#define CONFIG_CMD_SCSI
> > +#define CONFIG_CMD_FAT
> > +#define CONFIG_CMD_EXT2
> > +#define CONFIG_DOS_PARTITION
> > +#define CONFIG_BOARD_LATE_INIT
> > +
> > +#define CONFIG_SYS_SATA1   (CONFIG_SYS_IMMR
> + 0x0220)
> > +#define CONFIG_SYS_SATA2   (CONFIG_SYS_IMMR
> + 0x0221)
> 
>Why do we have CONFIG_SYS_SATA1 and CONFIG_SYS_SATA2 here and
> then CONFIG_SYS_SATA in another file (see later below)?
> CONFIG_SYS_SATA1 and CONFIG_SYS_SATA seem to have the same macro
> value : (CONFIG_SYS_IMMR + 0x0220)
> 

normally we put all those definitions in board specific head file.

but config.h is created for all layerscape ARMv8 board too which include 
ls2080a and ls1043a.
So I add those definitions here for ls2080a to avoid defining them in every 
ls2080a board head file.
For ls1043a, only ls1043aqds supports SATA, so, I put all those definitions in 
board head file which is the normal way.
It may lead to a little confusion, but I think it is acceptable.

Regards,
Yuantian

> > +
> > +#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
> > +#define CONFIG_SYS_SCSI_MAX_LUN  

Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board

[Yuantian Tang]

Hi Sinan Akman,

> -Original Message-
> From: Sinan Akman [mailto:si...@writeme.com]
> Sent: Tuesday, December 01, 2015 2:29 PM
> To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>; Sun York-R58495
> <york...@freescale.com>
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
> ARMv8 board
> 
> 
>    Hi Yuan
> 
> On 01/12/15 01:16 AM, Yuantian Tang wrote:
> > Hi Sinan Akman,
> >
> > Please see my explanation inline.
> >
> >> -Original Message-
> >> From: Sinan Akman [mailto:si...@writeme.com]
> >> Sent: Tuesday, December 01, 2015 1:28 AM
> >> To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>; Sun
> >> York-R58495 <york...@freescale.com>
> >> Cc: u-boot@lists.denx.de
> >> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
> >> ARMv8 board
> >>
> >>
> >> Hi Yuan
> >>
> >> On 30/11/15 02:44 AM, yuantian.t...@freescale.com wrote:
> >>> From: Tang Yuantian <yuantian.t...@freescale.com>
> >>>
> >>> Freescale ARM-based Layerscape contains a SATA controller which
> >>> comply with the serial ATA 3.0 specification and the AHCI 1.3
> specification.
> >>> This patch adds SATA feature on ls2080aqds, ls2080ardb and
> >>> ls1043aqds boards.
> >>>
> >>> Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com>
> >>> ---
> >>> v4:
> >>>   - rebase to lastest git tree
> >>>   - add another ARMv8 platform which is ls1043aqds
> >>> v3:
> >>>   - rename ls2085a to ls2080a
> >>>   - rebase to the latest git tree
> >>>   - replace the magic number with micro variable
> >>> v2:
> >>>   - rebase to the latest git tree
> >>>
> >>>arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 43
> >> +++
> >>>arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++
> >>>arch/arm/include/asm/arch-fsl-layerscape/soc.h| 31
> >> 
> >>>include/configs/ls1043aqds.h  | 17 +
> >>>4 files changed, 109 insertions(+)
> >>>
> >>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> index 8896b70..574ffc4 100644
> >>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> @@ -6,6 +6,8 @@
> >>>
> >>>#include 
> >>>#include 
> >>> +#include 
> >>> +#include 
> >>>#include 
> >>>#include 
> >>>#include 
> >>> @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
> >>>   erratum_a009203();
> >>>}
> >>>
> >>> +#ifdef CONFIG_SCSI_AHCI_PLAT
> >>> +int sata_init(void)
> >>> +{
> >>> + struct ccsr_ahci __iomem *ccsr_ahci;
> >>> +
> >>> + ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
> >>> + out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> >>> + out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> >>> +
> >>> + ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
> >>> + out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> >>> + out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> >>> +
> >>> + ahci_init((void __iomem *)CONFIG_SYS_SATA1);
> >>> + scsi_scan(0);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +#endif
> >>> +
> >>>#elif defined(CONFIG_LS1043A)
> >>> +#ifdef CONFIG_SCSI_AHCI_PLAT
> >>> +int sata_init(void)
> >>> +{
> >>> + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
> >>> +
> >>> + out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> >>> + out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
> >>> + out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
> >>> + out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
> >>> +
> >>> + ahci_init((void __iomem *)CONFIG_SYS_SATA);
> >>> + scsi_scan(0);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +#endif
> >>> +
> >>>void fsl_lsch2_early_init_f(void)
> >>>{
> >>>   struct ccsr_cci400 *cci = (str

Re: [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

[Yuantian Tang]

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR 
controller with contents untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related 
code.

Regards,
Yuantian

> -Original Message-
> From: Joakim Tjernlund [mailto:joakim.tjernl...@transmode.se]
> Sent: Thursday, November 05, 2015 4:04 PM
> To: Sun York-R58495 ; u-boot@lists.denx.de
> Cc: c...@cumulusnetworks.com; Sharma Bhupesh-B45370
> ; tr...@konsulko.com;
> l.majew...@samsung.com; Tang Yuantian-B29983
> ; Kushwaha Prabhakar-B32579
> ; Liu Shengzhou-B36685
> ; yamad...@jp.panasonic.com
> Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for
> LSCH3
> 
> On Wed, 2015-11-04 at 10:03 -0800, York Sun wrote:
> > This patch set revises the DDR driver to support higher speed for DDR4
> > under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
> > Single quad-rank DIMM is not supported yet.
> 
> Hi York
> 
> Seeing these patches reminds me about something I have been mening to
> ask, Is it possible init the ddr controller/ddr ram (using ECC also) but still
> retain (parts of) memory contents?
> 
> I am looking at keeping data at the end of memory when performing a warm
> start, but still init the controll/ddr ram (without D_INIT set).
> This way one could pick up any changes to DDR timing if needed.
> Before reboot, ddr ram is set to Self Refresh(SR).
> 
>  Jocke
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Re: [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

[Yuantian Tang]

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Friday, November 06, 2015 1:42 AM
> To: Joakim Tjernlund <joakim.tjernl...@transmode.se>; Tang Yuantian-
> B29983 <yuantian.t...@freescale.com>; u-boot@lists.denx.de
> Cc: Kushwaha Prabhakar-B32579 <prabha...@freescale.com>; Sharma
> Bhupesh-B45370 <bhupesh.sha...@freescale.com>; tr...@konsulko.com;
> Liu Shengzhou-B36685 <shengzhou@freescale.com>;
> c...@cumulusnetworks.com; l.majew...@samsung.com;
> yamad...@jp.panasonic.com
> Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for
> LSCH3
> 
> 
> 
> On 11/05/2015 01:55 AM, Joakim Tjernlund wrote:
> > On Thu, 2015-11-05 at 08:23 +, Yuantian Tang wrote:
> >> Hi Jocke,
> >>
> >> we achieved deep sleep mode that did exactly what you asked for.
> >> If waken up from deep sleep, soc will resume from uboot and
> >> re-initialized DDR controller with contents untouched.
> >> Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP
> related code.
> >
> > Looking at it now and it looks the same as for ddr3? Some questions though:
> >  289if (is_warm_boot()) {
> >  289 /* enter self-refresh */
> >  290 temp_sdram_cfg = ddr_in32(>sdram_cfg_2);
> >  291 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
> >  292 ddr_out32(>sdram_cfg_2, temp_sdram_cfg);
> >
> > Why do you need to force SR here? The DDR RAM must already be in SR at
> this point?
> > I come from CPU reset state so my DDR controller has HW default values
> > so this does not feel safe.
> 
> This may be redundant. If the code runs to this line, it should come back from
> a deep sleep. The core is in reset state but the DDR controller is not. It 
> should
> be in self-refresh mode. I will leave that to Yuantian to comment.
> 
This is mandatory.  the steps are: re-enter SR mode, enable DDR controller, 
exit SR mode. We do that to smooth the transition and avoid any glitch caused 
when controller takes over memory.

Regards,
Yuantian
 
> >
> >  293 /* do board specific memory setup */
> >  294 board_mem_sleep_setup();
> >  295
> >  296 temp_sdram_cfg = (ddr_in32(>sdram_cfg) |
> SDRAM_CFG_BI);
> > SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to
> > change some DDR RAM timing/config due to a bug? Then you would have
> to force a cold start.
> >
> > Do you use ECC? Seems to be some issues with ECC if you skip D_INIT
> >
> 
> To perform a warm start, the data in DDR is preserved. So you don't need to
> init the data again for ECC. To preserve data, you cannot run D_INIT again,
> which will destroy the data for sure.
> 
> York
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Re: [U-Boot] [PATCH] arm: ls1021atwr: optimize the deep sleep latency

[Yuantian Tang]

Hi York,

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, October 15, 2015 5:34 AM
> To: Tang Yuantian-B29983 
> Cc: u-boot@lists.denx.de; Wang Huan-B18965 ;
> Kushwaha Prabhakar-B32579 
> Subject: Re: [PATCH] arm: ls1021atwr: optimize the deep sleep latency
> 
> 
> 
> On 09/24/2015 12:52 AM, Tang Yuantian wrote:
> > It will take more than 1s when wake up from deep sleep. Most of the
> > time is spent on outputing information. This patch reduced the deep
> > sleep latency by:
> > 1. avoid outputing system informaton
> > 2. remove flush cache after DDR restore 3. skip reloading second stage
> > uboot binary when SD boot
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> >  board/freescale/common/arm_sleep.c  |  4 
> >  board/freescale/ls1021atwr/ls1021atwr.c | 19 +--
> >  2 files changed, 17 insertions(+), 6 deletions(-)
> >
> > diff --git a/board/freescale/common/arm_sleep.c
> > b/board/freescale/common/arm_sleep.c
> > index 8e8b7fa..a498c65 100644
> > --- a/board/freescale/common/arm_sleep.c
> > +++ b/board/freescale/common/arm_sleep.c
> > @@ -12,7 +12,6 @@
> >  #include 
> >  #endif
> >  #include 
> > -#include 
> >
> >  #if defined(CONFIG_LS102XA)
> >  #include 
> > @@ -65,8 +64,6 @@ static void dp_ddr_restore(void)
> >
> > for (i = 0; i < DDR_BUFF_LEN / 8; i++)
> > *dst++ = *src++;
> > -
> > -   flush_dcache_all();
> >  }
> >
> >  static void dp_resume_prepare(void)
> > @@ -74,7 +71,6 @@ static void dp_resume_prepare(void)
> > dp_ddr_restore();
> > board_sleep_prepare();
> > armv7_init_nonsec();
> > -   cleanup_before_linux();
> >  #ifdef CONFIG_U_QE
> > u_qe_resume();
> >  #endif
> > diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
> > b/board/freescale/ls1021atwr/ls1021atwr.c
> > index 228dbf8..236376b 100644
> > --- a/board/freescale/ls1021atwr/ls1021atwr.c
> > +++ b/board/freescale/ls1021atwr/ls1021atwr.c
> > @@ -521,8 +521,10 @@ int board_early_init_f(void)
> > }
> >
> >  #if defined(CONFIG_DEEP_SLEEP)
> > -   if (is_warm_boot())
> > -   fsl_dp_disable_console();
> > +   if (is_warm_boot()) {
> > +   timer_init();
> > +   dram_init();
> > +   }
> >  #endif
> >
> > return 0;
> > @@ -531,6 +533,8 @@ int board_early_init_f(void)  #ifdef
> > CONFIG_SPL_BUILD  void board_init_f(ulong dummy)  {
> > +   void (*second_uboot)(void);
> > +
> > /* Clear the BSS */
> > memset(__bss_start, 0, __bss_end - __bss_start);
> >
> > @@ -551,6 +555,17 @@ void board_init_f(ulong dummy)
> > enable_devices_ns_access(_dev[7], 1);  #endif
> >
> > +   /*
> > +* if it is woken up from deep sleep, then jump to second
> > +* stage uboot and continue executing without recopying
> > +* it from SD since it has already been reserved in memeory
> > +* in last boot.
> > +*/
> > +   if (is_warm_boot()) {
> > +   second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
> > +   second_uboot();
> > +   }
> > +
> > board_init_r(NULL, 0);
> >  }
> >  #endif
> >
> 
> Yuantian,
> 
> Please explain more why the second stage u-boot is reserved? Wouldn't
> Linux overwrite the memory?
> 
If both CONFIG_DEEP_SLEEP and CONFIG_SD_BOOT are defined,
The DDR memory the second stage uboot occupied whould be reserved.
It is achieved in commit: 41ba57d0c which is the first patch to add the deep 
sleep support.

This patch doesn't reserve any memory, it just utilized the fact that the 
second stage uboot has been reserved already if deep sleep is enabled.

Regards,
Yuantian

> York
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Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

 -Original Message-
 From: Kushwaha Prabhakar-B32579
 Sent: Wednesday, August 19, 2015 8:54 PM
 To: Tang Yuantian-B29983; Sun York-R58495
 Cc: u-boot@lists.denx.de; Wang Huan-B18965
 Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
 
 
 
 Regards,
 Prabhakar
 
  -Original Message-
  From: Tang Yuantian-B29983
  Sent: Wednesday, August 19, 2015 10:17 AM
  To: Kushwaha Prabhakar-B32579; Sun York-R58495
  Cc: u-boot@lists.denx.de; Wang Huan-B18965
  Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
  board
 
 
 
   -Original Message-
   From: Kushwaha Prabhakar-B32579
   Sent: Wednesday, August 19, 2015 12:15 PM
   To: Tang Yuantian-B29983; Sun York-R58495
   Cc: u-boot@lists.denx.de; Wang Huan-B18965
   Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
   board
  
  
-Original Message-
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 8:01 AM
To: Sun York-R58495
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-
   B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and
twr
   board
   
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +#define SATA_ECC_REG_ADDR  0x20220520
  +   unsigned int __iomem *ecc_reg = (void
  *)SATA_ECC_REG_ADDR;
 #endif
  +
  +   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
  +   out_le32(ccsr_ahci-pp2c, 0x28183411);
  +   out_le32(ccsr_ahci-pp3c, 0x0e081004);
  +   out_le32(ccsr_ahci-pp4c, 0x00480811);
  +   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
  +   out_le32(ccsr_ahci-ptc, 0x0825);

  
   It looks to be SoC specific configuration. It should be in soc files
   not in board files.
  
  On other LS platforms we only need to set one register which is
  out_le32(ccsr_ahci-ppcfg, 0xa003fffe).
  There are did much same settings about sata between LS platforms.
  I thought about merging all the LS sata initialization together.
  Please see the patch:
  http://patchwork.ozlabs.org/patch/497983/
  But I didn't see much benefit this way. So I send the sata patch one
  platform to another.
 
 
 
 Problem is not with solution. Problem is with the place.
 This SoC errata fix but in board file. It should be in arch/arm/cpu/armv7
 
OK, I will put it under arch/arm/cpu/armv7/, just like what I did in SDK.

Regards,
Yuantian

 --prabhakar

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Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

 -Original Message-
 From: Kushwaha Prabhakar-B32579
 Sent: Thursday, August 20, 2015 9:33 AM
 To: Tang Yuantian-B29983; Sun York-R58495
 Cc: u-boot@lists.denx.de; Wang Huan-B18965
 Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
 
  -Original Message-
  From: Tang Yuantian-B29983
  Sent: Thursday, August 20, 2015 6:52 AM
  To: Kushwaha Prabhakar-B32579 prabha...@freescale.com; Sun York-
  R58495 york...@freescale.com
  Cc: u-boot@lists.denx.de; Wang Huan-B18965
 alison.w...@freescale.com
  Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
  board
 
 
 
   -Original Message-
   From: Kushwaha Prabhakar-B32579
   Sent: Wednesday, August 19, 2015 8:54 PM
   To: Tang Yuantian-B29983; Sun York-R58495
   Cc: u-boot@lists.denx.de; Wang Huan-B18965
   Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
   board
  
  
  
   Regards,
   Prabhakar
  
-Original Message-
From: Tang Yuantian-B29983
Sent: Wednesday, August 19, 2015 10:17 AM
To: Kushwaha Prabhakar-B32579; Sun York-R58495
Cc: u-boot@lists.denx.de; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and
twr board
   
   
   
 -Original Message-
 From: Kushwaha Prabhakar-B32579
 Sent: Wednesday, August 19, 2015 12:15 PM
 To: Tang Yuantian-B29983; Sun York-R58495
 Cc: u-boot@lists.denx.de; Wang Huan-B18965
 Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and
 twr board


  -Original Message-
  From: Tang Yuantian-B29983
  Sent: Wednesday, August 19, 2015 8:01 AM
  To: Sun York-R58495
  Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang
  Huan-
 B18965
  Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds
  and twr
 board
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+#define SATA_ECC_REG_ADDR  0x20220520
+   unsigned int __iomem *ecc_reg = (void
*)SATA_ECC_REG_ADDR;
   #endif
+
+   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
+   out_le32(ccsr_ahci-pp2c, 0x28183411);
+   out_le32(ccsr_ahci-pp3c, 0x0e081004);
+   out_le32(ccsr_ahci-pp4c, 0x00480811);
+   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
+   out_le32(ccsr_ahci-ptc, 0x0825);
  

 It looks to be SoC specific configuration. It should be in soc
 files not in board files.

On other LS platforms we only need to set one register which is
out_le32(ccsr_ahci-ppcfg, 0xa003fffe).
There are did much same settings about sata between LS platforms.
I thought about merging all the LS sata initialization together.
Please see the patch:
http://patchwork.ozlabs.org/patch/497983/
But I didn't see much benefit this way. So I send the sata patch
one platform to another.
   
  
  
   Problem is not with solution. Problem is with the place.
   This SoC errata fix but in board file. It should be in
   arch/arm/cpu/armv7
  
  OK, I will put it under arch/arm/cpu/armv7/, just like what I did in SDK.
 
  Regards,
  Yuantian
 
 
 This workaround can also go in FSL-SATA driver.
 
There is no fsl-sata driver for ls sata. This patch just added the stub before 
ahci driver is called.
So I will put this workaround and sata configuration together.
If there are any impropriate please inform me.

Regards,
Yuantian
 --prabhakar
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Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

OK, I will  updated this patch.

Regards,
Yuantian

From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

Sorry for top posting, replying from my phone.

Please use macros instead of numbers. It's still better than putting magic 
numbers in the code. And please move it out of board files.

York

 Original message 
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +#define SATA_ECC_REG_ADDR  0x20220520
  +   unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
 #endif
  +
  +   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
  +   out_le32(ccsr_ahci-pp2c, 0x28183411);
  +   out_le32(ccsr_ahci-pp3c, 0x0e081004);
  +   out_le32(ccsr_ahci-pp4c, 0x00480811);
  +   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
  +   out_le32(ccsr_ahci-ptc, 0x0825);

 What are these numbers?

I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for 
sata. They are gotten from validation team.
Their meanings are documented in RM. Is it necessary to re-explain bit by bit 
again?
Same reasons for ls2085.

Regards,
Yuantian

  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +   out_le32(ecc_reg, 0x0002);
  +#endif

 Same here.

  +}
  +
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +static int ls1021a_sata_start(void)
  +{
  +   struct ccsr_gur *gur = (struct ccsr_gur
 *)CONFIG_SYS_FSL_GUTS_ADDR;
  +   u32 cfg;
  +   int rc = -1;
  +
  +   cfg = in_be32(gur-rcwsr[4])  RCWSR4_SRDS1_PRTCL_MASK;
  +   cfg = RCWSR4_SRDS1_PRTCL_SHIFT;
  +
  +   if (cfg != 0x30  cfg != 0x70) {
  +   printf(SATA disabled: serdes protocol doesn't support\n);
  +   return rc;
  +   }
  +
  +   rc = ahci_init((void __iomem *)AHCI_BASE_ADDR);
  +   if (rc)
  +   return rc;
  +
  +   scsi_scan(0);
  +
  +   return 0;
  +}
  +#endif
  +
   #ifdef CONFIG_LS102XA_NS_ACCESS
   static struct csu_ns_dev ns_dev[] = {
   { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
  @@ -327,6 +375,8 @@ int board_early_init_f(void)
   fsl_dp_disable_console();
   #endif
 
  +   ls1021a_sata_init();

 Is it OK to run this init regardless SerDes protocol?

  +
   return 0;
   }
 
  @@ -388,6 +438,17 @@ void board_init_f(ulong dummy)  }  #endif
 
  +#ifdef CONFIG_BOARD_LATE_INIT
  +int board_late_init(void)
  +{
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +   ls1021a_sata_start();
  +#endif
  +
  +   return 0;
  +}
  +#endif
  +
   void config_etseccm_source(int etsec_gtx_125_mux)  {
   struct ccsr_scfg *scfg = (struct ccsr_scfg
  *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
  a/board/freescale/ls1021atwr/ls1021atwr.c
  b/board/freescale/ls1021atwr/ls1021atwr.c
  index b7458a9..6a964c3 100644
  --- a/board/freescale/ls1021atwr/ls1021atwr.c
  +++ b/board/freescale/ls1021atwr/ls1021atwr.c
  @@ -22,6 +22,8 @@
   #include tsec.h
   #include fsl_sec.h
   #include spl.h
  +#include ahci.h
  +#include scsi.h
   #include ../common/sleep.h
   #ifdef CONFIG_U_QE
   #include ../../../drivers/qe/qe.h
  @@ -173,6 +175,52 @@ struct cpld_data {
   u8 rev2;/* Reserved */
   };
 
  +static void ls1021a_sata_init(void)
  +{
  +   struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407

 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be
 in board file.

 York
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Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

I don't understand. This workaround is our board specific and actually ls1021 
specific. I thought about merging all the LS SATA initialization into one file, 
but that didn't reduce many code. So I add this one by one board.

Regards,
Yuantian

From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

The soc workarounds belongs to soc file, not board file, so you don't have to 
copy the code to every board. Our boards are not the only boards with this SoC.

York

 Original message 
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

Sorry for top posting, replying from my phone.

Please use macros instead of numbers. It's still better than putting magic 
numbers in the code. And please move it out of board files.

Yuantian:
Please move what out of board files, these magic numbers or sata init function?

Regards,
Yuantian

York

 Original message 
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +#define SATA_ECC_REG_ADDR  0x20220520
  +   unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
 #endif
  +
  +   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
  +   out_le32(ccsr_ahci-pp2c, 0x28183411);
  +   out_le32(ccsr_ahci-pp3c, 0x0e081004);
  +   out_le32(ccsr_ahci-pp4c, 0x00480811);
  +   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
  +   out_le32(ccsr_ahci-ptc, 0x0825);

 What are these numbers?

I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for 
sata. They are gotten from validation team.
Their meanings are documented in RM. Is it necessary to re-explain bit by bit 
again?
Same reasons for ls2085.

Regards,
Yuantian

  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +   out_le32(ecc_reg, 0x0002);
  +#endif

 Same here.

  +}
  +
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +static int ls1021a_sata_start(void)
  +{
  +   struct ccsr_gur *gur = (struct ccsr_gur
 *)CONFIG_SYS_FSL_GUTS_ADDR;
  +   u32 cfg;
  +   int rc = -1;
  +
  +   cfg = in_be32(gur-rcwsr[4])  RCWSR4_SRDS1_PRTCL_MASK;
  +   cfg = RCWSR4_SRDS1_PRTCL_SHIFT;
  +
  +   if (cfg != 0x30  cfg != 0x70) {
  +   printf(SATA disabled: serdes protocol doesn't support\n);
  +   return rc;
  +   }
  +
  +   rc = ahci_init((void __iomem *)AHCI_BASE_ADDR);
  +   if (rc)
  +   return rc;
  +
  +   scsi_scan(0);
  +
  +   return 0;
  +}
  +#endif
  +
   #ifdef CONFIG_LS102XA_NS_ACCESS
   static struct csu_ns_dev ns_dev[] = {
   { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
  @@ -327,6 +375,8 @@ int board_early_init_f(void)
   fsl_dp_disable_console();
   #endif
 
  +   ls1021a_sata_init();

 Is it OK to run this init regardless SerDes protocol?

  +
   return 0;
   }
 
  @@ -388,6 +438,17 @@ void board_init_f(ulong dummy)  }  #endif
 
  +#ifdef CONFIG_BOARD_LATE_INIT
  +int board_late_init(void)
  +{
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +   ls1021a_sata_start();
  +#endif
  +
  +   return 0;
  +}
  +#endif
  +
   void config_etseccm_source(int etsec_gtx_125_mux)  {
   struct ccsr_scfg *scfg = (struct ccsr_scfg
  *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
  a/board/freescale/ls1021atwr/ls1021atwr.c
  b/board/freescale/ls1021atwr/ls1021atwr.c
  index b7458a9..6a964c3 100644
  --- a/board/freescale/ls1021atwr/ls1021atwr.c
  +++ b/board/freescale/ls1021atwr/ls1021atwr.c
  @@ -22,6 +22,8 @@
   #include tsec.h
   #include fsl_sec.h
   #include spl.h
  +#include ahci.h
  +#include scsi.h
   #include ../common/sleep.h
   #ifdef CONFIG_U_QE
   #include ../../../drivers/qe/qe.h
  @@ -173,6 +175,52 @@ struct cpld_data {
   u8 rev2;/* Reserved */
   };
 
  +static void ls1021a_sata_init(void)
  +{
  +   struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407

 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be
 in board file.

 York
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Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

 -Original Message-
 From: Kushwaha Prabhakar-B32579
 Sent: Wednesday, August 19, 2015 12:15 PM
 To: Tang Yuantian-B29983; Sun York-R58495
 Cc: u-boot@lists.denx.de; Wang Huan-B18965
 Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
 
 
  -Original Message-
  From: Tang Yuantian-B29983
  Sent: Wednesday, August 19, 2015 8:01 AM
  To: Sun York-R58495
  Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-
 B18965
  Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr
 board
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+#define SATA_ECC_REG_ADDR  0x20220520
+   unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
   #endif
+
+   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
+   out_le32(ccsr_ahci-pp2c, 0x28183411);
+   out_le32(ccsr_ahci-pp3c, 0x0e081004);
+   out_le32(ccsr_ahci-pp4c, 0x00480811);
+   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
+   out_le32(ccsr_ahci-ptc, 0x0825);
  
 
 It looks to be SoC specific configuration. It should be in soc files not in 
 board
 files.
 
On other LS platforms we only need to set one register which is 
out_le32(ccsr_ahci-ppcfg, 0xa003fffe).
There are did much same settings about sata between LS platforms.
I thought about merging all the LS sata initialization together.
Please see the patch:
http://patchwork.ozlabs.org/patch/497983/
But I didn't see much benefit this way. So I send the sata patch one platform 
to another.

Regards,
Yuantian

 --prabhakar
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Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +#define SATA_ECC_REG_ADDR  0x20220520
  +   unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
 #endif
  +
  +   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
  +   out_le32(ccsr_ahci-pp2c, 0x28183411);
  +   out_le32(ccsr_ahci-pp3c, 0x0e081004);
  +   out_le32(ccsr_ahci-pp4c, 0x00480811);
  +   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
  +   out_le32(ccsr_ahci-ptc, 0x0825);
 
 What are these numbers?
 
I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for 
sata. They are gotten from validation team.
Their meanings are documented in RM. Is it necessary to re-explain bit by bit 
again?
Same reasons for ls2085.

Regards,
Yuantian
 
  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +   out_le32(ecc_reg, 0x0002);
  +#endif
 
 Same here.
 
  +}
  +
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +static int ls1021a_sata_start(void)
  +{
  +   struct ccsr_gur *gur = (struct ccsr_gur
 *)CONFIG_SYS_FSL_GUTS_ADDR;
  +   u32 cfg;
  +   int rc = -1;
  +
  +   cfg = in_be32(gur-rcwsr[4])  RCWSR4_SRDS1_PRTCL_MASK;
  +   cfg = RCWSR4_SRDS1_PRTCL_SHIFT;
  +
  +   if (cfg != 0x30  cfg != 0x70) {
  +   printf(SATA disabled: serdes protocol doesn't support\n);
  +   return rc;
  +   }
  +
  +   rc = ahci_init((void __iomem *)AHCI_BASE_ADDR);
  +   if (rc)
  +   return rc;
  +
  +   scsi_scan(0);
  +
  +   return 0;
  +}
  +#endif
  +
   #ifdef CONFIG_LS102XA_NS_ACCESS
   static struct csu_ns_dev ns_dev[] = {
  { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
  @@ -327,6 +375,8 @@ int board_early_init_f(void)
  fsl_dp_disable_console();
   #endif
 
  +   ls1021a_sata_init();
 
 Is it OK to run this init regardless SerDes protocol?
 
  +
  return 0;
   }
 
  @@ -388,6 +438,17 @@ void board_init_f(ulong dummy)  }  #endif
 
  +#ifdef CONFIG_BOARD_LATE_INIT
  +int board_late_init(void)
  +{
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +   ls1021a_sata_start();
  +#endif
  +
  +   return 0;
  +}
  +#endif
  +
   void config_etseccm_source(int etsec_gtx_125_mux)  {
  struct ccsr_scfg *scfg = (struct ccsr_scfg
  *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
  a/board/freescale/ls1021atwr/ls1021atwr.c
  b/board/freescale/ls1021atwr/ls1021atwr.c
  index b7458a9..6a964c3 100644
  --- a/board/freescale/ls1021atwr/ls1021atwr.c
  +++ b/board/freescale/ls1021atwr/ls1021atwr.c
  @@ -22,6 +22,8 @@
   #include tsec.h
   #include fsl_sec.h
   #include spl.h
  +#include ahci.h
  +#include scsi.h
   #include ../common/sleep.h
   #ifdef CONFIG_U_QE
   #include ../../../drivers/qe/qe.h
  @@ -173,6 +175,52 @@ struct cpld_data {
  u8 rev2;/* Reserved */
   };
 
  +static void ls1021a_sata_init(void)
  +{
  +   struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
 
 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be
 in board file.
 
 York
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Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

Sorry for top posting, replying from my phone.

Please use macros instead of numbers. It's still better than putting magic 
numbers in the code. And please move it out of board files.

Yuantian:
Please move what out of board files, these magic numbers or sata init function?

Regards,
Yuantian

York

 Original message 
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +#define SATA_ECC_REG_ADDR  0x20220520
  +   unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
 #endif
  +
  +   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
  +   out_le32(ccsr_ahci-pp2c, 0x28183411);
  +   out_le32(ccsr_ahci-pp3c, 0x0e081004);
  +   out_le32(ccsr_ahci-pp4c, 0x00480811);
  +   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
  +   out_le32(ccsr_ahci-ptc, 0x0825);

 What are these numbers?

I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for 
sata. They are gotten from validation team.
Their meanings are documented in RM. Is it necessary to re-explain bit by bit 
again?
Same reasons for ls2085.

Regards,
Yuantian

  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +   out_le32(ecc_reg, 0x0002);
  +#endif

 Same here.

  +}
  +
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +static int ls1021a_sata_start(void)
  +{
  +   struct ccsr_gur *gur = (struct ccsr_gur
 *)CONFIG_SYS_FSL_GUTS_ADDR;
  +   u32 cfg;
  +   int rc = -1;
  +
  +   cfg = in_be32(gur-rcwsr[4])  RCWSR4_SRDS1_PRTCL_MASK;
  +   cfg = RCWSR4_SRDS1_PRTCL_SHIFT;
  +
  +   if (cfg != 0x30  cfg != 0x70) {
  +   printf(SATA disabled: serdes protocol doesn't support\n);
  +   return rc;
  +   }
  +
  +   rc = ahci_init((void __iomem *)AHCI_BASE_ADDR);
  +   if (rc)
  +   return rc;
  +
  +   scsi_scan(0);
  +
  +   return 0;
  +}
  +#endif
  +
   #ifdef CONFIG_LS102XA_NS_ACCESS
   static struct csu_ns_dev ns_dev[] = {
   { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
  @@ -327,6 +375,8 @@ int board_early_init_f(void)
   fsl_dp_disable_console();
   #endif
 
  +   ls1021a_sata_init();

 Is it OK to run this init regardless SerDes protocol?

  +
   return 0;
   }
 
  @@ -388,6 +438,17 @@ void board_init_f(ulong dummy)  }  #endif
 
  +#ifdef CONFIG_BOARD_LATE_INIT
  +int board_late_init(void)
  +{
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +   ls1021a_sata_start();
  +#endif
  +
  +   return 0;
  +}
  +#endif
  +
   void config_etseccm_source(int etsec_gtx_125_mux)  {
   struct ccsr_scfg *scfg = (struct ccsr_scfg
  *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
  a/board/freescale/ls1021atwr/ls1021atwr.c
  b/board/freescale/ls1021atwr/ls1021atwr.c
  index b7458a9..6a964c3 100644
  --- a/board/freescale/ls1021atwr/ls1021atwr.c
  +++ b/board/freescale/ls1021atwr/ls1021atwr.c
  @@ -22,6 +22,8 @@
   #include tsec.h
   #include fsl_sec.h
   #include spl.h
  +#include ahci.h
  +#include scsi.h
   #include ../common/sleep.h
   #ifdef CONFIG_U_QE
   #include ../../../drivers/qe/qe.h
  @@ -173,6 +175,52 @@ struct cpld_data {
   u8 rev2;/* Reserved */
   };
 
  +static void ls1021a_sata_init(void)
  +{
  +   struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407

 Looks like ERRATUM A008407 is a SoC erratum. The workaround shouldn't be
 in board file.

 York
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Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

Yes, this is a ls1021 specific errata.
Maybe we need to name the errata micro better.

Regards,
Yuantian

From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:57 AM
To: Tang Yuantian-B29983
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board


Yuantian,



In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying 
this is a board erratum, not an SoC erratum?



York


From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board


I don't understand. This workaround is our board specific and actually ls1021 
specific. I thought about merging all the LS SATA initialization into one file, 
but that didn't reduce many code. So I add this one by one board.



Regards,

Yuantian



From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



The soc workarounds belongs to soc file, not board file, so you don't have to 
copy the code to every board. Our boards are not the only boards with this SoC.



York



 Original message 

From: Tang Yuantian-B29983

Date:08/18/2015 20:34 (GMT-08:00)

To: Sun York-R58495

Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965

Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board







From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



Sorry for top posting, replying from my phone.



Please use macros instead of numbers. It's still better than putting magic 
numbers in the code. And please move it out of board files.



Yuantian:

Please move what out of board files, these magic numbers or sata init function?



Regards,

Yuantian



York



 Original message 

From: Tang Yuantian-B29983

Date:08/18/2015 19:31 (GMT-08:00)

To: Sun York-R58495

Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965

Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +#define SATA_ECC_REG_ADDR  0x20220520
  +   unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
 #endif
  +
  +   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
  +   out_le32(ccsr_ahci-pp2c, 0x28183411);
  +   out_le32(ccsr_ahci-pp3c, 0x0e081004);
  +   out_le32(ccsr_ahci-pp4c, 0x00480811);
  +   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
  +   out_le32(ccsr_ahci-ptc, 0x0825);

 What are these numbers?

I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for 
sata. They are gotten from validation team.
Their meanings are documented in RM. Is it necessary to re-explain bit by bit 
again?
Same reasons for ls2085.

Regards,
Yuantian

  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +   out_le32(ecc_reg, 0x0002);
  +#endif

 Same here.

  +}
  +
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +static int ls1021a_sata_start(void)
  +{
  +   struct ccsr_gur *gur = (struct ccsr_gur
 *)CONFIG_SYS_FSL_GUTS_ADDR;
  +   u32 cfg;
  +   int rc = -1;
  +
  +   cfg = in_be32(gur-rcwsr[4])  RCWSR4_SRDS1_PRTCL_MASK;
  +   cfg = RCWSR4_SRDS1_PRTCL_SHIFT;
  +
  +   if (cfg != 0x30  cfg != 0x70) {
  +   printf(SATA disabled: serdes protocol doesn't support\n);
  +   return rc;
  +   }
  +
  +   rc = ahci_init((void __iomem *)AHCI_BASE_ADDR);
  +   if (rc)
  +   return rc;
  +
  +   scsi_scan(0);
  +
  +   return 0;
  +}
  +#endif
  +
   #ifdef CONFIG_LS102XA_NS_ACCESS
   static struct csu_ns_dev ns_dev[] = {
   { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
  @@ -327,6 +375,8 @@ int board_early_init_f(void)
   fsl_dp_disable_console();
   #endif
 
  +   ls1021a_sata_init();

 Is it OK to run this init regardless SerDes protocol?

  +
   return 0;
   }
 
  @@ -388,6 +438,17 @@ void board_init_f(ulong dummy)  }  #endif
 
  +#ifdef CONFIG_BOARD_LATE_INIT
  +int board_late_init(void)
  +{
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +   ls1021a_sata_start();
  +#endif
  +
  +   return 0;
  +}
  +#endif
  +
   void config_etseccm_source(int etsec_gtx_125_mux)  {
   struct ccsr_scfg *scfg = (struct ccsr_scfg
  *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git
  a/board/freescale/ls1021atwr/ls1021atwr.c
  b/board/freescale/ls1021atwr/ls1021atwr.c
  index b7458a9..6a964c3 100644
 

Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

On ls2085 we had a soc file which can put all the soc specific function in it.
But on ls1021, there is no such file unless I create one for SATA.

Please see the patch I first submit. Do you prefer this way?
http://patchwork.ozlabs.org/patch/497983/

Regards,
Yuantian

From: Sun York-R58495
Sent: Wednesday, August 19, 2015 12:39 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

That's exactly what I mean. It is ls1021 soc erratum, not board specific.

York

 Original message 
From: Tang Yuantian-B29983
Date:08/18/2015 21:36 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

Yes, this is a ls1021 specific errata.
Maybe we need to name the errata micro better.

Regards,
Yuantian

From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:57 AM
To: Tang Yuantian-B29983
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board


Yuantian,



In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying 
this is a board erratum, not an SoC erratum?



York


From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board


I don't understand. This workaround is our board specific and actually ls1021 
specific. I thought about merging all the LS SATA initialization into one file, 
but that didn't reduce many code. So I add this one by one board.



Regards,

Yuantian



From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



The soc workarounds belongs to soc file, not board file, so you don't have to 
copy the code to every board. Our boards are not the only boards with this SoC.



York



 Original message 

From: Tang Yuantian-B29983

Date:08/18/2015 20:34 (GMT-08:00)

To: Sun York-R58495

Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965

Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board







From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



Sorry for top posting, replying from my phone.



Please use macros instead of numbers. It's still better than putting magic 
numbers in the code. And please move it out of board files.



Yuantian:

Please move what out of board files, these magic numbers or sata init function?



Regards,

Yuantian



York



 Original message 

From: Tang Yuantian-B29983

Date:08/18/2015 19:31 (GMT-08:00)

To: Sun York-R58495

Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965

Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +#define SATA_ECC_REG_ADDR  0x20220520
  +   unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
 #endif
  +
  +   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
  +   out_le32(ccsr_ahci-pp2c, 0x28183411);
  +   out_le32(ccsr_ahci-pp3c, 0x0e081004);
  +   out_le32(ccsr_ahci-pp4c, 0x00480811);
  +   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
  +   out_le32(ccsr_ahci-ptc, 0x0825);

 What are these numbers?

I don't like magic number either, but I don't have a choice.
These numbers are used to overwrite the default value which are not working for 
sata. They are gotten from validation team.
Their meanings are documented in RM. Is it necessary to re-explain bit by bit 
again?
Same reasons for ls2085.

Regards,
Yuantian

  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +   out_le32(ecc_reg, 0x0002);
  +#endif

 Same here.

  +}
  +
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +static int ls1021a_sata_start(void)
  +{
  +   struct ccsr_gur *gur = (struct ccsr_gur
 *)CONFIG_SYS_FSL_GUTS_ADDR;
  +   u32 cfg;
  +   int rc = -1;
  +
  +   cfg = in_be32(gur-rcwsr[4])  RCWSR4_SRDS1_PRTCL_MASK;
  +   cfg = RCWSR4_SRDS1_PRTCL_SHIFT;
  +
  +   if (cfg != 0x30  cfg != 0x70) {
  +   printf(SATA disabled: serdes protocol doesn't support\n);
  +   return rc;
  +   }
  +
  +   rc = ahci_init((void __iomem *)AHCI_BASE_ADDR);
  +   if (rc)
  +

Re: [U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

OK, I will work with Prabhakar on this.

This is freescale specific settings and workaround. Other boards out of 
freescale don't use this.

Regards,
Yuantian

From: Sun York-R58495
Sent: Wednesday, August 19, 2015 12:47 PM
To: Tang Yuantian-B29983
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board


No, the old patch still use board files. Even it is a common board file, it is 
not common for other than freescale boards.



ls2085 didn't have an soc file to start with. When you have a situation like 
this, you create one. I will be out in next few days, please work with 
Prabhakar.



York




From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 9:43 PM
To: Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board


On ls2085 we had a soc file which can put all the soc specific function in it.

But on ls1021, there is no such file unless I create one for SATA.



Please see the patch I first submit. Do you prefer this way?

http://patchwork.ozlabs.org/patch/497983/



Regards,

Yuantian



From: Sun York-R58495
Sent: Wednesday, August 19, 2015 12:39 PM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



That's exactly what I mean. It is ls1021 soc erratum, not board specific.



York



 Original message 

From: Tang Yuantian-B29983

Date:08/18/2015 21:36 (GMT-08:00)

To: Sun York-R58495

Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965

Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



Yes, this is a ls1021 specific errata.

Maybe we need to name the errata micro better.



Regards,

Yuantian



From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:57 AM
To: Tang Yuantian-B29983
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



Yuantian,



In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying 
this is a board erratum, not an SoC erratum?



York





From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



I don't understand. This workaround is our board specific and actually ls1021 
specific. I thought about merging all the LS SATA initialization into one file, 
but that didn't reduce many code. So I add this one by one board.



Regards,

Yuantian



From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:38 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



The soc workarounds belongs to soc file, not board file, so you don't have to 
copy the code to every board. Our boards are not the only boards with this SoC.



York



 Original message 

From: Tang Yuantian-B29983

Date:08/18/2015 20:34 (GMT-08:00)

To: Sun York-R58495

Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965

Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board







From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de; Kushwaha 
Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



Sorry for top posting, replying from my phone.



Please use macros instead of numbers. It's still better than putting magic 
numbers in the code. And please move it out of board files.



Yuantian:

Please move what out of board files, these magic numbers or sata init function?



Regards,

Yuantian



York



 Original message 

From: Tang Yuantian-B29983

Date:08/18/2015 19:31 (GMT-08:00)

To: Sun York-R58495

Cc: u-boot@lists.denx.demailto:u-boot@lists.denx.de, Kushwaha 
Prabhakar-B32579 , Wang Huan-B18965

Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board



  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +#define SATA_ECC_REG_ADDR  0x20220520
  +   unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
 #endif
  +
  +   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
  +   out_le32(ccsr_ahci-pp2c, 0x28183411);
  +   out_le32(ccsr_ahci-pp3c, 0x0e081004);
  +   out_le32(ccsr_ahci-pp4c, 0x00480811);
  +   

Re: [U-Boot] [PATCH 1/2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian Tang]

 -Original Message-
 From: Wang Huan-B18965
 Sent: Friday, August 14, 2015 3:59 PM
 To: Tang Yuantian-B29983; Sun York-R58495
 Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Tang Yuantian-
 B29983
 Subject: RE: [PATCH 1/2] arm/ls1021a: Add sata support on qds and twr board
 
 Hi, Yuantian,
 
  From: Tang Yuantian yuantian.t...@freescale.com
 
  Freescale ARM-based Layerscape LS102xA contain a SATA controller which
  comply with the serial ATA 3.0 specification and the AHCI 1.3
  specification.
  This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
   arch/arm/include/asm/arch-ls102xa/config.h| 15 ++
   arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 24 +
   board/freescale/ls1021aqds/ls1021aqds.c   | 60
  +++
   board/freescale/ls1021atwr/ls1021atwr.c   | 60
  +++
   4 files changed, 159 insertions(+)
 
  diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
  b/arch/arm/include/asm/arch-ls102xa/config.h
  index c55cdef..a4a5d84 100644
  --- a/arch/arm/include/asm/arch-ls102xa/config.h
  +++ b/arch/arm/include/asm/arch-ls102xa/config.h
  @@ -79,6 +79,21 @@
   #define CONFIG_SYS_PCIE2_PHYS_ADDR
   (CONFIG_SYS_PCIE2_PHYS_BASE +
  \
 
 CONFIG_SYS_PCIE2_VIRT_ADDR)
 
  +/* SATA */
  +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR
 + 0x0220)
  +#define CONFIG_BOARD_LATE_INIT
  +#define CONFIG_CMD_SCSI
  +#define CONFIG_LIBATA
  +#define CONFIG_SCSI_AHCI
  +#define CONFIG_SCSI_AHCI_PLAT
  +#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
  +#define CONFIG_SYS_SCSI_MAX_LUN1
  +#define CONFIG_SYS_SCSI_MAX_DEVICE
   (CONFIG_SYS_SCSI_MAX_SCSI_ID
  * \
  +
   CONFIG_SYS_SCSI_MAX_LUN)
  +#define CONFIG_CMD_FAT
  +#define CONFIG_DOS_PARTITION
  +#define CONFIG_SYS_FSL_ERRATUM_A008407
  +
   #ifdef CONFIG_DDR_SPD
   #define CONFIG_SYS_FSL_DDR_BE
   #define CONFIG_VERY_BIG_RAM
  diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
  b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
  index d34044a..211fe1d 100644
  --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
  +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
  @@ -397,4 +397,28 @@ struct ccsr_cci400 {
  u8 res_e004[0x1 - 0xe004];
   };
 
  +/* AHCI (sata) register map */
  +struct ccsr_ahci {
  +   u32 res1[0xa4/4];   /* 0x0 - 0xa4 */
  +   u32 pcfg;   /* port config */
  +   u32 ppcfg;  /* port phy1 config */
  +   u32 pp2c;   /* port phy2 config */
  +   u32 pp3c;   /* port phy3 config */
  +   u32 pp4c;   /* port phy4 config */
  +   u32 pp5c;   /* port phy5 config */
  +   u32 paxic;  /* port AXI config */
  +   u32 axicc;  /* AXI cache control */
  +   u32 axipc;  /* AXI PROT control */
  +   u32 ptc;/* port Trans Config */
  +   u32 pts;/* port Trans Status */
  +   u32 plc;/* port link config */
  +   u32 plc1;   /* port link config1 */
  +   u32 plc2;   /* port link config2 */
  +   u32 pls;/* port link status */
  +   u32 pls1;   /* port link status1 */
  +   u32 pcmdc;  /* port CMD config */
  +   u32 ppcs;   /* port phy control status */
  +   u32 pberr;  /* port 0/1 BIST error */
  +   u32 cmds;   /* port 0/1 CMD status error */
  +};
   #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
  diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
  b/board/freescale/ls1021aqds/ls1021aqds.c
  index ce5cb52..c7ac953 100644
  --- a/board/freescale/ls1021aqds/ls1021aqds.c
  +++ b/board/freescale/ls1021aqds/ls1021aqds.c
  @@ -18,6 +18,8 @@
   #include fsl_ifc.h
   #include fsl_sec.h
   #include spl.h
  +#include ahci.h
  +#include scsi.h
 
   #include ../common/sleep.h
   #include ../common/qixis.h
  @@ -54,6 +56,51 @@ enum {
  GE1_CLK125,
   };
 
  +static void ls1021a_sata_init(void)
  +{
  +   struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +   unsigned int __iomem *dcfg_ecc = (void *)0x20220520; #endif
 [Alison Wang] Is it possible to use #define instead of magic number?

OK, sure , thanks.

Yuantian,

  +
  +   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
  +   out_le32(ccsr_ahci-pp2c, 0x28183411);
  +   out_le32(ccsr_ahci-pp3c, 0x0e081004);
  +   out_le32(ccsr_ahci-pp4c, 0x00480811);
  +   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
  +   out_le32(ccsr_ahci-ptc, 0x0825);
  +
  +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
  +   out_le32(dcfg_ecc, 0x0002);
  +#endif
  +}
  +
  +#ifdef CONFIG_SCSI_AHCI_PLAT
  +static int ls1021a_sata_start(void)
  +{
  +   struct ccsr_gur *gur = (struct ccsr_gur
  *)CONFIG_SYS_FSL_GUTS_ADDR;
  +   u32 cfg;
  +   int rc = -1;
  +
  +   cfg = in_be32(gur-rcwsr[4])  RCWSR4_SRDS1_PRTCL_MASK;
  +   cfg = RCWSR4_SRDS1_PRTCL_SHIFT;
  +
  +   if (cfg != 0x30  cfg != 0x70) {
  +   printf(SATA disabled: serdes protocol 

Re: [U-Boot] [U-Boot, v2] ahci: Fix compiling warnings under 64bit platforms

[Yuantian Tang]

Thanks for pointing out. Fixed in patch v3.

Regards,
Yuantian

 -Original Message-
 From: Tom Rini [mailto:tr...@konsulko.com]
 Sent: Thursday, July 09, 2015 9:48 AM
 To: Tang Yuantian-B29983
 Cc: Xie Shaohui-B21989; u-boot@lists.denx.de
 Subject: Re: [U-Boot,v2] ahci: Fix compiling warnings under 64bit platforms
 
 On Tue, Jul 07, 2015 at 03:48:26PM +0800, tang yuantian wrote:
 
  From: Tang Yuantian yuantian.t...@freescale.com
 
  When compling under 64bit platforms, there are lots of warnings,
  like:
 
  drivers/block/ahci.c:114:18: warning: cast to pointer from integer  of
  different size [-Wint-to-pointer-cast]
u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;
^
  drivers/block/ahci.c: In function ?.hci_host_init?.
  drivers/block/ahci.c:218:49: warning: cast from pointer to integer  of
  different size [-Wpointer-to-int-cast]
 probe_ent-port[i].port_mmio = ahci_port_base((u32) mmio, i);
 
  ..
 
  Signed-off-by: Shaohui Xie shaohui@freescale.com
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
 
 This introduces a warning with ELDK 5.5 on
 nitrogen6q,novena,ot1200_spl,nitrogen6q2g,m53evk,mx6qsabrelite,udoo_q
 uad,ima3-mx53,tb
 s2910,cm_fx6,ot1200,gwventana,mx53loco:
 
 ../drivers/block/dwc_ahsata.c:169:32: warning: assignment makes pointer
 from integer without a cast [enabled by default]
 ../drivers/block/dwc_ahsata.c: In function 'ahci_port_start':
 ../drivers/block/dwc_ahsata.c:523:2: warning: format '%x' expects argument
 of type 'unsigned int', but argument 2 has type 'ulong'
 [-Wformat=]
 
 --
 Tom
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Re: [U-Boot] [PATCH v2] ahci: Fix compiling warnings under 64bit platforms

[Yuantian Tang]

 -Original Message-
 From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
 Sent: Tuesday, July 07, 2015 7:20 PM
 To: Tang Yuantian-B29983
 Cc: tr...@konsulko.com; Xie Shaohui-B21989; u-boot@lists.denx.de
 Subject: Re: [U-Boot] [PATCH v2] ahci: Fix compiling warnings under 64bit
 platforms
 
 Hello yuantian.t...@freescale.com,
 
 On Tue, 7 Jul 2015 15:48:26 +0800, yuantian.t...@freescale.com
 yuantian.t...@freescale.com wrote:
  From: Tang Yuantian yuantian.t...@freescale.com
 
  When compling under 64bit platforms, there are lots of warnings,
  like:
 
  drivers/block/ahci.c:114:18: warning: cast to pointer from integer  of
  different size [-Wint-to-pointer-cast]
u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;
^
  drivers/block/ahci.c: In function ?.hci_host_init?.
  drivers/block/ahci.c:218:49: warning: cast from pointer to integer  of
  different size [-Wpointer-to-int-cast]
 probe_ent-port[i].port_mmio = ahci_port_base((u32) mmio, i);
 
  ..
 
  Signed-off-by: Shaohui Xie shaohui@freescale.com
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
  v2:
  - refined some type casts
 
 Out of curiosity, which toolchain are you using?
 
ARCH=arm64 
CROSS_COMPILE=gcc-linaro-aarch64-linux-gnu-4.8-2013.12_linux/bin/aarch64-linux-gnu-

I believe that any cross compile for arm64 will cause those warnings.

Regards,
Yuantian

 Amicalement,
 --
 Albert.
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Re: [U-Boot] [PATCH] ahci: Fix compiling warnings under 64bit platforms

[Yuantian Tang]

Please see the reply in line.

 -Original Message-
 From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
 Sent: Friday, July 03, 2015 10:41 PM
 To: Tang Yuantian-B29983
 Cc: Tom Rini; Hans de Goede; U-Boot Mailing List; Xie Shaohui-B21989
 Subject: Re: [PATCH] ahci: Fix compiling warnings under 64bit platforms
  @@ -135,9 +135,9 @@ struct ahci_sg {
   };
 
   struct ahci_ioports {
  -   u32 cmd_addr;
  -   u32 scr_addr;
  -   u32 port_mmio;
  +   void __iomem*cmd_addr;
  +   void __iomem*scr_addr;
  +   void __iomem*port_mmio;
 
 You could change those to ulong instead of pointers. Also there is
 map_sysmem() which converts a physical address (which can be defined
 as 32-bit even on a 64-bit machine if so-decided) into a pointer.
 
I prefer to use void __iomem * here for port_mmio because it is aligned to 
ahci_probe_ent-mmio_base which is also void __iomem *.
Cmd_addr and scr_addr are aligned to port_mmio also.

The rest of your comments will be addressed in next version.

Regards,
Yuantian

  struct ahci_cmd_hdr *cmd_slot;
  struct ahci_sg  *cmd_tbl_sg;
  u32 cmd_tbl;
  --
  2.1.0.27.g96db324
 
 
 Regards,
 Simon
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Re: [U-Boot] [PATCH] mpc85xx/t102xqds: convert deep sleep to generic board interface

[Yuantian Tang]

Hi York,

 -Original Message-
 From: Sun York-R58495
 Sent: Saturday, January 17, 2015 1:23 AM
 To: Tang Yuantian-B29983
 Cc: u-boot@lists.denx.de
 Subject: Re: [PATCH] mpc85xx/t102xqds: convert deep sleep to generic board
 interface
 
 Yuantian,
 
 On 01/15/2015 06:23 PM, Tang Yuantian-B29983 wrote:
  Hi York,
 
  Yes, I did it on purpose. T102XQDS is not supported in SDK1.7 anymore.
  So I don't want to put more efforts to add SPI/NAND/SD boot deep sleep
 support.
 
 That's not a good reason. Regardless if Freescale SDK supports a board, as 
 far as
 it benefits the community, we keep the support.
 
  That means t102xqds only supports nor-boot deep sleep and need not to
 update spl.c.
 
  It is the same case for T1040QDS.
 
 A note in readme would be nice. I am not going to push for a fix. Not having 
 the
 console silenced is no big deal in case someone uses SPL with deep sleep.

I am not sure I understand you right, but Non-nor deep sleep support is more 
than just disabling console.
We need to update board head file, like t102xqds.h, as well.
I think you are right. We should add non-nor boot support.

Please apply these patches. I will send another two patch to support QDS 
non-nor boot deep sleep on qds.

Regards,
Yuantian

 
 York
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Re: [U-Boot] [PATCH] mpc85xx/t102xqds: convert deep sleep to generic board interface

[Yuantian Tang]

Hi York,

Yes, I did it on purpose. T102XQDS is not supported in SDK1.7 anymore.
So I don't want to put more efforts to add SPI/NAND/SD boot deep sleep support.
That means t102xqds only supports nor-boot deep sleep and need not to update 
spl.c. 

It is the same case for T1040QDS.

Thanks,
Yuantian

 -Original Message-
 From: Sun York-R58495
 Sent: Friday, January 16, 2015 2:02 AM
 To: Tang Yuantian-B29983
 Cc: u-boot@lists.denx.de
 Subject: Re: [PATCH] mpc85xx/t102xqds: convert deep sleep to generic board
 interface
 
 Yuantian,
 
 On 12/17/2014 05:55 PM, Tang Yuantian wrote:
  A new deep sleep interface is introduced to support generic board
  structure. Converts it to use new interface.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
   board/freescale/t102xqds/ddr.c  | 19 +++
   board/freescale/t102xqds/t102xqds.c | 23 +++
   include/configs/T102xQDS.h  |  3 +++
   3 files changed, 33 insertions(+), 12 deletions(-)
 
 You disable console in spl.c for RDB, but not for QDS. Is that what you want?
 
 York

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Re: [U-Boot] [PATCH] mpc85xx: clean up the old deep sleep framework

[Yuantian Tang]

Hello York,

The following 3 patches, which are independent to each other, should be applied 
first before this one get applied.
You can apply these 4 patches in the order I sent them.

1. mpc85xx/t102xrdb: convert deep sleep to generic board interface
http://patchwork.ozlabs.org/patch/422189/ 
2. mpc85xx/t1040qds: convert deep sleep to generic board interface
http://patchwork.ozlabs.org/patch/422451/
3. mpc85xx/t102xqds: convert deep sleep to generic board interface
http://patchwork.ozlabs.org/patch/422447/

Thanks,
Yuantian

 -Original Message-
 From: York Sun [mailto:york...@freescale.com]
 Sent: Thursday, December 18, 2014 10:31 AM
 To: Tang Yuantian-B29983
 Cc: u-boot@lists.denx.de
 Subject: Re: [PATCH] mpc85xx: clean up the old deep sleep framework
 
 On 12/17/2014 06:26 PM, Tang Yuantian wrote:
  All the boards that support deep sleep feature are converted to deep
  sleep generic board interface. The old interface which support
  non-generic board is not used anymore. So clean it up.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
 
 I know for sure we have some patches pending. It would be helpful if you list 
 all
 the dependency so I won't apply this one first. It will be a good habit for 
 all future
 patches.
 
 York
 

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Re: [U-Boot] [PATCH v2 2/2] fsl/ls1021qds: Add deep sleep support

[Yuantian Tang]

Hello York,

This patch's dependent patch is merged into mainline. So there is no dependency 
for this patch anymore.

Thanks,
Yuantian

 -Original Message-
 From: Tang Yuantian [mailto:yuantian.t...@freescale.com]
 Sent: Wednesday, December 17, 2014 12:58 PM
 To: albert.u.b...@aribaud.net; Sun York-R58495
 Cc: u-boot@lists.denx.de; Tang Yuantian-B29983
 Subject: [PATCH v2 2/2] fsl/ls1021qds: Add deep sleep support
 
 Add deep sleep support on Freescale LS1021QDS platform.
 
 Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
 ---
 based on: u-boot-fsl-qoriq master.
 depends on patch: http://patchwork.ozlabs.org/patch/420999/
 which is applied to u-boot-mpc85xx master, awaiting upstream.
 v2:
   - added sd boot deep sleep support
 
  arch/arm/cpu/armv7/ls102xa/fdt.c| 19 +++
  board/freescale/ls1021aqds/ddr.c| 17 +
  board/freescale/ls1021aqds/ls1021aqds.c | 26 ++
  include/configs/ls1021aqds.h|  8 +++-
  4 files changed, 69 insertions(+), 1 deletion(-)
 
 diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c
 b/arch/arm/cpu/armv7/ls102xa/fdt.c
 index 989780d..4f226e9 100644
 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c
 +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
 @@ -133,4 +133,23 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
   do_fixup_by_compat_u32(blob, fsl, ls1021a-flexcan,
  clock-frequency, busclk / 2, 1);
 +
 +#if defined(CONFIG_DEEP_SLEEP)  defined(CONFIG_SD_BOOT)
 +#define UBOOT_HEAD_LEN   0x1000
 + /*
 +  * Reserved memory in SD boot deep sleep case.
 +  * Second stage uboot binary and malloc space should be reserved.
 +  * If the memory they occupied has not been reserved, then this
 +  * space would be used by kernel and overwritten in uboot when
 +  * deep sleep resume, which cause deep sleep failed.
 +  * Since second uboot binary has a head, that space need to be
 +  * reserved either(assuming its size is less than 0x1000).
 +  */
 + off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE -
 UBOOT_HEAD_LEN,
 + CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
 + UBOOT_HEAD_LEN);
 + if (off  0)
 + printf(Failed to reserve memory for SD boot deep sleep: %s\n,
 +fdt_strerror(off));
 +#endif
  }
 diff --git a/board/freescale/ls1021aqds/ddr.c 
 b/board/freescale/ls1021aqds/ddr.c
 index a539ff9..6435bf9 100644
 --- a/board/freescale/ls1021aqds/ddr.c
 +++ b/board/freescale/ls1021aqds/ddr.c
 @@ -7,6 +7,7 @@
  #include common.h
  #include fsl_ddr_sdram.h
  #include fsl_ddr_dimm_params.h
 +#include asm/io.h
  #include ddr.h
 
  DECLARE_GLOBAL_DATA_PTR;
 @@ -149,6 +150,17 @@ int fsl_ddr_get_dimm_params(dimm_params_t
 *pdimm,  }  #endif
 
 +#if defined(CONFIG_DEEP_SLEEP)
 +void board_mem_sleep_setup(void)
 +{
 + void __iomem *qixis_base = (void *)QIXIS_BASE;
 +
 + /* does not provide HW signals for power management */
 + clrbits_8(qixis_base + 0x21, 0x2);
 + udelay(1);
 +}
 +#endif
 +
  phys_size_t initdram(int board_type)
  {
   phys_size_t dram_size;
 @@ -159,6 +171,11 @@ phys_size_t initdram(int board_type)  #else
   dram_size =  fsl_ddr_sdram_size();
  #endif
 +
 +#if defined(CONFIG_DEEP_SLEEP)  !defined(CONFIG_SPL_BUILD)
 + fsl_dp_resume();
 +#endif
 +
   return dram_size;
  }
 
 diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
 b/board/freescale/ls1021aqds/ls1021aqds.c
 index f08e54f..97da47d 100644
 --- a/board/freescale/ls1021aqds/ls1021aqds.c
 +++ b/board/freescale/ls1021aqds/ls1021aqds.c
 @@ -20,6 +20,7 @@
  #include fsl_sec.h
  #include spl.h
 
 +#include ../common/sleep.h
  #include ../common/qixis.h
  #include ls1021aqds_qixis.h
  #ifdef CONFIG_U_QE
 @@ -195,6 +196,11 @@ int board_early_init_f(void)
* allow barrier transaction to DDR again */
   out_le32(cci-ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 
 +#if defined(CONFIG_DEEP_SLEEP)
 + if (is_warm_boot())
 + fsl_dp_disable_console();
 +#endif
 +
   return 0;
  }
 
 @@ -231,6 +237,11 @@ void board_init_f(ulong dummy)
 
   get_clocks();
 
 +#if defined(CONFIG_DEEP_SLEEP)
 + if (is_warm_boot())
 + fsl_dp_disable_console();
 +#endif
 +
   preloader_console_init();
 
  #ifdef CONFIG_SPL_I2C_SUPPORT
 @@ -503,6 +514,21 @@ int board_init(void)
   return 0;
  }
 
 +#if defined(CONFIG_DEEP_SLEEP)
 +void board_sleep_prepare(void)
 +{
 + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
 +
 + /* Set CCI-400 control override register to
 +  * enable barrier transaction */
 + out_le32(cci-ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 +
 +#ifdef CONFIG_LS102XA_NS_ACCESS
 + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); #endif } #endif
 +
  int ft_board_setup(void *blob, bd_t *bd)  {
   ft_cpu_setup(blob, bd);
 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index
 

Re: [U-Boot] [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation

[Yuantian Tang]

 -Original Message-
 From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
 Sent: Monday, October 27, 2014 5:42 PM
 To: Tang Yuantian-B29983
 Cc: Sun York-R58495; u-boot@lists.denx.de; Jin Zhengxiong-R64188
 Subject: Re: [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable
 before relocation
 
 Hello Yuantian,
 
 On Thu, 16 Oct 2014 04:42:06 +, Yuantian Tang
 yuantian.t...@freescale.com wrote:
Wouldn't it be better to declare gic_dist_base as a local variable?
   It is only used  once outside function armv7_switch_nonsec(). It
   could be replaced with
get_gicd_base_address() call.
   
   I am with you. That's what I did in the first version of this patch.
   Patch links is at: http://patchwork.ozlabs.org/patch/391065/
   But Albert seems have some concerns. The attached is what we discussed.
 
 FTR, I only had concerns with the patch subject / commit summary.
 Regarding the patch itself, I just asked whether the global was not used as 
 some
 means of coordination which would have been broken by turning it into a local,
 but you had checked, so that was fine.
 
   Now on the second thought, I prefer the way this patch proposed
   because if we define gic_dist_base as local variable, That means
   function
   get_gicd_base_address() should be usable at any time in any mode.
   Can we make sure of that in the future?
  
   I don't strongly object introducing a new local variable. But I
   don't see how the global variable is useful. Function
   get_gicd_base_address() should be available all the time. It reads
   PERIPHBASE register, or return a macro. It hasn't changed since the
   first patch added it in 2013. Not sure if the original author Andre 
   Przywara is
 available to comments.
  
  Thanks for your comments.
  If no one objects the original patch, I like to resubmit it.
 
  Hi Albert, what's your opinion on this?
 
 
 Which 'original patch' do you mean?
 
 If it is http://patchwork.ozlabs.org/patch/391065/ then I'm fine with it and 
 will
 apply it.
 
Yes, it is.
But I marked it as superseded because, as you suggested, this patch is resent 
as part of deep sleep patch set.
I will send deep sleep patch set v2 to address TOM's concerns. You can apply 
them all together.

Thanks,
Yuantian

  Regards,
  Yuantian
 
   York
  
 
 Amicalement,
 --
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Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian Tang]

 -Original Message-
 From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Tom Rini
 Sent: Wednesday, October 22, 2014 9:54 PM
 To: Tang Yuantian-B29983
 Cc: albert.u.b...@aribaud.net; Jin Zhengxiong-R64188; u-boot@lists.denx.de;
 Sun York-R58495
 Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for
 Freescale QorIQ platforms
 
 On Sun, Sep 28, 2014 at 04:59:45PM +0800, yuantian.t...@freescale.com
 wrote:
  From: Tang Yuantian yuantian.t...@freescale.com
 
  When Freescale QorIQ SoCs wake up from deep sleep, control is passed
  to the primary core that starts executing uboot. After re-initialized
  some IP blocks, like DDRC, kernel will take responsibility to continue
  to restore environment it leaves before.
 
  This patch adds the deep sleep framework support for all Freescale
  QorIQ platforms that use generic_board configuation.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
   common/board_f.c   | 10 +
   drivers/ddr/fsl/arm_ddr_gen3.c | 48
 +-
   include/fsl_ddr_sdram.h|  2 ++
   include/fsl_sleep.h| 32 
   4 files changed, 87 insertions(+), 5 deletions(-)  create mode 100644
  include/fsl_sleep.h
 
  diff --git a/common/board_f.c b/common/board_f.c index
  e6aa298..b736d29 100644
  --- a/common/board_f.c
  +++ b/common/board_f.c
  @@ -56,6 +56,9 @@
   #endif
   #include dm/root.h
   #include linux/compiler.h
  +#ifdef CONFIG_FSL_DEEP_SLEEP
  +#include fsl_sleep.h
  +#endif
 
   /*
* Pointer to initial global data area @@ -921,6 +924,9 @@ static
  init_fnc_t init_sequence_f[] = {  #if defined(CONFIG_MIPS) ||
  defined(CONFIG_PPC)
  init_func_ram,
   #endif
  +#ifdef CONFIG_FSL_DEEP_SLEEP
  +   fsl_dp_resume,
  +#endif
 
 Is there not an existing hook you can use here instead?  Is misc_init_f too 
 early?
Misc_init_f is too early, we need to put it between DDR initialization and 
relocation.

 If we're going to add a new hook in here, it needs to be somewhat generically
 named, with the requirements of the system spelled out.  
It is Freescale specific. Wouldn't be a misleading for other platforms that 
don't jump to kernel here?

 Some TI parts have a
 (setting aside marketing-speak) similar function and I believe the U-Boot 
 patches
 for that use an existing hook to notice what happened and do what's needed.
Which function did you refer to? I can check if it can be used.

Thanks,
Yuantian

 Thanks!
 

 --
 Tom
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Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian Tang]

Thanks for your hint. Unfortunately I can't find such place.
It needs to be placed between DDR initialization and relocation.
It is used on both PPC and ARM platforms.
Do you have any sugguestions?

Thanks,
Yuantian

From: Sun York-R58495
Sent: Thursday, October 23, 2014 11:06 AM
To: Tang Yuantian-B29983; Tom Rini
Cc: albert.u.b...@aribaud.net; Jin Zhengxiong-R64188; u-boot@lists.denx.de
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for 
Freescale QorIQ platforms


Yuantian,

Tom didn't suggest a specific hook. If you can use existing one, you don't have 
to create a new one. It's preferred if you can find a good place in existing 
xxx_f functions.

York

 Original Message 
From: Tang Yuantian-B29983
Sent: Wed, 22/10/2014 19:53
To: Tom Rini
CC: albert.u.b...@aribaud.netmailto:albert.u.b...@aribaud.net; Jin 
Zhengxiong-R64188 ; u-boot@lists.denx.demailto:u-boot@lists.denx.de; Sun 
York-R58495
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for 
Freescale QorIQ platforms

 -Original Message-
 From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Tom Rini
 Sent: Wednesday, October 22, 2014 9:54 PM
 To: Tang Yuantian-B29983
 Cc: albert.u.b...@aribaud.netmailto:albert.u.b...@aribaud.net; Jin 
 Zhengxiong-R64188; u-boot@lists.denx.demailto:u-boot@lists.denx.de;
 Sun York-R58495
 Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for
 Freescale QorIQ platforms

 On Sun, Sep 28, 2014 at 04:59:45PM +0800, 
 yuantian.t...@freescale.commailto:yuantian.t...@freescale.com
 wrote:
  From: Tang Yuantian 
  yuantian.t...@freescale.commailto:yuantian.t...@freescale.com
 
  When Freescale QorIQ SoCs wake up from deep sleep, control is passed
  to the primary core that starts executing uboot. After re-initialized
  some IP blocks, like DDRC, kernel will take responsibility to continue
  to restore environment it leaves before.
 
  This patch adds the deep sleep framework support for all Freescale
  QorIQ platforms that use generic_board configuation.
 
  Signed-off-by: Tang Yuantian 
  yuantian.t...@freescale.commailto:yuantian.t...@freescale.com
  ---
   common/board_f.c   | 10 +
   drivers/ddr/fsl/arm_ddr_gen3.c | 48
 +-
   include/fsl_ddr_sdram.h|  2 ++
   include/fsl_sleep.h| 32 
   4 files changed, 87 insertions(+), 5 deletions(-)  create mode 100644
  include/fsl_sleep.h
 
  diff --git a/common/board_f.c b/common/board_f.c index
  e6aa298..b736d29 100644
  --- a/common/board_f.c
  +++ b/common/board_f.c
  @@ -56,6 +56,9 @@
   #endif
   #include dm/root.h
   #include linux/compiler.h
  +#ifdef CONFIG_FSL_DEEP_SLEEP
  +#include fsl_sleep.h
  +#endif
 
   /*
* Pointer to initial global data area @@ -921,6 +924,9 @@ static
  init_fnc_t init_sequence_f[] = {  #if defined(CONFIG_MIPS) ||
  defined(CONFIG_PPC)
   init_func_ram,
   #endif
  +#ifdef CONFIG_FSL_DEEP_SLEEP
  +   fsl_dp_resume,
  +#endif

 Is there not an existing hook you can use here instead?  Is misc_init_f too 
 early?
Misc_init_f is too early, we need to put it between DDR initialization and 
relocation.

 If we're going to add a new hook in here, it needs to be somewhat generically
 named, with the requirements of the system spelled out.
It is Freescale specific. Wouldn't be a misleading for other platforms that 
don't jump to kernel here?

 Some TI parts have a
 (setting aside marketing-speak) similar function and I believe the U-Boot 
 patches
 for that use an existing hook to notice what happened and do what's needed.
Which function did you refer to? I can check if it can be used.

Thanks,
Yuantian

 Thanks!


 --
 Tom
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Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian Tang]

Thanks for your suggestions.
It sounds reasonable. I prefer the first one because we need to add calls in 
initdram() anyway.

Let's also take a look at what TI did and see if we can follow.

Thanks,
Yuantian

From: Sun York-R58495
Sent: Thursday, October 23, 2014 12:15 PM
To: Tang Yuantian-B29983; Tom Rini
Cc: albert.u.b...@aribaud.net; Jin Zhengxiong-R64188; u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for 
Freescale QorIQ platforms

Yuantian,

I examined current code closely and have two suggestions:

1. In initdram() function, add a call to fsl_dp_resume()
It is rational because the deep sleep resume is mainly dealing with memory. 
Doing this means you need to add calls to all boards with deep sleep feature 
enabled, not a lot at this moment.
2. Add a new hook at exact location you proposed
But change to a more generic name, eg misc_ram. Add a weak function misc_ram() 
doing nothing. Then you can add misc_ram() in board file where it is needed.

Both require to put a hook in all boards with deep sleep enabled.

York



From: Tang Yuantian-B29983 
yuantian.t...@freescale.commailto:yuantian.t...@freescale.com
Date: Wednesday, October 22, 2014 8:26 PM
To: York Sun york...@freescale.commailto:york...@freescale.com, Tom Rini 
tr...@ti.commailto:tr...@ti.com
Cc: albert.u.b...@aribaud.netmailto:albert.u.b...@aribaud.net 
albert.u.b...@aribaud.netmailto:albert.u.b...@aribaud.net, Jin 
Zhengxiong-R64188 jason@freescale.commailto:jason@freescale.com, 
u-boot@lists.denx.demailto:u-boot@lists.denx.de 
u-boot@lists.denx.demailto:u-boot@lists.denx.de
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for 
Freescale QorIQ platforms

Thanks for your hint. Unfortunately I can't find such place.
It needs to be placed between DDR initialization and relocation.
It is used on both PPC and ARM platforms.
Do you have any sugguestions?

Thanks,
Yuantian

From: Sun York-R58495
Sent: Thursday, October 23, 2014 11:06 AM
To: Tang Yuantian-B29983; Tom Rini
Cc: albert.u.b...@aribaud.netmailto:albert.u.b...@aribaud.net; Jin 
Zhengxiong-R64188; u-boot@lists.denx.demailto:u-boot@lists.denx.de
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for 
Freescale QorIQ platforms


Yuantian,

Tom didn't suggest a specific hook. If you can use existing one, you don't have 
to create a new one. It's preferred if you can find a good place in existing 
xxx_f functions.

York

 Original Message 
From: Tang Yuantian-B29983
Sent: Wed, 22/10/2014 19:53
To: Tom Rini
CC: albert.u.b...@aribaud.netmailto:albert.u.b...@aribaud.net; Jin 
Zhengxiong-R64188 ; u-boot@lists.denx.demailto:u-boot@lists.denx.de; Sun 
York-R58495
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for 
Freescale QorIQ platforms

 -Original Message-
 From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Tom Rini
 Sent: Wednesday, October 22, 2014 9:54 PM
 To: Tang Yuantian-B29983
 Cc: albert.u.b...@aribaud.netmailto:albert.u.b...@aribaud.net; Jin 
 Zhengxiong-R64188; u-boot@lists.denx.demailto:u-boot@lists.denx.de;
 Sun York-R58495
 Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for
 Freescale QorIQ platforms

 On Sun, Sep 28, 2014 at 04:59:45PM +0800, 
 yuantian.t...@freescale.commailto:yuantian.t...@freescale.com
 wrote:
  From: Tang Yuantian 
  yuantian.t...@freescale.commailto:yuantian.t...@freescale.com
 
  When Freescale QorIQ SoCs wake up from deep sleep, control is passed
  to the primary core that starts executing uboot. After re-initialized
  some IP blocks, like DDRC, kernel will take responsibility to continue
  to restore environment it leaves before.
 
  This patch adds the deep sleep framework support for all Freescale
  QorIQ platforms that use generic_board configuation.
 
  Signed-off-by: Tang Yuantian 
  yuantian.t...@freescale.commailto:yuantian.t...@freescale.com
  ---
   common/board_f.c   | 10 +
   drivers/ddr/fsl/arm_ddr_gen3.c | 48
 +-
   include/fsl_ddr_sdram.h|  2 ++
   include/fsl_sleep.h| 32 
   4 files changed, 87 insertions(+), 5 deletions(-)  create mode 100644
  include/fsl_sleep.h
 
  diff --git a/common/board_f.c b/common/board_f.c index
  e6aa298..b736d29 100644
  --- a/common/board_f.c
  +++ b/common/board_f.c
  @@ -56,6 +56,9 @@
   #endif
   #include dm/root.h
   #include linux/compiler.h
  +#ifdef CONFIG_FSL_DEEP_SLEEP
  +#include fsl_sleep.h
  +#endif
 
   /*
* Pointer to initial global data area @@ -921,6 +924,9 @@ static
  init_fnc_t init_sequence_f[] = {  #if defined(CONFIG_MIPS) ||
  defined(CONFIG_PPC)
   init_func_ram,
   #endif
  +#ifdef CONFIG_FSL_DEEP_SLEEP
  +   fsl_dp_resume,
  +#endif

 Is there not an existing hook you can use here instead?  Is misc_init_f too 
 early?
Misc_init_f is too early, we need to put it between DDR initialization and 
relocation.

 If we're going 

Re: [U-Boot] [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation

[Yuantian Tang]

 -Original Message-
 From: Sun York-R58495
 Sent: Wednesday, October 15, 2014 11:44 PM
 To: Tang Yuantian-B29983; albert.u.b...@aribaud.net
 Cc: u-boot@lists.denx.de; Jin Zhengxiong-R64188
 Subject: Re: [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable
 before relocation
 
 On 10/09/2014 01:11 AM, yuantian.t...@freescale.com wrote:
  From: Tang Yuantian yuantian.t...@freescale.com
 
  Defining variable gic_dist_addr as a globe one prevents function
  armv7_init_nonsec() from being used before relocation which is the
  case in the deep sleep resume process on Freescale QorIQ SoC
  platforms.
  This patch removes this limitation by adding a extra same meaning
  local variable. In this way, no exsiting codes get corrupts.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
   arch/arm/cpu/armv7/virt-v7.c | 14 --
   1 file changed, 8 insertions(+), 6 deletions(-)
 
  diff --git a/arch/arm/cpu/armv7/virt-v7.c
  b/arch/arm/cpu/armv7/virt-v7.c index 651ca40..e1dfce9 100644
  --- a/arch/arm/cpu/armv7/virt-v7.c
  +++ b/arch/arm/cpu/armv7/virt-v7.c
  @@ -75,6 +75,7 @@ int armv7_init_nonsec(void)  {
  unsigned int reg;
  unsigned itlinesnr, i;
  +   unsigned long gic_base_addr;
 
  /* check whether the CPU supports the security extensions */
  reg = read_id_pfr1();
  @@ -89,23 +90,24 @@ int armv7_init_nonsec(void)
   * any access to it will trap.
   */
 
  -   gic_dist_addr = get_gicd_base_address();
  -   if (gic_dist_addr == -1)
  +   gic_base_addr = get_gicd_base_address();
  +   gic_dist_addr = gic_base_addr;
  +   if (gic_base_addr == -1)
  return -1;
 
  /* enable the GIC distributor */
  -   writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
  -  gic_dist_addr + GICD_CTLR);
  +   writel(readl(gic_base_addr + GICD_CTLR) | 0x03,
  +  gic_base_addr + GICD_CTLR);
 
  /* TYPER[4:0] contains an encoded number of available interrupts */
  -   itlinesnr = readl(gic_dist_addr + GICD_TYPER)  0x1f;
  +   itlinesnr = readl(gic_base_addr + GICD_TYPER)  0x1f;
 
  /* set all bits in the GIC group registers to one to allow access
   * from non-secure state. The first 32 interrupts are private per
   * CPU and will be set later when enabling the GIC for each core
   */
  for (i = 1; i = itlinesnr; i++)
  -   writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
  +   writel((unsigned)-1, gic_base_addr + GICD_IGROUPRn + 4 * i);
 
   #ifndef CONFIG_ARMV7_PSCI
  smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen),
  -1);
 
 
 Wouldn't it be better to declare gic_dist_base as a local variable? It is 
 only used
 once outside function armv7_switch_nonsec(). It could be replaced with
 get_gicd_base_address() call.
 
I am with you. That's what I did in the first version of this patch. Patch 
links is at: http://patchwork.ozlabs.org/patch/391065/
But Albert seems have some concerns. The attached is what we discussed.

Now on the second thought, I prefer the way this patch proposed because if we 
define gic_dist_base as local variable,
That means function get_gicd_base_address() should be usable at any time in any 
mode. Can we make sure of that in the future?

Regards,
Yuantian

 York

---BeginMessage---
Hello Albert,

 -Original Message-
 From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
 Sent: Friday, September 19, 2014 11:58 PM
 To: Tang Yuantian-B29983
 Subject: Re: [PATCH] ARM: HYP/non-sec: Make a variable as a local one

  
   Did you check that the global was not used as a common variable
   between the functions?
  
  Yes, I grep it globally. It was referred by only 2 places which are both in 
  virt-v7.c
 file.

 The grepping alone does not prove it's not used as a common variable.
 If it's read then written in one function and read in another, then maing it 
 local
 will probably cause ugly issues.

That's not going to happen. This variable would be assigned a value of GIC 
BASE ADDRESS.
In any time, it is only allowed to read, no permission to write.
If you are not sure about this, I can do this in another way which is adding a 
local variable and
assigned gic_dist_addr to it. That would not break any existing code.

Thanks,
Yuantian

  I will fix the subject.

 Thanks.

  Thanks,
  Yuantian
 
   Amicalement,
   --
   Albert.


 Amicalement,
 --
 Albert.
---End Message---
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Re: [U-Boot] [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation

[Yuantian Tang]

  Wouldn't it be better to declare gic_dist_base as a local variable?
 It is only used  once outside function armv7_switch_nonsec(). It could
 be replaced with
  get_gicd_base_address() call.
 
 I am with you. That's what I did in the first version of this patch.
 Patch links is at: http://patchwork.ozlabs.org/patch/391065/
 But Albert seems have some concerns. The attached is what we discussed.
 
 Now on the second thought, I prefer the way this patch proposed because
 if we define gic_dist_base as local variable, That means function
 get_gicd_base_address() should be usable at any time in any mode. Can
 we make sure of that in the future?
 
 I don't strongly object introducing a new local variable. But I don't see how 
 the
 global variable is useful. Function get_gicd_base_address() should be 
 available all
 the time. It reads PERIPHBASE register, or return a macro. It hasn't changed
 since the first patch added it in 2013. Not sure if the original author Andre
 Przywara is available to comments.
 
Thanks for your comments.
If no one objects the original patch, I like to resubmit it.

Hi Albert, what's your opinion on this?

Regards,
Yuantian

 York
 

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Re: [U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms

[Yuantian Tang]

PING.

Thanks,
Yuantian

 -Original Message-
 From: yuantian.t...@freescale.com [mailto:yuantian.t...@freescale.com]
 Sent: Thursday, October 09, 2014 4:12 PM
 To: albert.u.b...@aribaud.net
 Cc: u-boot@lists.denx.de; Jin Zhengxiong-R64188; Sun York-R58495; Tang
 Yuantian-B29983
 Subject: [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms
 
 From: Tang Yuantian yuantian.t...@freescale.com
 
 These patches depend on the following patches:
 https://patchwork.ozlabs.org/patch/389949/
 https://patchwork.ozlabs.org/patch/389950/
 https://patchwork.ozlabs.org/patch/389951/
 https://patchwork.ozlabs.org/patch/389952/
 
 Tang Yuantian (4):
   Add deep sleep framework support for Freescale QorIQ platforms
   ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation
   arm: ls102xa: Fixed a register definition error
   arm: ls1021qds: Add deep sleep support
 
  arch/arm/cpu/armv7/virt-v7.c  | 14 +++---
  arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
  board/freescale/ls1021aqds/ddr.c  |  7 +++
  board/freescale/ls1021aqds/ls1021aqds.c   | 60
 +++
  common/board_f.c  | 10 
  drivers/ddr/fsl/arm_ddr_gen3.c| 48
 --
  include/configs/ls1021aqds.h  |  4 ++
  include/fsl_ddr_sdram.h   |  2 +
  include/fsl_sleep.h   | 32 
  9 files changed, 167 insertions(+), 12 deletions(-)  create mode 100644
 include/fsl_sleep.h
 
 --
 2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms

[Yuantian Tang]

 -Original Message-
 From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
 Sent: Monday, October 13, 2014 5:46 PM
 To: Tang Yuantian-B29983
 Cc: u-boot@lists.denx.de; Jin Zhengxiong-R64188; Sun York-R58495
 Subject: Re: [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms
 
 Hi Yuantian,
 
 On Mon, 13 Oct 2014 09:41:35 +, Yuantian Tang
 yuantian.t...@freescale.com wrote:
 
  PING.
 
 This submission is only 4 days old, across a week ending. Can you please wait 
 a
 bit longer before pinging?
 
Yeah, I should've waited longer.
That you responded so quickly to the patches I sent earlier makes me think you 
are always a quick responder.
Take your time.

Thanks,
Yuantian
  Thanks,
  Yuantian
 
 Amicalement,
 --
 Albert.
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Re: [U-Boot] [PATCH] arm: ls102xa: Fixed a register definition error

[Yuantian Tang]

OK, if you say so.

Thanks,
Yuantian

 -Original Message-
 From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
 Sent: Friday, September 19, 2014 11:59 PM
 To: Tang Yuantian-B29983
 Cc: Wang Huan-B18965; Lu Jingchang-B35083; Jin Zhengxiong-R64188;
 Kushwaha Prabhakar-B32579; u-boot@lists.denx.de
 Subject: Re: [PATCH] arm: ls102xa: Fixed a register definition error
 
 Hi Yuantian,
 
 On Fri, 19 Sep 2014 01:45:52 +, Yuantian Tang
 yuantian.t...@freescale.com wrote:
 
 
   -Original Message-
   From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
   Sent: Thursday, September 18, 2014 7:25 PM
   To: Tang Yuantian-B29983
   Cc: Wang Huan-B18965; Lu Jingchang-B35083; Jin Zhengxiong-R64188;
   Kushwaha Prabhakar-B32579; u-boot@lists.denx.de
   Subject: Re: [PATCH] arm: ls102xa: Fixed a register definition error
  
   Hi Tang,
  
   On Thu, 18 Sep 2014 17:12:06 +0800, Tang Yuantian
   yuantian.t...@freescale.com wrote:
  
There are 8 SCFG_SPARECR registers in SCFG memory block, not just one.
   
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
   
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..b5db720 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,7 +182,7 @@ struct ccsr_scfg {
u32 etsecmcr;
u32 sdhciovserlcr;
u32 resv14[61];
-   u32 sparecr;
+   u32 sparecr[8];
 };
   
 /* Clocking */
  
   Obviously the original code was not problematic as sparecr was not
   used. Is your change dictated by a patch or series that you are
   preparing and that will use sparecr?
  
  Yes, they will be used by deep sleep patches I am preparing.
 
 Then please post them inside the deep sleep patch series.
 
  Thanks,
  Yuantian
 
   Amicalement,
 
 Amicalement,
 --
 Albert.
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Re: [U-Boot] [PATCH] arm: ls102xa: Fixed a register definition error

[Yuantian Tang]

 -Original Message-
 From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
 Sent: Thursday, September 18, 2014 7:25 PM
 To: Tang Yuantian-B29983
 Cc: Wang Huan-B18965; Lu Jingchang-B35083; Jin Zhengxiong-R64188;
 Kushwaha Prabhakar-B32579; u-boot@lists.denx.de
 Subject: Re: [PATCH] arm: ls102xa: Fixed a register definition error
 
 Hi Tang,
 
 On Thu, 18 Sep 2014 17:12:06 +0800, Tang Yuantian
 yuantian.t...@freescale.com wrote:
 
  There are 8 SCFG_SPARECR registers in SCFG memory block, not just one.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
   arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)
 
  diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
  b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
  index 7995fe2..b5db720 100644
  --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
  +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
  @@ -182,7 +182,7 @@ struct ccsr_scfg {
  u32 etsecmcr;
  u32 sdhciovserlcr;
  u32 resv14[61];
  -   u32 sparecr;
  +   u32 sparecr[8];
   };
 
   /* Clocking */
 
 Obviously the original code was not problematic as sparecr was not used. Is 
 your
 change dictated by a patch or series that you are preparing and that will use
 sparecr?
 
Yes, they will be used by deep sleep patches I am preparing.

Thanks,
Yuantian

 Amicalement,
 --
 Albert.
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Re: [U-Boot] [PATCH] ARM: HYP/non-sec: Make a variable as a local one

[Yuantian Tang]

 -Original Message-
 From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
 Sent: Thursday, September 18, 2014 5:44 PM
 To: Tang Yuantian-B29983
 Cc: andre.przyw...@linaro.org; i...@hellion.org.uk; marc.zyng...@arm.com;
 u-boot@lists.denx.de; Jin Zhengxiong-R64188
 Subject: Re: [PATCH] ARM: HYP/non-sec: Make a variable as a local one
 
 Hi Tang,
 
 Please fix subject / commit summary to indicate which variable is to be made
 local.
 
 On Thu, 18 Sep 2014 17:12:34 +0800, Tang Yuantian
 yuantian.t...@freescale.com wrote:
 
  Defining variable gic_dist_addr as a globe one prevents some
  functions, which use this variable, from being used before relocation
  which happened in the deep sleep resume process on Freescale SoC
  platforms.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
   arch/arm/cpu/armv7/virt-v7.c | 9 +++--
   1 file changed, 7 insertions(+), 2 deletions(-)
 
  diff --git a/arch/arm/cpu/armv7/virt-v7.c
  b/arch/arm/cpu/armv7/virt-v7.c index 651ca40..b69fd37 100644
  --- a/arch/arm/cpu/armv7/virt-v7.c
  +++ b/arch/arm/cpu/armv7/virt-v7.c
  @@ -15,8 +15,6 @@
   #include asm/io.h
   #include asm/secure.h
 
  -unsigned long gic_dist_addr;
  -
   static unsigned int read_id_pfr1(void)  {
  unsigned int reg;
  @@ -68,6 +66,12 @@ static void kick_secondary_cpus_gic(unsigned long
  gicdaddr)
 
   void __weak smp_kick_all_cpus(void)
   {
  +   unsigned long gic_dist_addr;
  +
  +   gic_dist_addr = get_gicd_base_address();
  +   if (gic_dist_addr == -1)
  +   return;
  +
  kick_secondary_cpus_gic(gic_dist_addr);
   }
 
  @@ -75,6 +79,7 @@ int armv7_init_nonsec(void)  {
  unsigned int reg;
  unsigned itlinesnr, i;
  +   unsigned long gic_dist_addr;
 
  /* check whether the CPU supports the security extensions */
  reg = read_id_pfr1();
 
 Did you check that the global was not used as a common variable between the
 functions?
 
Yes, I grep it globally. It was referred by only 2 places which are both in 
virt-v7.c file.

I will fix the subject.

Thanks,
Yuantian

 Amicalement,
 --
 Albert.
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Re: [U-Boot] [PATCH 2/2 v2] mpc85xx/t104x: Add deep sleep framework support

[Yuantian Tang]

 
  Could you be more specific? What *path* should I give?
  If I do the below, I got error:
 
  $ make O=/home/tangyt/opensource/u-boot/
/home/tangyt/opensource/u-boot is not clean, please run 'make
 mrproper'
in the '/home/tangyt/opensource/u-boot' directory.
  make[1]: *** [prepare3] Error 1
  make: *** [sub-make] Error 2
 
 
 It is out-of-tree compiling. You should use a clean path.
 
 cd u-boot source)
 mkdir ../build
 make O=../build T1040QDS_config
 make O=../build
 
 You should add other flags you normally use.
 
 York
 
I reproduced this issue. 
I am trying to fix it. Meanwhile please continue to review.

Regards,
Yuantian
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Re: [U-Boot] [PATCH 2/2 v2] mpc85xx/t104x: Add deep sleep framework support

[Yuantian Tang]

 -Original Message-
 From: Sun York-R58495
 Sent: Tuesday, March 11, 2014 1:45 AM
 To: Tang Yuantian-B29983
 Cc: u-boot@lists.denx.de; Li Yang-Leo-R58472; Jin Zhengxiong-R64188; Wood
 Scott-B07421
 Subject: Re: [PATCH 2/2 v2] mpc85xx/t104x: Add deep sleep framework
 support
 
 On 02/28/2014 03:09 AM, yuantian.t...@freescale.com wrote:
  From: Tang Yuantian yuantian.t...@freescale.com
 
  When T104x soc wakes up from deep sleep, control is passed to the
  primary core that starts executing uboot. After re-initialized some IP
  blocks, like DDRC, kernel will take responsibility to continue to
  restore environment it leaves before.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
  v2:
  - added explaination for CONFIG_DEEP_SLEEP
  - fixed some issues
 
   README |  4 +++
   arch/powerpc/cpu/mpc85xx/asm-offsets.c | 24 ++
 
 Please fix the out-of-tree compiling issue. You will see it if you run
 make with O=path parameter.
 
 York

Could you be more specific? What *path* should I give?
If I do the below, I got error:

$ make O=/home/tangyt/opensource/u-boot/
  /home/tangyt/opensource/u-boot is not clean, please run 'make mrproper'
  in the '/home/tangyt/opensource/u-boot' directory.
make[1]: *** [prepare3] Error 1
make: *** [sub-make] Error 2

Thanks,
Yuantian
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[U-Boot] test

[Yuantian Tang]

have a test. please ignore.



Regards,

yuantian


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[U-Boot] how to get rid of No base64 encoded MIME text parts?

[Yuantian Tang]

Hi all,

I keep receiving Message rejected. No base64 encoded MIME text parts allowed. 
when I reply email.


Could someone tell me how to find base64 encoded MIME text parts?

Thanks,
Yuantian

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