[PATCH v2 4/4] board: freescale: ls1088a: declare MC reserved regions
Populate the device tree with the MC reserved memory regions. Signed-off-by: Laurentiu Tudor --- board/freescale/ls1088a/ls1088a.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 65593f10a3f5..7674e31a268a 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -983,6 +983,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); #endif fdt_fixup_icid(blob); -- 2.17.1
[PATCH v2 3/4] board: freescale: ls2080a: declare MC reserved regions
Populate the device tree with the MC reserved memory regions. Signed-off-by: Laurentiu Tudor --- board/freescale/ls2080aqds/ls2080aqds.c | 1 + board/freescale/ls2080ardb/ls2080ardb.c | 1 + 2 files changed, 2 insertions(+) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index ba25e9b0b8fc..5c94c83121b5 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -325,6 +325,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); #endif fdt_fixup_icid(blob); diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 8d340f17a256..5c30de83d841 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -522,6 +522,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); #endif fdt_fixup_icid(blob); -- 2.17.1
[PATCH v2 2/4] drivers: net: fsl-mc: add support for MC reserved memory
Add support for declaring in device tree the reserved memory ranges
required for MC. Since the MC firmware acts as any DMA master present
in the SoC, the reserved memory ranges need also be identity mapped
in the SMMU, so create the required 'iommu-addresses' property in
the reserved memory nodes.
For now this support is used only on LX2160A SoCs.
Signed-off-by: Laurentiu Tudor
---
board/freescale/lx2160a/lx2160a.c | 1 +
drivers/net/fsl-mc/mc.c | 110 ++
include/fsl-mc/fsl_mc.h | 1 +
3 files changed, 112 insertions(+)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index d631a11ff667..688d81f04f64 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -834,6 +834,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_FSL_MC_ENET
fdt_fsl_mc_fixup_iommu_map_entry(blob);
fdt_fixup_board_enet(blob);
+ fdt_reserve_mc_mem(blob, 0x4000);
#endif
fdt_fixup_icid(blob);
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 984616fb65c0..f5c5057bec10 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -30,6 +30,8 @@
#include
#include
#include
+#include
+#include
#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK(~(MC_RAM_BASE_ADDR_ALIGNMENT -
1))
@@ -929,6 +931,114 @@ unsigned long mc_get_dram_block_size(void)
return dram_block_size;
}
+/**
+ * Populate the device tree with MC reserved memory ranges.
+ */
+void fdt_reserve_mc_mem(void *blob, u32 mc_icid)
+{
+ u32 phandle, mc_ph;
+ int noff, ret, i;
+ char mem_name[16];
+ struct fdt_memory mc_mem_ranges[] = {
+ {
+ .start = 0,
+ .end = 0
+ },
+ {
+ .start = CFG_SYS_FSL_MC_BASE,
+ .end = CFG_SYS_FSL_MC_BASE + CFG_SYS_FSL_MC_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_NI_BASE,
+ .end = CFG_SYS_FSL_NI_BASE + CFG_SYS_FSL_NI_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_QBMAN_BASE,
+ .end = CFG_SYS_FSL_QBMAN_BASE +
+ CFG_SYS_FSL_QBMAN_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_PEBUF_BASE,
+ .end = CFG_SYS_FSL_PEBUF_BASE +
+ CFG_SYS_FSL_PEBUF_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_CCSR_BASE,
+ .end = CFG_SYS_FSL_CCSR_BASE + CFG_SYS_FSL_CCSR_SIZE - 1
+ }
+ };
+
+ mc_mem_ranges[0].start = gd->arch.resv_ram;
+ mc_mem_ranges[0].end = mc_mem_ranges[0].start +
+ mc_get_dram_block_size() - 1;
+
+ for (i = 0; i < ARRAY_SIZE(mc_mem_ranges); i++) {
+ noff = fdt_node_offset_by_compatible(blob, -1, "fsl,qoriq-mc");
+ if (noff < 0) {
+ printf("WARN: failed to get MC node: %d\n", noff);
+ return;
+ }
+ mc_ph = fdt_get_phandle(blob, noff);
+ if (!mc_ph) {
+ mc_ph = fdt_create_phandle(blob, noff);
+ if (!mc_ph) {
+ printf("WARN: failed to get MC node phandle\n");
+ return;
+ }
+ }
+
+ sprintf(mem_name, "mc-mem%d", i);
+ ret = fdtdec_add_reserved_memory(blob, mem_name,
+_mem_ranges[i], NULL, 0,
+, 0);
+ if (ret < 0) {
+ printf("ERROR: failed to reserve MC memory: %d\n", ret);
+ return;
+ }
+
+ noff = fdt_node_offset_by_phandle(blob, phandle);
+ if (noff < 0) {
+ printf("ERROR: failed get resvmem node offset: %d\n",
+ noff);
+ return;
+ }
+ ret = fdt_setprop_u32(blob, noff, "iommu-addresses", mc_ph);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'iommu-addresses': %d\n",
+ ret);
+ return;
+ }
+ ret = fdt_appendprop_u64(blob, noff, "iommu-addresses",
+mc_mem_ranges[i].start);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'iommu-addresses': %d\n",
+
[PATCH v2 1/4] armv8: fsl-layerscape: make some functions static
Some functions are not used outside this file, so make them static.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index ad20d71717b3..c22e73253c3c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -23,8 +23,8 @@ static void set_icid(struct icid_id_table *tbl, int size)
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
-#ifdef CONFIG_SYS_DPAA_FMAN
-void set_fman_icids(struct fman_icid_id_table *tbl, int size)
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+static void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
@@ -71,7 +71,7 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32
*ids, int num_ids)
return 0;
}
-int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
+static int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
struct icid_id_table *tbl, int size)
{
int i, err, off;
@@ -98,7 +98,7 @@ int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
}
#ifdef CONFIG_SYS_DPAA_FMAN
-int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+static int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
const int size)
{
int i;
@@ -111,7 +111,7 @@ int get_fman_port_icid(int port_id, struct
fman_icid_id_table *tbl,
return -1;
}
-void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
+static void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
const char *compat)
{
int noff, len, icid;
@@ -140,7 +140,7 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int
smmu_ph,
}
}
-void fdt_fixup_fman_icids(void *blob, int smmu_ph)
+static void fdt_fixup_fman_icids(void *blob, int smmu_ph)
{
static const char * const compats[] = {
"fsl,fman-v3-port-oh",
--
2.17.1
[PATCH v2 0/4] armv8: fsl-layerscape: add support for MC reserved memory
Add support for declaring in device tree the reserved memory ranges required for MC. Since the MC firmware acts as any DMA master present in the SoC, the reserved memory ranges need also be identity mapped in the SMMU, so create the required 'iommu-addresses' property in the reserved memory nodes. Changes in v2: - added a cover letter - dropped patch creating useless bypass mapping in SMMU Laurentiu Tudor (4): armv8: fsl-layerscape: make some functions static drivers: net: fsl-mc: add support for MC reserved memory board: freescale: ls2080a: declare MC reserved regions board: freescale: ls1088a: declare MC reserved regions arch/arm/cpu/armv8/fsl-layerscape/icid.c | 12 +-- board/freescale/ls1088a/ls1088a.c| 1 + board/freescale/ls2080aqds/ls2080aqds.c | 1 + board/freescale/ls2080ardb/ls2080ardb.c | 1 + board/freescale/lx2160a/lx2160a.c| 1 + drivers/net/fsl-mc/mc.c | 110 +++ include/fsl-mc/fsl_mc.h | 1 + 7 files changed, 121 insertions(+), 6 deletions(-) -- 2.17.1
Re: [PATCH 3/5] armv8: fsl-layerscape: create bypass smmu mapping for MC
On 9/6/2023 11:09 PM, Robin Murphy wrote:
> On 2023-09-06 19:10, Laurentiu Tudor wrote:
>>
>>
>> On 9/6/2023 8:21 PM, Robin Murphy wrote:
>>> On 2023-09-06 17:01, Laurentiu Tudor wrote:
>>>> MC being a plain DMA master as any other device in the SoC and
>>>> being live at OS boot time, as soon as the SMMU is probed it
>>>> will immediately start triggering faults because there is no
>>>> mapping in the SMMU for the MC. Pre-create such a mapping in
>>>> the SMMU, being the OS's responsibility to preserve it.
>>>
>>> Does U-Boot enable the SMMU? AFAICS the only thing it knows how to do
>>> is explicitly turn it *off*, therefore programming other registers
>>> appears to be a complete waste of time.
>>
>> No, it doesn't enable SMMU but it does mark a SMR as valid for MC FW.
>> And the ARM SMMU driver subtly preserves it, see [1] (it's late and I
>> might be wrong, but I'll double check tomorrow). :-)
>
> No, that sets the SMR valid bit *if* the corresponding entry is
> allocated and marked as valid in the software state in smmu->smrs, which
> at probe time it isn't, because that's only just been allocated and is
> still zero-initialised. Unless, that is,
> arm_smmu_rmr_install_bypass_smr() found a reserved region and
> preallocated an entry to honour it. But even those entries are still
> constructed from scratch; we can't do anything with the existing
> SMR/S2CR register contents in general since they may be uninitialised
> random reset values, so we don't even look.
>
> Pay no attention to the qcom_smmu_cfg_probe() hack either - that only
> exists on the promise that the relevant platforms couldn't have their
> firmware updated to use proper RMRs.
>
> You're already doing the right thing in patch #2, so there's no need to
> waste code on doing a pointless wrong thing as well.
>
Spent quite a while (sorry!) trying to remember why this was needed but
don't have a clear answer. I suspect that the hack was used with early
iort rmr implementations.
Anyway, I retested without it both DT and ACPI and looks good. Will drop
the patch and resubmit the series.
---
Thanks & Best Regards, Laurentiu
>
>>> All that should matter to the OS, and that it is responsible for
>>> upholding, is the reserved memory regions from patch #2. For
>>> instance, if the OS is Linux, literally the first thing
>>> arm_smmu_device_reset() does is rewrite all the S2CRs and SMRs
>>> without so much as looking.
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/iommu/arm/arm-smmu/arm-smmu.c#n894
>>
>>
>> ---
>> Best Regards, Laurentiu
>>
>>>
>>>> Signed-off-by: Laurentiu Tudor
>>>> ---
>>>> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26
>>>> ---
>>>> .../asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++
>>>> 2 files changed, 32 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>>> index 3bfdc3f77431..870b99838ab5 100644
>>>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>>> @@ -376,6 +376,18 @@ void bypass_smmu(void)
>>>> val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) &
>>>> ~(SCR0_USFCFG_MASK);
>>>> out_le32(SMMU_NSCR0, val);
>>>> }
>>>> +
>>>> +void setup_smmu_mc_bypass(int icid, int mask)
>>>> +{
>>>> +u32 val;
>>>> +
>>>> +val = SMMU_SMR_VALID_MASK | (icid << SMMU_SMR_ID_SHIFT) |
>>>> +(mask << SMMU_SMR_MASK_SHIFT);
>>>> +out_le32(SMMU_REG_SMR(0), val);
>>>> +val = SMMU_S2CR_EXIDVALID_VALID_MASK | SMMU_S2CR_TYPE_BYPASS_MASK;
>>>> +out_le32(SMMU_REG_S2CR(0), val);
>>>> +}
>>>> +
>>>> void fsl_lsch3_early_init_f(void)
>>>> {
>>>> erratum_rcw_src();
>>>> @@ -402,10 +414,18 @@ void fsl_lsch3_early_init_f(void)
>>>> bypass_smmu();
>>>> #endif
>>>> -#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
>>>> -defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
>>>> -defined(CONFIG_ARCH_LX2162A)
>>>> +#ifdef CONFIG_ARCH_LS1028A
>>>> +set_icids();
>>>> +#endif
>>>> +
>>>> +#if de
Re: [PATCH 3/5] armv8: fsl-layerscape: create bypass smmu mapping for MC
On 9/6/2023 8:21 PM, Robin Murphy wrote:
On 2023-09-06 17:01, Laurentiu Tudor wrote:
MC being a plain DMA master as any other device in the SoC and
being live at OS boot time, as soon as the SMMU is probed it
will immediately start triggering faults because there is no
mapping in the SMMU for the MC. Pre-create such a mapping in
the SMMU, being the OS's responsibility to preserve it.
Does U-Boot enable the SMMU? AFAICS the only thing it knows how to do is
explicitly turn it *off*, therefore programming other registers appears
to be a complete waste of time.
No, it doesn't enable SMMU but it does mark a SMR as valid for MC FW.
And the ARM SMMU driver subtly preserves it, see [1] (it's late and I
might be wrong, but I'll double check tomorrow). :-)
All that should matter to the OS, and that it is responsible for
upholding, is the reserved memory regions from patch #2. For instance,
if the OS is Linux, literally the first thing arm_smmu_device_reset()
does is rewrite all the S2CRs and SMRs without so much as looking.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/iommu/arm/arm-smmu/arm-smmu.c#n894
---
Best Regards, Laurentiu
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26 ---
.../asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3bfdc3f77431..870b99838ab5 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -376,6 +376,18 @@ void bypass_smmu(void)
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) &
~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
}
+
+void setup_smmu_mc_bypass(int icid, int mask)
+{
+ u32 val;
+
+ val = SMMU_SMR_VALID_MASK | (icid << SMMU_SMR_ID_SHIFT) |
+ (mask << SMMU_SMR_MASK_SHIFT);
+ out_le32(SMMU_REG_SMR(0), val);
+ val = SMMU_S2CR_EXIDVALID_VALID_MASK | SMMU_S2CR_TYPE_BYPASS_MASK;
+ out_le32(SMMU_REG_S2CR(0), val);
+}
+
void fsl_lsch3_early_init_f(void)
{
erratum_rcw_src();
@@ -402,10 +414,18 @@ void fsl_lsch3_early_init_f(void)
bypass_smmu();
#endif
-#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
- defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
- defined(CONFIG_ARCH_LX2162A)
+#ifdef CONFIG_ARCH_LS1028A
+ set_icids();
+#endif
+
+#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS2080A)
+ set_icids();
+ setup_smmu_mc_bypass(0x300, 0);
+#endif
+
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
set_icids();
+ setup_smmu_mc_bypass(0x4000, 0);
#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index ca5e33379ba9..bec5355adaed 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -190,6 +190,15 @@
#define SCR0_CLIENTPD_MASK 0x0001
#define SCR0_USFCFG_MASK 0x0400
+#define SMMU_REG_SMR(n) (SMMU_BASE + 0x800 + ((n) << 2))
+#define SMMU_REG_S2CR(n) (SMMU_BASE + 0xc00 + ((n) << 2))
+#define SMMU_SMR_VALID_MASK 0x8000
+#define SMMU_SMR_MASK_MASK 0x
+#define SMMU_SMR_MASK_SHIFT 16
+#define SMMU_SMR_ID_MASK 0x
+#define SMMU_SMR_ID_SHIFT 0
+#define SMMU_S2CR_EXIDVALID_VALID_MASK 0x0400
+#define SMMU_S2CR_TYPE_BYPASS_MASK 0x0001
/* PCIe */
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
[PATCH 5/5] board: freescale: ls1088a: declare MC reserved regions
Populate the device tree with the MC reserved memory regions. Signed-off-by: Laurentiu Tudor --- board/freescale/ls1088a/ls1088a.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 65593f10a3f5..7674e31a268a 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -983,6 +983,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); #endif fdt_fixup_icid(blob); -- 2.17.1
[PATCH 4/5] board: freescale: ls2080a: declare MC reserved regions
Populate the device tree with the MC reserved memory regions. Signed-off-by: Laurentiu Tudor --- board/freescale/ls2080aqds/ls2080aqds.c | 1 + board/freescale/ls2080ardb/ls2080ardb.c | 1 + 2 files changed, 2 insertions(+) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index ba25e9b0b8fc..5c94c83121b5 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -325,6 +325,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); #endif fdt_fixup_icid(blob); diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 8d340f17a256..5c30de83d841 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -522,6 +522,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); #endif fdt_fixup_icid(blob); -- 2.17.1
[PATCH 3/5] armv8: fsl-layerscape: create bypass smmu mapping for MC
MC being a plain DMA master as any other device in the SoC and
being live at OS boot time, as soon as the SMMU is probed it
will immediately start triggering faults because there is no
mapping in the SMMU for the MC. Pre-create such a mapping in
the SMMU, being the OS's responsibility to preserve it.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26 ---
.../asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3bfdc3f77431..870b99838ab5 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -376,6 +376,18 @@ void bypass_smmu(void)
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
}
+
+void setup_smmu_mc_bypass(int icid, int mask)
+{
+ u32 val;
+
+ val = SMMU_SMR_VALID_MASK | (icid << SMMU_SMR_ID_SHIFT) |
+ (mask << SMMU_SMR_MASK_SHIFT);
+ out_le32(SMMU_REG_SMR(0), val);
+ val = SMMU_S2CR_EXIDVALID_VALID_MASK | SMMU_S2CR_TYPE_BYPASS_MASK;
+ out_le32(SMMU_REG_S2CR(0), val);
+}
+
void fsl_lsch3_early_init_f(void)
{
erratum_rcw_src();
@@ -402,10 +414,18 @@ void fsl_lsch3_early_init_f(void)
bypass_smmu();
#endif
-#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
- defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
- defined(CONFIG_ARCH_LX2162A)
+#ifdef CONFIG_ARCH_LS1028A
+ set_icids();
+#endif
+
+#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS2080A)
+ set_icids();
+ setup_smmu_mc_bypass(0x300, 0);
+#endif
+
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
set_icids();
+ setup_smmu_mc_bypass(0x4000, 0);
#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index ca5e33379ba9..bec5355adaed 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -190,6 +190,15 @@
#define SCR0_CLIENTPD_MASK 0x0001
#define SCR0_USFCFG_MASK 0x0400
+#define SMMU_REG_SMR(n)(SMMU_BASE + 0x800 + ((n) << 2))
+#define SMMU_REG_S2CR(n) (SMMU_BASE + 0xc00 + ((n) << 2))
+#define SMMU_SMR_VALID_MASK0x8000
+#define SMMU_SMR_MASK_MASK 0x
+#define SMMU_SMR_MASK_SHIFT16
+#define SMMU_SMR_ID_MASK 0x
+#define SMMU_SMR_ID_SHIFT 0
+#define SMMU_S2CR_EXIDVALID_VALID_MASK 0x0400
+#define SMMU_S2CR_TYPE_BYPASS_MASK 0x0001
/* PCIe */
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
--
2.17.1
[PATCH 2/5] drivers: net: fsl-mc: add support for MC reserved memory
Add support for declaring in device tree the reserved memory ranges
required for MC. Since the MC firmware acts as any DMA master present
in the SoC, the reserved memory ranges need also be identity mapped
in the SMMU, so create the required 'iommu-addresses' property in
the reserved memory nodes.
For now this support is used only on LX2160A SoCs.
Signed-off-by: Laurentiu Tudor
---
board/freescale/lx2160a/lx2160a.c | 1 +
drivers/net/fsl-mc/mc.c | 110 ++
include/fsl-mc/fsl_mc.h | 1 +
3 files changed, 112 insertions(+)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index d631a11ff667..688d81f04f64 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -834,6 +834,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_FSL_MC_ENET
fdt_fsl_mc_fixup_iommu_map_entry(blob);
fdt_fixup_board_enet(blob);
+ fdt_reserve_mc_mem(blob, 0x4000);
#endif
fdt_fixup_icid(blob);
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 984616fb65c0..f5c5057bec10 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -30,6 +30,8 @@
#include
#include
#include
+#include
+#include
#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK(~(MC_RAM_BASE_ADDR_ALIGNMENT -
1))
@@ -929,6 +931,114 @@ unsigned long mc_get_dram_block_size(void)
return dram_block_size;
}
+/**
+ * Populate the device tree with MC reserved memory ranges.
+ */
+void fdt_reserve_mc_mem(void *blob, u32 mc_icid)
+{
+ u32 phandle, mc_ph;
+ int noff, ret, i;
+ char mem_name[16];
+ struct fdt_memory mc_mem_ranges[] = {
+ {
+ .start = 0,
+ .end = 0
+ },
+ {
+ .start = CFG_SYS_FSL_MC_BASE,
+ .end = CFG_SYS_FSL_MC_BASE + CFG_SYS_FSL_MC_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_NI_BASE,
+ .end = CFG_SYS_FSL_NI_BASE + CFG_SYS_FSL_NI_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_QBMAN_BASE,
+ .end = CFG_SYS_FSL_QBMAN_BASE +
+ CFG_SYS_FSL_QBMAN_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_PEBUF_BASE,
+ .end = CFG_SYS_FSL_PEBUF_BASE +
+ CFG_SYS_FSL_PEBUF_SIZE - 1
+ },
+ {
+ .start = CFG_SYS_FSL_CCSR_BASE,
+ .end = CFG_SYS_FSL_CCSR_BASE + CFG_SYS_FSL_CCSR_SIZE - 1
+ }
+ };
+
+ mc_mem_ranges[0].start = gd->arch.resv_ram;
+ mc_mem_ranges[0].end = mc_mem_ranges[0].start +
+ mc_get_dram_block_size() - 1;
+
+ for (i = 0; i < ARRAY_SIZE(mc_mem_ranges); i++) {
+ noff = fdt_node_offset_by_compatible(blob, -1, "fsl,qoriq-mc");
+ if (noff < 0) {
+ printf("WARN: failed to get MC node: %d\n", noff);
+ return;
+ }
+ mc_ph = fdt_get_phandle(blob, noff);
+ if (!mc_ph) {
+ mc_ph = fdt_create_phandle(blob, noff);
+ if (!mc_ph) {
+ printf("WARN: failed to get MC node phandle\n");
+ return;
+ }
+ }
+
+ sprintf(mem_name, "mc-mem%d", i);
+ ret = fdtdec_add_reserved_memory(blob, mem_name,
+_mem_ranges[i], NULL, 0,
+, 0);
+ if (ret < 0) {
+ printf("ERROR: failed to reserve MC memory: %d\n", ret);
+ return;
+ }
+
+ noff = fdt_node_offset_by_phandle(blob, phandle);
+ if (noff < 0) {
+ printf("ERROR: failed get resvmem node offset: %d\n",
+ noff);
+ return;
+ }
+ ret = fdt_setprop_u32(blob, noff, "iommu-addresses", mc_ph);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'iommu-addresses': %d\n",
+ ret);
+ return;
+ }
+ ret = fdt_appendprop_u64(blob, noff, "iommu-addresses",
+mc_mem_ranges[i].start);
+ if (ret < 0) {
+ printf("ERROR: failed to set 'iommu-addresses': %d\n",
+
[PATCH 1/5] armv8: fsl-layerscape: make some functions static
Some functions are not used outside this file, so make them static.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index ad20d71717b3..c22e73253c3c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -23,8 +23,8 @@ static void set_icid(struct icid_id_table *tbl, int size)
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
-#ifdef CONFIG_SYS_DPAA_FMAN
-void set_fman_icids(struct fman_icid_id_table *tbl, int size)
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+static void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
@@ -71,7 +71,7 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32
*ids, int num_ids)
return 0;
}
-int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
+static int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
struct icid_id_table *tbl, int size)
{
int i, err, off;
@@ -98,7 +98,7 @@ int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
}
#ifdef CONFIG_SYS_DPAA_FMAN
-int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+static int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
const int size)
{
int i;
@@ -111,7 +111,7 @@ int get_fman_port_icid(int port_id, struct
fman_icid_id_table *tbl,
return -1;
}
-void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
+static void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
const char *compat)
{
int noff, len, icid;
@@ -140,7 +140,7 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int
smmu_ph,
}
}
-void fdt_fixup_fman_icids(void *blob, int smmu_ph)
+static void fdt_fixup_fman_icids(void *blob, int smmu_ph)
{
static const char * const compats[] = {
"fsl,fman-v3-port-oh",
--
2.17.1
Re: [PATCH v3 0/3] fsl-layerscape: drop support for obsolete PPA secure firmware
Hi Tom, On 8/23/2023 5:43 PM, Tom Rini wrote: On Wed, Aug 23, 2023 at 04:25:43PM +0300, laurentiu.tu...@nxp.com wrote: From: Laurentiu Tudor Support for this in-house secure firmware was discontinued long time ago so remove it. First couple of patches delete the defconfigs that use it (split in two to be <100KB) and the third one removes the actual PPA support. Changes in v3: - fixed some merge conflicts Changes in v2: - split the defconfig removal patch in two because it was too big and was filtered out by the ML Note that you don't need to split large patches, they just need to be approved before they're sent out to the list, which typically happens during normal US business hours (when I'm awake). That was my bad. I noticed way too late after I've made the split that the big patch was in fact approved. --- Best Regards, Laurentiu
[PATCH v3 2/3] configs: layerscape: delete defconfigs using legacy PPA secure FW (part2)
From: Laurentiu Tudor PPA was a secure firmware developed in-house which is no longer supported and replaced by TF-A quite some years ago. This makes the defconfigs that make use of PPA obsolete, so remove them. Signed-off-by: Laurentiu Tudor --- configs/ls1046aqds_SECURE_BOOT_defconfig | 108 -- configs/ls1046aqds_defconfig | 110 -- configs/ls1046aqds_lpuart_defconfig | 112 -- configs/ls1046aqds_nand_defconfig | 139 -- configs/ls1046aqds_qspi_defconfig | 101 - configs/ls1046aqds_sdcard_ifc_defconfig | 139 -- configs/ls1046aqds_sdcard_qspi_defconfig | 128 configs/ls1046ardb_emmc_defconfig | 122 --- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 99 - configs/ls1046ardb_qspi_defconfig | 102 - configs/ls1046ardb_qspi_spl_defconfig | 130 .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 123 configs/ls1046ardb_sdcard_defconfig | 122 --- configs/ls1088aqds_defconfig | 112 -- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 107 -- configs/ls1088aqds_qspi_defconfig | 108 -- configs/ls1088aqds_sdcard_ifc_defconfig | 130 configs/ls1088aqds_sdcard_qspi_defconfig | 128 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 104 - configs/ls1088ardb_qspi_defconfig | 105 - ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 124 configs/ls1088ardb_sdcard_qspi_defconfig | 124 configs/ls2081ardb_defconfig | 96 configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 96 configs/ls2088ardb_qspi_defconfig | 101 - 25 files changed, 2870 deletions(-) delete mode 100644 configs/ls1046aqds_SECURE_BOOT_defconfig delete mode 100644 configs/ls1046aqds_defconfig delete mode 100644 configs/ls1046aqds_lpuart_defconfig delete mode 100644 configs/ls1046aqds_nand_defconfig delete mode 100644 configs/ls1046aqds_qspi_defconfig delete mode 100644 configs/ls1046aqds_sdcard_ifc_defconfig delete mode 100644 configs/ls1046aqds_sdcard_qspi_defconfig delete mode 100644 configs/ls1046ardb_emmc_defconfig delete mode 100644 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1046ardb_qspi_defconfig delete mode 100644 configs/ls1046ardb_qspi_spl_defconfig delete mode 100644 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig delete mode 100644 configs/ls1046ardb_sdcard_defconfig delete mode 100644 configs/ls1088aqds_defconfig delete mode 100644 configs/ls1088aqds_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1088aqds_qspi_defconfig delete mode 100644 configs/ls1088aqds_sdcard_ifc_defconfig delete mode 100644 configs/ls1088aqds_sdcard_qspi_defconfig delete mode 100644 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1088ardb_qspi_defconfig delete mode 100644 configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1088ardb_sdcard_qspi_defconfig delete mode 100644 configs/ls2081ardb_defconfig delete mode 100644 configs/ls2088ardb_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls2088ardb_qspi_defconfig diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig deleted file mode 100644 index 5bdcc868ba20.. --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ /dev/null @@ -1,108 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=2500 -CONFIG_TARGET_LS1046AQDS=y -CONFIG_TEXT_BASE=0x6010 -CONFIG_SYS_MALLOC_LEN=0x12 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_ENV_SIZE=0x2 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" -CONFIG_FSL_LS_PPA=y -CONFIG_PCI=y -CONFIG_AHCI=y -CONFIG_NXP_ESBC=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_MEMTEST_START=0x8000 -CONFIG_SYS_MEMTEST_END=0x9fff -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=6000.nor:2m@0x10(nor_bank0_uboot),40m@0x110(nor_bank0_fit),7m(nor_bank0_user),2m@0x410(nor_b
[PATCH v3 1/3] configs: layerscape: delete defconfigs using legacy PPA secure FW (part1)
From: Laurentiu Tudor PPA was a secure firmware developed in-house which is no longer supported and replaced by TF-A quite some years ago. This makes the defconfigs that make use of PPA obsolete, so remove them. Signed-off-by: Laurentiu Tudor --- configs/ls1012a2g5rdb_qspi_defconfig | 69 - configs/ls1012afrdm_qspi_defconfig| 67 - .../ls1012afrwy_qspi_SECURE_BOOT_defconfig| 72 - configs/ls1012afrwy_qspi_defconfig| 72 - configs/ls1012aqds_qspi_defconfig | 95 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 77 -- configs/ls1012ardb_qspi_defconfig | 77 -- configs/ls1043aqds_defconfig | 107 -- configs/ls1043aqds_lpuart_defconfig | 109 -- configs/ls1043aqds_nand_defconfig | 138 -- configs/ls1043aqds_nor_ddr3_defconfig | 108 -- configs/ls1043aqds_qspi_defconfig | 98 - configs/ls1043aqds_sdcard_ifc_defconfig | 135 - configs/ls1043aqds_sdcard_qspi_defconfig | 124 configs/ls1043ardb_SECURE_BOOT_defconfig | 99 - configs/ls1043ardb_defconfig | 100 - configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_nand_defconfig | 128 .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_sdcard_defconfig | 126 configs/ls2080aqds_SECURE_BOOT_defconfig | 108 -- configs/ls2080aqds_defconfig | 109 -- configs/ls2080aqds_sdcard_defconfig | 116 --- configs/ls2080ardb_SECURE_BOOT_defconfig | 106 -- configs/ls2080ardb_defconfig | 107 -- 25 files changed, 2595 deletions(-) delete mode 100644 configs/ls1012a2g5rdb_qspi_defconfig delete mode 100644 configs/ls1012afrdm_qspi_defconfig delete mode 100644 configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1012afrwy_qspi_defconfig delete mode 100644 configs/ls1012aqds_qspi_defconfig delete mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1012ardb_qspi_defconfig delete mode 100644 configs/ls1043aqds_defconfig delete mode 100644 configs/ls1043aqds_lpuart_defconfig delete mode 100644 configs/ls1043aqds_nand_defconfig delete mode 100644 configs/ls1043aqds_nor_ddr3_defconfig delete mode 100644 configs/ls1043aqds_qspi_defconfig delete mode 100644 configs/ls1043aqds_sdcard_ifc_defconfig delete mode 100644 configs/ls1043aqds_sdcard_qspi_defconfig delete mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_defconfig delete mode 100644 configs/ls1043ardb_nand_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_nand_defconfig delete mode 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_sdcard_defconfig delete mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig delete mode 100644 configs/ls2080aqds_defconfig delete mode 100644 configs/ls2080aqds_sdcard_defconfig delete mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig delete mode 100644 configs/ls2080ardb_defconfig diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig deleted file mode 100644 index 72b590a73b4c.. --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=2500 -CONFIG_TARGET_LS1012A2G5RDB=y -CONFIG_TEXT_BASE=0x4010 -CONFIG_SYS_MALLOC_LEN=0x50 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x30 -CONFIG_ENV_SECT_SIZE=0x4 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_SYS_MEMTEST_START=0x8000 -CONFIG_SYS_MEMTEST_END=0x9fff -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_QSPI_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=25" -CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_GREPENV=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVE
[PATCH v3 3/3] fsl-layerscape: drop obsolete PPA secure firmware support
From: Laurentiu Tudor PPA was a secure firmware developed in-house which is no longer supported and replaced by TF-A quite some years ago. Drop support for it. Signed-off-by: Laurentiu Tudor --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 60 arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 - arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 284 -- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 34 --- .../arm/include/asm/arch-fsl-layerscape/ppa.h | 12 - arch/arm/include/asm/fsl_secure_boot.h| 9 - board/freescale/ls1012afrdm/Kconfig | 11 - board/freescale/ls1012afrdm/ls1012afrdm.c | 6 - board/freescale/ls1012aqds/Kconfig| 8 - board/freescale/ls1012aqds/ls1012aqds.c | 6 - board/freescale/ls1012ardb/Kconfig| 12 - board/freescale/ls1012ardb/ls1012ardb.c | 6 - board/freescale/ls1028a/Kconfig | 12 - board/freescale/ls1028a/ls1028a.c | 7 - board/freescale/ls1043aqds/Kconfig| 16 - board/freescale/ls1043aqds/ls1043aqds.c | 5 - board/freescale/ls1043ardb/Kconfig| 14 - board/freescale/ls1043ardb/ls1043ardb.c | 5 - board/freescale/ls1046aqds/Kconfig| 16 - board/freescale/ls1046aqds/ls1046aqds.c | 5 - board/freescale/ls1046ardb/Kconfig| 14 - board/freescale/ls1046ardb/ls1046ardb.c | 5 - board/freescale/ls1088a/Kconfig | 28 -- board/freescale/ls1088a/ls1088a.c | 5 - board/freescale/ls2080aqds/Kconfig| 16 - board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/Kconfig| 16 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - board/traverse/ten64/ten64.c | 1 - env/Kconfig | 2 +- include/configs/ls1046a_common.h | 3 +- 31 files changed, 2 insertions(+), 627 deletions(-) delete mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa.c delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ppa.h diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a8b493e2f875..c45e4e63b4bb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -390,66 +390,6 @@ config HAS_FEATURE_ENHANCED_MSI bool default y if ARCH_LS1043A -menu "Layerscape PPA" -config FSL_LS_PPA - bool "FSL Layerscape PPA firmware support" - depends on !ARMV8_PSCI - select ARMV8_SEC_FIRMWARE_SUPPORT - select SEC_FIRMWARE_ARMV8_PSCI - select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 - help - The FSL Primary Protected Application (PPA) is a software component - which is loaded during boot stage, and then remains resident in RAM - and runs in the TrustZone after boot. - Say y to enable it. - -config SPL_FSL_LS_PPA - bool "FSL Layerscape PPA firmware support for SPL build" - depends on !ARMV8_PSCI - select SPL_ARMV8_SEC_FIRMWARE_SUPPORT - select SEC_FIRMWARE_ARMV8_PSCI - select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 - help - The FSL Primary Protected Application (PPA) is a software component - which is loaded during boot stage, and then remains resident in RAM - and runs in the TrustZone after boot. This is to load PPA during SPL - stage instead of the RAM version of U-Boot. Once PPA is initialized, - the rest of U-Boot (including RAM version) runs at EL2. -choice - prompt "FSL Layerscape PPA firmware loading-media select" - depends on FSL_LS_PPA - default SYS_LS_PPA_FW_IN_MMC if SD_BOOT - default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT - default SYS_LS_PPA_FW_IN_XIP - -config SYS_LS_PPA_FW_IN_XIP - bool "XIP" - help - Say Y here if the PPA firmware locate at XIP flash, such - as NOR or QSPI flash. - -config SYS_LS_PPA_FW_IN_MMC - bool "eMMC or SD Card" - help - Say Y here if the PPA firmware locate at eMMC/SD card. - -config SYS_LS_PPA_FW_IN_NAND - bool "NAND" - help - Say Y here if the PPA firmware locate at NAND flash. - -endchoice - -config LS_PPA_ESBC_HDR_SIZE - hex "Length of PPA ESBC header" - depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP - default 0x2000 - help - Length (in bytes) of PPA ESBC header to be copied from MMC/SD or - NAND to memory to validate PPA image. - -endmenu - config SYS_FSL_ERRATUM_A008997 bool "Workaround for USB PHY erratum A008997" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 598c36ee660a..eefdf12369c3 100644 --- a/arch/arm/cpu/armv8/fsl-layer
[PATCH v3 0/3] fsl-layerscape: drop support for obsolete PPA secure firmware
From: Laurentiu Tudor Support for this in-house secure firmware was discontinued long time ago so remove it. First couple of patches delete the defconfigs that use it (split in two to be <100KB) and the third one removes the actual PPA support. Changes in v3: - fixed some merge conflicts Changes in v2: - split the defconfig removal patch in two because it was too big and was filtered out by the ML Laurentiu Tudor (3): configs: layerscape: delete defconfigs using legacy PPA secure FW (part1) configs: layerscape: delete defconfigs using legacy PPA secure FW (part2) fsl-layerscape: drop obsolete PPA secure firmware support arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 60 arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 - arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 284 -- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 34 --- .../arm/include/asm/arch-fsl-layerscape/ppa.h | 12 - arch/arm/include/asm/fsl_secure_boot.h| 9 - board/freescale/ls1012afrdm/Kconfig | 11 - board/freescale/ls1012afrdm/ls1012afrdm.c | 6 - board/freescale/ls1012aqds/Kconfig| 8 - board/freescale/ls1012aqds/ls1012aqds.c | 6 - board/freescale/ls1012ardb/Kconfig| 12 - board/freescale/ls1012ardb/ls1012ardb.c | 6 - board/freescale/ls1028a/Kconfig | 12 - board/freescale/ls1028a/ls1028a.c | 7 - board/freescale/ls1043aqds/Kconfig| 16 - board/freescale/ls1043aqds/ls1043aqds.c | 5 - board/freescale/ls1043ardb/Kconfig| 14 - board/freescale/ls1043ardb/ls1043ardb.c | 5 - board/freescale/ls1046aqds/Kconfig| 16 - board/freescale/ls1046aqds/ls1046aqds.c | 5 - board/freescale/ls1046ardb/Kconfig| 14 - board/freescale/ls1046ardb/ls1046ardb.c | 5 - board/freescale/ls1088a/Kconfig | 28 -- board/freescale/ls1088a/ls1088a.c | 5 - board/freescale/ls2080aqds/Kconfig| 16 - board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/Kconfig| 16 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - board/traverse/ten64/ten64.c | 1 - configs/ls1012a2g5rdb_qspi_defconfig | 69 - configs/ls1012afrdm_qspi_defconfig| 67 - .../ls1012afrwy_qspi_SECURE_BOOT_defconfig| 72 - configs/ls1012afrwy_qspi_defconfig| 72 - configs/ls1012aqds_qspi_defconfig | 95 -- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 77 - configs/ls1012ardb_qspi_defconfig | 77 - configs/ls1043aqds_defconfig | 107 --- configs/ls1043aqds_lpuart_defconfig | 109 --- configs/ls1043aqds_nand_defconfig | 138 - configs/ls1043aqds_nor_ddr3_defconfig | 108 --- configs/ls1043aqds_qspi_defconfig | 98 -- configs/ls1043aqds_sdcard_ifc_defconfig | 135 - configs/ls1043aqds_sdcard_qspi_defconfig | 124 configs/ls1043ardb_SECURE_BOOT_defconfig | 99 -- configs/ls1043ardb_defconfig | 100 -- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_nand_defconfig | 128 .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_sdcard_defconfig | 126 configs/ls1046aqds_SECURE_BOOT_defconfig | 108 --- configs/ls1046aqds_defconfig | 110 --- configs/ls1046aqds_lpuart_defconfig | 112 --- configs/ls1046aqds_nand_defconfig | 139 - configs/ls1046aqds_qspi_defconfig | 101 --- configs/ls1046aqds_sdcard_ifc_defconfig | 139 - configs/ls1046aqds_sdcard_qspi_defconfig | 128 configs/ls1046ardb_emmc_defconfig | 122 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 99 -- configs/ls1046ardb_qspi_defconfig | 102 --- configs/ls1046ardb_qspi_spl_defconfig | 130 .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 123 configs/ls1046ardb_sdcard_defconfig | 122 configs/ls1088aqds_defconfig | 112 --- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 107 --- configs/ls1088aqds_qspi_defconfig | 108 --- configs/ls1088aqds_sdcard_ifc_defconfig | 130 configs/ls1088aqds_sdcard_qspi_defconfig | 128 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 104 --- configs/ls1088ardb_qspi_defconfig | 105 --- ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 124 configs/ls1088ardb_sdcard_qspi_defconfig | 124 configs/ls2080aqds_SECURE_BOOT_defconfig | 108 --- configs/ls2080aqds_defconfig | 109 --- configs/ls2080aqds_sdcard_defcon
[PATCH v2 2/3] configs: layerscape: delete defconfigs using legacy PPA secure FW (part2)
From: Laurentiu Tudor PPA was a secure firmware developed in-house which is no longer supported and replaced by TF-A quite some years ago. This makes the defconfigs that make use of PPA obsolete, so remove them. Signed-off-by: Laurentiu Tudor --- configs/ls1046aqds_SECURE_BOOT_defconfig | 108 -- configs/ls1046aqds_defconfig | 110 -- configs/ls1046aqds_lpuart_defconfig | 112 -- configs/ls1046aqds_nand_defconfig | 139 -- configs/ls1046aqds_qspi_defconfig | 101 - configs/ls1046aqds_sdcard_ifc_defconfig | 139 -- configs/ls1046aqds_sdcard_qspi_defconfig | 128 configs/ls1046ardb_emmc_defconfig | 122 --- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 99 - configs/ls1046ardb_qspi_defconfig | 102 - configs/ls1046ardb_qspi_spl_defconfig | 130 .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 123 configs/ls1046ardb_sdcard_defconfig | 122 --- configs/ls1088aqds_defconfig | 112 -- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 107 -- configs/ls1088aqds_qspi_defconfig | 108 -- configs/ls1088aqds_sdcard_ifc_defconfig | 130 configs/ls1088aqds_sdcard_qspi_defconfig | 128 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 104 - configs/ls1088ardb_qspi_defconfig | 105 - ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 124 configs/ls1088ardb_sdcard_qspi_defconfig | 124 configs/ls2081ardb_defconfig | 96 configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 96 configs/ls2088ardb_qspi_defconfig | 101 - 25 files changed, 2870 deletions(-) delete mode 100644 configs/ls1046aqds_SECURE_BOOT_defconfig delete mode 100644 configs/ls1046aqds_defconfig delete mode 100644 configs/ls1046aqds_lpuart_defconfig delete mode 100644 configs/ls1046aqds_nand_defconfig delete mode 100644 configs/ls1046aqds_qspi_defconfig delete mode 100644 configs/ls1046aqds_sdcard_ifc_defconfig delete mode 100644 configs/ls1046aqds_sdcard_qspi_defconfig delete mode 100644 configs/ls1046ardb_emmc_defconfig delete mode 100644 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1046ardb_qspi_defconfig delete mode 100644 configs/ls1046ardb_qspi_spl_defconfig delete mode 100644 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig delete mode 100644 configs/ls1046ardb_sdcard_defconfig delete mode 100644 configs/ls1088aqds_defconfig delete mode 100644 configs/ls1088aqds_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1088aqds_qspi_defconfig delete mode 100644 configs/ls1088aqds_sdcard_ifc_defconfig delete mode 100644 configs/ls1088aqds_sdcard_qspi_defconfig delete mode 100644 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1088ardb_qspi_defconfig delete mode 100644 configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1088ardb_sdcard_qspi_defconfig delete mode 100644 configs/ls2081ardb_defconfig delete mode 100644 configs/ls2088ardb_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls2088ardb_qspi_defconfig diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig deleted file mode 100644 index 5bdcc868ba20.. --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ /dev/null @@ -1,108 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=2500 -CONFIG_TARGET_LS1046AQDS=y -CONFIG_TEXT_BASE=0x6010 -CONFIG_SYS_MALLOC_LEN=0x12 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_ENV_SIZE=0x2 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" -CONFIG_FSL_LS_PPA=y -CONFIG_PCI=y -CONFIG_AHCI=y -CONFIG_NXP_ESBC=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_MEMTEST_START=0x8000 -CONFIG_SYS_MEMTEST_END=0x9fff -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=6000.nor:2m@0x10(nor_bank0_uboot),40m@0x110(nor_bank0_fit),7m(nor_bank0_user),2m@0x410(nor_b
[PATCH v2 1/3] configs: layerscape: delete defconfigs using legacy PPA secure FW (part1)
From: Laurentiu Tudor PPA was a secure firmware developed in-house which is no longer supported and replaced by TF-A quite some years ago. This makes the defconfigs that make use of PPA obsolete, so remove them. Signed-off-by: Laurentiu Tudor --- configs/ls1012a2g5rdb_qspi_defconfig | 69 - configs/ls1012afrdm_qspi_defconfig| 67 - .../ls1012afrwy_qspi_SECURE_BOOT_defconfig| 72 - configs/ls1012afrwy_qspi_defconfig| 72 - configs/ls1012aqds_qspi_defconfig | 95 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 77 -- configs/ls1012ardb_qspi_defconfig | 77 -- configs/ls1043aqds_defconfig | 107 -- configs/ls1043aqds_lpuart_defconfig | 109 -- configs/ls1043aqds_nand_defconfig | 138 -- configs/ls1043aqds_nor_ddr3_defconfig | 108 -- configs/ls1043aqds_qspi_defconfig | 98 - configs/ls1043aqds_sdcard_ifc_defconfig | 135 - configs/ls1043aqds_sdcard_qspi_defconfig | 124 configs/ls1043ardb_SECURE_BOOT_defconfig | 99 - configs/ls1043ardb_defconfig | 100 - configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_nand_defconfig | 128 .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_sdcard_defconfig | 126 configs/ls2080aqds_SECURE_BOOT_defconfig | 108 -- configs/ls2080aqds_defconfig | 109 -- configs/ls2080aqds_sdcard_defconfig | 116 --- configs/ls2080ardb_SECURE_BOOT_defconfig | 107 -- configs/ls2080ardb_defconfig | 108 -- 25 files changed, 2597 deletions(-) delete mode 100644 configs/ls1012a2g5rdb_qspi_defconfig delete mode 100644 configs/ls1012afrdm_qspi_defconfig delete mode 100644 configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1012afrwy_qspi_defconfig delete mode 100644 configs/ls1012aqds_qspi_defconfig delete mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig delete mode 100644 configs/ls1012ardb_qspi_defconfig delete mode 100644 configs/ls1043aqds_defconfig delete mode 100644 configs/ls1043aqds_lpuart_defconfig delete mode 100644 configs/ls1043aqds_nand_defconfig delete mode 100644 configs/ls1043aqds_nor_ddr3_defconfig delete mode 100644 configs/ls1043aqds_qspi_defconfig delete mode 100644 configs/ls1043aqds_sdcard_ifc_defconfig delete mode 100644 configs/ls1043aqds_sdcard_qspi_defconfig delete mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_defconfig delete mode 100644 configs/ls1043ardb_nand_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_nand_defconfig delete mode 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_sdcard_defconfig delete mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig delete mode 100644 configs/ls2080aqds_defconfig delete mode 100644 configs/ls2080aqds_sdcard_defconfig delete mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig delete mode 100644 configs/ls2080ardb_defconfig diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig deleted file mode 100644 index 72b590a73b4c.. --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=2500 -CONFIG_TARGET_LS1012A2G5RDB=y -CONFIG_TEXT_BASE=0x4010 -CONFIG_SYS_MALLOC_LEN=0x50 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x30 -CONFIG_ENV_SECT_SIZE=0x4 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_SYS_MEMTEST_START=0x8000 -CONFIG_SYS_MEMTEST_END=0x9fff -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_QSPI_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=25" -CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_GREPENV=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVE
[PATCH v2 3/3] fsl-layerscape: drop obsolete PPA secure firmware support
From: Laurentiu Tudor PPA was a secure firmware developed in-house which is no longer supported and replaced by TF-A quite some years ago. Drop support for it. Signed-off-by: Laurentiu Tudor --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 60 arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 - arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 284 -- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 34 --- .../arm/include/asm/arch-fsl-layerscape/ppa.h | 12 - arch/arm/include/asm/fsl_secure_boot.h| 9 - board/freescale/ls1012afrdm/Kconfig | 11 - board/freescale/ls1012afrdm/ls1012afrdm.c | 6 - board/freescale/ls1012aqds/Kconfig| 8 - board/freescale/ls1012aqds/ls1012aqds.c | 6 - board/freescale/ls1012ardb/Kconfig| 12 - board/freescale/ls1012ardb/ls1012ardb.c | 6 - board/freescale/ls1028a/Kconfig | 12 - board/freescale/ls1028a/ls1028a.c | 7 - board/freescale/ls1043aqds/Kconfig| 16 - board/freescale/ls1043aqds/ls1043aqds.c | 5 - board/freescale/ls1043ardb/Kconfig| 14 - board/freescale/ls1043ardb/ls1043ardb.c | 5 - board/freescale/ls1046aqds/Kconfig| 16 - board/freescale/ls1046aqds/ls1046aqds.c | 5 - board/freescale/ls1046ardb/Kconfig| 14 - board/freescale/ls1046ardb/ls1046ardb.c | 5 - board/freescale/ls1088a/Kconfig | 28 -- board/freescale/ls1088a/ls1088a.c | 5 - board/freescale/ls2080aqds/Kconfig| 16 - board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/Kconfig| 16 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - board/traverse/ten64/ten64.c | 1 - env/Kconfig | 2 +- include/configs/ls1046a_common.h | 3 +- 31 files changed, 2 insertions(+), 627 deletions(-) delete mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa.c delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ppa.h diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a8b493e2f875..c45e4e63b4bb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -390,66 +390,6 @@ config HAS_FEATURE_ENHANCED_MSI bool default y if ARCH_LS1043A -menu "Layerscape PPA" -config FSL_LS_PPA - bool "FSL Layerscape PPA firmware support" - depends on !ARMV8_PSCI - select ARMV8_SEC_FIRMWARE_SUPPORT - select SEC_FIRMWARE_ARMV8_PSCI - select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 - help - The FSL Primary Protected Application (PPA) is a software component - which is loaded during boot stage, and then remains resident in RAM - and runs in the TrustZone after boot. - Say y to enable it. - -config SPL_FSL_LS_PPA - bool "FSL Layerscape PPA firmware support for SPL build" - depends on !ARMV8_PSCI - select SPL_ARMV8_SEC_FIRMWARE_SUPPORT - select SEC_FIRMWARE_ARMV8_PSCI - select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 - help - The FSL Primary Protected Application (PPA) is a software component - which is loaded during boot stage, and then remains resident in RAM - and runs in the TrustZone after boot. This is to load PPA during SPL - stage instead of the RAM version of U-Boot. Once PPA is initialized, - the rest of U-Boot (including RAM version) runs at EL2. -choice - prompt "FSL Layerscape PPA firmware loading-media select" - depends on FSL_LS_PPA - default SYS_LS_PPA_FW_IN_MMC if SD_BOOT - default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT - default SYS_LS_PPA_FW_IN_XIP - -config SYS_LS_PPA_FW_IN_XIP - bool "XIP" - help - Say Y here if the PPA firmware locate at XIP flash, such - as NOR or QSPI flash. - -config SYS_LS_PPA_FW_IN_MMC - bool "eMMC or SD Card" - help - Say Y here if the PPA firmware locate at eMMC/SD card. - -config SYS_LS_PPA_FW_IN_NAND - bool "NAND" - help - Say Y here if the PPA firmware locate at NAND flash. - -endchoice - -config LS_PPA_ESBC_HDR_SIZE - hex "Length of PPA ESBC header" - depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP - default 0x2000 - help - Length (in bytes) of PPA ESBC header to be copied from MMC/SD or - NAND to memory to validate PPA image. - -endmenu - config SYS_FSL_ERRATUM_A008997 bool "Workaround for USB PHY erratum A008997" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 598c36ee660a..eefdf12369c3 100644 --- a/arch/arm/cpu/armv8/fsl-layer
[PATCH v2 0/3] fsl-layerscape: drop support for obsolete PPA secure firmware
From: Laurentiu Tudor Support for this in-house secure firmware was discontinued long time ago so remove it. First couple of patches delete the defconfigs that use it (split in two to be <100KB) and the third one removes the actual PPA support. Changes in v2: - split the defconfig removal patch in two because it was too big and was filtered out by the ML Laurentiu Tudor (3): configs: layerscape: delete defconfigs using legacy PPA secure FW (part1) configs: layerscape: delete defconfigs using legacy PPA secure FW (part2) fsl-layerscape: drop obsolete PPA secure firmware support arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 60 arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 - arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 284 -- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 34 --- .../arm/include/asm/arch-fsl-layerscape/ppa.h | 12 - arch/arm/include/asm/fsl_secure_boot.h| 9 - board/freescale/ls1012afrdm/Kconfig | 11 - board/freescale/ls1012afrdm/ls1012afrdm.c | 6 - board/freescale/ls1012aqds/Kconfig| 8 - board/freescale/ls1012aqds/ls1012aqds.c | 6 - board/freescale/ls1012ardb/Kconfig| 12 - board/freescale/ls1012ardb/ls1012ardb.c | 6 - board/freescale/ls1028a/Kconfig | 12 - board/freescale/ls1028a/ls1028a.c | 7 - board/freescale/ls1043aqds/Kconfig| 16 - board/freescale/ls1043aqds/ls1043aqds.c | 5 - board/freescale/ls1043ardb/Kconfig| 14 - board/freescale/ls1043ardb/ls1043ardb.c | 5 - board/freescale/ls1046aqds/Kconfig| 16 - board/freescale/ls1046aqds/ls1046aqds.c | 5 - board/freescale/ls1046ardb/Kconfig| 14 - board/freescale/ls1046ardb/ls1046ardb.c | 5 - board/freescale/ls1088a/Kconfig | 28 -- board/freescale/ls1088a/ls1088a.c | 5 - board/freescale/ls2080aqds/Kconfig| 16 - board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/Kconfig| 16 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - board/traverse/ten64/ten64.c | 1 - configs/ls1012a2g5rdb_qspi_defconfig | 69 - configs/ls1012afrdm_qspi_defconfig| 67 - .../ls1012afrwy_qspi_SECURE_BOOT_defconfig| 72 - configs/ls1012afrwy_qspi_defconfig| 72 - configs/ls1012aqds_qspi_defconfig | 95 -- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 77 - configs/ls1012ardb_qspi_defconfig | 77 - configs/ls1043aqds_defconfig | 107 --- configs/ls1043aqds_lpuart_defconfig | 109 --- configs/ls1043aqds_nand_defconfig | 138 - configs/ls1043aqds_nor_ddr3_defconfig | 108 --- configs/ls1043aqds_qspi_defconfig | 98 -- configs/ls1043aqds_sdcard_ifc_defconfig | 135 - configs/ls1043aqds_sdcard_qspi_defconfig | 124 configs/ls1043ardb_SECURE_BOOT_defconfig | 99 -- configs/ls1043ardb_defconfig | 100 -- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_nand_defconfig | 128 .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_sdcard_defconfig | 126 configs/ls1046aqds_SECURE_BOOT_defconfig | 108 --- configs/ls1046aqds_defconfig | 110 --- configs/ls1046aqds_lpuart_defconfig | 112 --- configs/ls1046aqds_nand_defconfig | 139 - configs/ls1046aqds_qspi_defconfig | 101 --- configs/ls1046aqds_sdcard_ifc_defconfig | 139 - configs/ls1046aqds_sdcard_qspi_defconfig | 128 configs/ls1046ardb_emmc_defconfig | 122 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 99 -- configs/ls1046ardb_qspi_defconfig | 102 --- configs/ls1046ardb_qspi_spl_defconfig | 130 .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 123 configs/ls1046ardb_sdcard_defconfig | 122 configs/ls1088aqds_defconfig | 112 --- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 107 --- configs/ls1088aqds_qspi_defconfig | 108 --- configs/ls1088aqds_sdcard_ifc_defconfig | 130 configs/ls1088aqds_sdcard_qspi_defconfig | 128 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 104 --- configs/ls1088ardb_qspi_defconfig | 105 --- ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 124 configs/ls1088ardb_sdcard_qspi_defconfig | 124 configs/ls2080aqds_SECURE_BOOT_defconfig | 108 --- configs/ls2080aqds_defconfig | 109 --- configs/ls2080aqds_sdcard_defconfig | 116 --- conf
[PATCH 2/2] fsl-layerscape: drop obsolete PPA secure firmware support
From: Laurentiu Tudor PPA was a secure firmware developed in-house which is no longer supported and replaced by TF-A quite some years ago. Drop support for it. Signed-off-by: Laurentiu Tudor --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 60 arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 - arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 284 -- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 34 --- .../arm/include/asm/arch-fsl-layerscape/ppa.h | 12 - arch/arm/include/asm/fsl_secure_boot.h| 9 - board/freescale/ls1012afrdm/Kconfig | 11 - board/freescale/ls1012afrdm/ls1012afrdm.c | 6 - board/freescale/ls1012aqds/Kconfig| 8 - board/freescale/ls1012aqds/ls1012aqds.c | 6 - board/freescale/ls1012ardb/Kconfig| 12 - board/freescale/ls1012ardb/ls1012ardb.c | 6 - board/freescale/ls1028a/Kconfig | 12 - board/freescale/ls1028a/ls1028a.c | 7 - board/freescale/ls1043aqds/Kconfig| 16 - board/freescale/ls1043aqds/ls1043aqds.c | 5 - board/freescale/ls1043ardb/Kconfig| 14 - board/freescale/ls1043ardb/ls1043ardb.c | 5 - board/freescale/ls1046aqds/Kconfig| 16 - board/freescale/ls1046aqds/ls1046aqds.c | 5 - board/freescale/ls1046ardb/Kconfig| 14 - board/freescale/ls1046ardb/ls1046ardb.c | 5 - board/freescale/ls1088a/Kconfig | 28 -- board/freescale/ls1088a/ls1088a.c | 5 - board/freescale/ls2080aqds/Kconfig| 16 - board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/Kconfig| 16 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - board/traverse/ten64/ten64.c | 1 - env/Kconfig | 2 +- include/configs/ls1046a_common.h | 3 +- 31 files changed, 2 insertions(+), 627 deletions(-) delete mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa.c delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ppa.h diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a8b493e2f875..c45e4e63b4bb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -390,66 +390,6 @@ config HAS_FEATURE_ENHANCED_MSI bool default y if ARCH_LS1043A -menu "Layerscape PPA" -config FSL_LS_PPA - bool "FSL Layerscape PPA firmware support" - depends on !ARMV8_PSCI - select ARMV8_SEC_FIRMWARE_SUPPORT - select SEC_FIRMWARE_ARMV8_PSCI - select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 - help - The FSL Primary Protected Application (PPA) is a software component - which is loaded during boot stage, and then remains resident in RAM - and runs in the TrustZone after boot. - Say y to enable it. - -config SPL_FSL_LS_PPA - bool "FSL Layerscape PPA firmware support for SPL build" - depends on !ARMV8_PSCI - select SPL_ARMV8_SEC_FIRMWARE_SUPPORT - select SEC_FIRMWARE_ARMV8_PSCI - select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 - help - The FSL Primary Protected Application (PPA) is a software component - which is loaded during boot stage, and then remains resident in RAM - and runs in the TrustZone after boot. This is to load PPA during SPL - stage instead of the RAM version of U-Boot. Once PPA is initialized, - the rest of U-Boot (including RAM version) runs at EL2. -choice - prompt "FSL Layerscape PPA firmware loading-media select" - depends on FSL_LS_PPA - default SYS_LS_PPA_FW_IN_MMC if SD_BOOT - default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT - default SYS_LS_PPA_FW_IN_XIP - -config SYS_LS_PPA_FW_IN_XIP - bool "XIP" - help - Say Y here if the PPA firmware locate at XIP flash, such - as NOR or QSPI flash. - -config SYS_LS_PPA_FW_IN_MMC - bool "eMMC or SD Card" - help - Say Y here if the PPA firmware locate at eMMC/SD card. - -config SYS_LS_PPA_FW_IN_NAND - bool "NAND" - help - Say Y here if the PPA firmware locate at NAND flash. - -endchoice - -config LS_PPA_ESBC_HDR_SIZE - hex "Length of PPA ESBC header" - depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP - default 0x2000 - help - Length (in bytes) of PPA ESBC header to be copied from MMC/SD or - NAND to memory to validate PPA image. - -endmenu - config SYS_FSL_ERRATUM_A008997 bool "Workaround for USB PHY erratum A008997" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 598c36ee660a..eefdf12369c3 100644 --- a/arch/arm/cpu/armv8/fsl-layer
[PATCH 0/2] fsl-layerscape: drop support for obsolete PPA secure firmware
From: Laurentiu Tudor Support for this in-house secure firmware was discontinued long time ago so remove it. First patch deletes the defconfigs that use it and the second one removes the actual support. Laurentiu Tudor (2): configs: layerscape: delete defconfigs using legacy PPA secure FW fsl-layerscape: drop obsolete PPA secure firmware support arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 60 arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 - arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 284 -- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 34 --- .../arm/include/asm/arch-fsl-layerscape/ppa.h | 12 - arch/arm/include/asm/fsl_secure_boot.h| 9 - board/freescale/ls1012afrdm/Kconfig | 11 - board/freescale/ls1012afrdm/ls1012afrdm.c | 6 - board/freescale/ls1012aqds/Kconfig| 8 - board/freescale/ls1012aqds/ls1012aqds.c | 6 - board/freescale/ls1012ardb/Kconfig| 12 - board/freescale/ls1012ardb/ls1012ardb.c | 6 - board/freescale/ls1028a/Kconfig | 12 - board/freescale/ls1028a/ls1028a.c | 7 - board/freescale/ls1043aqds/Kconfig| 16 - board/freescale/ls1043aqds/ls1043aqds.c | 5 - board/freescale/ls1043ardb/Kconfig| 14 - board/freescale/ls1043ardb/ls1043ardb.c | 5 - board/freescale/ls1046aqds/Kconfig| 16 - board/freescale/ls1046aqds/ls1046aqds.c | 5 - board/freescale/ls1046ardb/Kconfig| 14 - board/freescale/ls1046ardb/ls1046ardb.c | 5 - board/freescale/ls1088a/Kconfig | 28 -- board/freescale/ls1088a/ls1088a.c | 5 - board/freescale/ls2080aqds/Kconfig| 16 - board/freescale/ls2080aqds/ls2080aqds.c | 5 - board/freescale/ls2080ardb/Kconfig| 16 - board/freescale/ls2080ardb/ls2080ardb.c | 5 - board/traverse/ten64/ten64.c | 1 - configs/ls1012a2g5rdb_qspi_defconfig | 69 - configs/ls1012afrdm_qspi_defconfig| 67 - .../ls1012afrwy_qspi_SECURE_BOOT_defconfig| 72 - configs/ls1012afrwy_qspi_defconfig| 72 - configs/ls1012aqds_qspi_defconfig | 95 -- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 77 - configs/ls1012ardb_qspi_defconfig | 77 - configs/ls1043aqds_defconfig | 107 --- configs/ls1043aqds_lpuart_defconfig | 109 --- configs/ls1043aqds_nand_defconfig | 138 - configs/ls1043aqds_nor_ddr3_defconfig | 108 --- configs/ls1043aqds_qspi_defconfig | 98 -- configs/ls1043aqds_sdcard_ifc_defconfig | 135 - configs/ls1043aqds_sdcard_qspi_defconfig | 124 configs/ls1043ardb_SECURE_BOOT_defconfig | 99 -- configs/ls1043ardb_defconfig | 100 -- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_nand_defconfig | 128 .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 124 configs/ls1043ardb_sdcard_defconfig | 126 configs/ls1046aqds_SECURE_BOOT_defconfig | 108 --- configs/ls1046aqds_defconfig | 110 --- configs/ls1046aqds_lpuart_defconfig | 112 --- configs/ls1046aqds_nand_defconfig | 139 - configs/ls1046aqds_qspi_defconfig | 101 --- configs/ls1046aqds_sdcard_ifc_defconfig | 139 - configs/ls1046aqds_sdcard_qspi_defconfig | 128 configs/ls1046ardb_emmc_defconfig | 122 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 99 -- configs/ls1046ardb_qspi_defconfig | 102 --- configs/ls1046ardb_qspi_spl_defconfig | 130 .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 123 configs/ls1046ardb_sdcard_defconfig | 122 configs/ls1088aqds_defconfig | 112 --- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 107 --- configs/ls1088aqds_qspi_defconfig | 108 --- configs/ls1088aqds_sdcard_ifc_defconfig | 130 configs/ls1088aqds_sdcard_qspi_defconfig | 128 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 104 --- configs/ls1088ardb_qspi_defconfig | 105 --- ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 124 configs/ls1088ardb_sdcard_qspi_defconfig | 124 configs/ls2080aqds_SECURE_BOOT_defconfig | 108 --- configs/ls2080aqds_defconfig | 109 --- configs/ls2080aqds_sdcard_defconfig | 116 --- configs/ls2080ardb_SECURE_BOOT_defconfig | 107 --- configs/ls2080ardb_defconfig | 108 --- configs/ls2081ardb_defconfig | 96 -- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 96 -- configs
Re: [PATCHv2] arm64: gic-v3-its: Clear the Pending table before enabling LPIs
Hi Zhiqiang,
On 3/5/2021 4:21 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
> must contain only zeros on initial allocation, and this must be visible
> to the Redistributors, or else the effect is UNPREDICTABLE".
>
> And as the following statement, we here clear the whole Pending tables
> instead of the first 1KB.
> "An LPI Pending table that contains only zeros, including in the first 1KB,
> indicates that there are no pending LPIs.
> The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
> if the first 1KB of the LPI Pending table and the rest of the table contain
> only zeros, this must indicate that there are no pending LPIs."
>
> And there isn't any pending LPI under U-Boot, so it's unnecessary to
> load the contents of the Pending table during the enablement, then set
> the GICR_PENDBASER.PTZ flag.
>
> Signed-off-by: Hou Zhiqiang
> ---
> V2:
> - Clear the Pending tables using virtual address.
> - Correct some typos in the change log.
>
> arch/arm/lib/gic-v3-its.c | 13 +++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
> index f5a921b3d1..2dadc48a50 100644
> --- a/arch/arm/lib/gic-v3-its.c
> +++ b/arch/arm/lib/gic-v3-its.c
> @@ -3,6 +3,7 @@
> * Copyright 2019 Broadcom.
> */
> #include
> +#include
> #include
> #include
> #include
> @@ -108,6 +109,8 @@ int gic_lpi_tables_init(void)
> int i;
> u64 redist_lpi_base;
> u64 pend_base;
> + ulong pend_tab_total_sz;
> + void *pend_tab_va;
>
> if (gic_v3_its_get_gic_addr())
> return -EINVAL;
> @@ -160,7 +163,12 @@ int gic_lpi_tables_init(void)
> }
> }
>
> - redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
I don't think you want to drop this.
> + pend_tab_total_sz = priv.num_redist * LPI_PENDBASE_SZ;
> + pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz,
> + MAP_NOCACHE);
> + memset(pend_tab_va, 0, pend_tab_total_sz);
> + flush_cache((ulong)pend_tab_va, pend_tab_total_sz);
Given that the memory is mapped as non-cacheable, is this flush necessary?
---
Best Regards, Laurentiu
> + unmap_physmem(pend_tab_va, MAP_NOCACHE);
>
> pend_base = priv.gicr_base + GICR_PENDBASER;
> for (i = 0; i < priv.num_redist; i++) {
> @@ -168,7 +176,8 @@ int gic_lpi_tables_init(void)
>
> val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
> GICR_PENDBASER_INNERSHAREABLE |
> - GICR_PENDBASER_RAWAWB);
> + GICR_PENDBASER_RAWAWB |
> + GICR_PENDBASER_PTZ);
>
> writeq(val, (uintptr_t)(pend_base + offset));
> tmp = readq((uintptr_t)(pend_base + offset));
>
[PATCH v5 4/4] pci: layerscape: add a way of specifying additional iommu mappings
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor --- .../fsl-layerscape/doc/README.pci_iommu_extra | 67 drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 328 ++ 3 files changed, 407 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra new file mode 100644 index 00..43db4d8e94 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra @@ -0,0 +1,67 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Specifying extra IOMMU mappings for PCI controllers + +This feature can be enabled through the PCI_IOMMU_EXTRA_MAPPINGS Kconfig option. + +The "pci_iommu_extra" env var or "pci-iommu-extra" device tree property (to be +used for example in more static scenarios such as hardwired PCI endpoints that +get initialized later in the system setup) allows two things: + - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number + of VFs that will ever be created for it + - for hot-plug case, specify the B.D.F with which the device will show up on + the PCI bus + +The env var consists of a list of , pairs for a certain pci bus +identified by its controller's base register address, as defined in the "reg" +property in the device tree. + +pci_iommu_extra = pci@, + pci@,... + +where: + is the base register address of the pci controller for which the +subsequent , pairs apply + identifies to which B.D.F the action applies to + can be: +- "vfs=" to specify that for the PCI EP identified previously by + the to include mappings for of VFs. + The variant "noari_vfs=" is available to disable taking ARI into + account. +- "hp" to specify that on this there will be a hot-plugged device so + it needs a mapping +The device tree property must be placed under the correct pci controller node +and only the bdf and action pairs need to be specified, like this: + +pci-iommu-extra = "..."; + +Note: the env var has priority over the device tree property. + +For example, given this configuration on bus 6: + +=> pci 6 +Scanning PCI devices on bus 6 +BusDevFun VendorId DeviceId Device Class Sub-Class +_ +06.00.00 0x8086 0x1572 Network controller 0x00 +06.00.01 0x8086 0x1572 Network controller 0x00 + +The following u-boot env var will create iommu mappings for 3 VFs for each PF: + +=> setenv pci_iommu_extra pci@0x380,6.0.0,vfs=3,6.0.1,vfs=3 + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "6.0.0,vfs=3,6.0.1,vfs=3"; + +To add an iommu mapping for a hot-plugged device, please see following example: + +=> setenv pci_iommu_extra pci@0x380,2.16.0,hp + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "2.16.0,hp"; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index dd1cc65229..af92784950 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -179,6 +179,18 @@ config PCIE_LAYERSCAPE_RC configured to Root Complex mode by clearing the corresponding bit of RCW[HOST_AGT_PEX]. +config PCI_IOMMU_EXTRA_MAPPINGS + bool "Support for specifying extra IOMMU mappings for PCI" + depends on PCIE_LAYERSCAPE_RC + help + Enable support for specifying extra IOMMU mappings for PCI + controllers through a special env var called "pci_iommu_extra" or + through a device tree property named "pci-iommu-extra" placed in + the node describing the PCI controller. + The intent is to cover SR-IOV scenarios which need mappings for VFs + and PCI hot-plug scenarios. More documentation can be found under: + arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra + config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint
[PATCH v5 3/4] pci: add a few ARI related defines
From: Laurentiu Tudor Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor --- include/pci.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/pci.h b/include/pci.h index 1c5b36617e..d1ccf6c963 100644 --- a/include/pci.h +++ b/include/pci.h @@ -495,12 +495,18 @@ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */ +#define PCI_EXP_DEVCAP236 /* Device Capabilities 2 */ +#define PCI_EXP_DEVCAP2_ARI 0x0020 /* ARI Forwarding Supported */ +#define PCI_EXP_DEVCTL240 /* Device Control 2 */ +#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ + #define PCI_EXP_LNKCTL248 /* Link Control 2 */ /* Single Root I/O Virtualization Registers */ #define PCI_SRIOV_CAP 0x04/* SR-IOV Capabilities */ #define PCI_SRIOV_CTRL 0x08/* SR-IOV Control */ #define PCI_SRIOV_CTRL_VFE0x01/* VF Enable */ #define PCI_SRIOV_CTRL_MSE0x08/* VF Memory Space Enable */ +#define PCI_SRIOV_CTRL_ARI0x10/* ARI Capable Hierarchy */ #define PCI_SRIOV_INITIAL_VF 0x0c/* Initial VFs */ #define PCI_SRIOV_TOTAL_VF 0x0e/* Total VFs */ #define PCI_SRIOV_NUM_VF 0x10/* Number of VFs */ -- 2.17.1
[PATCH v4 0/4] Support for specifying extra IOMMU mappings for PCI
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add support for specifying extra IOMMU mappings for PCI controllers through a special env var called "pci_iommu_extra" or through a device tree property named "pci-iommu-extra" placed in the node describing the PCI controller. More detailed information can be found in the final patch. Changes in v5: - dropped useless NULL check for variable 'compat' in patch 2 Changes in v4: - rebased - fixed compilation issue on ls1021a based boards Changes in v3: - rebased - trimmed commit message of the last patch - minor adjustments to the readme file Changes in v2: - add ARI support and use it by default - option to disable ARI - fixes in BDF calculation - reorganized code a bit - added more comments Laurentiu Tudor (4): pci: layerscape: move per-pci device fdt fixup in a function pci: layerscape: move pci node search in a common function pci: add a few ARI related defines pci: layerscape: add a way of specifying additional iommu mappings .../fsl-layerscape/doc/README.pci_iommu_extra | 67 +++ drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 460 +++--- include/pci.h | 6 + 4 files changed, 480 insertions(+), 65 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra -- 2.17.1
[PATCH v5 2/4] pci: layerscape: move pci node search in a common function
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 76 +
1 file changed, 34 insertions(+), 42 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 7c55e3d249..fdbfd82740 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -22,6 +22,34 @@
#include "pcie_layerscape.h"
#include "pcie_layerscape_fixup_common.h"
+static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc)
+{
+ int nodeoffset;
+ uint svr;
+ char *compat = NULL;
+
+ /* find pci controller node */
+ nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
+ pcie_rc->dbi_res.start);
+ if (nodeoffset < 0) {
+#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+ svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
+ if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A)
+ compat = "fsl,ls2088a-pcie";
+ else
+ compat = CONFIG_FSL_PCIE_COMPAT;
+
+ nodeoffset =
+ fdt_node_offset_by_compat_reg(blob, compat,
+ pcie_rc->dbi_res.start);
+#endif
+ }
+
+ return nodeoffset;
+}
+
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
/*
* Return next available LUT index.
@@ -127,30 +155,11 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
u32 iommu_map[4];
int nodeoffset;
int lenp;
- uint svr;
- char *compat = NULL;
struct ls_pcie *pcie = pcie_rc->pcie;
- /* find pci controller node */
- nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie_rc->dbi_res.start);
- if (nodeoffset < 0) {
-#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A)
- compat = "fsl,ls2088a-pcie";
- else
- compat = CONFIG_FSL_PCIE_COMPAT;
-
- if (compat)
- nodeoffset = fdt_node_offset_by_compat_reg(blob,
- compat, pcie_rc->dbi_res.start);
-#endif
- if (nodeoffset < 0)
- return;
- }
+ nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
+ if (nodeoffset < 0)
+ return;
/* get phandle to iommu controller */
prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", );
@@ -232,28 +241,11 @@ static void fdt_fixup_pcie_ls(void *blob)
static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
{
int off;
- uint svr;
- char *compat = NULL;
struct ls_pcie *pcie = pcie_rc->pcie;
- off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie_rc->dbi_res.start);
- if (off < 0) {
-#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A)
- compat = "fsl,ls2088a-pcie";
- else
- compat = CONFIG_FSL_PCIE_COMPAT;
- if (compat)
- off = fdt_node_offset_by_compat_reg(blob,
- compat, pcie_rc->dbi_res.start);
-#endif
- if (off < 0)
- return;
- }
+ off = fdt_pcie_get_nodeoffset(blob, pcie_rc);
+ if (off < 0)
+ return;
if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
--
2.17.1
[PATCH v5 1/4] pci: layerscape: move per-pci device fdt fixup in a function
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 60 -
1 file changed, 34 insertions(+), 26 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 8315b0b590..7c55e3d249 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -174,12 +174,41 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
}
}
+static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf,
+ struct ls_pcie_rc *pcie_rc)
+{
+ int streamid, index;
+
+ streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
+ pcie_rc->pcie->idx);
+ if (streamid < 0) {
+ printf("ERROR: out of stream ids for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+ pcie_rc->stream_id_cur++;
+
+ index = ls_pcie_next_lut_index(pcie_rc);
+ if (index < 0) {
+ printf("ERROR: out of LUT indexes for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8, streamid);
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
+ /* update iommu-map in device tree */
+ fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
+
+ return 0;
+}
+
static void fdt_fixup_pcie_ls(void *blob)
{
struct udevice *dev, *bus;
struct ls_pcie_rc *pcie_rc;
- int streamid;
- int index;
pci_dev_t bdf;
/* Scan all known buses */
@@ -190,32 +219,11 @@ static void fdt_fixup_pcie_ls(void *blob)
bus = bus->parent;
pcie_rc = dev_get_priv(bus);
- streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
- pcie_rc->pcie->idx);
- if (streamid < 0) {
- debug("ERROR: no stream ids free\n");
- continue;
- } else {
- pcie_rc->stream_id_cur++;
- }
-
- index = ls_pcie_next_lut_index(pcie_rc);
- if (index < 0) {
- debug("ERROR: no LUT indexes free\n");
- continue;
- }
-
/* the DT fixup must be relative to the hose first_busno */
bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
- /* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8,
- streamid);
- /* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8,
- streamid);
- /* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8,
- streamid);
+
+ if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0)
+ break;
}
pcie_board_fix_fdt(blob);
}
--
2.17.1
[PATCH v4 4/4] pci: layerscape: add a way of specifying additional iommu mappings
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor --- .../fsl-layerscape/doc/README.pci_iommu_extra | 67 drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 328 ++ 3 files changed, 407 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra new file mode 100644 index 00..43db4d8e94 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra @@ -0,0 +1,67 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Specifying extra IOMMU mappings for PCI controllers + +This feature can be enabled through the PCI_IOMMU_EXTRA_MAPPINGS Kconfig option. + +The "pci_iommu_extra" env var or "pci-iommu-extra" device tree property (to be +used for example in more static scenarios such as hardwired PCI endpoints that +get initialized later in the system setup) allows two things: + - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number + of VFs that will ever be created for it + - for hot-plug case, specify the B.D.F with which the device will show up on + the PCI bus + +The env var consists of a list of , pairs for a certain pci bus +identified by its controller's base register address, as defined in the "reg" +property in the device tree. + +pci_iommu_extra = pci@, + pci@,... + +where: + is the base register address of the pci controller for which the +subsequent , pairs apply + identifies to which B.D.F the action applies to + can be: +- "vfs=" to specify that for the PCI EP identified previously by + the to include mappings for of VFs. + The variant "noari_vfs=" is available to disable taking ARI into + account. +- "hp" to specify that on this there will be a hot-plugged device so + it needs a mapping +The device tree property must be placed under the correct pci controller node +and only the bdf and action pairs need to be specified, like this: + +pci-iommu-extra = "..."; + +Note: the env var has priority over the device tree property. + +For example, given this configuration on bus 6: + +=> pci 6 +Scanning PCI devices on bus 6 +BusDevFun VendorId DeviceId Device Class Sub-Class +_ +06.00.00 0x8086 0x1572 Network controller 0x00 +06.00.01 0x8086 0x1572 Network controller 0x00 + +The following u-boot env var will create iommu mappings for 3 VFs for each PF: + +=> setenv pci_iommu_extra pci@0x380,6.0.0,vfs=3,6.0.1,vfs=3 + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "6.0.0,vfs=3,6.0.1,vfs=3"; + +To add an iommu mapping for a hot-plugged device, please see following example: + +=> setenv pci_iommu_extra pci@0x380,2.16.0,hp + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "2.16.0,hp"; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index dd1cc65229..af92784950 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -179,6 +179,18 @@ config PCIE_LAYERSCAPE_RC configured to Root Complex mode by clearing the corresponding bit of RCW[HOST_AGT_PEX]. +config PCI_IOMMU_EXTRA_MAPPINGS + bool "Support for specifying extra IOMMU mappings for PCI" + depends on PCIE_LAYERSCAPE_RC + help + Enable support for specifying extra IOMMU mappings for PCI + controllers through a special env var called "pci_iommu_extra" or + through a device tree property named "pci-iommu-extra" placed in + the node describing the PCI controller. + The intent is to cover SR-IOV scenarios which need mappings for VFs + and PCI hot-plug scenarios. More documentation can be found under: + arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra + config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint
[PATCH v4 3/4] pci: add a few ARI related defines
From: Laurentiu Tudor Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor --- include/pci.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/pci.h b/include/pci.h index 1c5b36617e..d1ccf6c963 100644 --- a/include/pci.h +++ b/include/pci.h @@ -495,12 +495,18 @@ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */ +#define PCI_EXP_DEVCAP236 /* Device Capabilities 2 */ +#define PCI_EXP_DEVCAP2_ARI 0x0020 /* ARI Forwarding Supported */ +#define PCI_EXP_DEVCTL240 /* Device Control 2 */ +#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ + #define PCI_EXP_LNKCTL248 /* Link Control 2 */ /* Single Root I/O Virtualization Registers */ #define PCI_SRIOV_CAP 0x04/* SR-IOV Capabilities */ #define PCI_SRIOV_CTRL 0x08/* SR-IOV Control */ #define PCI_SRIOV_CTRL_VFE0x01/* VF Enable */ #define PCI_SRIOV_CTRL_MSE0x08/* VF Memory Space Enable */ +#define PCI_SRIOV_CTRL_ARI0x10/* ARI Capable Hierarchy */ #define PCI_SRIOV_INITIAL_VF 0x0c/* Initial VFs */ #define PCI_SRIOV_TOTAL_VF 0x0e/* Total VFs */ #define PCI_SRIOV_NUM_VF 0x10/* Number of VFs */ -- 2.17.1
[PATCH v4 2/4] pci: layerscape: move pci node search in a common function
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 78 +
1 file changed, 36 insertions(+), 42 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 7c55e3d249..715c1a7788 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -22,6 +22,36 @@
#include "pcie_layerscape.h"
#include "pcie_layerscape_fixup_common.h"
+static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc)
+{
+ int nodeoffset;
+ uint svr;
+ char *compat = NULL;
+
+ /* find pci controller node */
+ nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
+ pcie_rc->dbi_res.start);
+ if (nodeoffset < 0) {
+#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+ svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
+ if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A)
+ compat = "fsl,ls2088a-pcie";
+ else
+ compat = CONFIG_FSL_PCIE_COMPAT;
+
+ if (!compat)
+ return nodeoffset;
+ nodeoffset =
+ fdt_node_offset_by_compat_reg(blob, compat,
+ pcie_rc->dbi_res.start);
+#endif
+ }
+
+ return nodeoffset;
+}
+
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
/*
* Return next available LUT index.
@@ -127,30 +157,11 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
u32 iommu_map[4];
int nodeoffset;
int lenp;
- uint svr;
- char *compat = NULL;
struct ls_pcie *pcie = pcie_rc->pcie;
- /* find pci controller node */
- nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie_rc->dbi_res.start);
- if (nodeoffset < 0) {
-#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A)
- compat = "fsl,ls2088a-pcie";
- else
- compat = CONFIG_FSL_PCIE_COMPAT;
-
- if (compat)
- nodeoffset = fdt_node_offset_by_compat_reg(blob,
- compat, pcie_rc->dbi_res.start);
-#endif
- if (nodeoffset < 0)
- return;
- }
+ nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
+ if (nodeoffset < 0)
+ return;
/* get phandle to iommu controller */
prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", );
@@ -232,28 +243,11 @@ static void fdt_fixup_pcie_ls(void *blob)
static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
{
int off;
- uint svr;
- char *compat = NULL;
struct ls_pcie *pcie = pcie_rc->pcie;
- off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie_rc->dbi_res.start);
- if (off < 0) {
-#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A)
- compat = "fsl,ls2088a-pcie";
- else
- compat = CONFIG_FSL_PCIE_COMPAT;
- if (compat)
- off = fdt_node_offset_by_compat_reg(blob,
- compat, pcie_rc->dbi_res.start);
-#endif
- if (off < 0)
- return;
- }
+ off = fdt_pcie_get_nodeoffset(blob, pcie_rc);
+ if (off < 0)
+ return;
if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
--
2.17.1
[PATCH v4 1/4] pci: layerscape: move per-pci device fdt fixup in a function
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 60 -
1 file changed, 34 insertions(+), 26 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 8315b0b590..7c55e3d249 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -174,12 +174,41 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
}
}
+static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf,
+ struct ls_pcie_rc *pcie_rc)
+{
+ int streamid, index;
+
+ streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
+ pcie_rc->pcie->idx);
+ if (streamid < 0) {
+ printf("ERROR: out of stream ids for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+ pcie_rc->stream_id_cur++;
+
+ index = ls_pcie_next_lut_index(pcie_rc);
+ if (index < 0) {
+ printf("ERROR: out of LUT indexes for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8, streamid);
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
+ /* update iommu-map in device tree */
+ fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
+
+ return 0;
+}
+
static void fdt_fixup_pcie_ls(void *blob)
{
struct udevice *dev, *bus;
struct ls_pcie_rc *pcie_rc;
- int streamid;
- int index;
pci_dev_t bdf;
/* Scan all known buses */
@@ -190,32 +219,11 @@ static void fdt_fixup_pcie_ls(void *blob)
bus = bus->parent;
pcie_rc = dev_get_priv(bus);
- streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
- pcie_rc->pcie->idx);
- if (streamid < 0) {
- debug("ERROR: no stream ids free\n");
- continue;
- } else {
- pcie_rc->stream_id_cur++;
- }
-
- index = ls_pcie_next_lut_index(pcie_rc);
- if (index < 0) {
- debug("ERROR: no LUT indexes free\n");
- continue;
- }
-
/* the DT fixup must be relative to the hose first_busno */
bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
- /* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8,
- streamid);
- /* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8,
- streamid);
- /* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8,
- streamid);
+
+ if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0)
+ break;
}
pcie_board_fix_fdt(blob);
}
--
2.17.1
[PATCH v4 0/4] Support for specifying extra IOMMU mappings for PCI
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add support for specifying extra IOMMU mappings for PCI controllers through a special env var called "pci_iommu_extra" or through a device tree property named "pci-iommu-extra" placed in the node describing the PCI controller. More detailed information can be found in the final patch. Changes in v4: - rebased - fixed compilation issue on ls1021a based boards Changes in v3: - rebased - trimmed commit message of the last patch - minor adjustments to the readme file Changes in v2: - add ARI support and use it by default - option to disable ARI - fixes in BDF calculation - reorganized code a bit - added more comments Laurentiu Tudor (4): pci: layerscape: move per-pci device fdt fixup in a function pci: layerscape: move pci node search in a common function pci: add a few ARI related defines pci: layerscape: add a way of specifying additional iommu mappings .../fsl-layerscape/doc/README.pci_iommu_extra | 67 +++ drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 460 +++--- include/pci.h | 6 + 4 files changed, 480 insertions(+), 65 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra -- 2.17.1
[PATCH v3 4/4] pci: layerscape: add a way of specifying additional iommu mappings
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor --- .../fsl-layerscape/doc/README.pci_iommu_extra | 67 drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 328 ++ 3 files changed, 407 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra new file mode 100644 index 00..43db4d8e94 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra @@ -0,0 +1,67 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Specifying extra IOMMU mappings for PCI controllers + +This feature can be enabled through the PCI_IOMMU_EXTRA_MAPPINGS Kconfig option. + +The "pci_iommu_extra" env var or "pci-iommu-extra" device tree property (to be +used for example in more static scenarios such as hardwired PCI endpoints that +get initialized later in the system setup) allows two things: + - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number + of VFs that will ever be created for it + - for hot-plug case, specify the B.D.F with which the device will show up on + the PCI bus + +The env var consists of a list of , pairs for a certain pci bus +identified by its controller's base register address, as defined in the "reg" +property in the device tree. + +pci_iommu_extra = pci@, + pci@,... + +where: + is the base register address of the pci controller for which the +subsequent , pairs apply + identifies to which B.D.F the action applies to + can be: +- "vfs=" to specify that for the PCI EP identified previously by + the to include mappings for of VFs. + The variant "noari_vfs=" is available to disable taking ARI into + account. +- "hp" to specify that on this there will be a hot-plugged device so + it needs a mapping +The device tree property must be placed under the correct pci controller node +and only the bdf and action pairs need to be specified, like this: + +pci-iommu-extra = "..."; + +Note: the env var has priority over the device tree property. + +For example, given this configuration on bus 6: + +=> pci 6 +Scanning PCI devices on bus 6 +BusDevFun VendorId DeviceId Device Class Sub-Class +_ +06.00.00 0x8086 0x1572 Network controller 0x00 +06.00.01 0x8086 0x1572 Network controller 0x00 + +The following u-boot env var will create iommu mappings for 3 VFs for each PF: + +=> setenv pci_iommu_extra pci@0x380,6.0.0,vfs=3,6.0.1,vfs=3 + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "6.0.0,vfs=3,6.0.1,vfs=3"; + +To add an iommu mapping for a hot-plugged device, please see following example: + +=> setenv pci_iommu_extra pci@0x380,2.16.0,hp + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "2.16.0,hp"; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 5e0a39396b..b31254bf41 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -141,6 +141,18 @@ config PCIE_LAYERSCAPE_RC configured to Root Complex mode by clearing the corresponding bit of RCW[HOST_AGT_PEX]. +config PCI_IOMMU_EXTRA_MAPPINGS + bool "Support for specifying extra IOMMU mappings for PCI" + depends on PCIE_LAYERSCAPE_RC + help + Enable support for specifying extra IOMMU mappings for PCI + controllers through a special env var called "pci_iommu_extra" or + through a device tree property named "pci-iommu-extra" placed in + the node describing the PCI controller. + The intent is to cover SR-IOV scenarios which need mappings for VFs + and PCI hot-plug scenarios. More documentation can be found under: + arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra + config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint
[PATCH v3 3/4] pci: add a few ARI and SRIOV related defines
From: Laurentiu Tudor Add a few defines related to ARI and SRIOV configuration. Signed-off-by: Laurentiu Tudor --- include/pci.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/include/pci.h b/include/pci.h index 2089db9f16..88a09505a5 100644 --- a/include/pci.h +++ b/include/pci.h @@ -492,6 +492,20 @@ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */ +#define PCI_EXP_DEVCAP236 /* Device Capabilities 2 */ +#define PCI_EXP_DEVCAP2_ARI 0x0020 /* ARI Forwarding Supported */ +#define PCI_EXP_DEVCTL240 /* Device Control 2 */ +#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ + +/* PCI SR-IOV Configuration */ +#define PCI_SRIOV_CTRL 8 /* SR-IOV Control Register */ +#define PCI_SRIOV_CTRL_VF_EN 0x0001 /* VF Enable */ +#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ +#define PCI_SRIOV_TOTAL_VFS14 /* TotalVFs */ +#define PCI_SRIOV_NUM_VFS 16 /* NumVFs */ +#define PCI_SRIOV_VF_OFFSET20 /* First VF Offset */ +#define PCI_SRIOV_VF_STRIDE22 /* VF Stride */ + #define PCI_EXP_LNKCTL248 /* Link Control 2 */ /* Include the ID list */ -- 2.17.1
[PATCH v3 1/4] pci: layerscape: move per-pci device fdt fixup in a function
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 60 -
1 file changed, 34 insertions(+), 26 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 8315b0b590..7c55e3d249 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -174,12 +174,41 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
}
}
+static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf,
+ struct ls_pcie_rc *pcie_rc)
+{
+ int streamid, index;
+
+ streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
+ pcie_rc->pcie->idx);
+ if (streamid < 0) {
+ printf("ERROR: out of stream ids for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+ pcie_rc->stream_id_cur++;
+
+ index = ls_pcie_next_lut_index(pcie_rc);
+ if (index < 0) {
+ printf("ERROR: out of LUT indexes for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8, streamid);
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
+ /* update iommu-map in device tree */
+ fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
+
+ return 0;
+}
+
static void fdt_fixup_pcie_ls(void *blob)
{
struct udevice *dev, *bus;
struct ls_pcie_rc *pcie_rc;
- int streamid;
- int index;
pci_dev_t bdf;
/* Scan all known buses */
@@ -190,32 +219,11 @@ static void fdt_fixup_pcie_ls(void *blob)
bus = bus->parent;
pcie_rc = dev_get_priv(bus);
- streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
- pcie_rc->pcie->idx);
- if (streamid < 0) {
- debug("ERROR: no stream ids free\n");
- continue;
- } else {
- pcie_rc->stream_id_cur++;
- }
-
- index = ls_pcie_next_lut_index(pcie_rc);
- if (index < 0) {
- debug("ERROR: no LUT indexes free\n");
- continue;
- }
-
/* the DT fixup must be relative to the hose first_busno */
bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
- /* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8,
- streamid);
- /* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8,
- streamid);
- /* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8,
- streamid);
+
+ if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0)
+ break;
}
pcie_board_fix_fdt(blob);
}
--
2.17.1
[PATCH v3 2/4] pci: layerscape: move pci node search in a common function
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 68 +
1 file changed, 30 insertions(+), 38 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 7c55e3d249..9e93841ccd 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -111,32 +111,18 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob,
fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
}
-/*
- * An iommu-map is a property to be added to the pci controller
- * node. It is a table, where each entry consists of 4 fields
- * e.g.:
- *
- * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
- * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
- */
-static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
- struct ls_pcie_rc *pcie_rc,
- u32 devid, u32 streamid)
+static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc)
{
- u32 *prop;
- u32 iommu_map[4];
int nodeoffset;
- int lenp;
uint svr;
char *compat = NULL;
- struct ls_pcie *pcie = pcie_rc->pcie;
/* find pci controller node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
pcie_rc->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
+ svr = SVR_SOC_VER(get_svr());
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
svr == SVR_LS2081A || svr == SVR_LS2041A)
@@ -148,10 +134,33 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
nodeoffset = fdt_node_offset_by_compat_reg(blob,
compat, pcie_rc->dbi_res.start);
#endif
- if (nodeoffset < 0)
- return;
}
+ return nodeoffset;
+}
+
+/*
+ * An iommu-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
+ struct ls_pcie_rc *pcie_rc,
+ u32 devid, u32 streamid)
+{
+ u32 *prop;
+ u32 iommu_map[4];
+ int nodeoffset;
+ int lenp;
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
+ if (nodeoffset < 0)
+ return;
+
/* get phandle to iommu controller */
prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", );
if (prop == NULL) {
@@ -232,28 +241,11 @@ static void fdt_fixup_pcie_ls(void *blob)
static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
{
int off;
- uint svr;
- char *compat = NULL;
struct ls_pcie *pcie = pcie_rc->pcie;
- off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie_rc->dbi_res.start);
- if (off < 0) {
-#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A)
- compat = "fsl,ls2088a-pcie";
- else
- compat = CONFIG_FSL_PCIE_COMPAT;
- if (compat)
- off = fdt_node_offset_by_compat_reg(blob,
- compat, pcie_rc->dbi_res.start);
-#endif
- if (off < 0)
- return;
- }
+ off = fdt_pcie_get_nodeoffset(blob, pcie_rc);
+ if (off < 0)
+ return;
if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
--
2.17.1
[PATCH v3 0/4] Support for specifying extra IOMMU mappings for PCI
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add support for specifying extra IOMMU mappings for PCI controllers through a special env var called "pci_iommu_extra" or through a device tree property named "pci-iommu-extra" placed in the node describing the PCI controller. More detailed information can be found in the final patch. Changes in v3: - rebased - trimmed commit message of the last patch - minor adjustments to the readme file Changes in v2: - add ARI support and use it by default - option to disable ARI - fixes in BDF calculation - reorganized code a bit - added more comments Laurentiu Tudor (4): pci: layerscape: move per-pci device fdt fixup in a function pci: layerscape: move pci node search in a common function pci: add a few ARI and SRIOV related defines pci: layerscape: add a way of specifying additional iommu mappings .../fsl-layerscape/doc/README.pci_iommu_extra | 67 +++ drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 450 +++--- include/pci.h | 14 + 4 files changed, 482 insertions(+), 61 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra -- 2.17.1
[PATCH v2 4/4] pci: layerscape: add a way of specifying additional iommu mappings
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus The env var consists of a list of , pairs for a certain pci bus identified by its controller's base register address, as defined in the "reg" property in the device tree. pci_iommu_extra = pci@, pci@,... where: is the register base address of the pci controller for which the subsequent , pairs apply identifies to which B.D.F the action applies to can be: - "vfs=" to specify that for the PCI EP identified previously by the to include mappings for of VFs. The variant "noari_vfs=" is available to disable taking ARI into account. - "hp" to specify that on this there will be a hot-plugged device so it needs a mapping The device tree property must be placed under the correct pci controller node and only the bdf and action pairs need to be specified, like this: pci-iommu-extra = "..."; Note: the env var takes priority over the device tree property. For example, given this configuration on bus 6: => pci 6 Scanning PCI devices on bus 6 BusDevFun VendorId DeviceId Device Class Sub-Class _ 06.00.00 0x8086 0x1572 Network controller 0x00 06.00.01 0x8086 0x1572 Network controller 0x00 The following u-boot env var will create iommu mappings for 3 VFs for each PF: => setenv pci_iommu_extra pci@0x380,6.0.0,vfs=3,6.0.1,vfs=3 For the device tree case, this would be specified like this: pci-iommu-extra = "6.0.0,vfs=3,6.0.1,vfs=3"; To add an iommu mapping for a hot-plugged device, please see following example: => setenv pci_iommu_extra pci@0x380,2.16.0,hp For the device tree case, this would be specified like this: pci-iommu-extra = "2.16.0,hp"; Signed-off-by: Laurentiu Tudor --- .../fsl-layerscape/doc/README.pci_iommu_extra | 66 drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 327 ++ 3 files changed, 405 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra new file mode 100644 index 00..10217ea046 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra @@ -0,0 +1,66 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Specifying extra IOMMU mappings for PCI controllers + +This feature can be enabled through the PCI_IOMMU_EXTRA_MAPPINGS Kconfig option. + +The "pci_iommu_extra" env var or "pci-iommu-extra" device tree property (to be +used for example in more static scenarios such as hardwired PCI endpoints that +get initialized later in the system setup) allows two things: + - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number + of VFs that will ever be created for it + - for hot-plug case, specify the B.D.F with which the device will show up on + the PCI bus + +The env var consists of a list of , pairs for a certain pci bus +identified by its controller's base register address, as defined in the "reg" +property in the device tree. + +pci_iommu_extra = pci@, + pci@,... + +where: + is the register base address of the pci controller for which the +subsequent , pairs apply + identifies to which B.D.F the action applies to can be: +- "vfs=" to specify that for the PCI EP identified previously by + the to include mappings for of VFs. + The variant "noari_vfs=" is available to disable taking ARI into + account. +- "hp" to specify that on this there will be a hot-plugged device so + it needs a mapping +The device tree property must be placed under the correct pci controller node +and only the bdf and action pairs need to be specified, like this: + +pci-iommu-extra = "..."; + +Note: the env var has priority over the device tree property. + +For example, given this configuration on bus 6: + +=> pci 6 +Scanning PCI devices on bus 6 +BusDevFun VendorId DeviceId Device Class Sub-Class +__
[PATCH v2 3/4] pci: add a few ARI and SRIOV related defines
From: Laurentiu Tudor Add a few defines related to ARI and SRIOV configuration. Signed-off-by: Laurentiu Tudor --- include/pci.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/pci.h b/include/pci.h index 281f353916..c76b73497d 100644 --- a/include/pci.h +++ b/include/pci.h @@ -492,8 +492,19 @@ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN0xfff8 /* Physical Slot Number */ +#define PCI_EXP_DEVCAP236 /* Device Capabilities 2 */ +#define PCI_EXP_DEVCAP2_ARI 0x0020 /* ARI Forwarding Supported */ #define PCI_EXP_LNKCTL248 /* Link Control 2 */ +/* PCI SR-IOV Configuration */ +#define PCI_SRIOV_CTRL 8 /* SR-IOV Control Register */ +#define PCI_SRIOV_CTRL_VF_EN 0x0001 /* VF Enable */ +#define PCI_SRIOV_CTRL_ARI0x0010 /* ARI Capable Hierarchy */ +#define PCI_SRIOV_TOTAL_VFS14 /* TotalVFs */ +#define PCI_SRIOV_NUM_VFS 16 /* NumVFs */ +#define PCI_SRIOV_VF_OFFSET20 /* First VF Offset */ +#define PCI_SRIOV_VF_STRIDE22 /* VF Stride */ + /* Include the ID list */ #include -- 2.17.1
[PATCH v2 0/4] Support for specifying extra IOMMU mappings for PCI
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add support for specifying extra IOMMU mappings for PCI controllers through a special env var called "pci_iommu_extra" or through a device tree property named "pci-iommu-extra" placed in the node describing the PCI controller. More detailed information can be found in the final patch. Changes in v2: - add ARI support and use it by default - option to disable ARI - fixes in BDF calculation - reorganized code a bit - added more comments Laurentiu Tudor (4): pci: layerscape: move per-pci device fdt fixup in a function pci: layerscape: move pci node search in a common function pci: add a few ARI and SRIOV related defines pci: layerscape: add a way of specifying additional iommu mappings .../fsl-layerscape/doc/README.pci_iommu_extra | 66 +++ drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 466 +++--- include/pci.h | 11 + 4 files changed, 476 insertions(+), 79 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra -- 2.17.1
[PATCH v2 2/4] pci: layerscape: move pci node search in a common function
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 87 ++---
1 file changed, 30 insertions(+), 57 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 1e812b2e6d..75adf09c52 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -53,19 +53,8 @@ static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie,
int index, u32 devid,
lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
}
-/*
- * An msi-map is a property to be added to the pci controller
- * node. It is a table, where each entry consists of 4 fields
- * e.g.:
- *
- * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
- * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
- */
-static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
- u32 devid, u32 streamid)
+static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie *pcie)
{
- u32 *prop;
- u32 phandle;
int nodeoffset;
uint svr;
char *compat = NULL;
@@ -75,7 +64,7 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct
ls_pcie *pcie,
pcie->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
+ svr = SVR_SOC_VER(get_svr());
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
svr == SVR_LS2081A || svr == SVR_LS2041A)
@@ -86,10 +75,30 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob,
struct ls_pcie *pcie,
nodeoffset = fdt_node_offset_by_compat_reg(blob,
compat, pcie->dbi_res.start);
#endif
- if (nodeoffset < 0)
- return;
}
+ return nodeoffset;
+}
+
+/*
+ * An msi-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
+{
+ u32 *prop;
+ u32 phandle;
+ int nodeoffset;
+
+ nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie);
+ if (nodeoffset < 0)
+ return;
+
/* get phandle to MSI controller */
prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
if (prop == NULL) {
@@ -121,29 +130,10 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
struct ls_pcie *pcie,
u32 iommu_map[4];
int nodeoffset;
int lenp;
- uint svr;
- char *compat = NULL;
- /* find pci controller node */
- nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
- if (nodeoffset < 0) {
-#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A)
- compat = "fsl,ls2088a-pcie";
- else
- compat = CONFIG_FSL_PCIE_COMPAT;
-
- if (compat)
- nodeoffset = fdt_node_offset_by_compat_reg(blob,
- compat, pcie->dbi_res.start);
-#endif
- if (nodeoffset < 0)
- return;
- }
+ nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie);
+ if (nodeoffset < 0)
+ return;
/* get phandle to iommu controller */
prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", );
@@ -224,27 +214,10 @@ static void fdt_fixup_pcie_ls(void *blob)
static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
{
int off;
- uint svr;
- char *compat = NULL;
- off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
- if (off < 0) {
-#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
-
[PATCH v2 1/4] pci: layerscape: move per-pci device fdt fixup in a function
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 58 -
1 file changed, 33 insertions(+), 25 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 76e680481a..1e812b2e6d 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -167,12 +167,40 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
struct ls_pcie *pcie,
}
}
+static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf,
+ struct ls_pcie *pcie)
+{
+ int streamid, index;
+
+ streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
+ if (streamid < 0) {
+ printf("ERROR: out of stream ids for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+ pcie->stream_id_cur++;
+
+ index = ls_pcie_next_lut_index(pcie);
+ if (index < 0) {
+ printf("ERROR: out of LUT indexes for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_lut_set_mapping(pcie, index, bdf >> 8, streamid);
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8, streamid);
+ /* update iommu-map in device tree */
+ fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8, streamid);
+
+ return 0;
+}
+
static void fdt_fixup_pcie_ls(void *blob)
{
struct udevice *dev, *bus;
struct ls_pcie *pcie;
- int streamid;
- int index;
pci_dev_t bdf;
/* Scan all known buses */
@@ -183,31 +211,11 @@ static void fdt_fixup_pcie_ls(void *blob)
bus = bus->parent;
pcie = dev_get_priv(bus);
- streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
- if (streamid < 0) {
- debug("ERROR: no stream ids free\n");
- continue;
- } else {
- pcie->stream_id_cur++;
- }
-
- index = ls_pcie_next_lut_index(pcie);
- if (index < 0) {
- debug("ERROR: no LUT indexes free\n");
- continue;
- }
-
/* the DT fixup must be relative to the hose first_busno */
bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
- /* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
- streamid);
- /* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
- streamid);
- /* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
- streamid);
+
+ if (fdt_fixup_pcie_device_ls(blob, bdf, pcie) < 0)
+ break;
}
pcie_board_fix_fdt(blob);
}
--
2.17.1
[PATCH 1/3] pci: layerscape: move per-pci device fdt fixup in a function
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 58 -
1 file changed, 33 insertions(+), 25 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 25a3c3870c..12ee5e3f20 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -167,12 +167,40 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
struct ls_pcie *pcie,
}
}
+static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf,
+ struct ls_pcie *pcie)
+{
+ int streamid, index;
+
+ streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
+ if (streamid < 0) {
+ printf("ERROR: out of stream ids for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+ pcie->stream_id_cur++;
+
+ index = ls_pcie_next_lut_index(pcie);
+ if (index < 0) {
+ printf("ERROR: out of LUT indexes for BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return -ENOENT;
+ }
+
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_lut_set_mapping(pcie, index, bdf >> 8, streamid);
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8, streamid);
+ /* update iommu-map in device tree */
+ fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8, streamid);
+
+ return 0;
+}
+
static void fdt_fixup_pcie_ls(void *blob)
{
struct udevice *dev, *bus;
struct ls_pcie *pcie;
- int streamid;
- int index;
pci_dev_t bdf;
/* Scan all known buses */
@@ -183,31 +211,11 @@ static void fdt_fixup_pcie_ls(void *blob)
bus = bus->parent;
pcie = dev_get_priv(bus);
- streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
- if (streamid < 0) {
- debug("ERROR: no stream ids free\n");
- continue;
- } else {
- pcie->stream_id_cur++;
- }
-
- index = ls_pcie_next_lut_index(pcie);
- if (index < 0) {
- debug("ERROR: no LUT indexes free\n");
- continue;
- }
-
/* the DT fixup must be relative to the hose first_busno */
bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
- /* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
- streamid);
- /* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
- streamid);
- /* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
- streamid);
+
+ if (fdt_fixup_pcie_device_ls(blob, bdf, pcie) < 0)
+ break;
}
pcie_board_fix_fdt(blob);
}
--
2.17.1
[PATCH 3/3] pci: layerscape: add a way of specifying additional iommu mappings
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus The env var consists of a list of , pairs for a certain pci bus identified by its controller's base register address, as defined in the "reg" property in the device tree. pci_iommu_extra = pci@, pci@,... where: is the register base address of the pci controller for which the subsequent , pairs apply identifies to which B.D.F the action applies to can be: - "vfs=" to specify that for the PCI EP identified previously by the to include mappings for of VFs - "hp" to specify that on this there will be a hot-plugged device so it needs a mapping The device tree property must be placed under the correct pci controller node and only the bdf and action pairs need to be specified, like this: pci-iommu-extra = "..."; For example, given this configuration on bus 6: => pci 6 Scanning PCI devices on bus 6 BusDevFun VendorId DeviceId Device Class Sub-Class _ 06.00.00 0x8086 0x1572 Network controller 0x00 06.00.01 0x8086 0x1572 Network controller 0x00 The following u-boot env var will create iommu mappings for 3 VFs for each PF: => setenv pci_iommu_extra pci@0x380,6.0.0,vfs=3,6.0.1,vfs=3 For the device tree case, this would be specified like this: pci-iommu-extra = "6.0.0,vfs=3,6.0.1,vfs=3"; To add an iommu mapping for a hot-plugged device, please see following example: => setenv pci_iommu_extra pci@0x380,6.2.0,hp For the device tree case, this would be specified like this: pci-iommu-extra = "6.2.0,hp"; Signed-off-by: Laurentiu Tudor --- .../fsl-layerscape/doc/README.pci_iommu_extra | 68 +++ drivers/pci/Kconfig | 12 ++ drivers/pci/pcie_layerscape_fixup.c | 178 ++ 3 files changed, 258 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra new file mode 100644 index 00..cb1388796b --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra @@ -0,0 +1,68 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Specifying extra IOMMU mappings for PCI controllers + +This feature can be enabled through the PCI_IOMMU_EXTRA_MAPPINGS +Kconfig option. + +The "pci_iommu_extra" env var or "pci-iommu-extra" device tree +property (to be used for example in more static scenarios such +as hardwired PCI endpoints that get initialized later in the system +setup) allows two things: + - for a SRIOV capable PCI EP identified by its B.D.F specify + the maximum number of VFs that will ever be created for it + - for hot-plug case, specify the B.D.F with which the device + will show up on the PCI bus + +The env var consists of a list of , pairs for a certain +pci bus identified by its controller's base register address, as +defined in the "reg" property in the device tree. + +pci_iommu_extra = pci@, + pci@,... + +where: + is the register base address of the pci controller for which +the subsequent , pairs apply + identifies to which B.D.F the action applies to + can be: +- "vfs=" to specify that for the PCI EP identified + previously by the to include mappings for of VFs +- "hp" to specify that on this there will be a hot-plugged + device so it needs a mapping +The device tree property must be placed under the correct pci +controller node and only the bdf and action pairs need to be specified, +like this: + +pci-iommu-extra = "..."; + +For example, given this configuration on bus 6: + +=> pci 6 +Scanning PCI devices on bus 6 +BusDevFun VendorId DeviceId Device Class Sub-Class +_ +06.00.00 0x8086 0x1572 Network controller 0x00 +06.00.01 0x8086 0x1572 Network controller 0x00 + +The following u-boot env var will create iommu mappings for 3 VFs +for each PF: + +=> setenv pci_iommu_extra pci@0x380,6.0.0,vfs=3,6.0.1,vfs=3 + +For the device tree case, this would
[PATCH 0/3] Support for specifying extra IOMMU mappings for PCI
From: Laurentiu Tudor In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add support for specifying extra IOMMU mappings for PCI controllers through a special env var called "pci_iommu_extra" or through a device tree property named "pci-iommu-extra" placed in the node describing the PCI controller. More detailed information can be found in the final patch. Laurentiu Tudor (3): pci: layerscape: move per-pci device fdt fixup in a function pci: layerscape: move pci node search in a common function pci: layerscape: add a way of specifying additional iommu mappings .../fsl-layerscape/doc/README.pci_iommu_extra | 68 drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 317 +- 3 files changed, 318 insertions(+), 79 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra -- 2.17.1
[PATCH 2/3] pci: layerscape: move pci node search in a common function
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 87 ++---
1 file changed, 30 insertions(+), 57 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 12ee5e3f20..64738453e1 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -53,19 +53,8 @@ static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie,
int index, u32 devid,
lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
}
-/*
- * An msi-map is a property to be added to the pci controller
- * node. It is a table, where each entry consists of 4 fields
- * e.g.:
- *
- * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
- * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
- */
-static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
- u32 devid, u32 streamid)
+static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie *pcie)
{
- u32 *prop;
- u32 phandle;
int nodeoffset;
uint svr;
char *compat = NULL;
@@ -75,7 +64,7 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct
ls_pcie *pcie,
pcie->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
+ svr = SVR_SOC_VER(get_svr());
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
svr == SVR_LS2081A || svr == SVR_LS2041A)
@@ -86,10 +75,30 @@ static void fdt_pcie_set_msi_map_entry_ls(void *blob,
struct ls_pcie *pcie,
nodeoffset = fdt_node_offset_by_compat_reg(blob,
compat, pcie->dbi_res.start);
#endif
- if (nodeoffset < 0)
- return;
}
+ return nodeoffset;
+}
+
+/*
+ * An msi-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
+{
+ u32 *prop;
+ u32 phandle;
+ int nodeoffset;
+
+ nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie);
+ if (nodeoffset < 0)
+ return;
+
/* get phandle to MSI controller */
prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
if (prop == NULL) {
@@ -121,29 +130,10 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
struct ls_pcie *pcie,
u32 iommu_map[4];
int nodeoffset;
int lenp;
- uint svr;
- char *compat = NULL;
- /* find pci controller node */
- nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
- if (nodeoffset < 0) {
-#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A)
- compat = "fsl,ls2088a-pcie";
- else
- compat = CONFIG_FSL_PCIE_COMPAT;
-
- if (compat)
- nodeoffset = fdt_node_offset_by_compat_reg(blob,
- compat, pcie->dbi_res.start);
-#endif
- if (nodeoffset < 0)
- return;
- }
+ nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie);
+ if (nodeoffset < 0)
+ return;
/* get phandle to iommu controller */
prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", );
@@ -224,27 +214,10 @@ static void fdt_fixup_pcie_ls(void *blob)
static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
{
int off;
- uint svr;
- char *compat = NULL;
- off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
- if (off < 0) {
-#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
-
[PATCH] drivers: net: fsl-mc: fixup msi-map property
Similarly to iommu-map, the msi-map property must also be fixed up
in the device tree, in order for the icid -> streamid translation
be possible in the MSI case as well.
Signed-off-by: Laurentiu Tudor
---
drivers/net/fsl-mc/mc.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index fee372968a..9c4ba7dbda 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -317,7 +317,7 @@ void fdt_fixup_mc_ddr(u64 *base, u64 *size)
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
{
u32 *prop;
- u32 iommu_map[4];
+ u32 iommu_map[4], phandle;
int offset;
int lenp;
@@ -346,6 +346,21 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
fdt_setprop_inplace(blob, offset, "iommu-map",
iommu_map, sizeof(iommu_map));
+
+ /* get phandle to MSI controller */
+ prop = (u32 *)fdt_getprop(blob, offset, "msi-parent", 0);
+ if (!prop) {
+ debug("\n%s: ERROR: missing msi-parent\n", __func__);
+ return;
+ }
+ phandle = fdt32_to_cpu(*prop);
+
+ /* also set msi-map property */
+ fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
+ fdt_appendprop_u32(blob, offset, "msi-map", phandle);
+ fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
+ fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_END -
+ FSL_DPAA2_STREAM_ID_START + 1);
}
static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
--
2.17.1
[PATCH v2 0/2] fdtdec: support multiple phandles in memory carveout
Content-Type: text/plain; charset="us-ascii" fdtdec_set_carveout() is limited to only one phandle. Fix this limitation by adding support for multiple phandles and also add an unit test for the function. Changes in v2: - added a unit test for the function (Simon) - added a cover letter Laurentiu Tudor (2): fdtdec: support multiple phandles in memory carveout test: fdtdec: test fdtdec_set_carveout() lib/fdtdec.c | 36 + test/dm/Makefile | 1 + test/dm/fdtdec.c | 60 3 files changed, 87 insertions(+), 10 deletions(-) create mode 100644 test/dm/fdtdec.c -- 2.17.1
[PATCH v2 1/2] fdtdec: support multiple phandles in memory carveout
fdtdec_set_carveout() is limited to only one phandle. Fix this
limitation by adding support for multiple phandles.
Signed-off-by: Laurentiu Tudor
---
lib/fdtdec.c | 36 ++--
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index eb11fc898e..9ecfa2a2d7 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1433,14 +1433,9 @@ int fdtdec_set_carveout(void *blob, const char *node,
const char *prop_name,
const struct fdt_memory *carveout)
{
uint32_t phandle;
- int err, offset;
+ int err, offset, len;
fdt32_t value;
-
- /* XXX implement support for multiple phandles */
- if (index > 0) {
- debug("invalid index %u\n", index);
- return -FDT_ERR_BADOFFSET;
- }
+ void *prop;
err = fdtdec_add_reserved_memory(blob, name, carveout, );
if (err < 0) {
@@ -1456,10 +1451,31 @@ int fdtdec_set_carveout(void *blob, const char *node,
const char *prop_name,
value = cpu_to_fdt32(phandle);
- err = fdt_setprop(blob, offset, prop_name, , sizeof(value));
+ if (!fdt_getprop(blob, offset, prop_name, )) {
+ if (len == -FDT_ERR_NOTFOUND)
+ len = 0;
+ else
+ return len;
+ }
+
+ if ((index + 1) * sizeof(value) > len) {
+ err = fdt_setprop_placeholder(blob, offset, prop_name,
+ (index + 1) * sizeof(value),
+ );
+ if (err < 0) {
+ debug("failed to resize reserved memory property: %s\n",
+ fdt_strerror(err));
+ return err;
+ }
+ }
+
+ err = fdt_setprop_inplace_namelen_partial(blob, offset, prop_name,
+ strlen(prop_name),
+ index * sizeof(value),
+ , sizeof(value));
if (err < 0) {
- debug("failed to set %s property for node %s: %d\n", prop_name,
- node, err);
+ debug("failed to update %s property for node %s: %s\n",
+ prop_name, node, fdt_strerror(err));
return err;
}
--
2.17.1
[PATCH v2 2/2] test: fdtdec: test fdtdec_set_carveout()
Add a new test for fdtdec_set_carveout().
Signed-off-by: Laurentiu Tudor
---
test/dm/Makefile | 1 +
test/dm/fdtdec.c | 60
2 files changed, 61 insertions(+)
create mode 100644 test/dm/fdtdec.c
diff --git a/test/dm/Makefile b/test/dm/Makefile
index dd1ceff86c..53caa29fbb 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_LED) += led.o
obj-$(CONFIG_DM_MAILBOX) += mailbox.o
obj-$(CONFIG_DM_MMC) += mmc.o
obj-y += ofnode.o
+obj-y += fdtdec.o
obj-$(CONFIG_OSD) += osd.o
obj-$(CONFIG_DM_VIDEO) += panel.o
obj-$(CONFIG_DM_PCI) += pci.o
diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
new file mode 100644
index 00..6636af48d7
--- /dev/null
+++ b/test/dm/fdtdec.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static int dm_test_fdtdec_set_carveout(struct unit_test_state *uts)
+{
+ struct fdt_memory resv;
+ void *blob;
+ const fdt32_t *prop;
+ int blob_sz, len, offset;
+
+ blob_sz = fdt_totalsize(gd->fdt_blob) + 4096;
+ blob = malloc(blob_sz);
+ ut_assertnonnull(blob);
+
+ /* Make a writtable copy of the fdt blob */
+ ut_assertok(fdt_open_into(gd->fdt_blob, blob, blob_sz));
+
+ resv.start = 0x1000;
+ resv.end = 0x2000;
+ ut_assertok(fdtdec_set_carveout(blob, "/a-test",
+ "memory-region", 2, "test_resv1",
+ ));
+
+ resv.start = 0x1;
+ resv.end = 0x2;
+ ut_assertok(fdtdec_set_carveout(blob, "/a-test",
+ "memory-region", 1, "test_resv2",
+ ));
+
+ resv.start = 0x10;
+ resv.end = 0x20;
+ ut_assertok(fdtdec_set_carveout(blob, "/a-test",
+ "memory-region", 0, "test_resv3",
+ ));
+
+ offset = fdt_path_offset(blob, "/a-test");
+ ut_assert(offset > 0);
+ prop = fdt_getprop(blob, offset, "memory-region", );
+ ut_assertnonnull(prop);
+
+ ut_asserteq(len, 12);
+ ut_assert(fdt_node_offset_by_phandle(blob, fdt32_to_cpu(prop[0])) > 0);
+ ut_assert(fdt_node_offset_by_phandle(blob, fdt32_to_cpu(prop[1])) > 0);
+ ut_assert(fdt_node_offset_by_phandle(blob, fdt32_to_cpu(prop[2])) > 0);
+
+ free(blob);
+
+ return 0;
+}
+DM_TEST(dm_test_fdtdec_set_carveout,
+ DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT | DM_TESTF_FLAT_TREE);
+
--
2.17.1
Re: [PATCH] fdtdec: support multiple phandles in memory carveout
Hi Simon, On 4/2/2020 5:34 AM, Simon Glass wrote: > Hi, > > On Tue, 31 Mar 2020 at 07:16, Laurentiu Tudor wrote: >> >> fdtdec_set_carveout() is limited to only one phandle. Fix this >> limitation by adding support for multiple phandles. >> >> Signed-off-by: Laurentiu Tudor >> --- >> lib/fdtdec.c | 36 ++-- >> 1 file changed, 26 insertions(+), 10 deletions(-) >> > > Please can you add a test for this function? You could put it in > test/dm/fdtdec.c - see ofnode.c for an example. > Sure, I'll look into it. Thanks. --- Best regards, Laurentiu
[PATCH] fdtdec: support multiple phandles in memory carveout
fdtdec_set_carveout() is limited to only one phandle. Fix this
limitation by adding support for multiple phandles.
Signed-off-by: Laurentiu Tudor
---
lib/fdtdec.c | 36 ++--
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index eb11fc898e..9ecfa2a2d7 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1433,14 +1433,9 @@ int fdtdec_set_carveout(void *blob, const char *node,
const char *prop_name,
const struct fdt_memory *carveout)
{
uint32_t phandle;
- int err, offset;
+ int err, offset, len;
fdt32_t value;
-
- /* XXX implement support for multiple phandles */
- if (index > 0) {
- debug("invalid index %u\n", index);
- return -FDT_ERR_BADOFFSET;
- }
+ void *prop;
err = fdtdec_add_reserved_memory(blob, name, carveout, );
if (err < 0) {
@@ -1456,10 +1451,31 @@ int fdtdec_set_carveout(void *blob, const char *node,
const char *prop_name,
value = cpu_to_fdt32(phandle);
- err = fdt_setprop(blob, offset, prop_name, , sizeof(value));
+ if (!fdt_getprop(blob, offset, prop_name, )) {
+ if (len == -FDT_ERR_NOTFOUND)
+ len = 0;
+ else
+ return len;
+ }
+
+ if ((index + 1) * sizeof(value) > len) {
+ err = fdt_setprop_placeholder(blob, offset, prop_name,
+ (index + 1) * sizeof(value),
+ );
+ if (err < 0) {
+ debug("failed to resize reserved memory property: %s\n",
+ fdt_strerror(err));
+ return err;
+ }
+ }
+
+ err = fdt_setprop_inplace_namelen_partial(blob, offset, prop_name,
+ strlen(prop_name),
+ index * sizeof(value),
+ , sizeof(value));
if (err < 0) {
- debug("failed to set %s property for node %s: %d\n", prop_name,
- node, err);
+ debug("failed to update %s property for node %s: %s\n",
+ prop_name, node, fdt_strerror(err));
return err;
}
--
2.17.1
Re: [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines
Hi Priyanka,
On 18.10.2019 12:01, Laurentiu Tudor wrote:
> From: Laurentiu Tudor
>
> These macros should only be used when CONFIG_FSL_CAAM is present.
>
> Signed-off-by: Laurentiu Tudor
> Reviewed-by: Horia Geant??
Looks like our mail server messed Horia's name here. Do you think you
could fix by hand when you'll pick up the patch?
---
Thanks & Best Regards, Laurentiu
> ---
> Changes in v2:
> - added Reviewed-by tag
>
> arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
> arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> index d9d125e8ba..9462298fbf 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> @@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
> SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
> SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
> SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
> +#ifdef CONFIG_FSL_CAAM
> SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
> @@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = {
> SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
> +#endif
> };
>
> int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
> index 49e27553b1..23743ae10c 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
> @@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = {
> SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
> SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
> SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
> +#ifdef CONFIG_FSL_CAAM
> SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
> @@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = {
> SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
> +#endif
> };
>
> int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
>
___
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U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 5/6] armv8: lx2160a: add icid setup for platform devices
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geant??
---
Changes in v2:
- added Reviewed-by tag
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
.../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +-
.../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +
board/freescale/lx2160a/lx2160a.c | 2 +
include/fsl_sec.h | 3 +-
7 files changed, 58 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index f00ef817b1..e398aecd12 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -24,6 +24,7 @@ endif
ifneq ($(CONFIG_ARCH_LX2160A),)
obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
+obj-y += icid.o lx2160_ids.o
endif
ifneq ($(CONFIG_ARCH_LS2080A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
new file mode 100644
index 00..3a0ed1fa55
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+struct icid_id_table icid_tbl[] = {
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+ SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID),
+ SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID),
+ SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID),
+ SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 924f5f3fe8..4dea8361fc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void)
#endif
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
- defined(CONFIG_ARCH_LS2080A)
+ defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
set_icids();
#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 0e4bf331fd..d46477d96e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -447,7 +447,9 @@ struct ccsr_gur {
u8 res_538[0x550 - 0x538]; /* add more registers when needed */
u32 sata1_amqr;
u32 sata2_amqr;
- u8 res_558[0x570-0x558]; /* add more registers when needed */
+ u32 sata3_amqr;
+ u32 sata4_amqr;
+ u8 res_560[0x570 - 0x560]; /* add more registers when needed */
u32 misc1_amqr;
u8 res_574[0x590-0x574]; /* add more registers when needed */
u32 spare1_amqr;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 93bdcc4caa..0b36416ad3 100644
--- a/arch/arm/include/asm/
[U-Boot] [PATCH v2 6/6] armv8: ls1028a: add erratum A-050382 workaround
From: Laurentiu Tudor Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR register in DCFG is not correctly forwarded to the SMMU. The workaround consists in programming the eDMA ICID in the eDMA_AMQR register in DCFG to 40. Signed-off-by: Laurentiu Tudor --- Changes in v2: - reworded commit message and comment (Priyanka) arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 24c606a232..046dcf539e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,6 +45,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A050382 imply PANIC_HANG config ARCH_LS1043A @@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool +config SYS_FSL_ERRATUM_A050382 + bool config SYS_FSL_HAS_RGMII bool diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 0b36416ad3..94ea99a349 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -105,7 +105,22 @@ #define FSL_SEC_JR4_STREAM_ID 68 #define FSL_SDMMC2_STREAM_ID 69 + +/* + * Erratum A-050382 workaround + * + * Description: + * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not + * correctly forwarded to the SMMU. + * Workaround: + * Program eDMA ICID in the eDMA_AMQR register in DCFG to 40. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A050382 +#define FSL_EDMA_STREAM_ID 40 +#else #define FSL_EDMA_STREAM_ID 70 +#endif + #define FSL_GPU_STREAM_ID 71 #define FSL_DISPLAY_STREAM_ID 72 #define FSL_SATA3_STREAM_ID73 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses
From: Laurentiu Tudor LX2160A chips have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor --- Changes in v2: - explicitly mention the chip on which these are needed (Priyanka) arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 4f050470dd..0e4bf331fd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -87,6 +87,8 @@ /* SATA */ #define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR + 0x0220) #define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR + 0x0221) +#define AHCI_BASE_ADDR3(CONFIG_SYS_IMMR + 0x0222) +#define AHCI_BASE_ADDR4(CONFIG_SYS_IMMR + 0x0223) /* QDMA */ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x0738) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled
From: Laurentiu Tudor If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this compilation error happens: arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by wrapping with CONFIG_IS_ENABLED(). Signed-off-by: Laurentiu Tudor --- Changes in v2: - use CONFIG_IS_ENABLED() (Horia) arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 37e2fe4e66..3c06a55cb8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -166,7 +166,7 @@ extern int fman_icid_tbl_sz; #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ - (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ + (CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \ (FSL_SEC_JR##jr_num##_OFFSET == \ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ ? NULL \ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/6] armv8: ls2088a: add icid setup for platform devices
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
---
Changes in v2:
- setup ICIDs for all 6 DECOs not only 4 (Horia)
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls2088_ids.c | 35 +++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +-
board/freescale/ls2080aqds/ls2080aqds.c | 3 ++
board/freescale/ls2080ardb/ls2080ardb.c | 3 ++
5 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index efecbc07e7..f00ef817b1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,6 +28,7 @@ endif
ifneq ($(CONFIG_ARCH_LS2080A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
+obj-y += icid.o ls2088_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1043A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
new file mode 100644
index 00..e6403b7952
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+struct icid_id_table icid_tbl[] = {
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_SATA1_STREAM_ID),
+ SET_SATA_ICID(2, "fsl,ls2080a-ahci", FSL_SATA2_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3fd34e3a43..924f5f3fe8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -341,7 +341,8 @@ void fsl_lsch3_early_init_f(void)
bypass_smmu();
#endif
-#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
+#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
+ defined(CONFIG_ARCH_LS2080A)
set_icids();
#endif
}
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index 91c80353ed..25e80c8ac6 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include "../common/qixis.h"
@@ -358,6 +359,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
+
return 0;
}
#endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index e20267f27c..6a1b8e3f53 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
@@ -478,6 +479,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
+
return 0;
}
#endif
--
2.17.1
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[U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines
From: Laurentiu Tudor
These macros should only be used when CONFIG_FSL_CAAM is present.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geant??
---
Changes in v2:
- added Reviewed-by tag
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
index d9d125e8ba..9462298fbf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
@@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
index 49e27553b1..23743ae10c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
@@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = {
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
--
2.17.1
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Re: [U-Boot] [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices
On 18.10.2019 09:20, Priyanka Jain wrote:
>
>
>> -Original Message-
>> From: u-boot-boun...@linux.nxdi.nxp.com > boun...@linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor
>> Sent: Thursday, October 17, 2019 2:52 PM
>> To: u-boot@lists.denx.de; Prabhakar X
>> Subject: [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform
>> devices
>>
>> From: Laurentiu Tudor
>>
>> Add ICID setup for the platform devices contained on this chip: usb, sata,
>> sdhc, sec.
>>
>> Signed-off-by: Laurentiu Tudor
>> ---
>> arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
>> .../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++
>> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
>> .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +-
>> .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +
>> board/freescale/lx2160a/lx2160a.c | 2 +
>> include/fsl_sec.h | 3 +-
>> 7 files changed, 58 insertions(+), 4 deletions(-) create mode 100644
>> arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> index f00ef817b1..e398aecd12 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> @@ -24,6 +24,7 @@ endif
>>
>> ifneq ($(CONFIG_ARCH_LX2160A),)
>> obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
>> +obj-y += icid.o lx2160_ids.o
>> endif
>>
>> ifneq ($(CONFIG_ARCH_LS2080A),)
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
>> new file mode 100644
>> index 00..3a0ed1fa55
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
>> @@ -0,0 +1,48 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2019 NXP
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
>> +SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
>> +SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID),
>> +SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID),
>> +SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID),
>> +SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), #ifdef
>> +CONFIG_FSL_CAAM
>> +SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), #endif };
>> +
>> +int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> index 924f5f3fe8..4dea8361fc 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> @@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void) #endif
>>
>> #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
>> -defined(CONFIG_ARCH_LS2080A)
>> +defined(CONFIG_ARCH_LS2080A) || defined(
Re: [U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled
On 18.10.2019 09:32, Horia Geanta wrote: > On 10/17/2019 12:21 PM, Laurentiu Tudor wrote: >> From: Laurentiu Tudor >> >> If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this >> compilation error happens: >> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: >> 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) >> >> Fix it by adding an intermediate macro to handle the problem. >> >> Signed-off-by: Laurentiu Tudor >> --- >> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 8 +++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h >> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h >> index 37e2fe4e66..398bb4eb86 100644 >> --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h >> @@ -164,9 +164,15 @@ extern int fman_icid_tbl_sz; >> QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ >> QDMA_BASE_ADDR, QDMA_IS_LE) >> >> +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT >> +#define SEC_FW_SUPPORT CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT >> +#else >> +#define SEC_FW_SUPPORT 0 >> +#endif >> + >> #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ >> SET_ICID_ENTRY( \ >> -(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ >> +(SEC_FW_SUPPORT && \ >> (FSL_SEC_JR##jr_num##_OFFSET == \ >> SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ >> ? NULL \ >> > How about using CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) instead of > CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT? > That's pretty cool, didn't new about it. Sure I'll use it. --- Thanks & Best Regards, Laurentiu ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 6/6] armv8: ls1028a: erratum A050382 workaround
From: Laurentiu Tudor Description: The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not correctly forwarded to the SMMU. Workaround: Program eDMA ICID in the eDMA_AMQR register in DCFG to 0x28. Signed-off-by: Laurentiu Tudor --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 24c606a232..046dcf539e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,6 +45,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A050382 imply PANIC_HANG config ARCH_LS1043A @@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool +config SYS_FSL_ERRATUM_A050382 + bool config SYS_FSL_HAS_RGMII bool diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 0b36416ad3..4c9e1e72f0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -105,7 +105,22 @@ #define FSL_SEC_JR4_STREAM_ID 68 #define FSL_SDMMC2_STREAM_ID 69 + +/* + * Erratum A050382 workaround + * + * Description: + * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not + * correctly forwarded to the SMMU. + * Workaround: + * Program eDMA ICID in the eDMA_AMQR register in DCFG to 0x28. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A050382 +#define FSL_EDMA_STREAM_ID 40 +#else #define FSL_EDMA_STREAM_ID 70 +#endif + #define FSL_GPU_STREAM_ID 71 #define FSL_DISPLAY_STREAM_ID 72 #define FSL_SATA3_STREAM_ID73 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
.../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +-
.../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +
board/freescale/lx2160a/lx2160a.c | 2 +
include/fsl_sec.h | 3 +-
7 files changed, 58 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index f00ef817b1..e398aecd12 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -24,6 +24,7 @@ endif
ifneq ($(CONFIG_ARCH_LX2160A),)
obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
+obj-y += icid.o lx2160_ids.o
endif
ifneq ($(CONFIG_ARCH_LS2080A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
new file mode 100644
index 00..3a0ed1fa55
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+struct icid_id_table icid_tbl[] = {
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+ SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID),
+ SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID),
+ SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID),
+ SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 924f5f3fe8..4dea8361fc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void)
#endif
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
- defined(CONFIG_ARCH_LS2080A)
+ defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
set_icids();
#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 0e4bf331fd..f86835a33d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -447,7 +447,9 @@ struct ccsr_gur {
u8 res_538[0x550 - 0x538]; /* add more registers when needed */
u32 sata1_amqr;
u32 sata2_amqr;
- u8 res_558[0x570-0x558]; /* add more registers when needed */
+ u32 sata3_amqr;
+ u32 sata4_amqr;
+ u8 res_558[0x570 - 0x560]; /* add more registers when needed */
u32 misc1_amqr;
u8 res_574[0x590-0x574]; /* add more registers when needed */
u32 spare1_amqr;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 93bdcc4caa..0b36416ad3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-f
[U-Boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses
From: Laurentiu Tudor There are chips that have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 4f050470dd..0e4bf331fd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -87,6 +87,8 @@ /* SATA */ #define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR + 0x0220) #define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR + 0x0221) +#define AHCI_BASE_ADDR3(CONFIG_SYS_IMMR + 0x0222) +#define AHCI_BASE_ADDR4(CONFIG_SYS_IMMR + 0x0223) /* QDMA */ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x0738) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/6] armv8: ls2088a: add icid setup for platform devices
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls2088_ids.c | 33 +++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +-
board/freescale/ls2080aqds/ls2080aqds.c | 3 ++
board/freescale/ls2080ardb/ls2080ardb.c | 3 ++
5 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index efecbc07e7..f00ef817b1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,6 +28,7 @@ endif
ifneq ($(CONFIG_ARCH_LS2080A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
+obj-y += icid.o ls2088_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1043A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
new file mode 100644
index 00..9556e93de9
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+struct icid_id_table icid_tbl[] = {
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_SATA1_STREAM_ID),
+ SET_SATA_ICID(2, "fsl,ls2080a-ahci", FSL_SATA2_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3fd34e3a43..924f5f3fe8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -341,7 +341,8 @@ void fsl_lsch3_early_init_f(void)
bypass_smmu();
#endif
-#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
+#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
+ defined(CONFIG_ARCH_LS2080A)
set_icids();
#endif
}
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index 91c80353ed..25e80c8ac6 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include "../common/qixis.h"
@@ -358,6 +359,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
+
return 0;
}
#endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index e20267f27c..6a1b8e3f53 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
@@ -478,6 +479,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
+
return 0;
}
#endif
--
2.17.1
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[U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled
From: Laurentiu Tudor If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this compilation error happens: arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by adding an intermediate macro to handle the problem. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 37e2fe4e66..398bb4eb86 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -164,9 +164,15 @@ extern int fman_icid_tbl_sz; QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ QDMA_BASE_ADDR, QDMA_IS_LE) +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#define SEC_FW_SUPPORT CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#else +#define SEC_FW_SUPPORT 0 +#endif + #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ - (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ + (SEC_FW_SUPPORT && \ (FSL_SEC_JR##jr_num##_OFFSET == \ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ ? NULL \ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines
From: Laurentiu Tudor
These macros should only be used when CONFIG_FSL_CAAM is present.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
index d9d125e8ba..9462298fbf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
@@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
index 49e27553b1..23743ae10c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
@@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = {
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
--
2.17.1
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[U-Boot] [PATCH 3/5] armv8: fsl-layerscape: make icid setup endianness aware
From: Laurentiu Tudor
The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 5 ++-
.../asm/arch-fsl-layerscape/fsl_icid.h| 34 +--
2 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index b1a950e7f9..82c5a8b123 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -17,7 +17,10 @@ static void set_icid(struct icid_id_table *tbl, int size)
int i;
for (i = 0; i < size; i++)
- out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+ if (tbl[i].le)
+ out_le32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+ else
+ out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index f971af8d26..435ffb04fa 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -17,6 +17,7 @@ struct icid_id_table {
u32 reg;
phys_addr_t compat_addr;
phys_addr_t reg_addr;
+ bool le;
};
struct fman_icid_id_table {
@@ -30,18 +31,25 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph,
u32 *ids, int num_ids);
void set_icids(void);
void fdt_fixup_icid(void *blob);
-#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \
+#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
{ .compat = name, \
.id = idA, \
.reg = regA, \
.compat_addr = compataddr, \
.reg_addr = addr, \
+ .le = _le \
}
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define SCFG_IS_LE true
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define SCFG_IS_LE false
+#endif
+
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
- compataddr)
+ compataddr, SCFG_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
@@ -58,10 +66,10 @@ void fdt_fixup_icid(void *blob);
#define SET_QDMA_ICID(compat, streamid) \
SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
- QDMA_BASE_ADDR), \
+ QDMA_BASE_ADDR, false), \
SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
- QDMA_BASE_ADDR)
+ QDMA_BASE_ADDR, false)
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
@@ -81,22 +89,28 @@ void fdt_fixup_icid(void *blob);
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
CONFIG_SYS_FSL_QMAN_ADDR, \
- CONFIG_SYS_FSL_QMAN_ADDR)
+ CONFIG_SYS_FSL_QMAN_ADDR, false)
#define SET_BMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
offsetof(struct ccsr_bman, liodnr) + \
CONFIG_SYS_FSL_BMAN_ADDR, \
- CONFIG_SYS_FSL_BMAN_ADDR)
+ CONFIG_SYS_FSL_BMAN_ADDR, false)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
+#ifdef CONFIG_SYS_FSL_SEC_LE
+#define SEC_IS_LE true
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+#define SEC_IS_LE false
+#endif
+
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
- CONFIG_SYS_FSL_SEC_ADDR)
+ CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
SET_ICID_ENTRY( \
@@ -109,17 +123,17 @@ void fdt_fixup_icid(void *blob);
(((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
- FSL_SEC_JR##jr_num##_BASE_ADDR)
+ FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, 0)
+ CONFIG_SYS_FS
[U-Boot] [PATCH 4/5] armv8: ls1088a: add icid setup for platform devices
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 30 +++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++
.../asm/arch-fsl-layerscape/fsl_icid.h| 54 +++
.../asm/arch-fsl-layerscape/stream_id_lsch3.h | 6 +++
board/freescale/ls1088a/ls1088a.c | 4 ++
6 files changed, 89 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index a8d3cf91fc..aa88b93175 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -47,6 +47,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1088A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+obj-y += icid.o ls1088_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1028A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
new file mode 100644
index 00..956d6e78c8
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+struct icid_id_table icid_tbl[] = {
+ SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7414215208..467c34649f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -339,6 +339,10 @@ void fsl_lsch3_early_init_f(void)
if (fsl_check_boot_mode_secure() == 1)
bypass_smmu();
#endif
+
+#ifdef CONFIG_ARCH_LS1088A
+ set_icids();
+#endif
}
/* Get VDD in the unit mV from voltage ID */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 435ffb04fa..feb3304364 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -40,6 +40,14 @@ void fdt_fixup_icid(void *blob);
.le = _le \
}
+#ifdef CONFIG_SYS_FSL_SEC_LE
+#define SEC_IS_LE true
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+#define SEC_IS_LE false
+#endif
+
+#ifdef CONFIG_FSL_LSCH2
+
#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
#define SCFG_IS_LE true
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
@@ -100,11 +108,7 @@ void fdt_fixup_icid(void *blob);
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
-#ifdef CONFIG_SYS_FSL_SEC_LE
-#define SEC_IS_LE true
-#elif defined(CONFIG_SYS_FSL_SEC_BE)
-#define SEC_IS_LE false
-#endif
+#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
@@ -112,6 +116,38 @@ void fdt_fixup_icid(void *blob);
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+extern struct fman_icid_id_table fman_icid_tbl[];
+extern int fman_icid_tbl_sz;
+
+#else /* CONFIG_FSL_LSCH2 */
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define GUR_IS_LE true
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define GUR_IS_LE false
+#endif
+
+#define SET_GUR_ICID(compat, streamid, name, compataddr) \
+ SET_ICID_ENTRY(compat, streamid, streamid, \
+ offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+ compataddr, GUR_IS_LE)
+
+#define SET_USB_ICID(usb_num, compat, streamid) \
+ SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
+ CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+
+#define SET_SATA_ICID(sata_num, compat, streamid) \
+ SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
+
[U-Boot] [PATCH 2/5] armv8: fsl-layerscape: add base addresses for several devices
From: Laurentiu Tudor Add CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices. Signed-off-by: Laurentiu Tudor --- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 7cd5333ff4..84bed8d423 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -25,6 +25,8 @@ #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x0037) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x0114) +#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR +#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x0115) #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0124) #endif @@ -79,10 +81,23 @@ #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x1)) + 0x110) #define TZASC_REGION_ID_ACCESS_0(x)((TZASC1_BASE + (x * 0x1)) + 0x114) +/* EDMA */ +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c) + /* SATA */ #define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR + 0x0220) #define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR + 0x0221) +/* QDMA */ +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x0738) +#define QMAN_CQSIDR_REG0x20a80 + +/* DISPLAY */ +#define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e08) + +/* GPU */ +#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c) + /* SFP */ #define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0x00e80200) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/5] armv8: ls1028a: add icid setup for platform devices
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, edma, qdma, gpu, display and sec.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 33
.../arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
.../asm/arch-fsl-layerscape/fsl_icid.h| 38 +--
.../asm/arch-fsl-layerscape/immap_lsch3.h | 6 ++-
.../asm/arch-fsl-layerscape/stream_id_lsch3.h | 7 +++-
board/freescale/ls1028a/ls1028a.c | 3 ++
8 files changed, 76 insertions(+), 16 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index aa88b93175..efecbc07e7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -52,4 +52,5 @@ endif
ifneq ($(CONFIG_ARCH_LS1028A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
+obj-y += icid.o ls1028_ids.o
endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
new file mode 100644
index 00..d9d125e8ba
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+struct icid_id_table icid_tbl[] = {
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+ SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
+ SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
+ SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
+ SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
+ SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
index 956d6e78c8..49e27553b1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
@@ -9,7 +9,7 @@
#include
struct icid_id_table icid_tbl[] = {
- SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 467c34649f..eca21db289 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -340,7 +340,7 @@ void fsl_lsch3_early_init_f(void)
bypass_smmu();
#endif
-#ifdef CONFIG_ARCH_LS1088A
+#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
set_icids();
#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index feb3304364..37e2fe4e66 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -54,6 +54,8 @@ void fdt_fixup_icid(void *blob);
#define SCFG_IS_LE false
#endif
+#define QDMA_IS_LE false
+
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
@@ -71,14 +73,6 @@ void fdt_fixup_icid(void *blob);
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
CONFIG_SYS_FSL_ESDHC_ADDR)
-#define SET_QDMA_ICID(compat, streamid) \
- SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
- QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
- QDMA_BASE_ADDR, false), \
- SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
- QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
- QDMA_BASE_ADDR, false)
-
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610
[U-Boot] [PATCH 1/5] armv8: fsl-layerscape: add missing sec jr base address defines
From: Laurentiu Tudor Add defines for all the SEC job rings base addresses. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ee9b33becf..7cd5333ff4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -89,10 +89,18 @@ /* SEC */ #define CONFIG_SYS_FSL_SEC_OFFSET 0x0700ull #define CONFIG_SYS_FSL_JR0_OFFSET 0x0701ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x0702ull +#define FSL_SEC_JR2_OFFSET 0x0703ull +#define FSL_SEC_JR3_OFFSET 0x0704ull #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) #ifdef CONFIG_TFABOOT #ifdef CONFIG_NXP_LSCH3_2 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] armv8: ls1088a: add icid setup for platform devices
On 21.03.2019 17:10, Horia Geanta wrote:
> On 3/21/2019 2:42 PM, Tudor Laurentiu-B10716 wrote:
>> Hi Horia,
>>
>> On 21.03.2019 12:36, Horia Geanta wrote:
>>> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
#define SET_SEC_QI_ICID(streamid) \
- SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
+ SET_ICID_ENTRY("fsl,sec-v4.0", SEC_ICID_REG_VAL(streamid), \
>>> Is this a fix for LS104x? Then it should be a separate patch.
>>
>> Not really. I added an intermediate macro, SEC_ICID_REG_VAL(streamid)
>> that forms the correct register value starting from ICID, depending on
>> the chip version (the register layouts are different between the two).
>>
> This is the define
> #define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
>
> Thus the QI ICID for LS104x changes.
Ah, alright. Good point. I checked in the manuals and this unintended
change does indeed fix this register setup. I'm leaning towards
mentioning this collateral fix in the commit message.
+#else /* CONFIG_FSL_LSCH2 */
>>> [...]
+#define SEC_ICID_REG_VAL(streamid) ((streamid) << 24)
>>> ICID is in lower 6:0 bits, not in 31:24.
>>
>> That was also my initial impression but it didn't work (smmu global
>> faults with icid 0). Probably there's an ambiguity related to endianness
>> in the documentation.
>>
> Note that on DPAA 2.x both the core and device (CAAM) are little endian.
> Probably the problem is with the I/O accessors writing the CAAM registers.
>
> Instead of out_be32() use either sec_out32() (but this means splitting
> CAAM-specific code) or out_le32().
>
> CAAM endianness can be detected using CONFIG_SYS_FSL_SEC_LE /
> CONFIG_SYS_FSL_SEC_BE.
>
Thanks for the explanation. I think I can change the macros to take into
consideration the CONFIG_*s you pointed.
---
Best Regards, Laurentiu
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Re: [U-Boot] [PATCH 2/2] armv8: ls1088a: add icid setup for platform devices
Hi Horia,
On 21.03.2019 12:36, Horia Geanta wrote:
> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
>> +SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +};
> A single ICID is allocated to all SEC sub-blocks able to initiate
> transactions.
> I think at least the job rings should have different ICIDs, while the rest
> could
> share another ICID.
Actually let me take back my statement on the scarcity of the ICIDs. I
just noticed that in the allocation of the ICIDs we actually use just 64
[1] out of the total 128 available. I don't know why we do that, perhaps
it a legacy left over but anyway I've tested SEC with ICIDs > 63 and
tests passed.
In conclusion I'll update the ICID allocation for SEC in the following spin.
[1]
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h;h=e017d8b55895ba79328dd9281458e35a99b5900a;hb=HEAD#l99
---
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Re: [U-Boot] [PATCH 2/2] armv8: ls1088a: add icid setup for platform devices
Hi Horia,
On 21.03.2019 12:36, Horia Geanta wrote:
> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
>> +SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +};
> A single ICID is allocated to all SEC sub-blocks able to initiate
> transactions.
> I think at least the job rings should have different ICIDs, while the rest
> could
> share another ICID.
I agree here, problem is that on these chips ICIDs are scarce resource
because DPAA2 gets a big chunk of them. I'd suggest to leave them like
that and, if a user needs distinct, per JR ICIDs (s)he can easily tune them.
>> #define SET_SEC_QI_ICID(streamid) \
>> -SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
>> +SET_ICID_ENTRY("fsl,sec-v4.0", SEC_ICID_REG_VAL(streamid), \
> Is this a fix for LS104x? Then it should be a separate patch.
Not really. I added an intermediate macro, SEC_ICID_REG_VAL(streamid)
that forms the correct register value starting from ICID, depending on
the chip version (the register layouts are different between the two).
>> +#else /* CONFIG_FSL_LSCH2 */
> [...]
>> +#define SEC_ICID_REG_VAL(streamid) ((streamid) << 24)
> ICID is in lower 6:0 bits, not in 31:24.
That was also my initial impression but it didn't work (smmu global
faults with icid 0). Probably there's an ambiguity related to endianness
in the documentation.
>> +#endif /* !CONFIG_FSL_LSCH2 */
> Nitpick: comment for #endif should match #if condition, which is
> CONFIG_FSL_LSCH2.
>
Ok.
Thanks for the review!
---
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Re: [U-Boot] [PATCH 2/2] armv8: ls1088a: add icid setup for platform devices
Hi Horia,
On 21.03.2019 12:36, Horia Geanta wrote:
> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
>> +SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +};
> A single ICID is allocated to all SEC sub-blocks able to initiate
> transactions.
> I think at least the job rings should have different ICIDs, while the rest
> could
> share another ICID.
I agree here, problem is that on these chips ICIDs are scarce resource
because DPAA2 gets a big chunk of them. I'd suggest to leave them like
that and, if a user needs distinct, per JR ICIDs (s)he can easily tune them.
>> #define SET_SEC_QI_ICID(streamid) \
>> -SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
>> +SET_ICID_ENTRY("fsl,sec-v4.0", SEC_ICID_REG_VAL(streamid), \
> Is this a fix for LS104x? Then it should be a separate patch.
Not really. I added an intermediate macro, SEC_ICID_REG_VAL(streamid)
that forms the correct register value starting from ICID, depending on
the chip version (the register layouts are different between the two).
>> +#else /* CONFIG_FSL_LSCH2 */
> [...]
>> +#define SEC_ICID_REG_VAL(streamid) ((streamid) << 24)
> ICID is in lower 6:0 bits, not in 31:24.
That was also my initial impression but it didn't work (smmu global
faults with icid 0). Probably there's an ambiguity related to endianness
in the documentation.
>> +#endif /* !CONFIG_FSL_LSCH2 */
> Nitpick: comment for #endif should match #if condition, which is
> CONFIG_FSL_LSCH2.
>
Ok.
Thanks for the review!
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Re: [U-Boot] [PATCH v2 1/3] fsl_sec: fix register layout on Layerscape architectures
Hello,
Please disregards these 3 patches as I've resubmitted them by mistake.
I've updated their state in patchworks accordingly.
---
Best regards, Laurentiu
On 20.03.2019 16:31, laurentiu.tu...@nxp.com wrote:
> From: Laurentiu Tudor
>
> On Layerscape architectures the SEC memory map is 1MB and the
> register blocks contained in it are 64KB aligned, not 4KB as
> the ccsr_sec structure currently assumes. Fix the layout of
> the structure for these architectures.
>
> Signed-off-by: Laurentiu Tudor
> Reviewed-by: Horia Geanta
> Reviewed-by: Bharat Bhushan
> ---
> v2:
> - added Reviewed-by tags
>
> include/fsl_sec.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/include/fsl_sec.h b/include/fsl_sec.h
> index 16e3fcb5a1..be08a2b88b 100644
> --- a/include/fsl_sec.h
> +++ b/include/fsl_sec.h
> @@ -121,10 +121,18 @@ typedef struct ccsr_sec {
> u32 chanum_ls; /* CHA Number Register, LS */
> u32 secvid_ms; /* SEC Version ID Register, MS */
> u32 secvid_ls; /* SEC Version ID Register, LS */
> +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
> + u8 res9[0x6f020];
> +#else
> u8 res9[0x6020];
> +#endif
> u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
> u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
> +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
> + u8 res10[0x8ffd8];
> +#else
> u8 res10[0x8fd8];
> +#endif
> } ccsr_sec_t;
>
> #define SEC_CTPR_MS_AXI_LIODN 0x0800
>
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[U-Boot] [PATCH v2 2/3] armv8: fsl-layerscape: fix SEC QI ICID setup
From: Laurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geanta
Reviewed-by: Bharat Bhushan
---
v2:
- added Reviewed-by tags
arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +-
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 3 +--
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
index 0e8649427e..3bd993bebf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -43,7 +43,7 @@ struct icid_id_table icid_tbl[] = {
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
SET_QE_ICID(FSL_QE_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
- SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 2da9adab5b..abd847b5be 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -41,7 +41,7 @@ struct icid_id_table icid_tbl[] = {
SET_ETR_ICID(FSL_ETR_STREAM_ID),
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
- SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index f375fe7115..e7a8801262 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -93,8 +93,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
- (((streamid) << 16) | (streamid)), \
- offsetof(ccsr_sec_t, qilcr_ls) + \
+ 0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR)
--
2.17.1
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[U-Boot] [PATCH v2 3/3] armv8: fsl-layerscape: avoid DT fixup warning
From: Laurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geanta
Reviewed-by: Bharat Bhushan
---
v2:
- added Reviewed-by tags
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index e7a8801262..f971af8d26 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
struct icid_id_table {
const char *compat;
@@ -98,7 +99,13 @@ void fdt_fixup_icid(void *blob);
CONFIG_SYS_FSL_SEC_ADDR)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
- SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
+ SET_ICID_ENTRY( \
+ (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
+ (FSL_SEC_JR##jr_num##_OFFSET == \
+ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+ ? NULL \
+ : "fsl,sec-v4.0-job-ring"), \
+ streamid, \
(((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
--
2.17.1
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[U-Boot] [PATCH 2/2] armv8: ls1088a: add icid setup for platform devices
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different. Also, the initial static ICID
allocation left SEC out so update it by grabbing an ICID from the range
allocated to PCI and use it for SEC.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 31 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++
.../asm/arch-fsl-layerscape/fsl_icid.h| 43 ---
.../asm/arch-fsl-layerscape/stream_id_lsch3.h | 4 +-
board/freescale/ls1088a/ls1088a.c | 4 ++
6 files changed, 80 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index e9bc987a9c..86d572ea28 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -47,4 +47,5 @@ endif
ifneq ($(CONFIG_ARCH_LS1088A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+obj-y += icid.o ls1088_ids.o
endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
new file mode 100644
index 00..8f12a664d0
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+struct icid_id_table icid_tbl[] = {
+ SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
+
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 06f3edb302..cd91329edc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -332,6 +332,10 @@ void fsl_lsch3_early_init_f(void)
if (fsl_check_boot_mode_secure() == 1)
bypass_smmu();
#endif
+
+#ifdef CONFIG_ARCH_LS1088A
+ set_icids();
+#endif
}
/* Get VDD in the unit mV from voltage ID */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index f971af8d26..d1ad171bde 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -38,6 +38,7 @@ void fdt_fixup_icid(void *blob);
.reg_addr = addr, \
}
+#ifdef CONFIG_FSL_LSCH2
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
@@ -92,12 +93,44 @@ void fdt_fixup_icid(void *blob);
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
+#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
+
#define SET_SEC_QI_ICID(streamid) \
- SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
+ SET_ICID_ENTRY("fsl,sec-v4.0", SEC_ICID_REG_VAL(streamid), \
0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR)
+extern struct fman_icid_id_table fman_icid_tbl[];
+extern int fman_icid_tbl_sz;
+
+#else /* CONFIG_FSL_LSCH2 */
+
+#define SET_GUR_ICID(compat, streamid, name, compataddr) \
+ SET_ICID_ENTRY(compat, streamid, (streamid << 24), \
+ offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+ compataddr)
+
+#define SET_USB_ICID(usb_num, compat, streamid) \
+ SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
+ CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+
+#define SET_SATA_ICID(sata_num, compat, streamid) \
+ SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
+ AHCI_BASE_ADDR##sata_num)
+
+#define SET_SDHC_ICID(streamid) \
+ SET_GUR_ICID("fsl,esdhc", stre
[U-Boot] [PATCH v2 1/3] fsl_sec: fix register layout on Layerscape architectures
From: Laurentiu Tudor
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geanta
Reviewed-by: Bharat Bhushan
---
v2:
- added Reviewed-by tags
include/fsl_sec.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 16e3fcb5a1..be08a2b88b 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -121,10 +121,18 @@ typedef struct ccsr_sec {
u32 chanum_ls; /* CHA Number Register, LS */
u32 secvid_ms; /* SEC Version ID Register, MS */
u32 secvid_ls; /* SEC Version ID Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ u8 res9[0x6f020];
+#else
u8 res9[0x6020];
+#endif
u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ u8 res10[0x8ffd8];
+#else
u8 res10[0x8fd8];
+#endif
} ccsr_sec_t;
#define SEC_CTPR_MS_AXI_LIODN 0x0800
--
2.17.1
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[U-Boot] [PATCH 1/2] armv8: fsl-layerscape: add missing sec jr base address defines
From: Laurentiu Tudor Add defines for all the SEC job rings base addresses. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 9fab88ab2f..fc14fb6fe0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -89,10 +89,18 @@ /* SEC */ #define CONFIG_SYS_FSL_SEC_OFFSET 0x0700ull #define CONFIG_SYS_FSL_JR0_OFFSET 0x0701ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x0702ull +#define FSL_SEC_JR2_OFFSET 0x0703ull +#define FSL_SEC_JR3_OFFSET 0x0704ull #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) #ifdef CONFIG_TFABOOT #ifdef CONFIG_NXP_LSCH3_2 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] driver: net: fsl-mc: Fix DPC MAC address fixup
On 26.02.2019 17:41, Ioana Ciocoi Radulescu wrote:
> If node /board_info/ports does not exist in the DPC file,
> function mc_fixup_dpc() will skip not only MAC address fixup,
> but also the cache flush at the end. This may cause the other
> fixup changes (e.g. ICID relatd ones) to be ignored by MC.
>
> Fixes: 1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL")
>
> Signed-off-by: Ioana Radulescu
> ---
> drivers/net/fsl-mc/mc.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Laurentiu Tudor
---
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[U-Boot] [PATCH v2 3/3] armv8: fsl-layerscape: avoid DT fixup warning
From: Laurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geanta
Reviewed-by: Bharat Bhushan
---
v2:
- added Reviewed-by tags
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index e7a8801262..f971af8d26 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
struct icid_id_table {
const char *compat;
@@ -98,7 +99,13 @@ void fdt_fixup_icid(void *blob);
CONFIG_SYS_FSL_SEC_ADDR)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
- SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
+ SET_ICID_ENTRY( \
+ (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
+ (FSL_SEC_JR##jr_num##_OFFSET == \
+ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+ ? NULL \
+ : "fsl,sec-v4.0-job-ring"), \
+ streamid, \
(((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
--
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[U-Boot] [PATCH v2 2/3] armv8: fsl-layerscape: fix SEC QI ICID setup
From: Laurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geanta
Reviewed-by: Bharat Bhushan
---
v2:
- added Reviewed-by tags
arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +-
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 3 +--
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
index 0e8649427e..3bd993bebf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -43,7 +43,7 @@ struct icid_id_table icid_tbl[] = {
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
SET_QE_ICID(FSL_QE_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
- SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 2da9adab5b..abd847b5be 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -41,7 +41,7 @@ struct icid_id_table icid_tbl[] = {
SET_ETR_ICID(FSL_ETR_STREAM_ID),
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
- SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index f375fe7115..e7a8801262 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -93,8 +93,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
- (((streamid) << 16) | (streamid)), \
- offsetof(ccsr_sec_t, qilcr_ls) + \
+ 0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR)
--
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[U-Boot] [PATCH v2 1/3] fsl_sec: fix register layout on Layerscape architectures
From: Laurentiu Tudor
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geanta
Reviewed-by: Bharat Bhushan
---
v2:
- added Reviewed-by tags
include/fsl_sec.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 16e3fcb5a1..be08a2b88b 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -121,10 +121,18 @@ typedef struct ccsr_sec {
u32 chanum_ls; /* CHA Number Register, LS */
u32 secvid_ms; /* SEC Version ID Register, MS */
u32 secvid_ls; /* SEC Version ID Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ u8 res9[0x6f020];
+#else
u8 res9[0x6020];
+#endif
u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ u8 res10[0x8ffd8];
+#else
u8 res10[0x8fd8];
+#endif
} ccsr_sec_t;
#define SEC_CTPR_MS_AXI_LIODN 0x0800
--
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[U-Boot] [RESEND 3/3] armv8: fsl-layerscape: avoid DT fixup warning
From: Laurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index e7a8801262..f971af8d26 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
struct icid_id_table {
const char *compat;
@@ -98,7 +99,13 @@ void fdt_fixup_icid(void *blob);
CONFIG_SYS_FSL_SEC_ADDR)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
- SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
+ SET_ICID_ENTRY( \
+ (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
+ (FSL_SEC_JR##jr_num##_OFFSET == \
+ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+ ? NULL \
+ : "fsl,sec-v4.0-job-ring"), \
+ streamid, \
(((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
--
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[U-Boot] [RESEND 2/3] armv8: fsl-layerscape: fix SEC QI ICID setup
From: Laurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +-
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 3 +--
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
index 0e8649427e..3bd993bebf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -43,7 +43,7 @@ struct icid_id_table icid_tbl[] = {
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
SET_QE_ICID(FSL_QE_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
- SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 2da9adab5b..abd847b5be 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -41,7 +41,7 @@ struct icid_id_table icid_tbl[] = {
SET_ETR_ICID(FSL_ETR_STREAM_ID),
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
- SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index f375fe7115..e7a8801262 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -93,8 +93,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
- (((streamid) << 16) | (streamid)), \
- offsetof(ccsr_sec_t, qilcr_ls) + \
+ 0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR)
--
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[U-Boot] [RESEND 1/3] fsl_sec: fix register layout on Layerscape architectures
From: Laurentiu Tudor
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor
---
include/fsl_sec.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 16e3fcb5a1..be08a2b88b 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -121,10 +121,18 @@ typedef struct ccsr_sec {
u32 chanum_ls; /* CHA Number Register, LS */
u32 secvid_ms; /* SEC Version ID Register, MS */
u32 secvid_ls; /* SEC Version ID Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ u8 res9[0x6f020];
+#else
u8 res9[0x6020];
+#endif
u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ u8 res10[0x8ffd8];
+#else
u8 res10[0x8fd8];
+#endif
} ccsr_sec_t;
#define SEC_CTPR_MS_AXI_LIODN 0x0800
--
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Re: [U-Boot] [upstream-release] [PATCH] pci: layerscape: add option to statically allocate PCI StreamIDs
Hi Bharat,
Actually I've sent this patch by mistake, sorry for that.
I'll drop it and resend the patch series.
---
Best Regards, Laurentiu
On 30.01.2019 16:41, Bharat Bhushan wrote:
>
>
>> -Original Message-
>> From: upstream-release-boun...@linux.nxdi.nxp.com > boun...@linux.nxdi.nxp.com> On Behalf Of laurentiu.tu...@nxp.com
>> Sent: Wednesday, January 30, 2019 5:31 PM
>> To: u-boot@lists.denx.de; Prabhakar Kushwaha
>> ; York Sun
>> Cc: Laurentiu Tudor
>> Subject: [upstream-release] [PATCH] pci: layerscape: add option to statically
>> allocate PCI StreamIDs
>>
>> From: Laurentiu Tudor
>>
>> Certain PCI scenarios have more dynamic requirements, e.g. endpoints are
>> "hot-plugged" later in the system lifetime. Add a Kconfig option that allows
>> specifying a maximum number of end-points, per PCI controller and allocate
>> a StreamID for each one.
>>
>> Signed-off-by: Laurentiu Tudor
>> ---
>> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 28 +
>> drivers/pci/pcie_layerscape_fixup.c | 38 +++
>> 2 files changed, 66 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> index 2b086da79b..1d633d71a8 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> @@ -571,3 +571,31 @@ config TFABOOT
>> help
>>Enabling this will make a U-Boot binary that is capable of being
>>booted via TFA.
>> +
>> +menuconfig FSL_PCIE_STATIC_STREAM_IDS
>> +bool "Allocate PCI streamIDs statically"
>> +default n
>> +depends on PCIE_LAYERSCAPE
>> +help
>> + Statically allocate a certain number of StreamIDs for each PCI
>> + controller, instead of enumerating the connected endpoints and
>> + allocate a StreamID for each one. This allocation method can
>> + be used in more dynamic PCI scenarios, e.g. where endpoints are
>> + "hot-plugged" later in the system bringup, by statically specifying
>> + a maximum number of StreamIDs expected for each PCI controller.
>> +
>> +if FSL_PCIE_STATIC_STREAM_IDS
>> +
>> +config FSL_PCIE1_STREAM_IDS_COUNT
>> +default 3
>> +int "Maximum number of streamIDs to allocate for PCI1 controller"
>> +
>> +config FSL_PCIE2_STREAM_IDS_COUNT
>> +default 3
>> +int "Maximum number of streamIDs to allocate for PCI2 controller"
>> +
>> +config FSL_PCIE3_STREAM_IDS_COUNT
>> +default 3
>> +int "Maximum number of streamIDs to allocate for PCI3 controller"
>> +
>> +endif
>> diff --git a/drivers/pci/pcie_layerscape_fixup.c
>> b/drivers/pci/pcie_layerscape_fixup.c
>> index 1a17bd98aa..32355cbf2e 100644
>> --- a/drivers/pci/pcie_layerscape_fixup.c
>> +++ b/drivers/pci/pcie_layerscape_fixup.c
>> @@ -177,6 +177,7 @@ static void fdt_pcie_set_iommu_map_entry(void
>> *blob, struct ls_pcie *pcie,
>>
>> static void fdt_fixup_pcie(void *blob)
>> {
>> +#if !CONFIG_FSL_PCIE_STATIC_STREAM_IDS
>> struct udevice *dev, *bus;
>> struct ls_pcie *pcie;
>> int streamid;
>> @@ -215,6 +216,43 @@ static void fdt_fixup_pcie(void *blob)
>> fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
>> streamid);
>> }
>> +#else
>> +static const int streamid_cnt[] = {
>> +CONFIG_FSL_PCIE1_STREAM_IDS_COUNT,
>> +CONFIG_FSL_PCIE2_STREAM_IDS_COUNT,
>> +CONFIG_FSL_PCIE3_STREAM_IDS_COUNT
>
> Why 3 controllers?
>
>> +};
>> +struct ls_pcie *pcie;
>> +int i, streamid, index;
>> +pci_dev_t bdf;
>> +
>> +list_for_each_entry(pcie, _pcie_list, list) {
>> +for (i = 0; i < streamid_cnt[pcie->idx]; i++) {
>> +streamid = ls_pcie_next_streamid();
>> +if (streamid < 0) {
>> +debug("ERROR: no stream ids free\n");
>> +continue;
>
> Why to continue if we are out of stream-ids?
>
>> +}
>> +
>> +index = ls_pcie_next_lut_index(pcie);
>> +if (index < 0) {
>> +debug("ERROR: no LUT indexes free\n");
>> +con
[U-Boot] [PATCH] pci: layerscape: add option to statically allocate PCI StreamIDs
From: Laurentiu Tudor
Certain PCI scenarios have more dynamic requirements, e.g. endpoints
are "hot-plugged" later in the system lifetime. Add a Kconfig option
that allows specifying a maximum number of end-points, per PCI controller
and allocate a StreamID for each one.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 28 +
drivers/pci/pcie_layerscape_fixup.c | 38 +++
2 files changed, 66 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 2b086da79b..1d633d71a8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -571,3 +571,31 @@ config TFABOOT
help
Enabling this will make a U-Boot binary that is capable of being
booted via TFA.
+
+menuconfig FSL_PCIE_STATIC_STREAM_IDS
+ bool "Allocate PCI streamIDs statically"
+ default n
+ depends on PCIE_LAYERSCAPE
+ help
+ Statically allocate a certain number of StreamIDs for each PCI
+ controller, instead of enumerating the connected endpoints and
+ allocate a StreamID for each one. This allocation method can
+ be used in more dynamic PCI scenarios, e.g. where endpoints are
+ "hot-plugged" later in the system bringup, by statically specifying
+ a maximum number of StreamIDs expected for each PCI controller.
+
+if FSL_PCIE_STATIC_STREAM_IDS
+
+config FSL_PCIE1_STREAM_IDS_COUNT
+ default 3
+ int "Maximum number of streamIDs to allocate for PCI1 controller"
+
+config FSL_PCIE2_STREAM_IDS_COUNT
+ default 3
+ int "Maximum number of streamIDs to allocate for PCI2 controller"
+
+config FSL_PCIE3_STREAM_IDS_COUNT
+ default 3
+ int "Maximum number of streamIDs to allocate for PCI3 controller"
+
+endif
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 1a17bd98aa..32355cbf2e 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -177,6 +177,7 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct
ls_pcie *pcie,
static void fdt_fixup_pcie(void *blob)
{
+#if !CONFIG_FSL_PCIE_STATIC_STREAM_IDS
struct udevice *dev, *bus;
struct ls_pcie *pcie;
int streamid;
@@ -215,6 +216,43 @@ static void fdt_fixup_pcie(void *blob)
fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
streamid);
}
+#else
+ static const int streamid_cnt[] = {
+ CONFIG_FSL_PCIE1_STREAM_IDS_COUNT,
+ CONFIG_FSL_PCIE2_STREAM_IDS_COUNT,
+ CONFIG_FSL_PCIE3_STREAM_IDS_COUNT
+ };
+ struct ls_pcie *pcie;
+ int i, streamid, index;
+ pci_dev_t bdf;
+
+ list_for_each_entry(pcie, _pcie_list, list) {
+ for (i = 0; i < streamid_cnt[pcie->idx]; i++) {
+ streamid = ls_pcie_next_streamid();
+ if (streamid < 0) {
+ debug("ERROR: no stream ids free\n");
+ continue;
+ }
+
+ index = ls_pcie_next_lut_index(pcie);
+ if (index < 0) {
+ debug("ERROR: no LUT indexes free\n");
+ continue;
+ }
+
+ bdf = PCI_BDF(i, 0, 0);
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
+ streamid);
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
+ streamid);
+ /* update iommu-map in device tree */
+ fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
+streamid);
+ }
+ }
+#endif /* !CONFIG_FSL_PCIE_STATIC_STREAM_IDS */
}
#endif
--
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[U-Boot] [PATCH 3/3] armv8: fsl-layerscape: avoid DT fixup warning
From: Laurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index e7a8801262..f971af8d26 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
struct icid_id_table {
const char *compat;
@@ -98,7 +99,13 @@ void fdt_fixup_icid(void *blob);
CONFIG_SYS_FSL_SEC_ADDR)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
- SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
+ SET_ICID_ENTRY( \
+ (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
+ (FSL_SEC_JR##jr_num##_OFFSET == \
+ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+ ? NULL \
+ : "fsl,sec-v4.0-job-ring"), \
+ streamid, \
(((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
--
2.17.1
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[U-Boot] [PATCH 2/3] armv8: fsl-layerscape: fix SEC QI ICID setup
From: Laurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +-
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 3 +--
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
index 0e8649427e..3bd993bebf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -43,7 +43,7 @@ struct icid_id_table icid_tbl[] = {
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
SET_QE_ICID(FSL_QE_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
- SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 2da9adab5b..abd847b5be 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -41,7 +41,7 @@ struct icid_id_table icid_tbl[] = {
SET_ETR_ICID(FSL_ETR_STREAM_ID),
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
- SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index f375fe7115..e7a8801262 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -93,8 +93,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
- (((streamid) << 16) | (streamid)), \
- offsetof(ccsr_sec_t, qilcr_ls) + \
+ 0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR)
--
2.17.1
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[U-Boot] [PATCH 1/3] fsl_sec: fix register layout on Layerscape architectures
From: Laurentiu Tudor
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor
---
include/fsl_sec.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 16e3fcb5a1..be08a2b88b 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -121,10 +121,18 @@ typedef struct ccsr_sec {
u32 chanum_ls; /* CHA Number Register, LS */
u32 secvid_ms; /* SEC Version ID Register, MS */
u32 secvid_ls; /* SEC Version ID Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ u8 res9[0x6f020];
+#else
u8 res9[0x6020];
+#endif
u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ u8 res10[0x8ffd8];
+#else
u8 res10[0x8fd8];
+#endif
} ccsr_sec_t;
#define SEC_CTPR_MS_AXI_LIODN 0x0800
--
2.17.1
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[U-Boot] [PATCH] armv8: fsl-layerscape: properly configure qdma ICID
From: Laurentiu Tudor The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h| 6 +- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index a3f473fe28..f375fe7115 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -55,7 +55,11 @@ void fdt_fixup_icid(void *blob); CONFIG_SYS_FSL_ESDHC_ADDR) #define SET_QDMA_ICID(compat, streamid) \ - SET_SCFG_ICID(compat, streamid, dma_icid,\ + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ + QDMA_BASE_ADDR), \ + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ QDMA_BASE_ADDR) #define SET_EDMA_ICID(streamid) \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 4d0f16f21c..b4b7c3492e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -94,6 +94,7 @@ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220) #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x0738) +#define QMAN_CQSIDR_REG0x20a80 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x40ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x48ULL -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/4] armv8: ls1043a: enable icid setup for qman portals
From: Laurentiu Tudor
Enable support for ICID setup of qman portals and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor
---
drivers/misc/fsl_portals.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index d3137680ad..45eed22f6e 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -49,7 +49,7 @@ void setup_qbman_portals(void)
out_be32(>qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
}
#else
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
int i;
for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
@@ -197,7 +197,7 @@ void fdt_fixup_qportals(void *blob)
char compat[64];
int compat_len;
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
int smmu_ph = fdt_get_smmu_phandle(blob);
#endif
@@ -211,7 +211,8 @@ void fdt_fixup_qportals(void *blob)
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
while (off != -FDT_ERR_NOTFOUND) {
-#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1043A) || \
+defined(CONFIG_ARCH_LS1046A)
#ifdef CONFIG_FSL_CORENET
u32 liodns[2];
#endif
@@ -226,7 +227,7 @@ void fdt_fixup_qportals(void *blob)
int j;
#endif
-#endif /* CONFIG_PPC || CONFIG_ARCH_LS1046A */
+#endif /* CONFIG_PPC || CONFIG_ARCH_LS1043A || CONFIG_ARCH_LS1046A */
err = fdt_setprop(blob, off, "compatible", compat, compat_len);
if (err < 0)
goto err;
@@ -275,7 +276,7 @@ void fdt_fixup_qportals(void *blob)
goto err;
#endif
#else
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
if (smmu_ph >= 0) {
u32 icids[3];
--
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[U-Boot] [PATCH 2/4] armv8: ls1043a: advertise QMan v3 in configuration
From: Laurentiu Tudor The QMan IP block in this SoC is version 3.2 so advertise this in the SoC configuration header. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 8a05148136..bd4ca88e16 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -195,6 +195,7 @@ /* SoC related */ #ifdef CONFIG_ARCH_LS1043A #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/4] armv8: ls1043a: add icid setup support
From: Laurentiu Tudor
Reuse the existing ICID setup code done for LS1046A smmu enablement
and add the equivalent setup for LS1043A chips.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 90 +++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
.../asm/arch-fsl-layerscape/fsl_icid.h| 4 +
board/freescale/ls1043aqds/ls1043aqds.c | 3 +
board/freescale/ls1043ardb/ls1043ardb.c | 3 +
6 files changed, 102 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 5d6f68aad6..91fdbad8be 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -29,6 +29,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
+obj-y += icid.o ls1043_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1012A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
new file mode 100644
index 00..0e8649427e
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+};
+#endif
+
+struct icid_id_table icid_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
+ SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1),
+#endif
+
+ SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
+
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
+
+ SET_SATA_ICID("fsl,ls1043a-ahci", FSL_SATA_STREAM_ID),
+ SET_QDMA_ICID("fsl,ls1043a-qdma", FSL_QDMA_STREAM_ID),
+ SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
+ SET_ETR_ICID(FSL_ETR_STREAM_ID),
+ SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
+ SET_QE_ICID(FSL_QE_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct fman_icid_id_table fman_icid_tbl[] = {
+ /* port id, icid */
+ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END),
+
