From: Peng Fan van.free...@gmail.com
Add QuadSPI support for mx6sxsabresd board.
There are two 16MB S25FL128S flashes on board. They are connected to
QSPI2 interface. i.MX6SX supports two QuadSPI interfaces, QSPI1/2.
The two flash devices are connected to A1/B1 of QSPI2.
Signed-off-by: Peng Fan van.free...@gmail.com
---
arch/arm/cpu/armv7/mx6/clock.c | 50 +
arch/arm/include/asm/arch-mx6/clock.h | 3 ++
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++
drivers/spi/fsl_qspi.c | 30 +
include/configs/mx6sxsabresd.h | 14
5 files changed, 137 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5..8caa61d 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -340,6 +340,56 @@ static u32 get_mmdc_ch0_clk(void)
}
#endif
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+ u32 reg = 0;
+ /* Enable QuadSPI clock */
+ switch (qspi_num) {
+ case 0:
+ /* disable the clock gate */
+ clrbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(imx_ccm-cscmr1);
+ reg = ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+ reg |= ((1 MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+ (2 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+ writel(reg, imx_ccm-cscmr1);
+
+ /* enable the clock gate */
+ setbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+ break;
+ case 1:
+ /*
+* disable the clock gate
+* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+* disable both of them.
+*/
+ clrbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(imx_ccm-cs2cdr);
+ reg = ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+ reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+ writel(reg, imx_ccm-cs2cdr);
+
+ /*enable the clock gate*/
+ setbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+ break;
+ default:
+ break;
+ }
+}
+#endif
+
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(enum enet_freq freq)
{
diff --git a/arch/arm/include/asm/arch-mx6/clock.h
b/arch/arm/include/asm/arch-mx6/clock.h
index 339c789..9d0ba7a 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -60,4 +60,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
+#ifdef CONFIG_MX6SX
+void enable_qspi_clk(int qspi_num);
+#endif
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 5eaec1b..f9cad5a 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
}
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
