[U-Boot] [PATCH 2/3] ARM: OMAP5: clocks: Do not enable sgx clocks
From: Sricharan R r.sricha...@ti.com SGX clocks should be enabled only for OMAP5 ES1.0. So this can be removed. Signed-off-by: Sricharan R r.sricha...@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c |6 -- 1 file changed, 6 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 604fa42..842cf27 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -383,12 +383,6 @@ void enable_basic_clocks(void) clk_modules_explicit_en_essential, 1); - /* Select 384Mhz for GPU as its the POR for ES1.0 */ - setbits_le32((*prcm)-cm_sgx_sgx_clkctrl, - CLKSEL_GPU_HYD_GCLK_MASK); - setbits_le32((*prcm)-cm_sgx_sgx_clkctrl, - CLKSEL_GPU_CORE_GCLK_MASK); - /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)-cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/3] ARM: OMAP4+: Misc Cleanup
Misc cleanup. And also adding a Generic bus init and write functions for PMIC. This series is applied on top of u-boot-ti: git://git.denx.de/u-boot-ti.git Lokesh Vutla (2): ARM: OMAP4+: Cleanup header files ARM: OMAP4+: pmic: Make generic bus init and write functions Sricharan R (1): ARM: OMAP5: clocks: Do not enable sgx clocks arch/arm/cpu/armv7/omap-common/clocks-common.c |6 ++--- arch/arm/cpu/armv7/omap-common/vc.c| 14 ++- arch/arm/cpu/armv7/omap4/hw_data.c | 11 - arch/arm/cpu/armv7/omap4/prcm-regs.c |3 +++ arch/arm/cpu/armv7/omap5/hw_data.c |9 +++ arch/arm/cpu/armv7/omap5/prcm-regs.c |2 ++ arch/arm/include/asm/arch-omap4/clocks.h | 28 - arch/arm/include/asm/arch-omap4/cpu.h | 12 - arch/arm/include/asm/arch-omap4/omap.h | 14 --- arch/arm/include/asm/arch-omap4/sys_proto.h|2 +- arch/arm/include/asm/arch-omap5/clocks.h | 22 - arch/arm/include/asm/arch-omap5/cpu.h | 12 - arch/arm/include/asm/arch-omap5/omap.h | 31 +--- arch/arm/include/asm/arch-omap5/sys_proto.h|2 +- arch/arm/include/asm/omap_common.h |7 +++--- board/ti/omap5_uevm/evm.c | 12 ++--- board/ti/panda/panda.c | 20 +-- board/ti/sdp4430/sdp.c | 16 +++- drivers/usb/musb/omap3.c |4 ++- 19 files changed, 73 insertions(+), 154 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] ARM: OMAP4+: Cleanup header files
After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap4/prcm-regs.c |3 +++
arch/arm/cpu/armv7/omap5/prcm-regs.c |2 ++
arch/arm/include/asm/arch-omap4/clocks.h | 28 ---
arch/arm/include/asm/arch-omap4/cpu.h| 12
arch/arm/include/asm/arch-omap4/omap.h | 14 --
arch/arm/include/asm/arch-omap5/clocks.h | 22 -
arch/arm/include/asm/arch-omap5/cpu.h| 12
arch/arm/include/asm/arch-omap5/omap.h | 31 +-
arch/arm/include/asm/omap_common.h |4 +---
board/ti/omap5_uevm/evm.c| 12
board/ti/panda/panda.c | 20 +++
board/ti/sdp4430/sdp.c | 16 +--
drivers/usb/musb/omap3.c |4 +++-
13 files changed, 40 insertions(+), 140 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c
b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index 7225a30..7e71ca0 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -301,6 +301,8 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
.control_ldosram_iva_voltage_ctrl = 0x4A002320,
.control_ldosram_mpu_voltage_ctrl = 0x4A002324,
.control_ldosram_core_voltage_ctrl = 0x4A002328,
+ .control_usbotghs_ctrl = 0x4A00233C,
+ .control_padconf_core_base = 0x4A10,
.control_pbiaslite = 0x4A100600,
.control_lpddr2io1_0= 0x4A100638,
.control_lpddr2io1_1= 0x4A10063C,
@@ -312,4 +314,5 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
.control_lpddr2io2_3= 0x4A100654,
.control_efuse_1= 0x4A100700,
.control_efuse_2= 0x4A100704,
+ .control_padconf_wkup_base = 0x4A31E000,
};
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index e9f6a32..db779f2 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -311,6 +311,7 @@ struct prcm_regs const omap5_es1_prcm = {
struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_status = 0x4A002134,
+ .control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode= 0x4A002DA4,
.control_smart1io_padconf_0 = 0x4A002DA8,
@@ -358,6 +359,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_port_emif2_sdram_config= 0x4AE0C118,
.control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148,
+ .control_padconf_wkup_base = 0x4AE0C800,
.control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
.control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
.control_padconf_mode = 0x4AE0CDA8,
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h
b/arch/arm/include/asm/arch-omap4/clocks.h
index ed7a1c8..f544edf 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -34,25 +34,6 @@
*/
#define LDELAY 100
-#define CM_CLKMODE_DPLL_CORE 0x4A004120
-#define CM_CLKMODE_DPLL_PER0x4A008140
-#define CM_CLKMODE_DPLL_MPU0x4A004160
-#define CM_CLKSEL_CORE 0x4A004100
-
-/* DPLL register offsets */
-#define CM_CLKMODE_DPLL0
-#define CM_IDLEST_DPLL 0x4
-#define CM_AUTOIDLE_DPLL 0x8
-#define CM_CLKSEL_DPLL 0xC
-#define CM_DIV_M2_DPLL 0x10
-#define CM_DIV_M3_DPLL 0x14
-#define CM_DIV_M4_DPLL 0x18
-#define CM_DIV_M5_DPLL 0x1C
-#define CM_DIV_M6_DPLL 0x20
-#define CM_DIV_M7_DPLL 0x24
-
-#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
-
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 0)
@@ -94,8 +75,6 @@
#define CM_CLKSEL_DCC_EN_SHIFT 22
#define CM_CLKSEL_DCC_EN_MASK (1 22)
-#define OMAP4_DPLL_MAX_N 127
-
/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
@@ -181,9 +160,7 @@
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 25)
/* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ 3840
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
-#define OMAP_32K_CLK_FREQ 32768
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ400
@@ -234,11 +211,6 @@
#define ALTCLKSRC_MODE_ACTIVE 1
-/* Defines for DPLL setup */
-#define
[U-Boot] [PATCH 3/3] ARM: OMAP4+: pmic: Make generic bus init and write functions
Voltage scaling can be done in two ways:
- Using SR I2C
- Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |6 ++
arch/arm/cpu/armv7/omap-common/vc.c| 14 +-
arch/arm/cpu/armv7/omap4/hw_data.c | 11 ++-
arch/arm/cpu/armv7/omap5/hw_data.c |3 +++
arch/arm/include/asm/arch-omap4/sys_proto.h|2 +-
arch/arm/include/asm/arch-omap5/sys_proto.h|2 +-
arch/arm/include/asm/omap_common.h |3 +++
7 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 99910cd..0daf98c 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -487,6 +487,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
u32 offset = volt_mv;
int ret = 0;
+ pmic-pmic_bus_init();
/* See if we can first get the GPIO if needed */
if (pmic-gpio_en)
ret = gpio_request(pmic-gpio, PMIC_GPIO);
@@ -509,8 +510,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
debug(do_scale_vcore: volt - %d offset_code - 0x%x\n, volt_mv,
offset_code);
- if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
- vcore_reg, offset_code))
+ if (pmic-pmic_write(pmic-i2c_slave_addr, vcore_reg, offset_code))
printf(Scaling voltage failed for 0x%x\n, vcore_reg);
if (pmic-gpio_en)
@@ -525,8 +525,6 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
*/
void scale_vcores(struct vcores_data const *vcores)
{
- omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
-
do_scale_vcore(vcores-core.addr, vcores-core.value,
vcores-core.pmic);
diff --git a/arch/arm/cpu/armv7/omap-common/vc.c
b/arch/arm/cpu/armv7/omap-common/vc.c
index e6e5f78..911191d 100644
--- a/arch/arm/cpu/armv7/omap-common/vc.c
+++ b/arch/arm/cpu/armv7/omap-common/vc.c
@@ -17,6 +17,7 @@
#include common.h
#include asm/omap_common.h
#include asm/arch/sys_proto.h
+#include asm/arch/clocks.h
/*
* Define Master code if there are multiple masters on the I2C_SR bus.
@@ -57,7 +58,7 @@
* omap_vc_init() - Initialization for Voltage controller
* @speed_khz: I2C buspeed in KHz
*/
-void omap_vc_init(u16 speed_khz)
+static void omap_vc_init(u16 speed_khz)
{
u32 val;
u32 sys_clk_khz, cycles_hi, cycles_low;
@@ -137,3 +138,14 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8
reg_data)
/* All good.. */
return 0;
}
+
+void sri2c_init(void)
+{
+ static int sri2c = 1;
+
+ if (sri2c) {
+ omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+ sri2c = 0;
+ }
+ return;
+}
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c
b/arch/arm/cpu/armv7/omap4/hw_data.c
index 06a2fc8..02322cc 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -219,6 +219,9 @@ struct pmic_data twl6030_4430es1 = {
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct pmic_data twl6030 = {
@@ -226,6 +229,9 @@ struct pmic_data twl6030 = {
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct pmic_data tps62361 = {
@@ -233,7 +239,10 @@ struct pmic_data tps62361 = {
.step = 1, /* 10 mV represented in uV */
.start_code = 0,
.gpio = TPS62361_VSEL0_GPIO,
- .gpio_en = 1
+ .gpio_en = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct vcores_data omap4430_volts_es1 = {
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 842cf27..74e473d 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -289,6 +289,9 @@ struct pmic_data palmas = {
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct vcores_data omap5430_volts = {
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index
[U-Boot] [PATCH 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's
This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-0-3-ARM-OMAP4-Misc-Cleanup-tt155877.html Tested on DRA752 ES1.0, OMAP5432 ES2.0, MAKEALL for all armv7 board has been verified. Balaji T K (1): mmc: omap_hsmmc: add mmc1 pbias, ldo1 Lokesh Vutla (6): ARM: DRA7xx: Add control id code for DRA7xx ARM: DRA7xx: power Add support for tps659038 PMIC ARM: DRA7xx: clocks: Fixing i2c_init for PMIC ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's ARM: DRA7xx: Update pinmux data ARM: DRA7xx: clocks: Update PLL values Nishanth Menon (1): ARM: OMAP5: DRA7xx: support class 0 optimized voltages Sricharan R (4): ARM: DRA7xx: Change the Debug UART to UART1 ARM: DRA7xx: Correct the SYS_CLK to 20MHZ ARM: DRA7xx: Correct SRAM END address ARM: DRA7xx: EMIF: Change settings required for EVM board arch/arm/cpu/armv7/omap-common/clocks-common.c | 86 +--- arch/arm/cpu/armv7/omap-common/emif-common.c | 26 +++- arch/arm/cpu/armv7/omap-common/hwinit-common.c |2 - arch/arm/cpu/armv7/omap5/hw_data.c | 156 -- arch/arm/cpu/armv7/omap5/hwinit.c | 22 ++- arch/arm/cpu/armv7/omap5/prcm-regs.c |2 + arch/arm/cpu/armv7/omap5/sdram.c | 170 ++-- arch/arm/include/asm/arch-omap4/clocks.h |2 +- arch/arm/include/asm/arch-omap4/sys_proto.h|1 + arch/arm/include/asm/arch-omap5/clocks.h | 64 - arch/arm/include/asm/arch-omap5/mux_dra7xx.h |7 +- arch/arm/include/asm/arch-omap5/omap.h | 14 +- arch/arm/include/asm/arch-omap5/sys_proto.h|1 + arch/arm/include/asm/emif.h| 12 +- arch/arm/include/asm/omap_common.h | 26 +++- board/ti/dra7xx/mux_data.h | 38 -- drivers/mmc/omap_hsmmc.c | 26 ++-- drivers/power/palmas.c | 25 +++- include/configs/dra7xx_evm.h | 11 ++ include/configs/omap5_common.h |9 +- include/configs/omap5_uevm.h | 13 +- include/palmas.h |5 +- 22 files changed, 582 insertions(+), 136 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/12] ARM: DRA7xx: clocks: Fixing i2c_init for PMIC
In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c |1 + arch/arm/cpu/armv7/omap-common/hwinit-common.c |2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index c51c359..1861df4 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -721,6 +721,7 @@ void prcm_init(void) case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: enable_basic_clocks(); + timer_init(); scale_vcores(*omap_vcores); setup_dplls(); #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 1645120..5602b0e 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -202,8 +202,6 @@ void s_init(void) #endif prcm_init(); #ifdef CONFIG_SPL_BUILD - timer_init(); - /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/12] mmc: omap_hsmmc: add mmc1 pbias, ldo1
From: Balaji T K balaj...@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h |3 ++-
drivers/mmc/omap_hsmmc.c | 26 ++
drivers/power/palmas.c | 25 -
include/configs/omap5_common.h |4
include/configs/omap5_uevm.h |5 -
include/palmas.h |5 -
6 files changed, 48 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 15d429f..63378fb 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -96,9 +96,10 @@
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 27)
#define SDCARD_PWRDNZ (1 26)
#define SDCARD_BIAS_HIZ_MODE (1 25)
-#define SDCARD_BIAS_PWRDNZ (1 22)
+#define SDCARD_BIAS_PWRDNZ2(1 22)
#define SDCARD_PBIASLITE_VMODE (1 21)
#ifndef __ASSEMBLY__
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index afdfa88..60807df 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -113,23 +113,25 @@ static void omap5_pbias_config(struct mmc *mmc)
u32 value = 0;
value = readl((*ctrl)-control_pbias);
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
+ value = ~SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(10); /* wait 10 us */
+ value = ~SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
- palmas_mmc1_poweron_ldo();
+#if defined(CONFIG_DRA7XX)
+ palmas_mmc1_poweron_ldo1();
+#else
+ palmas_mmc1_poweron_ldo9();
+#endif
value = readl((*ctrl)-control_pbias);
- value = ~SDCARD_BIAS_HIZ_MODE;
- value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
+ value |= SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
-
- value = readl((*ctrl)-control_pbias);
- if (value (1 23)) {
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
- writel(value, (*ctrl)-control_pbias);
- }
+ udelay(150); /* wait 10 us */
+ value |= SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(150); /* wait 10 us */
}
#endif
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 09c832d..84ec881 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -28,7 +28,7 @@ void palmas_init_settings(void)
return;
}
-int palmas_mmc1_poweron_ldo(void)
+int palmas_mmc1_poweron_ldo9(void)
{
u8 val = 0;
@@ -50,3 +50,26 @@ int palmas_mmc1_poweron_ldo(void)
return 0;
}
+
+int palmas_mmc1_poweron_ldo1(void)
+{
+ u8 val = 0;
+
+ /* set LDO9 TWL6035 to 3V */
+ val = 0x2b; /* (3 -.9)*20 +1 */
+
+ if (palmas_i2c_write_u8(0x58, LDO1_VOLTAGE, val)) {
+ printf(twl6035: could not set LDO1 voltage\n);
+ return 1;
+ }
+
+ /* TURN ON LDO9 */
+ val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
+
+ if (palmas_i2c_write_u8(0x58, LDO1_CTRL, val)) {
+ printf(twl6035: could not turn on LDO1\n);
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index 9fef21c..f2c4c70 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -241,6 +241,10 @@
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PALMAS_POWER
+#endif
+
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 96c5955..69754c6 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -39,11 +39,6 @@
#define CONFIG_SYS_NS16550_COM3UART3_BASE
#define CONFIG_BAUDRATE115200
-/* TWL6035 */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PALMAS_POWER
-#endif
-
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
diff --git a/include/palmas.h b/include/palmas.h
index 3b18589..18a25ff 100644
--- a/include/palmas.h
+++ b/include/palmas.h
@@ -30,6 +30,8 @@
#define PALMAS_CHIP_ADDR 0x48
/* 0x1XY translates to page 1, register address 0xXY */
+#define LDO1_CTRL 0x50
+#define LDO1_VOLTAGE 0x51
#define LDO9_CTRL 0x60
#define LDO9_VOLTAGE 0x61
@@ -53,6 +55,7
[U-Boot] [PATCH 05/12] ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c |3 +++
arch/arm/include/asm/omap_common.h |8
2 files changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index e192fea..784aa11 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -201,6 +201,9 @@ void srcomp_enable(void)
u32 sysclk_ind = get_sys_clk_index();
u32 omap_rev= omap_revision();
+ if (!is_omap54xx())
+ return;
+
mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
div_factor = srcomp_parameters[sysclk_ind].divide_factor;
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 1435674..7007177 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -575,6 +575,14 @@ static inline u32 omap_revision(void)
extern u32 *const omap_si_rev;
return *omap_si_rev;
}
+
+#define OMAP54xx 0x5400
+
+static inline u8 is_omap54xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return ((*omap_si_rev 0xFF00) == OMAP54xx);
+}
#endif
/*
--
1.7.9.5
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/12] ARM: DRA7xx: Change the Debug UART to UART1
From: Sricharan R r.sricha...@ti.com Serial UART is connected to UART1. So add the change for the same. Signed-off-by: Sricharan R r.sricha...@ti.com --- include/configs/dra7xx_evm.h |3 +++ include/configs/omap5_common.h |4 include/configs/omap5_uevm.h |4 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 28a306b..b142049 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -35,4 +35,7 @@ #define CONFIG_DRA7XX /* in a TI DRA7XX core */ #define CONFIG_SYS_PROMPT DRA752 EVM # +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1UART1_BASE +#define CONFIG_BAUDRATE115200 #endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index deb5e9f..d57c0da 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -81,10 +81,6 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE(-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3UART3_BASE - -#define CONFIG_BAUDRATE115200 /* CPU */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index c791789..ba81e30 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -35,6 +35,10 @@ #include configs/omap5_common.h +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3UART3_BASE +#define CONFIG_BAUDRATE115200 + /* TWL6035 */ #ifndef CONFIG_SPL_BUILD #define CONFIG_PALMAS_POWER -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/12] ARM: DRA7xx: power Add support for tps659038 PMIC
TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 23 ++
arch/arm/cpu/armv7/omap5/hw_data.c | 38 +++-
arch/arm/include/asm/arch-omap4/sys_proto.h|1 +
arch/arm/include/asm/arch-omap5/clocks.h | 15 ++
arch/arm/include/asm/arch-omap5/sys_proto.h|1 +
arch/arm/include/asm/omap_common.h |3 ++
6 files changed, 80 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 0daf98c..c51c359 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -30,6 +30,7 @@
* MA 02111-1307 USA
*/
#include common.h
+#include i2c.h
#include asm/omap_common.h
#include asm/gpio.h
#include asm/arch/clocks.h
@@ -487,6 +488,9 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
u32 offset = volt_mv;
int ret = 0;
+ if (!volt_mv)
+ return;
+
pmic-pmic_bus_init();
/* See if we can first get the GPIO if needed */
if (pmic-gpio_en)
@@ -534,6 +538,15 @@ void scale_vcores(struct vcores_data const *vcores)
do_scale_vcore(vcores-mm.addr, vcores-mm.value,
vcores-mm.pmic);
+ do_scale_vcore(vcores-gpu.addr, vcores-gpu.value,
+ vcores-gpu.pmic);
+
+ do_scale_vcore(vcores-eve.addr, vcores-eve.value,
+ vcores-eve.pmic);
+
+ do_scale_vcore(vcores-iva.addr, vcores-iva.value,
+ vcores-iva.pmic);
+
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM magic bits */
writel(2, (*prcm)-prm_sldo_core_setup);
@@ -723,3 +736,13 @@ void prcm_init(void)
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
enable_basic_uboot_clocks();
}
+
+void gpi2c_init(void)
+{
+ static int gpi2c = 1;
+
+ if (gpi2c) {
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ gpi2c = 0;
+ }
+}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 74e473d..e9d34c1 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -26,6 +26,7 @@
* MA 02111-1307 USA
*/
#include common.h
+#include palmas.h
#include asm/arch/omap.h
#include asm/arch/sys_proto.h
#include asm/omap_common.h
@@ -294,6 +295,19 @@ struct pmic_data palmas = {
.pmic_write = omap_vc_bypass_send_value,
};
+struct pmic_data tps659038 = {
+ .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+ .step = 1, /* 10 mV represented in uV */
+ /*
+* Offset codes 1-6 all give the base voltage in Palmas
+* Offset code 0 switches OFF the SMPS
+*/
+ .start_code = 6,
+ .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
+ .pmic_bus_init = gpi2c_init,
+ .pmic_write = palmas_i2c_write_u8,
+};
+
struct vcores_data omap5430_volts = {
.mpu.value = VDD_MPU,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
@@ -322,6 +336,28 @@ struct vcores_data omap5430_volts_es2 = {
.mm.pmic = palmas,
};
+struct vcores_data dra752_volts = {
+ .mpu.value = VDD_MPU_DRA752,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
+ .mpu.pmic = tps659038,
+
+ .eve.value = VDD_EVE_DRA752,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
+ .eve.pmic = tps659038,
+
+ .gpu.value = VDD_GPU_DRA752,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
+ .gpu.pmic = tps659038,
+
+ .core.value = VDD_CORE_DRA752,
+ .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
+ .core.pmic = tps659038,
+
+ .iva.value = VDD_IVA_DRA752,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
+ .iva.pmic = tps659038,
+};
+
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
@@ -562,7 +598,7 @@ void hw_data_init(void)
case DRA752_ES1_0:
*prcm = dra7xx_prcm;
*dplls_data = dra7xx_dplls;
- *omap_vcores = omap5430_volts_es2;
+ *omap_vcores = dra752_volts;
*ctrl = dra7xx_ctrl;
break;
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 37d6c69..438cb96 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -57,6 +57,7 @@ u32 cortex_rev(void);
void init_omap_revision(void);
void do_io_settings(void);
void sri2c_init(void);
+void gpi2c_init(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void
[U-Boot] [PATCH 01/12] ARM: DRA7xx: Add control id code for DRA7xx
The registers that are used for device identification are changed from OMAP5 to DRA7xx. Using the correct registers for DRA7xx. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- arch/arm/include/asm/arch-omap5/clocks.h | 11 +++ arch/arm/include/asm/arch-omap5/omap.h |3 --- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 6673a02..ca75f63 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -239,4 +239,15 @@ * into microsec and passing the value. */ #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC31219 + +/* CONTROL ID CODE */ +#define CONTROL_CORE_ID_CODE 0x4A002204 +#define CONTROL_WKUP_ID_CODE 0x4AE0C204 + +#ifdef CONFIG_DRA7XX +#define CONTROL_ID_CODECONTROL_WKUP_ID_CODE +#else +#define CONTROL_ID_CODECONTROL_CORE_ID_CODE +#endif + #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 6dfedf4..df8222a 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -44,9 +44,6 @@ #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_ENDOMAP54XX_DRAM_ADDR_SPACE_END -/* CONTROL_ID_CODE */ -#define CONTROL_ID_CODE0x4A002204 - /* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/12] ARM: OMAP5: DRA7xx: support class 0 optimized voltages
From: Nishanth Menon n...@ti.com
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.
This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 58 +++-
arch/arm/cpu/armv7/omap5/hw_data.c | 10
arch/arm/include/asm/arch-omap5/clocks.h | 30
arch/arm/include/asm/omap_common.h | 11 +
4 files changed, 97 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 1861df4..928327a 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -521,6 +521,38 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
gpio_direction_output(pmic-gpio, 1);
}
+static u32 optimize_vcore_voltage(struct volts const *v)
+{
+ u32 val;
+ if (!v-value)
+ return 0;
+ if (!v-efuse.reg)
+ return v-value;
+
+ switch (v-efuse.reg_bits) {
+ case 16:
+ val = readw(v-efuse.reg);
+ break;
+ case 32:
+ val = readl(v-efuse.reg);
+ break;
+ default:
+ printf(Error: efuse 0x%08x bits=%d unknown\n,
+ v-efuse.reg, v-efuse.reg_bits);
+ return v-value;
+ }
+
+ if (!val) {
+ printf(Error: efuse 0x%08x bits=%d val=0, using %d\n,
+ v-efuse.reg, v-efuse.reg_bits, v-value);
+ return v-value;
+ }
+
+ debug(%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n,
+ __func__, v-efuse.reg, v-efuse.reg_bits, v-value, val);
+ return val;
+}
+
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
@@ -529,23 +561,25 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
*/
void scale_vcores(struct vcores_data const *vcores)
{
- do_scale_vcore(vcores-core.addr, vcores-core.value,
- vcores-core.pmic);
+ u32 val;
+
+ val = optimize_vcore_voltage(vcores-core);
+ do_scale_vcore(vcores-core.addr, val, vcores-core.pmic);
- do_scale_vcore(vcores-mpu.addr, vcores-mpu.value,
- vcores-mpu.pmic);
+ val = optimize_vcore_voltage(vcores-mpu);
+ do_scale_vcore(vcores-mpu.addr, val, vcores-mpu.pmic);
- do_scale_vcore(vcores-mm.addr, vcores-mm.value,
- vcores-mm.pmic);
+ val = optimize_vcore_voltage(vcores-mm);
+ do_scale_vcore(vcores-mm.addr, val, vcores-mm.pmic);
- do_scale_vcore(vcores-gpu.addr, vcores-gpu.value,
- vcores-gpu.pmic);
+ val = optimize_vcore_voltage(vcores-gpu);
+ do_scale_vcore(vcores-gpu.addr, val, vcores-gpu.pmic);
- do_scale_vcore(vcores-eve.addr, vcores-eve.value,
- vcores-eve.pmic);
+ val = optimize_vcore_voltage(vcores-eve);
+ do_scale_vcore(vcores-eve.addr, val, vcores-eve.pmic);
- do_scale_vcore(vcores-iva.addr, vcores-iva.value,
- vcores-iva.pmic);
+ val = optimize_vcore_voltage(vcores-iva);
+ do_scale_vcore(vcores-iva.addr, val, vcores-iva.pmic);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM magic bits */
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index e9d34c1..53aea93 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -338,22 +338,32 @@ struct vcores_data omap5430_volts_es2 = {
struct vcores_data dra752_volts = {
.mpu.value = VDD_MPU_DRA752,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
.mpu.pmic = tps659038,
.eve.value = VDD_EVE_DRA752,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
.eve.pmic = tps659038,
.gpu.value = VDD_GPU_DRA752,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
.gpu.pmic = tps659038,
.core.value = VDD_CORE_DRA752,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
[U-Boot] [PATCH 10/12] ARM: DRA7xx: Update pinmux data
Updating pinmux data as specified in the latest DM
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Balaji T K balaj...@ti.com
---
arch/arm/include/asm/arch-omap5/mux_dra7xx.h |7 +++--
board/ti/dra7xx/mux_data.h | 38 --
2 files changed, 29 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
index 55e9de6..5f2b0f9 100644
--- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
+++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
@@ -28,11 +28,14 @@
#include asm/types.h
+#define FSC(1 19)
+#define SSC(0 19)
+
#define IEN(1 18)
#define IDIS (0 18)
-#define PTU(3 16)
-#define PTD(1 16)
+#define PTU(1 17)
+#define PTD(0 17)
#define PEN(1 16)
#define PDIS (0 16)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 04c95fd..338a241 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -29,19 +29,29 @@
#include asm/arch/mux_dra7xx.h
const struct pad_conf_entry core_padconf_array_essential[] = {
- {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */
- {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */
- {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */
- {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */
- {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */
- {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */
- {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */
- {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */
- {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */
- {UART1_TXD, (M0)}, /* UART1_TXD */
- {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */
- {UART1_RTSN, (M0)}, /* UART1_RTSN */
- {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */
- {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */
+ {MMC1_CLK, (IEN | PTU | PDIS | M0)},/* MMC1_CLK */
+ {MMC1_CMD, (IEN | PTU | PDIS | M0)},/* MMC1_CMD */
+ {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+ {GPMC_A19, (IEN | PTU | PDIS | M1)},/* mmc2_dat4 */
+ {GPMC_A20, (IEN | PTU | PDIS | M1)},/* mmc2_dat5 */
+ {GPMC_A21, (IEN | PTU | PDIS | M1)},/* mmc2_dat6 */
+ {GPMC_A22, (IEN | PTU | PDIS | M1)},/* mmc2_dat7 */
+ {GPMC_A23, (IEN | PTU | PDIS | M1)},/* mmc2_clk */
+ {GPMC_A24, (IEN | PTU | PDIS | M1)},/* mmc2_dat0 */
+ {GPMC_A25, (IEN | PTU | PDIS | M1)},/* mmc2_dat1 */
+ {GPMC_A26, (IEN | PTU | PDIS | M1)},/* mmc2_dat2 */
+ {GPMC_A27, (IEN | PTU | PDIS | M1)},/* mmc2_dat3 */
+ {GPMC_CS1, (IEN | PTU | PDIS | M1)},/* mmm2_cmd */
+ {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
+ {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
+ {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
+ {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
+ {I2C1_SDA, (IEN | PTU | PDIS | M0)},/* I2C1_SDA */
+ {I2C1_SCL, (IEN | PTU | PDIS | M0)},/* I2C1_SCL */
};
#endif /* _MUX_DATA_DRA7XX_H_ */
--
1.7.9.5
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[U-Boot] [PATCH 07/12] ARM: DRA7xx: Correct the SYS_CLK to 20MHZ
From: Sricharan R r.sricha...@ti.com The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. Signed-off-by: Sricharan R r.sricha...@ti.com --- include/configs/dra7xx_evm.h |4 include/configs/omap5_common.h |1 - include/configs/omap5_uevm.h |3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index b142049..b0b0bda 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -38,4 +38,8 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1UART1_BASE #define CONFIG_BAUDRATE115200 + +/* Clock Defines */ +#define V_OSCK 2000/* Clock output from T2 */ + #endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index d57c0da..9fef21c 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -46,7 +46,6 @@ #define CONFIG_DISPLAY_BOARDINFO /* Clock Defines */ -#define V_OSCK 1920/* Clock output from T2 */ #define V_SCLK V_OSCK #define CONFIG_MISC_INIT_R diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index ba81e30..4f2d425 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -58,5 +58,8 @@ #define CONFIG_SYS_PROMPT OMAP5430 EVM # +/* Clock Defines */ +#define V_OSCK 1920/* Clock output from T2 */ + #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 #endif /* __CONFIG_OMAP5_EVM_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/12] ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 16 ++---
arch/arm/cpu/armv7/omap5/hw_data.c | 87 +++-
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap4/clocks.h |2 +-
arch/arm/include/asm/arch-omap5/clocks.h |8 ++-
arch/arm/include/asm/omap_common.h |3 +-
include/configs/dra7xx_evm.h |1 +
7 files changed, 72 insertions(+), 46 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 928327a..88d9392 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -50,13 +50,12 @@
const u32 sys_clk_array[8] = {
1200, /* 12 MHz */
- 1300, /* 13 MHz */
+ 2000, /* 20 MHz */
1680, /* 16.8 MHz */
1920, /* 19.2 MHz */
2600, /* 26 MHz */
2700, /* 27 MHz */
3840, /* 38.4 MHz */
- 2000, /* 20 MHz */
};
static inline u32 __get_sys_clk_index(void)
@@ -75,13 +74,6 @@ static inline u32 __get_sys_clk_index(void)
/* SYS_CLKSEL - 1 to match the dpll param array indices */
ind = (readl((*prcm)-cm_sys_clksel)
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
- /*
-* SYS_CLKSEL value for 20MHz is 0. This is introduced newly
-* in DRA7XX socs. SYS_CLKSEL -1 will be greater than
-* NUM_SYS_CLK. So considering the last 3 bits as the index
-* for the dpll param array.
-*/
- ind = CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
}
return ind;
}
@@ -441,6 +433,12 @@ static void setup_non_essential_dplls(void)
params = get_abe_dpll_params(*dplls_data);
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+
+ if (omap_revision() == DRA752_ES1_0)
+ /* Select the sys clk for dpll_abe */
+ clrsetbits_le32((*prcm)-cm_abe_pll_sys_clksel,
+ CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
+ CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
#else
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
/*
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 53aea93..8303390 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -100,14 +100,13 @@ static const struct dpll_params
mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
};
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
- {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},/* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},/* 16.8 MHz */
- {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},/* 19.2 MHz */
+ {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},/* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
- {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+ {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},/* 38.4 MHz */
};
static const struct dpll_params
@@ -133,15 +132,14 @@ static const struct dpll_params
};
static const struct dpll_params
- core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
- {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
- {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
- {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
+ core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
+ {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6
[U-Boot] [PATCH 08/12] ARM: DRA7xx: Correct SRAM END address
From: Sricharan R r.sricha...@ti.com
NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h |7 ---
include/configs/dra7xx_evm.h |3 +++
include/configs/omap5_uevm.h |3 +++
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index df8222a..15d429f 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -159,13 +159,6 @@ struct s32ktimer {
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
-/*
- * Non-secure SRAM Addresses
- * Non-secure RAM starts at 0x4030 for GP devices. But we keep SRAM_BASE
- * at 0x40304000(EMU base) so that our code works for both EMU and GP
- */
-#define NON_SECURE_SRAM_START 0x4030
-#define NON_SECURE_SRAM_END0x4032 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index b0b0bda..fc35f2f 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -42,4 +42,7 @@
/* Clock Defines */
#define V_OSCK 2000/* Clock output from T2 */
+#define NON_SECURE_SRAM_START 0x4030
+#define NON_SECURE_SRAM_END0x4038 /* Not inclusive */
+
#endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 4f2d425..96c5955 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -61,5 +61,8 @@
/* Clock Defines */
#define V_OSCK 1920/* Clock output from T2 */
+#define NON_SECURE_SRAM_START 0x4030
+#define NON_SECURE_SRAM_END0x4032 /* Not inclusive */
+
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
#endif /* __CONFIG_OMAP5_EVM_H */
--
1.7.9.5
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[U-Boot] [PATCH 12/12] ARM: DRA7xx: EMIF: Change settings required for EVM board
From: Sricharan R r.sricha...@ti.com
DRA7 EVM board has the below configuration. Adding the
settings for the same here.
2Gb_1_35V_DDR3L part * 2 on EMIF1
2Gb_1_35V_DDR3L part * 4 on EMIF2
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 26 +++-
arch/arm/cpu/armv7/omap5/hw_data.c | 21 +++-
arch/arm/cpu/armv7/omap5/hwinit.c| 19 +--
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/cpu/armv7/omap5/sdram.c | 170 --
arch/arm/include/asm/arch-omap5/omap.h |1 +
arch/arm/include/asm/emif.h | 12 +-
arch/arm/include/asm/omap_common.h |1 +
8 files changed, 220 insertions(+), 31 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 11e830a..f925e82 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -209,7 +209,8 @@ void emif_update_timings(u32 base, const struct emif_regs
*regs)
writel(regs-temp_alert_config, emif-emif_temp_alert_config);
writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1_shdw);
- if (omap_revision() = OMAP5430_ES1_0) {
+ if ((omap_revision() = OMAP5430_ES1_0) ||
+ (omap_revision() == DRA752_ES1_0)) {
writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
emif-emif_l3_config);
} else if (omap_revision() = OMAP4460_ES1_0) {
@@ -263,6 +264,18 @@ static void ddr3_leveling(u32 base, const struct emif_regs
*regs)
__udelay(130);
}
+static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1);
+ writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1_shdw);
+ config_data_eye_leveling_samples(base);
+
+ writel(regs-emif_rd_wr_lvl_ctl, emif-emif_rd_wr_lvl_ctl);
+ writel(regs-sdram_config, emif-emif_sdram_config);
+}
+
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -273,6 +286,7 @@ static void ddr3_init(u32 base, const struct emif_regs
*regs)
* defined, contents of mode Registers must be fully initialized.
* H/W takes care of this initialization
*/
+ writel(regs-sdram_config2, emif-emif_lpddr2_nvm_config);
writel(regs-sdram_config_init, emif-emif_sdram_config);
writel(regs-emif_ddr_phy_ctlr_1_init, emif-emif_ddr_phy_ctrl_1);
@@ -290,7 +304,10 @@ static void ddr3_init(u32 base, const struct emif_regs
*regs)
/* enable leveling */
writel(regs-emif_rd_wr_lvl_rmp_ctl, emif-emif_rd_wr_lvl_rmp_ctl);
- ddr3_leveling(base, regs);
+ if (omap_revision() == DRA752_ES1_0)
+ ddr3_sw_leveling(base, regs);
+ else
+ ddr3_leveling(base, regs);
}
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1078,7 +1095,10 @@ static void do_sdram_init(u32 base)
if (warm_reset() (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
- ddr3_leveling(base, regs);
+ if (omap_revision() == DRA752_ES1_0)
+ ddr3_sw_leveling(base, regs);
+ else
+ ddr3_leveling(base, regs);
}
/* Write to the shadow registers */
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 8303390..9374c6a 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -602,6 +602,17 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = {
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};
+const struct ctrl_ioregs ioregs_dra7xx_es1 = {
+ .ctrl_ddrch = 0x40404040,
+ .ctrl_lpddr2ch = 0x40404040,
+ .ctrl_ddr3ch = 0x80808080,
+ .ctrl_ddrio_0 = 0xbae8c631,
+ .ctrl_ddrio_1 = 0xb46318d8,
+ .ctrl_ddrio_2 = 0x8421,
+ .ctrl_emif_sdram_config_ext = 0xb2c0,
+ .ctrl_ddr_ctrl_ext_0 = 0xA200,
+};
+
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
@@ -644,14 +655,16 @@ void get_ioregs(const struct ctrl_ioregs **regs)
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = ioregs_omap5430;
- break;
+ break;
case OMAP5432_ES1_0:
*regs = ioregs_omap5432_es1;
- break;
+ break;
case OMAP5432_ES2_0:
- case DRA752_ES1_0:
*regs = ioregs_omap5432_es2;
- break;
+ break;
+ case DRA752_ES1_0:
+ *regs = ioregs_dra7xx_es1
Re: [U-Boot] [PATCH 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's
Hi, On Wednesday 29 May 2013 06:42 PM, Tom Rini wrote: On Wed, May 29, 2013 at 04:32:35PM +0530, Lokesh Vutla wrote: This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-0-3-ARM-OMAP4-Misc-Cleanup-tt155877.html Tested on DRA752 ES1.0, OMAP5432 ES2.0, MAKEALL for all armv7 board has been verified. Aside from a few comments, everything else looks good. Oh, and please test with MAKEALL -s omap as well as -c armv7, thanks! Thanks Tom. Will address your comments and post a V2. Ok will do MAKEALL for omap boards also. Regards, Lokesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 0/4] ARM: OMAP2+: Misc Cleanup
Misc cleanup.
And also adding a Generic bus init and write functions
for PMIC.
This series is applied on top of u-boot-ti:
git://git.denx.de/u-boot-ti.git
Testing:
Boot tested on OMAP5432 ES2.0, OMAP4460 PANDA.
Verified MAKEALL for armv7/omap boards.
Changes from v1:
* Created new patch for renaming arch-omap*/clocks.h to
arch-omap*/clock.h
Lokesh Vutla (3):
ARM: OMAP4+: Cleanup header files
ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h
ARM: OMAP4+: pmic: Make generic bus init and write functions
Sricharan R (1):
ARM: OMAP5: clocks: Do not enable sgx clocks
arch/arm/cpu/armv7/omap-common/clocks-common.c |8 ++---
arch/arm/cpu/armv7/omap-common/emif-common.c |2 +-
arch/arm/cpu/armv7/omap-common/vc.c| 14 -
arch/arm/cpu/armv7/omap3/clock.c |2 +-
arch/arm/cpu/armv7/omap4/hw_data.c | 13 ++--
arch/arm/cpu/armv7/omap4/prcm-regs.c |3 ++
arch/arm/cpu/armv7/omap5/hw_data.c | 11 +++
arch/arm/cpu/armv7/omap5/hwinit.c |2 +-
arch/arm/cpu/armv7/omap5/prcm-regs.c |2 ++
.../asm/arch-omap24xx/{clocks.h = clock.h}|0
.../include/asm/arch-omap3/{clocks.h = clock.h} |0
.../include/asm/arch-omap4/{clocks.h = clock.h} | 28 --
arch/arm/include/asm/arch-omap4/cpu.h | 12
arch/arm/include/asm/arch-omap4/omap.h | 14 -
arch/arm/include/asm/arch-omap4/sys_proto.h|4 +--
.../include/asm/arch-omap5/{clocks.h = clock.h} | 22 --
arch/arm/include/asm/arch-omap5/cpu.h | 12
arch/arm/include/asm/arch-omap5/omap.h | 31 +---
arch/arm/include/asm/arch-omap5/sys_proto.h|6 ++--
arch/arm/include/asm/omap_common.h |7 +++--
board/htkw/mcx/mcx.c |2 +-
board/teejet/mt_ventoux/mt_ventoux.c |2 +-
board/ti/omap2420h4/lowlevel_init.S|2 +-
board/ti/omap2420h4/mem.c |2 +-
board/ti/omap5_uevm/evm.c | 12 +---
board/ti/panda/panda.c | 22 --
board/ti/sdp4430/sdp.c | 16 ++
drivers/usb/musb/omap3.c |4 ++-
28 files changed, 87 insertions(+), 168 deletions(-)
rename arch/arm/include/asm/arch-omap24xx/{clocks.h = clock.h} (100%)
rename arch/arm/include/asm/arch-omap3/{clocks.h = clock.h} (100%)
rename arch/arm/include/asm/arch-omap4/{clocks.h = clock.h} (90%)
rename arch/arm/include/asm/arch-omap5/{clocks.h = clock.h} (90%)
--
1.7.9.5
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[U-Boot] [PATCH V2 1/4] ARM: OMAP4+: Cleanup header files
After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap4/prcm-regs.c |3 +++
arch/arm/cpu/armv7/omap5/prcm-regs.c |2 ++
arch/arm/include/asm/arch-omap4/clocks.h | 28 ---
arch/arm/include/asm/arch-omap4/cpu.h| 12
arch/arm/include/asm/arch-omap4/omap.h | 14 --
arch/arm/include/asm/arch-omap5/clocks.h | 22 -
arch/arm/include/asm/arch-omap5/cpu.h| 12
arch/arm/include/asm/arch-omap5/omap.h | 31 +-
arch/arm/include/asm/omap_common.h |4 +---
board/ti/omap5_uevm/evm.c| 12
board/ti/panda/panda.c | 20 +++
board/ti/sdp4430/sdp.c | 16 +--
drivers/usb/musb/omap3.c |4 +++-
13 files changed, 40 insertions(+), 140 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c
b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index 7225a30..7e71ca0 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -301,6 +301,8 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
.control_ldosram_iva_voltage_ctrl = 0x4A002320,
.control_ldosram_mpu_voltage_ctrl = 0x4A002324,
.control_ldosram_core_voltage_ctrl = 0x4A002328,
+ .control_usbotghs_ctrl = 0x4A00233C,
+ .control_padconf_core_base = 0x4A10,
.control_pbiaslite = 0x4A100600,
.control_lpddr2io1_0= 0x4A100638,
.control_lpddr2io1_1= 0x4A10063C,
@@ -312,4 +314,5 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
.control_lpddr2io2_3= 0x4A100654,
.control_efuse_1= 0x4A100700,
.control_efuse_2= 0x4A100704,
+ .control_padconf_wkup_base = 0x4A31E000,
};
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index e9f6a32..db779f2 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -311,6 +311,7 @@ struct prcm_regs const omap5_es1_prcm = {
struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_status = 0x4A002134,
+ .control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode= 0x4A002DA4,
.control_smart1io_padconf_0 = 0x4A002DA8,
@@ -358,6 +359,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_port_emif2_sdram_config= 0x4AE0C118,
.control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148,
+ .control_padconf_wkup_base = 0x4AE0C800,
.control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
.control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
.control_padconf_mode = 0x4AE0CDA8,
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h
b/arch/arm/include/asm/arch-omap4/clocks.h
index ed7a1c8..f544edf 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -34,25 +34,6 @@
*/
#define LDELAY 100
-#define CM_CLKMODE_DPLL_CORE 0x4A004120
-#define CM_CLKMODE_DPLL_PER0x4A008140
-#define CM_CLKMODE_DPLL_MPU0x4A004160
-#define CM_CLKSEL_CORE 0x4A004100
-
-/* DPLL register offsets */
-#define CM_CLKMODE_DPLL0
-#define CM_IDLEST_DPLL 0x4
-#define CM_AUTOIDLE_DPLL 0x8
-#define CM_CLKSEL_DPLL 0xC
-#define CM_DIV_M2_DPLL 0x10
-#define CM_DIV_M3_DPLL 0x14
-#define CM_DIV_M4_DPLL 0x18
-#define CM_DIV_M5_DPLL 0x1C
-#define CM_DIV_M6_DPLL 0x20
-#define CM_DIV_M7_DPLL 0x24
-
-#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
-
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 0)
@@ -94,8 +75,6 @@
#define CM_CLKSEL_DCC_EN_SHIFT 22
#define CM_CLKSEL_DCC_EN_MASK (1 22)
-#define OMAP4_DPLL_MAX_N 127
-
/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
@@ -181,9 +160,7 @@
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 25)
/* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ 3840
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
-#define OMAP_32K_CLK_FREQ 32768
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ400
@@ -234,11 +211,6 @@
#define ALTCLKSRC_MODE_ACTIVE 1
-/* Defines for DPLL setup */
-#define
[U-Boot] [PATCH V2 2/4] ARM: OMAP5: clocks: Do not enable sgx clocks
From: Sricharan R r.sricha...@ti.com SGX clocks should be enabled only for OMAP5 ES1.0. So this can be removed. Signed-off-by: Sricharan R r.sricha...@ti.com Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c |6 -- 1 file changed, 6 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 604fa42..842cf27 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -383,12 +383,6 @@ void enable_basic_clocks(void) clk_modules_explicit_en_essential, 1); - /* Select 384Mhz for GPU as its the POR for ES1.0 */ - setbits_le32((*prcm)-cm_sgx_sgx_clkctrl, - CLKSEL_GPU_HYD_GCLK_MASK); - setbits_le32((*prcm)-cm_sgx_sgx_clkctrl, - CLKSEL_GPU_CORE_GCLK_MASK); - /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)-cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 3/4] ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h
To be consistent with other ARM platforms,
renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |2 +-
arch/arm/cpu/armv7/omap-common/emif-common.c |2 +-
arch/arm/cpu/armv7/omap3/clock.c |2 +-
arch/arm/cpu/armv7/omap4/hw_data.c |2 +-
arch/arm/cpu/armv7/omap5/hw_data.c |2 +-
arch/arm/cpu/armv7/omap5/hwinit.c |2 +-
.../asm/arch-omap24xx/{clocks.h = clock.h}|0
.../include/asm/arch-omap3/{clocks.h = clock.h} |0
.../include/asm/arch-omap4/{clocks.h = clock.h} |0
arch/arm/include/asm/arch-omap4/sys_proto.h|2 +-
.../include/asm/arch-omap5/{clocks.h = clock.h} |0
arch/arm/include/asm/arch-omap5/sys_proto.h|4 ++--
board/htkw/mcx/mcx.c |2 +-
board/teejet/mt_ventoux/mt_ventoux.c |2 +-
board/ti/omap2420h4/lowlevel_init.S|2 +-
board/ti/omap2420h4/mem.c |2 +-
board/ti/panda/panda.c |2 +-
17 files changed, 14 insertions(+), 14 deletions(-)
rename arch/arm/include/asm/arch-omap24xx/{clocks.h = clock.h} (100%)
rename arch/arm/include/asm/arch-omap3/{clocks.h = clock.h} (100%)
rename arch/arm/include/asm/arch-omap4/{clocks.h = clock.h} (100%)
rename arch/arm/include/asm/arch-omap5/{clocks.h = clock.h} (100%)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 99910cd..e5c95db 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -32,7 +32,7 @@
#include common.h
#include asm/omap_common.h
#include asm/gpio.h
-#include asm/arch/clocks.h
+#include asm/arch/clock.h
#include asm/arch/sys_proto.h
#include asm/utils.h
#include asm/omap_gpio.h
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 11e830a..8823967 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -27,7 +27,7 @@
#include common.h
#include asm/emif.h
-#include asm/arch/clocks.h
+#include asm/arch/clock.h
#include asm/arch/sys_proto.h
#include asm/omap_common.h
#include asm/utils.h
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 09c51f6..81cc859 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -27,7 +27,7 @@
#include common.h
#include asm/io.h
-#include asm/arch/clocks.h
+#include asm/arch/clock.h
#include asm/arch/clocks_omap3.h
#include asm/arch/mem.h
#include asm/arch/sys_proto.h
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c
b/arch/arm/cpu/armv7/omap4/hw_data.c
index 06a2fc8..650319a 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -29,7 +29,7 @@
#include asm/arch/omap.h
#include asm/arch/sys_proto.h
#include asm/omap_common.h
-#include asm/arch/clocks.h
+#include asm/arch/clock.h
#include asm/omap_gpio.h
#include asm/io.h
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 842cf27..d2f5900 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -29,7 +29,7 @@
#include asm/arch/omap.h
#include asm/arch/sys_proto.h
#include asm/omap_common.h
-#include asm/arch/clocks.h
+#include asm/arch/clock.h
#include asm/omap_gpio.h
#include asm/io.h
#include asm/emif.h
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index e192fea..afb7000 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -32,7 +32,7 @@
#include asm/armv7.h
#include asm/arch/cpu.h
#include asm/arch/sys_proto.h
-#include asm/arch/clocks.h
+#include asm/arch/clock.h
#include asm/sizes.h
#include asm/utils.h
#include asm/arch/gpio.h
diff --git a/arch/arm/include/asm/arch-omap24xx/clocks.h
b/arch/arm/include/asm/arch-omap24xx/clock.h
similarity index 100%
rename from arch/arm/include/asm/arch-omap24xx/clocks.h
rename to arch/arm/include/asm/arch-omap24xx/clock.h
diff --git a/arch/arm/include/asm/arch-omap3/clocks.h
b/arch/arm/include/asm/arch-omap3/clock.h
similarity index 100%
rename from arch/arm/include/asm/arch-omap3/clocks.h
rename to arch/arm/include/asm/arch-omap3/clock.h
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h
b/arch/arm/include/asm/arch-omap4/clock.h
similarity index 100%
rename from arch/arm/include/asm/arch-omap4/clocks.h
rename to arch/arm/include/asm/arch-omap4/clock.h
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 039a1f2..1644ba6 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -22,7 +22,7 @@
#define
[U-Boot] [PATCH V2 4/4] ARM: OMAP4+: pmic: Make generic bus init and write functions
Voltage scaling can be done in two ways:
- Using SR I2C
- Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |6 ++
arch/arm/cpu/armv7/omap-common/vc.c| 14 +-
arch/arm/cpu/armv7/omap4/hw_data.c | 11 ++-
arch/arm/cpu/armv7/omap5/hw_data.c |3 +++
arch/arm/include/asm/arch-omap4/sys_proto.h|2 +-
arch/arm/include/asm/arch-omap5/sys_proto.h|2 +-
arch/arm/include/asm/omap_common.h |3 +++
7 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index e5c95db..a1ada58 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -487,6 +487,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
u32 offset = volt_mv;
int ret = 0;
+ pmic-pmic_bus_init();
/* See if we can first get the GPIO if needed */
if (pmic-gpio_en)
ret = gpio_request(pmic-gpio, PMIC_GPIO);
@@ -509,8 +510,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
debug(do_scale_vcore: volt - %d offset_code - 0x%x\n, volt_mv,
offset_code);
- if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
- vcore_reg, offset_code))
+ if (pmic-pmic_write(pmic-i2c_slave_addr, vcore_reg, offset_code))
printf(Scaling voltage failed for 0x%x\n, vcore_reg);
if (pmic-gpio_en)
@@ -525,8 +525,6 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
*/
void scale_vcores(struct vcores_data const *vcores)
{
- omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
-
do_scale_vcore(vcores-core.addr, vcores-core.value,
vcores-core.pmic);
diff --git a/arch/arm/cpu/armv7/omap-common/vc.c
b/arch/arm/cpu/armv7/omap-common/vc.c
index e6e5f78..a68f1d1 100644
--- a/arch/arm/cpu/armv7/omap-common/vc.c
+++ b/arch/arm/cpu/armv7/omap-common/vc.c
@@ -17,6 +17,7 @@
#include common.h
#include asm/omap_common.h
#include asm/arch/sys_proto.h
+#include asm/arch/clock.h
/*
* Define Master code if there are multiple masters on the I2C_SR bus.
@@ -57,7 +58,7 @@
* omap_vc_init() - Initialization for Voltage controller
* @speed_khz: I2C buspeed in KHz
*/
-void omap_vc_init(u16 speed_khz)
+static void omap_vc_init(u16 speed_khz)
{
u32 val;
u32 sys_clk_khz, cycles_hi, cycles_low;
@@ -137,3 +138,14 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8
reg_data)
/* All good.. */
return 0;
}
+
+void sri2c_init(void)
+{
+ static int sri2c = 1;
+
+ if (sri2c) {
+ omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+ sri2c = 0;
+ }
+ return;
+}
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c
b/arch/arm/cpu/armv7/omap4/hw_data.c
index 650319a..b97cad4 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -219,6 +219,9 @@ struct pmic_data twl6030_4430es1 = {
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct pmic_data twl6030 = {
@@ -226,6 +229,9 @@ struct pmic_data twl6030 = {
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct pmic_data tps62361 = {
@@ -233,7 +239,10 @@ struct pmic_data tps62361 = {
.step = 1, /* 10 mV represented in uV */
.start_code = 0,
.gpio = TPS62361_VSEL0_GPIO,
- .gpio_en = 1
+ .gpio_en = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct vcores_data omap4430_volts_es1 = {
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index d2f5900..585e318 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -289,6 +289,9 @@ struct pmic_data palmas = {
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct vcores_data omap5430_volts = {
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index
[U-Boot] [PATCH V2 01/12] ARM: DRA7xx: Add control id code for DRA7xx
The registers that are used for device identification are changed from OMAP5 to DRA7xx. Using the correct registers for DRA7xx. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- arch/arm/include/asm/arch-omap5/omap.h | 11 +-- include/configs/dra7xx_evm.h |3 ++- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 6dfedf4..3222996 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -44,8 +44,15 @@ #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_ENDOMAP54XX_DRAM_ADDR_SPACE_END -/* CONTROL_ID_CODE */ -#define CONTROL_ID_CODE0x4A002204 +/* CONTROL ID CODE */ +#define CONTROL_CORE_ID_CODE 0x4A002204 +#define CONTROL_WKUP_ID_CODE 0x4AE0C204 + +#ifdef CONFIG_DRA7XX +#define CONTROL_ID_CODECONTROL_WKUP_ID_CODE +#else +#define CONTROL_ID_CODECONTROL_CORE_ID_CODE +#endif /* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 28a306b..7826d13 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -28,11 +28,12 @@ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H +/* High Level Configuration Options */ +#define CONFIG_DRA7XX /* in a TI DRA7XX core */ #define CONFIG_ENV_IS_NOWHERE /* For now. */ #include configs/omap5_common.h -#define CONFIG_DRA7XX /* in a TI DRA7XX core */ #define CONFIG_SYS_PROMPT DRA752 EVM # #endif /* __CONFIG_DRA7XX_EVM_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 06/12] ARM: DRA7xx: Change the Debug UART to UART1
From: Sricharan R r.sricha...@ti.com Serial UART is connected to UART1. So add the change for the same. Signed-off-by: Sricharan R r.sricha...@ti.com --- include/configs/dra7xx_evm.h |3 +++ include/configs/omap5_common.h |4 include/configs/omap5_uevm.h |4 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 7826d13..35dec08 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -36,4 +36,7 @@ #define CONFIG_SYS_PROMPT DRA752 EVM # +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1UART1_BASE +#define CONFIG_BAUDRATE115200 #endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index deb5e9f..d57c0da 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -81,10 +81,6 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE(-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3UART3_BASE - -#define CONFIG_BAUDRATE115200 /* CPU */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index c791789..ba81e30 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -35,6 +35,10 @@ #include configs/omap5_common.h +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3UART3_BASE +#define CONFIG_BAUDRATE115200 + /* TWL6035 */ #ifndef CONFIG_SPL_BUILD #define CONFIG_PALMAS_POWER -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 05/12] ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c |3 +++
arch/arm/include/asm/omap_common.h |8
2 files changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index afb7000..40dbf45 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -201,6 +201,9 @@ void srcomp_enable(void)
u32 sysclk_ind = get_sys_clk_index();
u32 omap_rev= omap_revision();
+ if (!is_omap54xx())
+ return;
+
mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
div_factor = srcomp_parameters[sysclk_ind].divide_factor;
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 1435674..7007177 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -575,6 +575,14 @@ static inline u32 omap_revision(void)
extern u32 *const omap_si_rev;
return *omap_si_rev;
}
+
+#define OMAP54xx 0x5400
+
+static inline u8 is_omap54xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return ((*omap_si_rev 0xFF00) == OMAP54xx);
+}
#endif
/*
--
1.7.9.5
___
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[U-Boot] [PATCH V2 09/12] mmc: omap_hsmmc: add mmc1 pbias, ldo1
From: Balaji T K balaj...@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h |3 ++-
drivers/mmc/omap_hsmmc.c | 26 ++
drivers/power/palmas.c | 25 -
include/configs/omap5_common.h |4
include/configs/omap5_uevm.h |5 -
include/palmas.h |6 +-
6 files changed, 49 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 8105c14..9abb663 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -106,9 +106,10 @@
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 27)
#define SDCARD_PWRDNZ (1 26)
#define SDCARD_BIAS_HIZ_MODE (1 25)
-#define SDCARD_BIAS_PWRDNZ (1 22)
+#define SDCARD_BIAS_PWRDNZ2(1 22)
#define SDCARD_PBIASLITE_VMODE (1 21)
#ifndef __ASSEMBLY__
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index afdfa88..27d1f76 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -113,23 +113,25 @@ static void omap5_pbias_config(struct mmc *mmc)
u32 value = 0;
value = readl((*ctrl)-control_pbias);
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
+ value = ~SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(10); /* wait 10 us */
+ value = ~SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
- palmas_mmc1_poweron_ldo();
+#if defined(CONFIG_DRA7XX)
+ palmas_mmc1_poweron_ldo1();
+#else
+ palmas_mmc1_poweron_ldo9();
+#endif
value = readl((*ctrl)-control_pbias);
- value = ~SDCARD_BIAS_HIZ_MODE;
- value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
+ value |= SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
-
- value = readl((*ctrl)-control_pbias);
- if (value (1 23)) {
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
- writel(value, (*ctrl)-control_pbias);
- }
+ udelay(150); /* wait 150 us */
+ value |= SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(150); /* wait 150 us */
}
#endif
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 09c832d..1bcff52 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -28,7 +28,7 @@ void palmas_init_settings(void)
return;
}
-int palmas_mmc1_poweron_ldo(void)
+int palmas_mmc1_poweron_ldo9(void)
{
u8 val = 0;
@@ -50,3 +50,26 @@ int palmas_mmc1_poweron_ldo(void)
return 0;
}
+
+int palmas_mmc1_poweron_ldo1(void)
+{
+ u8 val = 0;
+
+ /* set LDO9 TWL6035 to 3V */
+ val = 0x2b; /* (3 - 0.9) * 20 + 1 */
+
+ if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_VOLTAGE, val)) {
+ printf(tps659038: could not set LDO1 voltage\n);
+ return 1;
+ }
+
+ /* TURN ON LDO9 */
+ val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
+
+ if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_CTRL, val)) {
+ printf(tps659038: could not turn on LDO1\n);
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index 83b91d1..ddf2ad4 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -238,6 +238,10 @@
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PALMAS_POWER
+#endif
+
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index ba81e30..f4a2d31 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -39,11 +39,6 @@
#define CONFIG_SYS_NS16550_COM3UART3_BASE
#define CONFIG_BAUDRATE115200
-/* TWL6035 */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PALMAS_POWER
-#endif
-
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
diff --git a/include/palmas.h b/include/palmas.h
index 3b18589..4218e18 100644
--- a/include/palmas.h
+++ b/include/palmas.h
@@ -28,8 +28,11 @@
/* I2C chip addresses */
#define PALMAS_CHIP_ADDR 0x48
+#define TPS659038_CHIP_ADDR0x58
/* 0x1XY translates to page 1, register address 0xXY */
+#define LDO1_CTRL 0x50
+#define LDO1_VOLTAGE
[U-Boot] [PATCH V2 02/12] ARM: DRA7xx: power Add support for tps659038 PMIC
TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 23 ++
arch/arm/cpu/armv7/omap5/hw_data.c | 38 +++-
arch/arm/include/asm/arch-omap4/sys_proto.h|1 +
arch/arm/include/asm/arch-omap5/clock.h| 15 ++
arch/arm/include/asm/arch-omap5/sys_proto.h|1 +
arch/arm/include/asm/omap_common.h |3 ++
6 files changed, 80 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index a1ada58..dc57516 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -30,6 +30,7 @@
* MA 02111-1307 USA
*/
#include common.h
+#include i2c.h
#include asm/omap_common.h
#include asm/gpio.h
#include asm/arch/clock.h
@@ -487,6 +488,9 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
u32 offset = volt_mv;
int ret = 0;
+ if (!volt_mv)
+ return;
+
pmic-pmic_bus_init();
/* See if we can first get the GPIO if needed */
if (pmic-gpio_en)
@@ -534,6 +538,15 @@ void scale_vcores(struct vcores_data const *vcores)
do_scale_vcore(vcores-mm.addr, vcores-mm.value,
vcores-mm.pmic);
+ do_scale_vcore(vcores-gpu.addr, vcores-gpu.value,
+ vcores-gpu.pmic);
+
+ do_scale_vcore(vcores-eve.addr, vcores-eve.value,
+ vcores-eve.pmic);
+
+ do_scale_vcore(vcores-iva.addr, vcores-iva.value,
+ vcores-iva.pmic);
+
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM magic bits */
writel(2, (*prcm)-prm_sldo_core_setup);
@@ -723,3 +736,13 @@ void prcm_init(void)
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
enable_basic_uboot_clocks();
}
+
+void gpi2c_init(void)
+{
+ static int gpi2c = 1;
+
+ if (gpi2c) {
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ gpi2c = 0;
+ }
+}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 585e318..90274a0 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -26,6 +26,7 @@
* MA 02111-1307 USA
*/
#include common.h
+#include palmas.h
#include asm/arch/omap.h
#include asm/arch/sys_proto.h
#include asm/omap_common.h
@@ -294,6 +295,19 @@ struct pmic_data palmas = {
.pmic_write = omap_vc_bypass_send_value,
};
+struct pmic_data tps659038 = {
+ .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+ .step = 1, /* 10 mV represented in uV */
+ /*
+* Offset codes 1-6 all give the base voltage in Palmas
+* Offset code 0 switches OFF the SMPS
+*/
+ .start_code = 6,
+ .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
+ .pmic_bus_init = gpi2c_init,
+ .pmic_write = palmas_i2c_write_u8,
+};
+
struct vcores_data omap5430_volts = {
.mpu.value = VDD_MPU,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
@@ -322,6 +336,28 @@ struct vcores_data omap5430_volts_es2 = {
.mm.pmic = palmas,
};
+struct vcores_data dra752_volts = {
+ .mpu.value = VDD_MPU_DRA752,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
+ .mpu.pmic = tps659038,
+
+ .eve.value = VDD_EVE_DRA752,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
+ .eve.pmic = tps659038,
+
+ .gpu.value = VDD_GPU_DRA752,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
+ .gpu.pmic = tps659038,
+
+ .core.value = VDD_CORE_DRA752,
+ .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
+ .core.pmic = tps659038,
+
+ .iva.value = VDD_IVA_DRA752,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
+ .iva.pmic = tps659038,
+};
+
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
@@ -562,7 +598,7 @@ void hw_data_init(void)
case DRA752_ES1_0:
*prcm = dra7xx_prcm;
*dplls_data = dra7xx_dplls;
- *omap_vcores = omap5430_volts_es2;
+ *omap_vcores = dra752_volts;
*ctrl = dra7xx_ctrl;
break;
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 38d4768..14479ba 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -57,6 +57,7 @@ u32 cortex_rev(void);
void init_omap_revision(void);
void do_io_settings(void);
void sri2c_init(void);
+void gpi2c_init(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void
[U-Boot] [PATCH V2 04/12] ARM: OMAP5: DRA7xx: support class 0 optimized voltages
From: Nishanth Menon n...@ti.com
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.
This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 58 +++-
arch/arm/cpu/armv7/omap5/hw_data.c | 10
arch/arm/include/asm/arch-omap5/clock.h| 30
arch/arm/include/asm/omap_common.h | 11 +
4 files changed, 97 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 0a5bda5..64fffd3 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -521,6 +521,38 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
gpio_direction_output(pmic-gpio, 1);
}
+static u32 optimize_vcore_voltage(struct volts const *v)
+{
+ u32 val;
+ if (!v-value)
+ return 0;
+ if (!v-efuse.reg)
+ return v-value;
+
+ switch (v-efuse.reg_bits) {
+ case 16:
+ val = readw(v-efuse.reg);
+ break;
+ case 32:
+ val = readl(v-efuse.reg);
+ break;
+ default:
+ printf(Error: efuse 0x%08x bits=%d unknown\n,
+ v-efuse.reg, v-efuse.reg_bits);
+ return v-value;
+ }
+
+ if (!val) {
+ printf(Error: efuse 0x%08x bits=%d val=0, using %d\n,
+ v-efuse.reg, v-efuse.reg_bits, v-value);
+ return v-value;
+ }
+
+ debug(%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n,
+ __func__, v-efuse.reg, v-efuse.reg_bits, v-value, val);
+ return val;
+}
+
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
@@ -529,23 +561,25 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct
pmic_data *pmic)
*/
void scale_vcores(struct vcores_data const *vcores)
{
- do_scale_vcore(vcores-core.addr, vcores-core.value,
- vcores-core.pmic);
+ u32 val;
+
+ val = optimize_vcore_voltage(vcores-core);
+ do_scale_vcore(vcores-core.addr, val, vcores-core.pmic);
- do_scale_vcore(vcores-mpu.addr, vcores-mpu.value,
- vcores-mpu.pmic);
+ val = optimize_vcore_voltage(vcores-mpu);
+ do_scale_vcore(vcores-mpu.addr, val, vcores-mpu.pmic);
- do_scale_vcore(vcores-mm.addr, vcores-mm.value,
- vcores-mm.pmic);
+ val = optimize_vcore_voltage(vcores-mm);
+ do_scale_vcore(vcores-mm.addr, val, vcores-mm.pmic);
- do_scale_vcore(vcores-gpu.addr, vcores-gpu.value,
- vcores-gpu.pmic);
+ val = optimize_vcore_voltage(vcores-gpu);
+ do_scale_vcore(vcores-gpu.addr, val, vcores-gpu.pmic);
- do_scale_vcore(vcores-eve.addr, vcores-eve.value,
- vcores-eve.pmic);
+ val = optimize_vcore_voltage(vcores-eve);
+ do_scale_vcore(vcores-eve.addr, val, vcores-eve.pmic);
- do_scale_vcore(vcores-iva.addr, vcores-iva.value,
- vcores-iva.pmic);
+ val = optimize_vcore_voltage(vcores-iva);
+ do_scale_vcore(vcores-iva.addr, val, vcores-iva.pmic);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM magic bits */
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 90274a0..bddcaed 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -338,22 +338,32 @@ struct vcores_data omap5430_volts_es2 = {
struct vcores_data dra752_volts = {
.mpu.value = VDD_MPU_DRA752,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
.mpu.pmic = tps659038,
.eve.value = VDD_EVE_DRA752,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
.eve.pmic = tps659038,
.gpu.value = VDD_GPU_DRA752,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
.gpu.pmic = tps659038,
.core.value = VDD_CORE_DRA752,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM
[U-Boot] [PATCH V2 11/12] ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 16 ++---
arch/arm/cpu/armv7/omap5/hw_data.c | 87 +++-
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap4/clock.h|2 +-
arch/arm/include/asm/arch-omap5/clock.h|8 ++-
arch/arm/include/asm/omap_common.h |3 +-
include/configs/dra7xx_evm.h |2 +
7 files changed, 73 insertions(+), 46 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 64fffd3..2e5a01e 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -50,13 +50,12 @@
const u32 sys_clk_array[8] = {
1200, /* 12 MHz */
- 1300, /* 13 MHz */
+ 2000, /* 20 MHz */
1680, /* 16.8 MHz */
1920, /* 19.2 MHz */
2600, /* 26 MHz */
2700, /* 27 MHz */
3840, /* 38.4 MHz */
- 2000, /* 20 MHz */
};
static inline u32 __get_sys_clk_index(void)
@@ -75,13 +74,6 @@ static inline u32 __get_sys_clk_index(void)
/* SYS_CLKSEL - 1 to match the dpll param array indices */
ind = (readl((*prcm)-cm_sys_clksel)
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
- /*
-* SYS_CLKSEL value for 20MHz is 0. This is introduced newly
-* in DRA7XX socs. SYS_CLKSEL -1 will be greater than
-* NUM_SYS_CLK. So considering the last 3 bits as the index
-* for the dpll param array.
-*/
- ind = CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
}
return ind;
}
@@ -441,6 +433,12 @@ static void setup_non_essential_dplls(void)
params = get_abe_dpll_params(*dplls_data);
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+
+ if (omap_revision() == DRA752_ES1_0)
+ /* Select the sys clk for dpll_abe */
+ clrsetbits_le32((*prcm)-cm_abe_pll_sys_clksel,
+ CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
+ CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
#else
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
/*
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index bddcaed..44552c3 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -100,14 +100,13 @@ static const struct dpll_params
mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
};
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
- {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},/* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},/* 16.8 MHz */
- {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},/* 19.2 MHz */
+ {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},/* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
- {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+ {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},/* 38.4 MHz */
};
static const struct dpll_params
@@ -133,15 +132,14 @@ static const struct dpll_params
};
static const struct dpll_params
- core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
- {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
- {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
- {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
+ core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
+ {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6
[U-Boot] [PATCH V2 12/12] ARM: DRA7xx: EMIF: Change settings required for EVM board
From: Sricharan R r.sricha...@ti.com
DRA7 EVM board has the below configuration. Adding the
settings for the same here.
2Gb_1_35V_DDR3L part * 2 on EMIF1
2Gb_1_35V_DDR3L part * 4 on EMIF2
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 26 +++-
arch/arm/cpu/armv7/omap5/hw_data.c | 21 +++-
arch/arm/cpu/armv7/omap5/hwinit.c| 19 +--
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/cpu/armv7/omap5/sdram.c | 170 --
arch/arm/include/asm/arch-omap5/omap.h |1 +
arch/arm/include/asm/emif.h | 12 +-
arch/arm/include/asm/omap_common.h |1 +
8 files changed, 220 insertions(+), 31 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 8823967..652e5a7 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -209,7 +209,8 @@ void emif_update_timings(u32 base, const struct emif_regs
*regs)
writel(regs-temp_alert_config, emif-emif_temp_alert_config);
writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1_shdw);
- if (omap_revision() = OMAP5430_ES1_0) {
+ if ((omap_revision() = OMAP5430_ES1_0) ||
+ (omap_revision() == DRA752_ES1_0)) {
writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
emif-emif_l3_config);
} else if (omap_revision() = OMAP4460_ES1_0) {
@@ -263,6 +264,18 @@ static void ddr3_leveling(u32 base, const struct emif_regs
*regs)
__udelay(130);
}
+static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1);
+ writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1_shdw);
+ config_data_eye_leveling_samples(base);
+
+ writel(regs-emif_rd_wr_lvl_ctl, emif-emif_rd_wr_lvl_ctl);
+ writel(regs-sdram_config, emif-emif_sdram_config);
+}
+
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -273,6 +286,7 @@ static void ddr3_init(u32 base, const struct emif_regs
*regs)
* defined, contents of mode Registers must be fully initialized.
* H/W takes care of this initialization
*/
+ writel(regs-sdram_config2, emif-emif_lpddr2_nvm_config);
writel(regs-sdram_config_init, emif-emif_sdram_config);
writel(regs-emif_ddr_phy_ctlr_1_init, emif-emif_ddr_phy_ctrl_1);
@@ -290,7 +304,10 @@ static void ddr3_init(u32 base, const struct emif_regs
*regs)
/* enable leveling */
writel(regs-emif_rd_wr_lvl_rmp_ctl, emif-emif_rd_wr_lvl_rmp_ctl);
- ddr3_leveling(base, regs);
+ if (omap_revision() == DRA752_ES1_0)
+ ddr3_sw_leveling(base, regs);
+ else
+ ddr3_leveling(base, regs);
}
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1078,7 +1095,10 @@ static void do_sdram_init(u32 base)
if (warm_reset() (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
- ddr3_leveling(base, regs);
+ if (omap_revision() == DRA752_ES1_0)
+ ddr3_sw_leveling(base, regs);
+ else
+ ddr3_leveling(base, regs);
}
/* Write to the shadow registers */
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 44552c3..56cf1f8 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -602,6 +602,17 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = {
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};
+const struct ctrl_ioregs ioregs_dra7xx_es1 = {
+ .ctrl_ddrch = 0x40404040,
+ .ctrl_lpddr2ch = 0x40404040,
+ .ctrl_ddr3ch = 0x80808080,
+ .ctrl_ddrio_0 = 0xbae8c631,
+ .ctrl_ddrio_1 = 0xb46318d8,
+ .ctrl_ddrio_2 = 0x8421,
+ .ctrl_emif_sdram_config_ext = 0xb2c0,
+ .ctrl_ddr_ctrl_ext_0 = 0xA200,
+};
+
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
@@ -644,14 +655,16 @@ void get_ioregs(const struct ctrl_ioregs **regs)
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = ioregs_omap5430;
- break;
+ break;
case OMAP5432_ES1_0:
*regs = ioregs_omap5432_es1;
- break;
+ break;
case OMAP5432_ES2_0:
- case DRA752_ES1_0:
*regs = ioregs_omap5432_es2;
- break;
+ break;
+ case DRA752_ES1_0:
+ *regs = ioregs_dra7xx_es1
[U-Boot] [PATCH V2 03/12] ARM: DRA7xx: clocks: Fixing i2c_init for PMIC
In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c |1 + arch/arm/cpu/armv7/omap-common/hwinit-common.c |2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index dc57516..0a5bda5 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -721,6 +721,7 @@ void prcm_init(void) case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: enable_basic_clocks(); + timer_init(); scale_vcores(*omap_vcores); setup_dplls(); #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 1645120..5602b0e 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -202,8 +202,6 @@ void s_init(void) #endif prcm_init(); #ifdef CONFIG_SPL_BUILD - timer_init(); - /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 08/12] ARM: DRA7xx: Correct SRAM END address
From: Sricharan R r.sricha...@ti.com
NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 3222996..8105c14 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -169,13 +169,14 @@ struct s32ktimer {
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
-/*
- * Non-secure SRAM Addresses
- * Non-secure RAM starts at 0x4030 for GP devices. But we keep SRAM_BASE
- * at 0x40304000(EMU base) so that our code works for both EMU and GP
- */
+#ifdef CONFIG_DRA7XX
+#define NON_SECURE_SRAM_START 0x4030
+#define NON_SECURE_SRAM_END0x4038 /* Not inclusive */
+#else
#define NON_SECURE_SRAM_START 0x4030
#define NON_SECURE_SRAM_END0x4032 /* Not inclusive */
+#endif
+
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
--
1.7.9.5
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[U-Boot] [PATCH V2 10/12] ARM: DRA7xx: Update pinmux data
Updating pinmux data as specified in the latest DM
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Balaji T K balaj...@ti.com
---
arch/arm/include/asm/arch-omap5/mux_dra7xx.h |7 +++--
board/ti/dra7xx/mux_data.h | 38 --
2 files changed, 29 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
index 55e9de6..5f2b0f9 100644
--- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
+++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
@@ -28,11 +28,14 @@
#include asm/types.h
+#define FSC(1 19)
+#define SSC(0 19)
+
#define IEN(1 18)
#define IDIS (0 18)
-#define PTU(3 16)
-#define PTD(1 16)
+#define PTU(1 17)
+#define PTD(0 17)
#define PEN(1 16)
#define PDIS (0 16)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 04c95fd..338a241 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -29,19 +29,29 @@
#include asm/arch/mux_dra7xx.h
const struct pad_conf_entry core_padconf_array_essential[] = {
- {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */
- {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */
- {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */
- {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */
- {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */
- {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */
- {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */
- {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */
- {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */
- {UART1_TXD, (M0)}, /* UART1_TXD */
- {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */
- {UART1_RTSN, (M0)}, /* UART1_RTSN */
- {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */
- {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */
+ {MMC1_CLK, (IEN | PTU | PDIS | M0)},/* MMC1_CLK */
+ {MMC1_CMD, (IEN | PTU | PDIS | M0)},/* MMC1_CMD */
+ {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+ {GPMC_A19, (IEN | PTU | PDIS | M1)},/* mmc2_dat4 */
+ {GPMC_A20, (IEN | PTU | PDIS | M1)},/* mmc2_dat5 */
+ {GPMC_A21, (IEN | PTU | PDIS | M1)},/* mmc2_dat6 */
+ {GPMC_A22, (IEN | PTU | PDIS | M1)},/* mmc2_dat7 */
+ {GPMC_A23, (IEN | PTU | PDIS | M1)},/* mmc2_clk */
+ {GPMC_A24, (IEN | PTU | PDIS | M1)},/* mmc2_dat0 */
+ {GPMC_A25, (IEN | PTU | PDIS | M1)},/* mmc2_dat1 */
+ {GPMC_A26, (IEN | PTU | PDIS | M1)},/* mmc2_dat2 */
+ {GPMC_A27, (IEN | PTU | PDIS | M1)},/* mmc2_dat3 */
+ {GPMC_CS1, (IEN | PTU | PDIS | M1)},/* mmm2_cmd */
+ {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
+ {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
+ {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
+ {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
+ {I2C1_SDA, (IEN | PTU | PDIS | M0)},/* I2C1_SDA */
+ {I2C1_SCL, (IEN | PTU | PDIS | M0)},/* I2C1_SCL */
};
#endif /* _MUX_DATA_DRA7XX_H_ */
--
1.7.9.5
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[U-Boot] [PATCH V2 07/12] ARM: DRA7xx: Correct the SYS_CLK to 20MHZ
From: Sricharan R r.sricha...@ti.com
The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/timer.c |1 +
arch/arm/include/asm/arch-omap4/clock.h |4
arch/arm/include/asm/arch-omap5/clock.h |8
include/configs/omap4_common.h |4
include/configs/omap5_common.h |4
5 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c
b/arch/arm/cpu/armv7/omap-common/timer.c
index 507f687..5926a5a 100644
--- a/arch/arm/cpu/armv7/omap-common/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -35,6 +35,7 @@
#include common.h
#include asm/io.h
#include asm/arch/cpu.h
+#include asm/arch/clock.h
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-omap4/clock.h
b/arch/arm/include/asm/arch-omap4/clock.h
index f544edf..d7b61c2 100644
--- a/arch/arm/include/asm/arch-omap4/clock.h
+++ b/arch/arm/include/asm/arch-omap4/clock.h
@@ -214,6 +214,10 @@
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
+/* Clock Defines */
+#define V_OSCK 3840/* Clock output from T2 */
+#define V_SCLK V_OSCK
+
struct omap4_scrm_regs {
u32 revision; /* 0x */
u32 pad00[63];
diff --git a/arch/arm/include/asm/arch-omap5/clock.h
b/arch/arm/include/asm/arch-omap5/clock.h
index 6d02835..86d4711 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -284,4 +284,12 @@
* into microsec and passing the value.
*/
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC31219
+
+#ifdef CONFIG_DRA7XX
+#define V_OSCK 2000/* Clock output from T2 */
+#else
+#define V_OSCK 1920/* Clock output from T2 */
+#endif
+
+#define V_SCLK V_OSCK
#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index d6448b0..3e5d36b 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -45,10 +45,6 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Clock Defines */
-#define V_OSCK 3840/* Clock output from T2 */
-#define V_SCLK V_OSCK
-
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index d57c0da..83b91d1 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -45,10 +45,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-/* Clock Defines */
-#define V_OSCK 1920/* Clock output from T2 */
-#define V_SCLK V_OSCK
-
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT
--
1.7.9.5
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[U-Boot] [PATCH V2 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's
This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-OMAP2-Misc-Cleanup-tt155949.html Testing: Boot tested on DRA752 ES1.0, OMAP5432 ES2.0, OMAP4460 PANDA Verified MAKEALL for armv7 and omap boards. Changes from v1: * Addressed comments from Tom Rini Balaji T K (1): mmc: omap_hsmmc: add mmc1 pbias, ldo1 Lokesh Vutla (6): ARM: DRA7xx: Add control id code for DRA7xx ARM: DRA7xx: power Add support for tps659038 PMIC ARM: DRA7xx: clocks: Fixing i2c_init for PMIC ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's ARM: DRA7xx: Update pinmux data ARM: DRA7xx: clocks: Update PLL values Nishanth Menon (1): ARM: OMAP5: DRA7xx: support class 0 optimized voltages Sricharan R (4): ARM: DRA7xx: Change the Debug UART to UART1 ARM: DRA7xx: Correct the SYS_CLK to 20MHZ ARM: DRA7xx: Correct SRAM END address ARM: DRA7xx: EMIF: Change settings required for EVM board arch/arm/cpu/armv7/omap-common/clocks-common.c | 86 +--- arch/arm/cpu/armv7/omap-common/emif-common.c | 26 +++- arch/arm/cpu/armv7/omap-common/hwinit-common.c |2 - arch/arm/cpu/armv7/omap-common/timer.c |1 + arch/arm/cpu/armv7/omap5/hw_data.c | 156 -- arch/arm/cpu/armv7/omap5/hwinit.c | 22 ++- arch/arm/cpu/armv7/omap5/prcm-regs.c |2 + arch/arm/cpu/armv7/omap5/sdram.c | 170 ++-- arch/arm/include/asm/arch-omap4/clock.h|6 +- arch/arm/include/asm/arch-omap4/sys_proto.h|1 + arch/arm/include/asm/arch-omap5/clock.h| 61 - arch/arm/include/asm/arch-omap5/mux_dra7xx.h |7 +- arch/arm/include/asm/arch-omap5/omap.h | 26 ++-- arch/arm/include/asm/arch-omap5/sys_proto.h|1 + arch/arm/include/asm/emif.h| 12 +- arch/arm/include/asm/omap_common.h | 26 +++- board/ti/dra7xx/mux_data.h | 38 -- drivers/mmc/omap_hsmmc.c | 26 ++-- drivers/power/palmas.c | 25 +++- include/configs/dra7xx_evm.h |8 +- include/configs/omap4_common.h |4 - include/configs/omap5_common.h | 12 +- include/configs/omap5_uevm.h |7 +- include/palmas.h |6 +- 24 files changed, 590 insertions(+), 141 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 09/12] mmc: omap_hsmmc: add mmc1 pbias, ldo1
Hi Lubomir,
On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balaj...@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h |3 ++-
drivers/mmc/omap_hsmmc.c | 26 ++
drivers/power/palmas.c | 25 -
include/configs/omap5_common.h |4
include/configs/omap5_uevm.h |5 -
include/palmas.h |6 +-
6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 09c832d..1bcff52 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -28,7 +28,7 @@ void palmas_init_settings(void)
return;
}
-int palmas_mmc1_poweron_ldo(void)
+int palmas_mmc1_poweron_ldo9(void)
{
u8 val = 0;
@@ -50,3 +50,26 @@ int palmas_mmc1_poweron_ldo(void)
return 0;
}
+
+int palmas_mmc1_poweron_ldo1(void)
+{
+ u8 val = 0;
+
+ /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with
TPS659038), you should add some comment above.
Ok ll add the comment.
+ val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from
http://patchwork.ozlabs.org/patch/244103/ where some values are
defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
+
+ if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_VOLTAGE, val)) {
+ printf(tps659038: could not set LDO1 voltage\n);
+ return 1;
+ }
+
+ /* TURN ON LDO9 */
LDO9?
+ val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
Bit LDO_ON in all LDOx_CTRL Palmas registers is Read-Only (and reflects the
current status of the LDO). While it makes no harm to try writing to it, this
may be misleading about actual LDO operation, and anyway has no sense.
Yes, I see a similar update in your patch for LDO9. ll do the same for
LDO1 also.
Thanks
Lokesh
+
+ if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_CTRL, val)) {
+ printf(tps659038: could not turn on LDO1\n);
+ return 1;
+ }
+
[snip]
/* I2C chip addresses */
#define PALMAS_CHIP_ADDR 0x48
+#define TPS659038_CHIP_ADDR0x58
Now we have a mess again. The files were recently renamed from twl6035.x
to palmas.x, implying that palmas is the generic family name of a series
of PMICs. Having TPS659038_CHIP_ADDR above is OK, but then we should have
TWL603X_CHIP_ADDR instead of PALMAS_CHIP_ADDR.
Best regards,
Lubomir
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[U-Boot] [PATCH V3] mmc: omap_hsmmc: add mmc1 pbias, ldo1
From: Balaji T K balaj...@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
* Addressed comments from lpo...@mm-sol.com
* Rebased on top of
http://patchwork.ozlabs.org/patch/244103/
arch/arm/include/asm/arch-omap5/omap.h |2 +-
drivers/mmc/omap_hsmmc.c | 26 ++
drivers/power/palmas.c | 25 -
include/configs/omap5_common.h |4
include/configs/omap5_uevm.h |5 -
include/palmas.h |8 +++-
6 files changed, 50 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 8105c14..1076494 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -106,9 +106,9 @@
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 27)
#define SDCARD_PWRDNZ (1 26)
#define SDCARD_BIAS_HIZ_MODE (1 25)
-#define SDCARD_BIAS_PWRDNZ (1 22)
#define SDCARD_PBIASLITE_VMODE (1 21)
#ifndef __ASSEMBLY__
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index afdfa88..3d3281e 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -113,23 +113,25 @@ static void omap5_pbias_config(struct mmc *mmc)
u32 value = 0;
value = readl((*ctrl)-control_pbias);
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
+ value = ~SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(10); /* wait 10 us */
+ value = ~SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
- palmas_mmc1_poweron_ldo();
+#if defined(CONFIG_DRA7XX)
+ tps659038_mmc1_poweron_ldo1();
+#else
+ palmas_mmc1_poweron_ldo9();
+#endif
value = readl((*ctrl)-control_pbias);
- value = ~SDCARD_BIAS_HIZ_MODE;
- value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
+ value |= SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
-
- value = readl((*ctrl)-control_pbias);
- if (value (1 23)) {
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
- writel(value, (*ctrl)-control_pbias);
- }
+ udelay(150); /* wait 150 us */
+ value |= SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(150); /* wait 150 us */
}
#endif
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 1f9bd7e..b94ed5d 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -37,7 +37,7 @@ void palmas_init_settings(void)
#endif
}
-int palmas_mmc1_poweron_ldo(void)
+int palmas_mmc1_poweron_ldo9(void)
{
u8 val = 0;
@@ -56,6 +56,29 @@ int palmas_mmc1_poweron_ldo(void)
return 0;
}
+int tps659038_mmc1_poweron_ldo1(void)
+{
+ u8 val = 0;
+
+ /* set LDO1 to 3V */
+ val = LDO_VOLT_3V0;
+
+ if (palmas_i2c_write_u8(TPS659038_CHIP_P1, LDO1_VOLTAGE, val)) {
+ printf(tps659038: could not set LDO1 voltage\n);
+ return 1;
+ }
+
+ /* TURN ON LDO1 */
+ val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
+
+ if (palmas_i2c_write_u8(TPS659038_CHIP_P1, LDO1_CTRL, val)) {
+ printf(tps659038: could not turn on LDO1\n);
+ return 1;
+ }
+
+ return 0;
+}
+
/*
* On some hardware the SD card socket and LDO9_IN are powered by an
* external 3.3 V regulator, while the output of LDO9 delivers VDDS_SDCARD
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index 83b91d1..ddf2ad4 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -238,6 +238,10 @@
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PALMAS_POWER
+#endif
+
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index ba81e30..f4a2d31 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -39,11 +39,6 @@
#define CONFIG_SYS_NS16550_COM3UART3_BASE
#define CONFIG_BAUDRATE115200
-/* TWL6035 */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PALMAS_POWER
-#endif
-
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
diff --git a/include/palmas.h b/include/palmas.h
index 7becb97..2355801 100644
--- a/include/palmas.h
+++ b/include/palmas.h
@@ -30,9 +30,14 @@
#define PALMAS_CHIP_P1 0x48
Re: [U-Boot] [PATCH V2 09/12] mmc: omap_hsmmc: add mmc1 pbias, ldo1
Hi Lubomir,,
On Tuesday 04 June 2013 01:28 AM, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir,
On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balaj...@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h |3 ++-
drivers/mmc/omap_hsmmc.c | 26 ++
drivers/power/palmas.c | 25 -
include/configs/omap5_common.h |4
include/configs/omap5_uevm.h |5 -
include/palmas.h |6 +-
6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
+ /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with
TPS659038), you should add some comment above.
Ok ll add the comment.
+ val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from
http://patchwork.ozlabs.org/patch/244103/ where some values are
defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/
tested/acked/nacked/whatever by nobody (except possibly a quick look by
Nishanth Menon, who had some objections). I wrote it when bringing up a
custom OMAP5 board, and most probably it shall not go into mainline in
its current form, if ever. I gave it only as an example of how things
could be done cleaner. Feel free to use the code as you wish, but I'm
afraid that applying it as a patch to your tree and basing upon it might
run you into problems when you later sync with mainline.
Ahh sorry, I was in a dilemma whether to ask this or not. Since it is
posted I assumed
that the patch ll get merged. I have already posted a patch on top of
your patch.
Ill wait for Tom to comment.
Tom, your opinion?
+
+ if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_VOLTAGE, val)) {
+ printf(tps659038: could not set LDO1 voltage\n);
+ return 1;
+ }
+
+ /* TURN ON LDO9 */
LDO9?
+ val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
Bit LDO_ON in all LDOx_CTRL Palmas registers is Read-Only (and reflects the
current status of the LDO). While it makes no harm to try writing to it, this
may be misleading about actual LDO operation, and anyway has no sense.
Yes, I see a similar update in your patch for LDO9. ll do the same for
LDO1 also.
But are you sure that the TPS659038 has the same LDOx_CTRL register layout
as the TWL6035/37? It belongs to the family, yes, but I don't have a
Register Manual for this chip... Hope you have checked.
Yes, TPS659038 has same LDOx_CTRL register layout.
Thanks,
Lokesh
Thanks
Lokesh
[snip]
Best regards,
Lubo
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Re: [U-Boot] [PATCH V2 09/12] mmc: omap_hsmmc: add mmc1 pbias, ldo1
On Wednesday 05 June 2013 02:36 AM, Tom Rini wrote: On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote: Hi Lokesh, Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote: Hi Lokesh, On 30/05/13 16:19, Lokesh Vutla wrote: From: Balaji T K balaj...@ti.com add dra mmc pbias support and ldo1 power on Signed-off-by: Balaji T K balaj...@ti.com Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- arch/arm/include/asm/arch-omap5/omap.h |3 ++- drivers/mmc/omap_hsmmc.c | 26 ++ drivers/power/palmas.c | 25 - include/configs/omap5_common.h |4 include/configs/omap5_uevm.h |5 - include/palmas.h |6 +- 6 files changed, 49 insertions(+), 20 deletions(-) [snip] + /* set LDO9 TWL6035 to 3V */ LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above. Ok ll add the comment. + val = 0x2b; /* (3 - 0.9) * 20 + 1 */ Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined. Yes, Ill rebase this patch on top of your patch and use those defines. Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline. Tom, your opinion? OK, so at the time it was nothing will really use this code except test functions. Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants. Ok. Ill add the first patch + cleanups and resend it. Thanks, Lokesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V4 09/12] mmc: omap_hsmmc: add mmc1 pbias, ldo1
From: Balaji T K balaj...@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V3:
* Addressed comments from Tom
arch/arm/include/asm/arch-omap5/omap.h |2 +-
drivers/mmc/omap_hsmmc.c | 26 +++---
drivers/power/palmas.c | 37 ++--
include/configs/omap5_common.h |4
include/configs/omap5_uevm.h |5 -
include/palmas.h | 12 +--
6 files changed, 59 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 9010666..abf6837 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -106,9 +106,9 @@
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 27)
#define SDCARD_PWRDNZ (1 26)
#define SDCARD_BIAS_HIZ_MODE (1 25)
-#define SDCARD_BIAS_PWRDNZ (1 22)
#define SDCARD_PBIASLITE_VMODE (1 21)
#ifndef __ASSEMBLY__
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index afdfa88..3d3281e 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -113,23 +113,25 @@ static void omap5_pbias_config(struct mmc *mmc)
u32 value = 0;
value = readl((*ctrl)-control_pbias);
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
+ value = ~SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(10); /* wait 10 us */
+ value = ~SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
- palmas_mmc1_poweron_ldo();
+#if defined(CONFIG_DRA7XX)
+ tps659038_mmc1_poweron_ldo1();
+#else
+ palmas_mmc1_poweron_ldo9();
+#endif
value = readl((*ctrl)-control_pbias);
- value = ~SDCARD_BIAS_HIZ_MODE;
- value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
+ value |= SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
-
- value = readl((*ctrl)-control_pbias);
- if (value (1 23)) {
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
- writel(value, (*ctrl)-control_pbias);
- }
+ udelay(150); /* wait 150 us */
+ value |= SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(150); /* wait 150 us */
}
#endif
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 09c832d..71c4bdc 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -28,23 +28,46 @@ void palmas_init_settings(void)
return;
}
-int palmas_mmc1_poweron_ldo(void)
+int palmas_mmc1_poweron_ldo9(void)
{
u8 val = 0;
/* set LDO9 TWL6035 to 3V */
- val = 0x2b; /* (3 -.9)*28 +1 */
+ val = LDO_VOLT_3V0;
- if (palmas_i2c_write_u8(0x48, LDO9_VOLTAGE, val)) {
- printf(twl6035: could not set LDO9 voltage.\n);
+ if (palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_VOLTAGE, val)) {
+ printf(twl603x: could not set LDO9 voltage.\n);
return 1;
}
/* TURN ON LDO9 */
- val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
+ val = LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
- if (palmas_i2c_write_u8(0x48, LDO9_CTRL, val)) {
- printf(twl6035: could not turn on LDO9.\n);
+ if (palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_CTRL, val)) {
+ printf(twl603x: could not turn on LDO9.\n);
+ return 1;
+ }
+
+ return 0;
+}
+
+int tps659038_mmc1_poweron_ldo1(void)
+{
+ u8 val = 0;
+
+ /* set LDO1 to 3V */
+ val = LDO_VOLT_3V0;
+
+ if (palmas_i2c_write_u8(TPS659038_CHIP_P1, LDO1_VOLTAGE, val)) {
+ printf(tps659038: could not set LDO1 voltage\n);
+ return 1;
+ }
+
+ /* TURN ON LDO1 */
+ val = LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
+
+ if (palmas_i2c_write_u8(TPS659038_CHIP_P1, LDO1_CTRL, val)) {
+ printf(tps659038: could not turn on LDO1\n);
return 1;
}
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index 83b91d1..ddf2ad4 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -238,6 +238,10 @@
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PALMAS_POWER
+#endif
+
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index ba81e30..f4a2d31 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
Re: [U-Boot] [PATCH V2 09/12] mmc: omap_hsmmc: add mmc1 pbias, ldo1
Hi Lubomir, On Thursday 06 June 2013 12:55 PM, Lubomir Popov wrote: Hi Tom, On 05/06/13 16:45, Tom Rini wrote: On Wed, Jun 05, 2013 at 11:03:26AM +0300, Lubomir Popov wrote: Hi Tom, On 05/06/13 00:06, Tom Rini wrote: On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote: Hi Lokesh, Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote: Hi Lokesh, On 30/05/13 16:19, Lokesh Vutla wrote: From: Balaji T K balaj...@ti.com add dra mmc pbias support and ldo1 power on Signed-off-by: Balaji T K balaj...@ti.com Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- arch/arm/include/asm/arch-omap5/omap.h |3 ++- drivers/mmc/omap_hsmmc.c | 26 ++ drivers/power/palmas.c | 25 - include/configs/omap5_common.h |4 include/configs/omap5_uevm.h |5 - include/palmas.h |6 +- 6 files changed, 49 insertions(+), 20 deletions(-) [snip] + /* set LDO9 TWL6035 to 3V */ LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above. Ok ll add the comment. + val = 0x2b; /* (3 - 0.9) * 20 + 1 */ Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined. Yes, Ill rebase this patch on top of your patch and use those defines. Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline. Tom, your opinion? OK, so at the time it was nothing will really use this code except test functions. Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants. Well, I'm not quite sure that this LDO9 function would be the only one used (or LDO1 on the DRA7xx board). Judging from omapboot for the OMAP5 boards for example, SMPS7 (it delivers the common 1.8 V I/O supply) is set to 'Forced PWM' mode in order to reduce board noise - there sure has been a reason to do so and sacrifice converter efficiency. Therefore I added similar functionality in my patch to the Palmas driver (and am explicitly calling it in my board init). The option to bypass LDO9 on OMAP5+TWL603x boards seems quite mandatory as well, if hardware is designed such that the SD card socket has a separate fixed 3.3 V supply which also powers the LDO9 input (the uEVM for example). On the DRA7xx+TPS659038 board the power scheme is different and this does not apply. OK, lets see. That so lets keep your patch as-is, since we've now got -ffunction-sections/-fdata-sections/--gc-sections on ARM for main U-Boot, these small things won't hurt like they used to. OK, but then I would like to do some cleanup first - remove the audio power stuff (shall have it in my board file), as well as either sort out the function naming: - Those functions that are specific to a SoC+PMIC combination are named e.g. twl603x_... or tps659038_... so that they explicitly indicate the hardware that they are working with (actually almost all functions are such). This is however sort of regression, and requires fixes in the files calling these functions; or, alternatively: - Introduce generic functions with fixed names, palmas_bla_bla(), sort of wrappers, which in their bodies perform the appropriate action based on the #ifdefs defining the platform hardware (where we could also define the particular LDO which for example a palmas_mmc1_poweron_ldo() generic function would manipulate). Drawback: again #ifdefs. Advantage: single place where this stuff is located, and where other PMIC/LDO combinations can be added without affecting other code. I think, we can have function pointers for and can populate data in the beginning or from board file based on Soc, similarly what we did for prcm structure. Regards, Lokesh And this generic palmas_mmc1_poweron_ldo() function would be called by another generic function, e.g. omap_sdmmc_poweron(), located in the board file, only if needed by the particular hardware. omap_sdmmc_poweron(), on its hand, is the function that is to be called from within the pbias routines in omap_hsmmc.c, and not the hardware- dependant functions directly. So we get the abstraction. What do you think? Lokesh, your opinion? Regards, Lubo ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's
Hi Tom, On Thursday 30 May 2013 06:49 PM, Lokesh Vutla wrote: This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-OMAP2-Misc-Cleanup-tt155949.html Do you have any further comments on this series ? Thanks and regards, Lokesh Testing: Boot tested on DRA752 ES1.0, OMAP5432 ES2.0, OMAP4460 PANDA Verified MAKEALL for armv7 and omap boards. Changes from v1: * Addressed comments from Tom Rini Balaji T K (1): mmc: omap_hsmmc: add mmc1 pbias, ldo1 Lokesh Vutla (6): ARM: DRA7xx: Add control id code for DRA7xx ARM: DRA7xx: power Add support for tps659038 PMIC ARM: DRA7xx: clocks: Fixing i2c_init for PMIC ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's ARM: DRA7xx: Update pinmux data ARM: DRA7xx: clocks: Update PLL values Nishanth Menon (1): ARM: OMAP5: DRA7xx: support class 0 optimized voltages Sricharan R (4): ARM: DRA7xx: Change the Debug UART to UART1 ARM: DRA7xx: Correct the SYS_CLK to 20MHZ ARM: DRA7xx: Correct SRAM END address ARM: DRA7xx: EMIF: Change settings required for EVM board arch/arm/cpu/armv7/omap-common/clocks-common.c | 86 +--- arch/arm/cpu/armv7/omap-common/emif-common.c | 26 +++- arch/arm/cpu/armv7/omap-common/hwinit-common.c |2 - arch/arm/cpu/armv7/omap-common/timer.c |1 + arch/arm/cpu/armv7/omap5/hw_data.c | 156 -- arch/arm/cpu/armv7/omap5/hwinit.c | 22 ++- arch/arm/cpu/armv7/omap5/prcm-regs.c |2 + arch/arm/cpu/armv7/omap5/sdram.c | 170 ++-- arch/arm/include/asm/arch-omap4/clock.h|6 +- arch/arm/include/asm/arch-omap4/sys_proto.h|1 + arch/arm/include/asm/arch-omap5/clock.h| 61 - arch/arm/include/asm/arch-omap5/mux_dra7xx.h |7 +- arch/arm/include/asm/arch-omap5/omap.h | 26 ++-- arch/arm/include/asm/arch-omap5/sys_proto.h|1 + arch/arm/include/asm/emif.h| 12 +- arch/arm/include/asm/omap_common.h | 26 +++- board/ti/dra7xx/mux_data.h | 38 -- drivers/mmc/omap_hsmmc.c | 26 ++-- drivers/power/palmas.c | 25 +++- include/configs/dra7xx_evm.h |8 +- include/configs/omap4_common.h |4 - include/configs/omap5_common.h | 12 +- include/configs/omap5_uevm.h |7 +- include/palmas.h |6 +- 24 files changed, 590 insertions(+), 141 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's
Hi, On Thursday 06 June 2013 07:07 PM, Lubomir Popov wrote: Hi Tom, On 06/06/13 16:26, Tom Rini wrote: On Thu, Jun 06, 2013 at 04:58:44PM +0530, Lokesh Vutla wrote: Hi Tom, On Thursday 30 May 2013 06:49 PM, Lokesh Vutla wrote: This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-OMAP2-Misc-Cleanup-tt155949.html Do you have any further comments on this series ? Sorry, everything looks good, and I think Lubomir's patch for MMC stuff (which means we drop 9/12 here, right?) should settle everything else out. Please be aware that my patch (latest in http://patchwork.ozlabs.org/patch/249405/) fixes the two palmas.* files only, while Lokesh's patch 9/12 affected 6 files in total (including these two). Yes Lubomir, you are correct. The patch 9/12 from Balaji , also includes a programming sequence update for pbias for OMAP5 ES2.0+ Soc's. Ill have that sequence alone and send a patch. Thanks and regards, Lokesh Lokesh, unfortunately you shall have to repost 9/12 after rebasing over my stuff, if it is applied. Regards, Lubo ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V5 09/12] mmc: omap_hsmmc: Update pbias programming
From: Balaji T K balaj...@ti.com
Update pbias programming sequence for OMAP5 ES2.0/DRA7
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V4:
* Rebased on top of http://patchwork.ozlabs.org/patch/249430/
arch/arm/include/asm/arch-omap5/omap.h |2 +-
drivers/mmc/omap_hsmmc.c | 20 +---
include/configs/omap5_common.h |4
include/configs/omap5_uevm.h |5 -
4 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 9010666..abf6837 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -106,9 +106,9 @@
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 27)
#define SDCARD_PWRDNZ (1 26)
#define SDCARD_BIAS_HIZ_MODE (1 25)
-#define SDCARD_BIAS_PWRDNZ (1 22)
#define SDCARD_PBIASLITE_VMODE (1 21)
#ifndef __ASSEMBLY__
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index afdfa88..975b2c5 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -113,23 +113,21 @@ static void omap5_pbias_config(struct mmc *mmc)
u32 value = 0;
value = readl((*ctrl)-control_pbias);
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
+ value = ~SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(10); /* wait 10 us */
+ value = ~SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
palmas_mmc1_poweron_ldo();
value = readl((*ctrl)-control_pbias);
- value = ~SDCARD_BIAS_HIZ_MODE;
- value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
+ value |= SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)-control_pbias);
-
- value = readl((*ctrl)-control_pbias);
- if (value (1 23)) {
- value = ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
- writel(value, (*ctrl)-control_pbias);
- }
+ udelay(150); /* wait 150 us */
+ value |= SDCARD_PWRDNZ;
+ writel(value, (*ctrl)-control_pbias);
+ udelay(150); /* wait 150 us */
}
#endif
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index 83b91d1..ddf2ad4 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -238,6 +238,10 @@
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PALMAS_POWER
+#endif
+
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index ba81e30..f4a2d31 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -39,11 +39,6 @@
#define CONFIG_SYS_NS16550_COM3UART3_BASE
#define CONFIG_BAUDRATE115200
-/* TWL6035 */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PALMAS_POWER
-#endif
-
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
--
1.7.9.5
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[U-Boot] [PATCH] ARM: DRA7: Add Maintainer
Adding Maintainer for DRA7xx. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- MAINTAINERS |4 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d86f0f1..2f4ea84 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -960,6 +960,10 @@ Hugo Villeneuve hugo.villene...@lyrtech.com SFFSDR ARM926EJS +Lokesh Vutla lokeshvu...@ti.com + + dra7xx_evm ARM ARMV7 (DRA7xx Soc) + Matt Waddel matt.wad...@linaro.org ca9x4_ct_vxpARM ARMV7 (Quad Core) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7] arm: dra7xx: Add silicon id support for DRA752 soc
Adding CPU detection support for the DRA752 ES1.0 soc.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/hwinit-common.c |9 +++--
arch/arm/cpu/armv7/omap5/hwinit.c |3 +++
arch/arm/include/asm/arch-omap5/omap.h |1 +
arch/arm/include/asm/omap_common.h |3 +++
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 60af7eb..05ff2e8 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -81,12 +81,17 @@ u32 cortex_rev(void)
void omap_rev_string(void)
{
u32 omap_rev = omap_revision();
+ u32 soc_variant = (omap_rev 0xF000) 28;
u32 omap_variant = (omap_rev 0x) 16;
u32 major_rev = (omap_rev 0x0F00) 8;
u32 minor_rev = (omap_rev 0x00F0) 4;
- printf(OMAP%x ES%x.%x\n, omap_variant, major_rev,
- minor_rev);
+ if (soc_variant)
+ printf(OMAP);
+ else
+ printf(DRA);
+ printf(%x ES%x.%x\n, omap_variant, major_rev,
+ minor_rev);
}
#ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index f083198..d8f711c 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -337,6 +337,9 @@ void init_omap_revision(void)
case OMAP5432_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5432_ES2_0;
break;
+ case DRA752_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = DRA752_ES1_0;
+ break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index d29be93..b632635 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -60,6 +60,7 @@
#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
+#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
/* STD_FUSE_PROD_ID_1 */
#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 0af0c33..785daff 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -554,4 +554,7 @@ static inline u32 omap_revision(void)
#define OMAP5432_ES1_0 0x54320100
#define OMAP5430_ES2_0 0x54300200
#define OMAP5432_ES2_0 0x54320200
+
+/* DRA7XX */
+#define DRA752_ES1_0 0x07520100
#endif /* _OMAP_COMMON_H_ */
--
1.7.9.5
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[U-Boot] [PATCH 5/7] arm: dra7xx: Add DDR related data for DRA752 ES1.0
DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/emif-common.c |2 +-
arch/arm/cpu/armv7/omap4/sdram_elpida.c | 18 +++---
arch/arm/cpu/armv7/omap5/hw_data.c |1 +
arch/arm/cpu/armv7/omap5/sdram.c | 26 --
arch/arm/include/asm/emif.h |1 +
5 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 0683b9f..9eb1279 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1191,7 +1191,7 @@ void dmm_init(u32 base)
writel(lisa_map_regs-dmm_lisa_map_0,
hw_lisa_map_regs-dmm_lisa_map_0);
- if (omap_revision() = OMAP4460_ES1_0) {
+ if (lisa_map_regs-is_ma_present) {
hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)MA_BASE;
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index 01da790..20fc552 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -94,14 +94,24 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80540300
+ .dmm_lisa_map_3 = 0x80540300,
+ .is_ma_present = 0x0
};
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80640300
+ .dmm_lisa_map_3 = 0x80640300,
+ .is_ma_present = 0x0
+};
+
+const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
+ .dmm_lisa_map_0 = 0xFF020100,
+ .dmm_lisa_map_1 = 0,
+ .dmm_lisa_map_2 = 0,
+ .dmm_lisa_map_3 = 0x80640300,
+ .is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
@@ -126,8 +136,10 @@ static void emif_get_dmm_regs_sdp(const struct
dmm_lisa_map_regs
if (omap_rev == OMAP4430_ES1_0)
*dmm_lisa_regs = lisa_map_2G_x_1_x_2;
- else
+ else if (omap_rev OMAP4460_ES1_0)
*dmm_lisa_regs = lisa_map_2G_x_2_x_2;
+ else
+ *dmm_lisa_regs = ma_lisa_map_2G_x_2_x_2;
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index d42974e..14adfb3 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -586,6 +586,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
*regs = ioregs_omap5432_es1;
break;
case OMAP5432_ES2_0:
+ case DRA752_ES1_0:
*regs = ioregs_omap5432_es2;
break;
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 2ef7fcd..6b461e4 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -155,7 +155,16 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
- .dmm_lisa_map_3 = 0xFF020100
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x0,
+ .dmm_lisa_map_3 = 0x80500100,
+ .is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
@@ -171,6 +180,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct
emif_regs **regs)
*regs = emif_regs_532_mhz_2cs_es2;
break;
case OMAP5432_ES2_0:
+ case DRA752_ES1_0:
default:
*regs = emif_regs_ddr3_532_mhz_1cs_es2;
}
@@ -182,7 +192,18 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs
**regs)
static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
**dmm_lisa_regs)
{
- *dmm_lisa_regs = lisa_map_4G_x_2_x_2;
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ case OMAP5432_ES1_0:
+ case OMAP5432_ES2_0:
+ *dmm_lisa_regs = lisa_map_4G_x_2_x_2;
+ break;
+ case DRA752_ES1_0:
+ default:
+ *dmm_lisa_regs = lisa_map_512M_x_1;
+ }
+
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
@@ -297,6 +318,7 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32
**regs
[U-Boot] [PATCH 2/7] arm: dra7xx: clock: Add the prcm changes
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap4/hw_data.c |2 +-
arch/arm/cpu/armv7/omap4/prcm-regs.c |2 +-
arch/arm/cpu/armv7/omap5/hw_data.c |6 +-
arch/arm/cpu/armv7/omap5/prcm-regs.c | 218 +++-
arch/arm/include/asm/arch-omap5/cpu.h |4 +
arch/arm/include/asm/arch-omap5/omap.h |9 +-
arch/arm/include/asm/omap_common.h | 15 ++-
7 files changed, 249 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c
b/arch/arm/cpu/armv7/omap4/hw_data.c
index 8d31d6d..3b27bc1 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -290,7 +290,7 @@ void enable_basic_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)-cm_l3_2_gpmc_clkctrl,
+ (*prcm)-cm_l3_gpmc_clkctrl,
(*prcm)-cm_memif_emif_1_clkctrl,
(*prcm)-cm_memif_emif_2_clkctrl,
(*prcm)-cm_l4cfg_l4_cfg_clkctrl,
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c
b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index c58ce8d..7225a30 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -153,7 +153,7 @@ struct prcm_regs const omap4_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_2_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 1701b09..22590f4 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -278,7 +278,7 @@ void enable_basic_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)-cm_l3_2_gpmc_clkctrl,
+ (*prcm)-cm_l3_gpmc_clkctrl,
(*prcm)-cm_memif_emif_1_clkctrl,
(*prcm)-cm_memif_emif_2_clkctrl,
(*prcm)-cm_l4cfg_l4_cfg_clkctrl,
@@ -503,6 +503,10 @@ void hw_data_init(void)
*omap_vcores = omap5430_volts_es2;
break;
+ case DRA752_ES1_0:
+ *prcm = dra7xx_prcm;
+ break;
+
default:
printf(\n INVALID OMAP REVISION );
}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 5e5abcc..c8f62d1 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -156,7 +156,7 @@ struct prcm_regs const omap5_es1_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_2_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
@@ -513,7 +513,7 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_2_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
@@ -664,3 +664,217 @@ struct prcm_regs const omap5_es2_prcm = {
.prm_sldo_mm_setup = 0x4ae07cd4,
.prm_sldo_mm_ctrl = 0x4ae07cd8,
};
+
+struct prcm_regs const dra7xx_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a005100,
+ .cm_clksel_abe = 0x4a005108,
+ .cm_dll_ctrl= 0x4a005110,
+ .cm_clkmode_dpll_core = 0x4a005120,
+ .cm_idlest_dpll_core= 0x4a005124,
+ .cm_autoidle_dpll_core = 0x4a005128,
+ .cm_clksel_dpll_core= 0x4a00512c,
+ .cm_div_m2_dpll_core= 0x4a005130,
+ .cm_div_m3_dpll_core= 0x4a005134,
+ .cm_div_h11_dpll_core = 0x4a005138,
+ .cm_div_h12_dpll_core = 0x4a00513c,
+ .cm_div_h13_dpll_core = 0x4a005140,
+ .cm_div_h14_dpll_core = 0x4a005144,
+ .cm_ssc_deltamstep_dpll_core= 0x4a005148,
+ .cm_ssc_modfreqdiv_dpll_core= 0x4a00514c,
+ .cm_div_h21_dpll_core = 0x4a005150,
+ .cm_div_h22_dpllcore= 0x4a005154,
+ .cm_div_h23_dpll_core = 0x4a005158
[U-Boot] [PATCH 4/7] arm: dra7xx: Add control module changes
Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |5 ++-
arch/arm/cpu/armv7/omap5/prcm-regs.c | 72 ++
arch/arm/include/asm/omap_common.h | 10 +
3 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 095af01..d42974e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -550,6 +550,7 @@ void hw_data_init(void)
*prcm = omap5_es1_prcm;
*dplls_data = omap5_dplls_es1;
*omap_vcores = omap5430_volts;
+ *ctrl = omap5_ctrl;
break;
case OMAP5430_ES2_0:
@@ -557,19 +558,19 @@ void hw_data_init(void)
*prcm = omap5_es2_prcm;
*dplls_data = omap5_dplls_es2;
*omap_vcores = omap5430_volts_es2;
+ *ctrl = omap5_ctrl;
break;
case DRA752_ES1_0:
*prcm = dra7xx_prcm;
*dplls_data = dra7xx_dplls;
*omap_vcores = omap5430_volts_es2;
+ *ctrl = dra7xx_ctrl;
break;
default:
printf(\n INVALID OMAP REVISION );
}
-
- *ctrl = omap5_ctrl;
}
void get_ioregs(const struct ctrl_ioregs **regs)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index c8f62d1..c2fce11 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -381,6 +381,78 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_efuse_13 = 0x4AE0CDF8,
};
+struct omap_sys_ctrl_regs const dra7xx_ctrl = {
+ .control_status = 0x4A002134,
+ .control_core_mmr_lock1 = 0x4A002540,
+ .control_core_mmr_lock2 = 0x4A002544,
+ .control_core_mmr_lock3 = 0x4A002548,
+ .control_core_mmr_lock4 = 0x4A00254C,
+ .control_core_mmr_lock5 = 0x4A002550,
+ .control_core_control_io1 = 0x4A002554,
+ .control_core_control_io2 = 0x4A002558,
+ .control_paconf_global = 0x4A002DA0,
+ .control_paconf_mode= 0x4A002DA4,
+ .control_smart1io_padconf_0 = 0x4A002DA8,
+ .control_smart1io_padconf_1 = 0x4A002DAC,
+ .control_smart1io_padconf_2 = 0x4A002DB0,
+ .control_smart2io_padconf_0 = 0x4A002DB4,
+ .control_smart2io_padconf_1 = 0x4A002DB8,
+ .control_smart2io_padconf_2 = 0x4A002DBC,
+ .control_smart3io_padconf_0 = 0x4A002DC0,
+ .control_smart3io_padconf_1 = 0x4A002DC4,
+ .control_pbias = 0x4A002E00,
+ .control_i2c_0 = 0x4A002E04,
+ .control_camera_rx = 0x4A002E08,
+ .control_hdmi_tx_phy= 0x4A002E0C,
+ .control_uniportm = 0x4A002E10,
+ .control_dsiphy = 0x4A002E14,
+ .control_mcbsplp= 0x4A002E18,
+ .control_usb2phycore= 0x4A002E1C,
+ .control_hdmi_1 = 0x4A002E20,
+ .control_hsi= 0x4A002E24,
+ .control_ddr3ch1_0 = 0x4A002E30,
+ .control_ddr3ch2_0 = 0x4A002E34,
+ .control_ddrch1_0 = 0x4A002E38,
+ .control_ddrch1_1 = 0x4A002E3C,
+ .control_ddrch2_0 = 0x4A002E40,
+ .control_ddrch2_1 = 0x4A002E44,
+ .control_lpddr2ch1_0= 0x4A002E48,
+ .control_lpddr2ch1_1= 0x4A002E4C,
+ .control_ddrio_0= 0x4A002E50,
+ .control_ddrio_1= 0x4A002E54,
+ .control_ddrio_2= 0x4A002E58,
+ .control_hyst_1 = 0x4A002E5C,
+ .control_usbb_hsic_control = 0x4A002E60,
+ .control_c2c= 0x4A002E64,
+ .control_core_control_spare_rw = 0x4A002E68,
+ .control_core_control_spare_r = 0x4A002E6C,
+ .control_core_control_spare_r_c0= 0x4A002E70,
+ .control_srcomp_north_side = 0x4A002E74,
+ .control_srcomp_south_side = 0x4A002E78,
+ .control_srcomp_east_side = 0x4A002E7C,
+ .control_srcomp_west_side = 0x4A002E80,
+ .control_srcomp_code_latch = 0x4A002E84,
+ .control_padconf_core_base = 0x4A003400
[U-Boot] [PATCH 3/7] arm: dra7xx: clock: Add the dplls data
A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 26 +-
arch/arm/cpu/armv7/omap4/hw_data.c |9 ++--
arch/arm/cpu/armv7/omap5/hw_data.c | 64 ++--
arch/arm/include/asm/omap_common.h |3 +-
4 files changed, 94 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 818a963..9ed1899 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -55,11 +55,12 @@ const u32 sys_clk_array[8] = {
2600, /* 26 MHz */
2700, /* 27 MHz */
3840, /* 38.4 MHz */
+ 2000, /* 20 MHz */
};
static inline u32 __get_sys_clk_index(void)
{
- u32 ind;
+ s8 ind;
/*
* For ES1 the ROM code calibration of sys clock is not reliable
* due to hw issue. So, use hard-coded value. If this value is not
@@ -73,6 +74,13 @@ static inline u32 __get_sys_clk_index(void)
/* SYS_CLKSEL - 1 to match the dpll param array indices */
ind = (readl((*prcm)-cm_sys_clksel)
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+ /*
+* SYS_CLKSEL value for 20MHz is 0. This is introduced newly
+* in DRA7XX socs. SYS_CLKSEL -1 will be greater than
+* NUM_SYS_CLK. So considering the last 3 bits as the index
+* for the dpll param array.
+*/
+ ind = CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
}
return ind;
}
@@ -201,12 +209,25 @@ const struct dpll_params *get_abe_dpll_params(struct
dplls const *dpll_data)
#endif
}
+static const struct dpll_params *get_ddr_dpll_params
+ (struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+
+ if (!dpll_data-ddr)
+ return NULL;
+ return dpll_data-ddr[sysclk_ind];
+}
+
static void do_setup_dpll(u32 const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
u32 temp, M, N;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+ if (!params)
+ return;
+
temp = readl(dpll_regs-cm_clksel_dpll);
if (check_for_lock(base)) {
@@ -397,6 +418,9 @@ static void setup_dplls(void)
#ifdef CONFIG_USB_EHCI_OMAP
setup_usb_dpll();
#endif
+ params = get_ddr_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)-cm_clkmode_dpll_ddrphy,
+ params, DPLL_LOCK, ddr);
}
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c
b/arch/arm/cpu/armv7/omap4/hw_data.c
index 3b27bc1..7551b98 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -182,7 +182,8 @@ struct dplls omap4430_dplls_es1 = {
#else
.abe = abe_dpll_params_32k_196608khz,
#endif
- .usb = usb_dpll_params_1920mhz
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
};
struct dplls omap4430_dplls = {
@@ -195,7 +196,8 @@ struct dplls omap4430_dplls = {
#else
.abe = abe_dpll_params_32k_196608khz,
#endif
- .usb = usb_dpll_params_1920mhz
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
};
struct dplls omap4460_dplls = {
@@ -208,7 +210,8 @@ struct dplls omap4460_dplls = {
#else
.abe = abe_dpll_params_32k_196608khz,
#endif
- .usb = usb_dpll_params_1920mhz
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
};
struct pmic_data twl6030_4430es1 = {
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 22590f4..095af01 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -98,6 +98,17 @@ static const struct dpll_params
mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}/* 38.4 MHz */
};
+static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
+ {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},/* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},/* 16.8 MHz */
+ {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 23, 1, -1, -1, -1
[U-Boot] [PATCH 0/7] arm: dra7xx: Add support for DRA7XX family Socs
DRA7XX is a high-performance, infotainment application device,
based on enhanced OMAP architecture integrated on a 28-nm technology.
This series adds support for DRA7XX family Socs and the data for
DRA752 ES1.0 soc.
This is on top of OMAP5 ES2.0 series
http://www.mail-archive.com/u-boot@lists.denx.de/msg105592.html
This series against OMAP5 ES2.0 series is available here:
git://gitorious.org/u-boot-shared/u-boot.git omap5_es2
Tested on DRA pre silicon platform, OMAP5430 ES2.0,
OMAP4430 ES2.1, OMAP4460 panda.
MAKEALL for all armv7 board has been verified.
Lokesh Vutla (7):
arm: dra7xx: Add silicon id support for DRA752 soc
arm: dra7xx: clock: Add the prcm changes
arm: dra7xx: clock: Add the dplls data
arm: dra7xx: Add control module changes for dra7xx socs
arm: dra7xx: Add DDR related data for DRA752 ES1.0
arm: dra7xx: Add board files for dra7xx socs
arm: dra7xx: Add dra7xx_evm build support
arch/arm/cpu/armv7/omap-common/clocks-common.c | 26 +-
arch/arm/cpu/armv7/omap-common/emif-common.c|2 +-
arch/arm/cpu/armv7/omap-common/hwinit-common.c |9 +-
arch/arm/cpu/armv7/omap4/hw_data.c | 11 +-
arch/arm/cpu/armv7/omap4/prcm-regs.c|2 +-
arch/arm/cpu/armv7/omap4/sdram_elpida.c | 18 +-
arch/arm/cpu/armv7/omap5/hw_data.c | 76 -
arch/arm/cpu/armv7/omap5/hwinit.c |3 +
arch/arm/cpu/armv7/omap5/prcm-regs.c| 290 ++-
arch/arm/cpu/armv7/omap5/sdram.c| 26 +-
arch/arm/include/asm/arch-omap5/cpu.h |4 +
arch/arm/include/asm/arch-omap5/mux_dra7xx.h| 344 +++
arch/arm/include/asm/arch-omap5/mux_omap5.h |8 -
arch/arm/include/asm/arch-omap5/omap.h | 10 +-
arch/arm/include/asm/arch-omap5/sys_proto.h |6 +-
arch/arm/include/asm/emif.h |1 +
arch/arm/include/asm/omap_common.h | 31 +-
board/ti/dra7xx/Makefile| 49
board/ti/dra7xx/evm.c | 103 +++
board/ti/dra7xx/mux_data.h | 47
boards.cfg |1 +
include/configs/dra7xx_evm.h| 40 +++
include/configs/{omap5_evm.h = omap5_common.h} | 20 +-
include/configs/omap5_evm.h | 240 +---
24 files changed, 1087 insertions(+), 280 deletions(-)
create mode 100644 arch/arm/include/asm/arch-omap5/mux_dra7xx.h
create mode 100644 board/ti/dra7xx/Makefile
create mode 100644 board/ti/dra7xx/evm.c
create mode 100644 board/ti/dra7xx/mux_data.h
create mode 100644 include/configs/dra7xx_evm.h
copy include/configs/{omap5_evm.h = omap5_common.h} (95%)
--
1.7.9.5
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[U-Boot] [PATCH 6/7] arm: dra7xx: Add board files for DRA7XX socs
Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com Signed-off-by: Nishant Kamat nska...@ti.com Signed-off-by: R Sricharan r.sricha...@ti.com --- arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 344 ++ arch/arm/include/asm/arch-omap5/mux_omap5.h |8 - arch/arm/include/asm/arch-omap5/sys_proto.h |6 +- board/ti/dra7xx/Makefile | 49 board/ti/dra7xx/evm.c| 103 board/ti/dra7xx/mux_data.h | 47 6 files changed, 548 insertions(+), 9 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap5/mux_dra7xx.h create mode 100644 board/ti/dra7xx/Makefile create mode 100644 board/ti/dra7xx/evm.c create mode 100644 board/ti/dra7xx/mux_data.h diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h new file mode 100644 index 000..55e9de6 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -0,0 +1,344 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated + * + * Nishant Kamat nska...@ti.com + * Lokesh Vutla lokeshvu...@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_DRA7XX_H_ +#define _MUX_DRA7XX_H_ + +#include asm/types.h + +#define IEN(1 18) +#define IDIS (0 18) + +#define PTU(3 16) +#define PTD(1 16) +#define PEN(1 16) +#define PDIS (0 16) + +#define WKEN (1 24) +#define WKDIS (0 24) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 +#define M8 8 +#define M9 9 +#define M1010 +#define M1111 +#define M1212 +#define M1313 +#define M1414 +#define M1515 + +#define SAFE_MODE M15 + +#define GPMC_AD0 0x000 +#define GPMC_AD1 0x004 +#define GPMC_AD2 0x008 +#define GPMC_AD3 0x00C +#define GPMC_AD4 0x010 +#define GPMC_AD5 0x014 +#define GPMC_AD6 0x018 +#define GPMC_AD7 0x01C +#define GPMC_AD8 0x020 +#define GPMC_AD9 0x024 +#define GPMC_AD10 0x028 +#define GPMC_AD11 0x02C +#define GPMC_AD12 0x030 +#define GPMC_AD13 0x034 +#define GPMC_AD14 0x038 +#define GPMC_AD15 0x03C +#define GPMC_A00x040 +#define GPMC_A10x044 +#define GPMC_A20x048 +#define GPMC_A30x04C +#define GPMC_A40x050 +#define GPMC_A50x054 +#define GPMC_A60x058 +#define GPMC_A70x05C +#define GPMC_A80x060 +#define GPMC_A90x064 +#define GPMC_A10 0x068 +#define GPMC_A11 0x06C +#define GPMC_A12 0x070 +#define GPMC_A13 0x074 +#define GPMC_A14 0x078 +#define GPMC_A15 0x07C +#define GPMC_A16 0x080 +#define GPMC_A17 0x084 +#define GPMC_A18 0x088 +#define GPMC_A19 0x08C +#define GPMC_A20 0x090 +#define GPMC_A21 0x094 +#define GPMC_A22 0x098 +#define GPMC_A23 0x09C +#define GPMC_A24 0x0A0 +#define GPMC_A25 0x0A4 +#define GPMC_A26 0x0A8 +#define GPMC_A27 0x0AC +#define GPMC_CS1 0x0B0 +#define GPMC_CS0 0x0B4 +#define GPMC_CS2 0x0B8 +#define GPMC_CS3 0x0BC +#define GPMC_CLK 0x0C0 +#define GPMC_ADVN_ALE 0x0C4 +#define GPMC_OEN_REN 0x0C8 +#define GPMC_WEN 0x0CC +#define GPMC_BEN0 0x0D0 +#define GPMC_BEN1 0x0D4 +#define GPMC_WAIT0 0x0D8 +#define VIN1A_CLK0 0x0DC +#define VIN1B_CLK1 0x0E0 +#define VIN1A_DE0 0x0E4 +#define VIN1A_FLD0 0x0E8 +#define VIN1A_HSYNC0 0x0EC +#define VIN1A_VSYNC0 0x0F0 +#define VIN1A_D0 0x0F4 +#define VIN1A_D1 0x0F8 +#define VIN1A_D2 0x0FC +#define VIN1A_D3 0x100 +#define VIN1A_D4 0x104 +#define VIN1A_D5 0x108 +#define VIN1A_D6 0x10C +#define VIN1A_D7 0x110 +#define VIN1A_D8 0x114 +#define VIN1A_D9 0x118 +#define VIN1A_D10 0x11C +#define VIN1A_D11 0x120 +#define
[U-Boot] [PATCH 7/7] arm: dra7xx: Add dra7xx_evm build support
Adding the build support for dra7xx_evm.
Reusing omap5_evm.h config by moving it to omap5_common.h
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
boards.cfg |1 +
include/configs/dra7xx_evm.h| 40
include/configs/{omap5_evm.h = omap5_common.h} | 20 +-
include/configs/omap5_evm.h | 240 +--
4 files changed, 55 insertions(+), 246 deletions(-)
create mode 100644 include/configs/dra7xx_evm.h
copy include/configs/{omap5_evm.h = omap5_common.h} (95%)
diff --git a/boards.cfg b/boards.cfg
index 98f7a14..fea1101 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -279,6 +279,7 @@ nokia_rx51 arm armv7 rx51
nokia
omap4_panda arm armv7 panda ti
omap4
omap4_sdp4430arm armv7 sdp4430 ti
omap4
omap5_evmarm armv7 omap5_evm ti
omap5
+dra7xx_evm arm armv7 dra7xx ti
omap5
s5p_goni arm armv7 goni
samsungs5pc1xx
smdkc100 arm armv7 smdkc100
samsungs5pc1xx
origen arm armv7 origen
samsungexynos
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
new file mode 100644
index 000..17747d2
--- /dev/null
+++ b/include/configs/dra7xx_evm.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Lokesh Vutla lokeshvu...@ti.com
+ *
+ * Configuration settings for the TI DRA7XX board.
+ * See omap5_common.h for omap5 common settings.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_DRA7XX_EVM_H
+#define __CONFIG_DRA7XX_EVM_H
+
+#include configs/omap5_common.h
+
+#define CONFIG_OMAP
+#define CONFIG_DRA7XX /* in a TI DRA7XX core */
+#define CONFIG_DRA752_EVM
+
+#define CONFIG_SYS_PROMPT DRA752 EVM #
+
+#endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_common.h
similarity index 95%
copy from include/configs/omap5_evm.h
copy to include/configs/omap5_common.h
index 1d3ac2b..db453df 100644
--- a/include/configs/omap5_evm.h
+++ b/include/configs/omap5_common.h
@@ -1,12 +1,12 @@
/*
- * (C) Copyright 2010
+ * (C) Copyright 2013
* Texas Instruments Incorporated.
* Sricharan R r.sricha...@ti.com
*
* Derived from OMAP4 done by:
* Aneesh V ane...@ti.com
*
- * Configuration settings for the TI EVM5430 board.
+ * TI OMAP5 AND DRA7XX common configuration settings
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -27,17 +27,15 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_OMAP5_COMMON_H
+#define __CONFIG_OMAP5_COMMON_H
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP/* in a TI OMAP core */
#define CONFIG_OMAP54XX/* which is a 54XX */
-#define CONFIG_OMAP5430/* which is in a 5430 */
-#define CONFIG_5430EVM /* working with EVM */
+#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP_GPIO
/* Get CPU defs */
@@ -96,10 +94,6 @@
#define CONFIG_DRIVER_OMAP34XX_I2C
#define CONFIG_I2C_MULTI_BUS
-/* TWL6035 */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_TWL6035_POWER
-#endif
/* MMC */
#define CONFIG_GENERIC_MMC
@@ -185,7 +179,6 @@
#define CONFIG_SYS_LONGHELP/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use hush command parser */
-#define CONFIG_SYS_PROMPT OMAP5430 EVM #
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
@@ -266,4 +259,4 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10/* 1 MB */
#define CONFIG_SPL_GPIO_SUPPORT
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_OMAP5_COMMON_H */
diff --git
Re: [U-Boot] [PATCH 7/7] arm: dra7xx: Add dra7xx_evm build support
On Friday 15 February 2013 10:06 PM, Tom Rini wrote: On Wed, Feb 13, 2013 at 12:59:09PM +0530, Lokesh Vutla wrote: Adding the build support for dra7xx_evm. Reusing omap5_evm.h config by moving it to omap5_common.h Signed-off-by: Lokesh Vutla lokeshvu...@ti.com Signed-off-by: R Sricharan r.sricha...@ti.com [snip] +#define CONFIG_DRA752_EVM [snip] #define CONFIG_OMAP5430 /* which is in a 5430 */ #define CONFIG_5430EVM/* working with EVM */ Are these three ever used? I don't see the two current OMAP5 ones anywhere and I suspect the new DRA one isn't either. Yes, you are right. ll remove these unused CONFIGs and send a V2. Regards, Lokesh I know we'll need separate config files at some point down the line, so I'm fine with creating a small dra7xx_evm config file. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 2/7] arm: dra7xx: clock: Add the prcm changes
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
[v2] Removed hard coded constants for PRM_DEVICE_BASE
and using the runtime assigned variable instead.
Also removed the unnecessary CONTROL_ID_CODE base
register change.
arch/arm/cpu/armv7/omap4/hw_data.c |2 +-
arch/arm/cpu/armv7/omap4/prcm-regs.c |2 +-
arch/arm/cpu/armv7/omap5/hw_data.c |6 +-
arch/arm/cpu/armv7/omap5/hwinit.c|9 +-
arch/arm/cpu/armv7/omap5/prcm-regs.c | 224 +-
arch/arm/include/asm/omap_common.h | 17 ++-
6 files changed, 252 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c
b/arch/arm/cpu/armv7/omap4/hw_data.c
index 8d31d6d..3b27bc1 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -290,7 +290,7 @@ void enable_basic_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)-cm_l3_2_gpmc_clkctrl,
+ (*prcm)-cm_l3_gpmc_clkctrl,
(*prcm)-cm_memif_emif_1_clkctrl,
(*prcm)-cm_memif_emif_2_clkctrl,
(*prcm)-cm_l4cfg_l4_cfg_clkctrl,
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c
b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index c58ce8d..7225a30 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -153,7 +153,7 @@ struct prcm_regs const omap4_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_2_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 1701b09..22590f4 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -278,7 +278,7 @@ void enable_basic_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)-cm_l3_2_gpmc_clkctrl,
+ (*prcm)-cm_l3_gpmc_clkctrl,
(*prcm)-cm_memif_emif_1_clkctrl,
(*prcm)-cm_memif_emif_2_clkctrl,
(*prcm)-cm_l4cfg_l4_cfg_clkctrl,
@@ -503,6 +503,10 @@ void hw_data_init(void)
*omap_vcores = omap5430_volts_es2;
break;
+ case DRA752_ES1_0:
+ *prcm = dra7xx_prcm;
+ break;
+
default:
printf(\n INVALID OMAP REVISION );
}
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index d8f711c..6ed 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -354,7 +354,12 @@ void reset_cpu(ulong ignored)
* So use cold reset in case instead.
*/
if (omap_rev == OMAP5430_ES1_0)
- writel(PRM_RSTCTRL_RESET 0x1, PRM_RSTCTRL);
+ writel(PRM_RSTCTRL_RESET 0x1, (*prcm)-prm_rstctrl);
else
- writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+ writel(PRM_RSTCTRL_RESET, (*prcm)-prm_rstctrl);
+}
+
+u32 warm_reset(void)
+{
+ return readl((*prcm)-prm_rstst) PRM_RSTST_WARM_RESET_MASK;
}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 5e5abcc..ade9875 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -156,7 +156,7 @@ struct prcm_regs const omap5_es1_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_2_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
@@ -296,6 +296,8 @@ struct prcm_regs const omap5_es1_prcm = {
.cm_wkup_bandgap_clkctrl = 0x4ae07888,
.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
+ .prm_rstctrl = 0x4ae07b00,
+ .prm_rstst = 0x4ae07b04,
.prm_vc_val_bypass = 0x4ae07ba0,
.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
@@ -513,7 +515,7 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_2_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
@@ -653,6 +655,8 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_wkup_bandgap_clkctrl = 0x4ae07988
[U-Boot] [PATCH V2 7/7] arm: dra7xx: Add dra7xx_evm build support
Adding the build support for dra7xx_evm.
Reusing omap5_evm.h config by moving it to omap5_common.h
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
[v2] Addressed Tom Rini's tr...@ti.com comments
boards.cfg |1 +
include/configs/dra7xx_evm.h| 36
include/configs/{omap5_evm.h = omap5_common.h} | 18 +-
include/configs/omap5_evm.h | 241 +--
4 files changed, 48 insertions(+), 248 deletions(-)
create mode 100644 include/configs/dra7xx_evm.h
copy include/configs/{omap5_evm.h = omap5_common.h} (94%)
diff --git a/boards.cfg b/boards.cfg
index 98f7a14..fea1101 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -279,6 +279,7 @@ nokia_rx51 arm armv7 rx51
nokia
omap4_panda arm armv7 panda ti
omap4
omap4_sdp4430arm armv7 sdp4430 ti
omap4
omap5_evmarm armv7 omap5_evm ti
omap5
+dra7xx_evm arm armv7 dra7xx ti
omap5
s5p_goni arm armv7 goni
samsungs5pc1xx
smdkc100 arm armv7 smdkc100
samsungs5pc1xx
origen arm armv7 origen
samsungexynos
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
new file mode 100644
index 000..10a4939
--- /dev/null
+++ b/include/configs/dra7xx_evm.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Lokesh Vutla lokeshvu...@ti.com
+ *
+ * Configuration settings for the TI DRA7XX board.
+ * See omap5_common.h for omap5 common settings.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_DRA7XX_EVM_H
+#define __CONFIG_DRA7XX_EVM_H
+
+#include configs/omap5_common.h
+
+#define CONFIG_DRA7XX /* in a TI DRA7XX core */
+#define CONFIG_SYS_PROMPT DRA752 EVM #
+
+#endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_common.h
similarity index 94%
copy from include/configs/omap5_evm.h
copy to include/configs/omap5_common.h
index 1d3ac2b..a162d63 100644
--- a/include/configs/omap5_evm.h
+++ b/include/configs/omap5_common.h
@@ -1,12 +1,12 @@
/*
- * (C) Copyright 2010
+ * (C) Copyright 2013
* Texas Instruments Incorporated.
* Sricharan R r.sricha...@ti.com
*
* Derived from OMAP4 done by:
* Aneesh V ane...@ti.com
*
- * Configuration settings for the TI EVM5430 board.
+ * TI OMAP5 AND DRA7XX common configuration settings
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -27,17 +27,14 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_OMAP5_COMMON_H
+#define __CONFIG_OMAP5_COMMON_H
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP/* in a TI OMAP core */
#define CONFIG_OMAP54XX/* which is a 54XX */
-#define CONFIG_OMAP5430/* which is in a 5430 */
-#define CONFIG_5430EVM /* working with EVM */
#define CONFIG_OMAP_GPIO
/* Get CPU defs */
@@ -96,10 +93,6 @@
#define CONFIG_DRIVER_OMAP34XX_I2C
#define CONFIG_I2C_MULTI_BUS
-/* TWL6035 */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_TWL6035_POWER
-#endif
/* MMC */
#define CONFIG_GENERIC_MMC
@@ -185,7 +178,6 @@
#define CONFIG_SYS_LONGHELP/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use hush command parser */
-#define CONFIG_SYS_PROMPT OMAP5430 EVM #
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
@@ -266,4 +258,4 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10/* 1 MB */
#define CONFIG_SPL_GPIO_SUPPORT
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_OMAP5_COMMON_H */
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h
Re: [U-Boot] [U-Boot, 6/7] arm: dra7xx: Add board files for DRA7XX socs
On Tuesday 12 March 2013 12:05 AM, Tom Rini wrote:
On Tue, Feb 12, 2013 at 09:29:08PM -, Lokesh Vutla wrote:
Adding new board files for DRA7XX socs.
The pad registers layout is changed completely from OMAP5
So introducing the new structure here and also adding the
minimal data.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Nishant Kamat nska...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Reviewed-by: Tom Rini tr...@ti.com
With the following change to adapt to the omap_mmc_init changes I've
also taken into u-boot-ti/master:
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index cd344da..7bbb549 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -96,8 +96,8 @@ void set_muxconf_regs_essential(void)
#if !defined(CONFIG_SPL_BUILD) defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- omap_mmc_init(1, 0, 0);
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
#endif
This is now applied to u-boot-ti/master, thanks!
Ok..Thanks..
Regards,
Lokesh
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[U-Boot] [PATCH] ARM: OMAP4+: Fix MA detection during SDRAM_AUTO_DETECTION
During SDRAM_AUTO_DETECTION MA is not configured. For Soc's OMAP4460 MA is present. So populating MA for the same. Tested on OMAP4430 PANDA, OMAP4460 PANDA. Reported-by: Dan Murphy dmur...@ti.com Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- arch/arm/cpu/armv7/omap-common/emif-common.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 11e830a..e6287cd 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1180,6 +1180,9 @@ void dmm_init(u32 base) /* TRAP for invalid TILER mappings in section 0 */ lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; + if (omap_revision() = OMAP4460_ES1_0) + lis_map_regs_calculated.is_ma_present = 1; + lisa_map_regs = lis_map_regs_calculated; #endif struct dmm_lisa_map_regs *hw_lisa_map_regs = -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm, am33xx: move s_init to a common place
Hi Heiko, On Thursday 20 June 2013 09:22 AM, Heiko Schocher wrote: Hello Tom, Am 14.06.2013 16:58, schrieb Tom Rini: On Fri, Jun 14, 2013 at 07:59:26AM +0200, Heiko Schocher wrote: Hello Tom, Am 13.06.2013 17:53, schrieb Tom Rini: On Thu, Jun 13, 2013 at 05:53:17AM +0200, Heiko Schocher wrote: move s_init from every board code to a common place. Signed-off-by: Heiko Schocher h...@denx.de Cc: Tom Rini tr...@ti.com Cc: Matt Porter mpor...@ti.com Cc: Lars Poeschel poesc...@lemonage.de Cc: Tom Rini tr...@ti.com Cc: Enric Balletbo i Serra eballe...@iseebcn.com --- This patch is based on the following patches: - [U-Boot,v2] arm, am33xx: move rtc32k_enable() to common place http://patchwork.ozlabs.org/patch/248908/ - [U-Boot] arm, am33xx: move uart soft reset code to common place http://patchwork.ozlabs.org/patch/248508/ These two apply best to u-boot-ti, and with them this patch doesn't apply cleanly. Please sort that out. I based my patches on u-boot ... I look at this .. The following adds moving ti814x_evm into the mix and I've sent Matt some binaries to give a whirl to test on the board: [...] /* * Basic board specific setup. Pinmux has been handled already. Please fold into v2 Signed-off-by: Tom Rini tr...@ti.com Ok, thanks! There's a minor bug in what I posted, however. ti814x needs timer_init called _before_ pll_init() as setting the sata clocks (which are shared with other periphrals that we do enable right now) needs udelay(50) to settle as we go along. That also needs to be commented in the code as I had to think about it for a bit to recall exactly what was going on. Do you have an update here for me? We can have a timer_init for am33xx boards also. It doesn't harm. So keep timer_init in your common s_init BTW: I just realized that I have on one of the three boards a problem, that in spl code calling the rtc32k_enable() crashes ... which votes against moving this to a common place ... I haveno real idea why ... did you heard from such a behaviour? Is there some am335x soc, which differs from the others? On which board it is giving a problem? Did you make sure clocks for rtc are enabled? I am making a cleanup series for am33xx boards. If you don't mind can I take this patch as part of my series. Thanks and regards, Lokesh You aren't using a different clock crystal rate than the reference platforms, are you? I know that's a problem that needs solving still. I am prospecting, whats going on here ... but have no real idea, why it is not possible to write this registers ... if writing this registers, cpu hang ... But I want to have a common function here ... maybe it is OK to make the rtc32k_enable() call configurable through a define? Saying CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K and document in the u-boot README this define, and why it is necessary? bye, Heiko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] ARM: AM33xx: Cleanup dplls data
Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/Makefile |1 +
arch/arm/cpu/armv7/am33xx/clock.c| 116 ++
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 222 +-
arch/arm/cpu/armv7/am33xx/emif4.c|4 +
arch/arm/include/asm/arch-am33xx/clock.h | 68
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 +
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
7 files changed, 232 insertions(+), 182 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile
b/arch/arm/cpu/armv7/am33xx/Makefile
index c97e30d..f4ccd2a 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -18,6 +18,7 @@ LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
COBJS-$(CONFIG_TI814X) += clock_ti814x.o
+COBJS-$(CONFIG_AM33XX) += clock.o
COBJS += sys_info.o
COBJS += mem.o
COBJS += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 000..a7f1d83
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,116 @@
+/*
+ * clock.c
+ *
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/clock.h
+#include asm/arch/hardware.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+const struct dpll_params *params)
+{
+ /* Setup post-dividers */
+ if (params-m2 = 0)
+ writel(params-m2, dpll_regs-cm_div_m2_dpll);
+ if (params-m3 = 0)
+ writel(params-m3, dpll_regs-cm_div_m3_dpll);
+ if (params-m4 = 0)
+ writel(params-m4, dpll_regs-cm_div_m4_dpll);
+ if (params-m5 = 0)
+ writel(params-m5, dpll_regs-cm_div_m5_dpll);
+ if (params-m6 = 0)
+ writel(params-m6, dpll_regs-cm_div_m6_dpll);
+}
+
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
+{
+ clrsetbits_le32(dpll_regs-cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_LOCK CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
+{
+ if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+ (void *)dpll_regs-cm_idlest_dpll, LDELAY)) {
+ printf(DPLL locking failed for 0x%x\n,
+ dpll_regs-cm_clkmode_dpll);
+ hang();
+ }
+}
+
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+ clrsetbits_le32(dpll_regs-cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_MN_BYPASS CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
+{
+ if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+ (void *)dpll_regs-cm_idlest_dpll, LDELAY)) {
+ printf(Bypassing DPLL failed 0x%x\n,
+ dpll_regs-cm_clkmode_dpll);
+ }
+}
+
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+ do_bypass_dpll(dpll_regs);
+ wait_for_bypass(dpll_regs);
+}
+
+static void do_setup_dpll(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
+{
+ u32 temp;
+
+ if (!params)
+ return;
+
+ temp = readl(dpll_regs-cm_clksel_dpll);
+
+ bypass_dpll(dpll_regs);
+
+ /* Set M N */
+ temp = ~CM_CLKSEL_DPLL_M_MASK;
+ temp |= (params-m CM_CLKSEL_DPLL_M_SHIFT) CM_CLKSEL_DPLL_M_MASK;
+
+ temp = ~CM_CLKSEL_DPLL_N_MASK;
+ temp |= (params-n CM_CLKSEL_DPLL_N_SHIFT) CM_CLKSEL_DPLL_N_MASK;
+
+ writel(temp, dpll_regs-cm_clksel_dpll);
+
+ setup_post_dividers(dpll_regs, params);
+
+ /* Wait till the DPLL locks */
+ do_lock_dpll(dpll_regs);
+ wait_for_lock(dpll_regs);
+}
+
+void setup_dplls(void)
+{
+ do_setup_dpll
[U-Boot] [PATCH 4/4] musb: Disable extra prints
There are many musb prints in SPL and U-Boot log.
These prints are required only during musb debug.
So replacing printk with pr_debug in musb_core.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/usb/musb-new/musb_core.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index da93571..a7d1c56 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -1311,9 +1311,7 @@ static int __devinit ep_config_from_table(struct musb
*musb)
break;
}
- printk(KERN_DEBUG %s: setup fifo_mode %d\n,
- musb_driver_name, fifo_mode);
-
+ pr_debug(%s: setup fifo_mode %d\n, musb_driver_name, fifo_mode);
done:
offset = fifo_setup(musb, hw_ep, ep0_cfg, 0);
@@ -1341,10 +1339,9 @@ done:
musb-nr_endpoints = max(epn, musb-nr_endpoints);
}
- printk(KERN_DEBUG %s: %d/%d max ep, %d/%d memory\n,
- musb_driver_name,
- n + 1, musb-config-num_eps * 2 - 1,
- offset, (1 (musb-config-ram_bits + 2)));
+ pr_debug(%s: %d/%d max ep, %d/%d memory\n, musb_driver_name, n + 1,
+musb-config-num_eps * 2 - 1, offset,
+(1 (musb-config-ram_bits + 2)));
if (!musb-bulk_ep) {
pr_debug(%s: missing bulk\n, musb_driver_name);
@@ -1447,8 +1444,7 @@ static int __devinit musb_core_init(u16 musb_type, struct
musb *musb)
if (reg MUSB_CONFIGDATA_SOFTCONE)
strcat(aInfo, , SoftConn);
- printk(KERN_DEBUG %s: ConfigData=0x%02x (%s)\n,
- musb_driver_name, reg, aInfo);
+ pr_debug(%s:ConfigData=0x%02x (%s)\n, musb_driver_name, reg, aInfo);
aDate[0] = 0;
if (MUSB_CONTROLLER_MHDRC == musb_type) {
@@ -1469,8 +1465,8 @@ static int __devinit musb_core_init(u16 musb_type, struct
musb *musb)
snprintf(aRevision, 32, %d.%d%s, MUSB_HWVERS_MAJOR(musb-hwvers),
MUSB_HWVERS_MINOR(musb-hwvers),
(musb-hwvers MUSB_HWVERS_RC) ? RC : );
- printk(KERN_DEBUG %s: %sHDRC RTL version %s %s\n,
- musb_driver_name, type, aRevision, aDate);
+ pr_debug(%s: %sHDRC RTL version %s %s\n, musb_driver_name, type,
+aRevision, aDate);
/* configure ep0 */
musb_configure_ep0(musb);
--
1.7.9.5
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[U-Boot] [PATCH 0/4] ARM: AM33xx: Cleanup clocks and hwinit
This series tries to cleanup code for AM33xx, inorder to ensure code reusabilty by moving the duplicated code to common place. This also helps in addition of new Soc with minimal changes. Testing: Boot tested on BeagleBone White/Black, AM35xx EVM, TI814x. Verified MAKEALL for armv7 and am33xx boards. This series is on top of u-boot merged with u-boot-arm. Heiko Schocher (1): ARM: AM33xx: Move s_init to a common place Lokesh Vutla (3): ARM: AM33xx: Cleanup dplls data ARM: AM33xx: Cleanup clocks layer musb: Disable extra prints arch/arm/cpu/armv7/am33xx/Makefile |1 + arch/arm/cpu/armv7/am33xx/board.c| 52 ++- arch/arm/cpu/armv7/am33xx/clock.c| 176 arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 497 +- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 25 +- arch/arm/cpu/armv7/am33xx/emif4.c| 11 +- arch/arm/include/asm/arch-am33xx/clock.h | 92 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |6 +- arch/arm/include/asm/arch-am33xx/sys_proto.h |6 +- board/isee/igep0033/board.c | 48 +-- board/phytec/pcm051/board.c | 48 +-- board/ti/am335x/board.c | 50 +-- board/ti/ti814x/evm.c| 65 +-- drivers/usb/musb-new/musb_core.c | 18 +- 14 files changed, 498 insertions(+), 597 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] ARM: AM33xx: Move s_init to a common place
From: Heiko Schocher h...@denx.de
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Heiko Schocher h...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c| 46 +--
arch/arm/cpu/armv7/am33xx/clock_ti814x.c |6 ++
arch/arm/cpu/armv7/am33xx/emif4.c|6 +-
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |6 +-
arch/arm/include/asm/arch-am33xx/sys_proto.h |5 +-
board/isee/igep0033/board.c | 49 +++-
board/phytec/pcm051/board.c | 48 +++-
board/ti/am335x/board.c | 52 +++--
board/ti/ti814x/evm.c| 67 +++---
9 files changed, 90 insertions(+), 195 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 1d743d6..3d08673 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -145,7 +145,7 @@ int arch_misc_init(void)
}
#ifdef CONFIG_SPL_BUILD
-void rtc32k_enable(void)
+static void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
@@ -161,11 +161,7 @@ void rtc32k_enable(void)
writel((1 3) | (1 6), rtc-osc);
}
-#define UART_RESET (0x1 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 0x3)
-
-void uart_soft_reset(void)
+static void uart_soft_reset(void)
{
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
u32 regval;
@@ -182,4 +178,42 @@ void uart_soft_reset(void)
regval |= UART_SMART_IDLE_EN;
writel(regval, uart_base-uartsyscfg);
}
+
+static void watchdog_disable(void)
+{
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ writel(0x, wdtimer-wdtwspr);
+ while (readl(wdtimer-wdtwwps) != 0x0)
+ ;
+ writel(0x, wdtimer-wdtwspr);
+ while (readl(wdtimer-wdtwwps) != 0x0)
+ ;
+}
#endif
+
+void s_init(void)
+{
+ /*
+* Save the boot parameters passed from romcode.
+* We cannot delay the saving further than this,
+* to prevent overwrites.
+*/
+#ifdef CONFIG_SPL_BUILD
+ save_omap_boot_params();
+ watchdog_disable();
+ timer_init();
+ set_uart_mux_conf();
+ setup_clocks_for_console();
+ uart_soft_reset();
+
+ gd = gdata;
+ preloader_console_init();
+
+ prcm_init();
+ set_mux_conf_regs();
+ /* Enable RTC32K clock */
+ rtc32k_enable();
+ sdram_init();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 1a23746..ca7d7ad 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -285,6 +285,12 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, cmalwon-ethernet1clkctrl);
while ((readl(cmalwon-ethernet1clkctrl) ENET_CLKCTRL_CMPL) != 0)
;
+
+ /* RTC clocks */
+ writel(PRCM_MOD_EN, cmalwon-rtcclkstctrl);
+ writel(PRCM_MOD_EN, cmalwon-rtcclkctrl);
+ while (readl(cmalwon-rtcclkctrl) != PRCM_MOD_EN)
+ ;
}
/*
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 47d3dee..3abb609 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -44,8 +44,6 @@ void dram_init_banksize(void)
#ifdef CONFIG_SPL_BUILD
-static struct dmm_lisa_map_regs *hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)DMM_BASE;
static struct vtp_reg *vtpreg[2] = {
(struct vtp_reg *)VTP0_CTRL_ADDR,
(struct vtp_reg *)VTP1_CTRL_ADDR};
@@ -53,6 +51,9 @@ static struct vtp_reg *vtpreg[2] = {
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
#endif
+#ifdef CONFIG_TI81XX
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+ (struct dmm_lisa_map_regs *)DMM_BASE;
void config_dmm(const struct dmm_lisa_map_regs *regs)
{
enable_dmm_clocks();
@@ -67,6 +68,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs)
writel(regs-dmm_lisa_map_1, hw_lisa_map_regs-dmm_lisa_map_1);
writel(regs-dmm_lisa_map_0, hw_lisa_map_regs-dmm_lisa_map_0);
}
+#endif
static void config_vtp(int nr)
{
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 89b63d9..dc49e7e 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -24,8 +24,10 @@
#define CONFIG_SYS_MPUCLK 550
#endif
-extern void pll_init(void);
-extern void
[U-Boot] [PATCH 2/4] ARM: AM33xx: Cleanup clocks layer
Cleaning up the clocks layer.
This helps in addition of new Soc with minimal
changes.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c |6 -
arch/arm/cpu/armv7/am33xx/clock.c | 62 +-
arch/arm/cpu/armv7/am33xx/clock_am33xx.c| 275 ---
arch/arm/cpu/armv7/am33xx/clock_ti814x.c| 19 +-
arch/arm/cpu/armv7/am33xx/emif4.c |1 -
arch/arm/include/asm/arch-am33xx/clock.h| 28 ++-
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 -
board/isee/igep0033/board.c | 11 +-
board/ti/am335x/board.c | 10 +-
board/ti/ti814x/evm.c | 12 +-
10 files changed, 193 insertions(+), 233 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index b935a29..1d743d6 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -64,12 +64,6 @@ int cpu_mmc_init(bd_t *bis)
}
#endif
-void setup_clocks_for_console(void)
-{
- /* Not yet implemented */
- return;
-}
-
/* AM33XX has two MUSB controllers which can be host or gadget */
#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) \
(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
index a7f1d83..372e369 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -106,7 +106,7 @@ static void do_setup_dpll(const struct dpll_regs *dpll_regs,
wait_for_lock(dpll_regs);
}
-void setup_dplls(void)
+static void setup_dplls(void)
{
do_setup_dpll(dpll_core_regs, dpll_core);
do_setup_dpll(dpll_mpu_regs, dpll_mpu);
@@ -114,3 +114,63 @@ void setup_dplls(void)
writel(0x300, cmwkup-clkdcoldodpllper);
do_setup_dpll(dpll_ddr_regs, dpll_ddr);
}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+ u32 bound = LDELAY;
+
+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl MODULE_CLKCTRL_IDLEST_MASK)
+MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf(Clock enable failed for 0x%p idlest 0x%x\n,
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32
enable_mode,
+ u32 wait_for_enable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ enable_mode MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug(Enable clock module - %p\n, clkctrl_addr);
+ if (wait_for_enable)
+ wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ enable_mode CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug(Enable clock domain - %p\n, clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+ u32 i, max = 100;
+
+ /* Put the clock domains in SW_WKUP mode */
+ for (i = 0; (i max) clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ }
+
+ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+ for (i = 0; (i max) clk_modules_explicit_en[i]; i++) {
+ enable_clock_module(clk_modules_explicit_en[i],
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+ wait_for_enable);
+ };
+}
+
+void prcm_init()
+{
+ enable_basic_clocks();
+ setup_dplls();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index e878b25..b0b5c8b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -22,17 +22,12 @@
#include asm/arch/hardware.h
#include asm/io.h
-#define PRCM_MOD_EN0x2
-#define PRCM_FORCE_WAKEUP 0x2
-#define PRCM_FUNCTL0x0
-
-#define CPGMAC0_IDLE 0x3
#define OSC(V_OSCK/100)
-const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct
Re: [U-Boot] [PATCH] arm, am33xx: move s_init to a common place
Hi Heiko, On Monday 24 June 2013 09:46 PM, Heiko Schocher wrote: Hello Lokesh, Am 24.06.2013 06:01, schrieb Lokesh Vutla: Hi Heiko, On Thursday 20 June 2013 09:22 AM, Heiko Schocher wrote: Hello Tom, Am 14.06.2013 16:58, schrieb Tom Rini: On Fri, Jun 14, 2013 at 07:59:26AM +0200, Heiko Schocher wrote: Hello Tom, Am 13.06.2013 17:53, schrieb Tom Rini: On Thu, Jun 13, 2013 at 05:53:17AM +0200, Heiko Schocher wrote: move s_init from every board code to a common place. Signed-off-by: Heiko Schocher h...@denx.de Cc: Tom Rini tr...@ti.com Cc: Matt Porter mpor...@ti.com Cc: Lars Poeschel poesc...@lemonage.de Cc: Tom Rini tr...@ti.com Cc: Enric Balletbo i Serra eballe...@iseebcn.com --- This patch is based on the following patches: - [U-Boot,v2] arm, am33xx: move rtc32k_enable() to common place http://patchwork.ozlabs.org/patch/248908/ - [U-Boot] arm, am33xx: move uart soft reset code to common place http://patchwork.ozlabs.org/patch/248508/ These two apply best to u-boot-ti, and with them this patch doesn't apply cleanly. Please sort that out. I based my patches on u-boot ... I look at this .. The following adds moving ti814x_evm into the mix and I've sent Matt some binaries to give a whirl to test on the board: [...] /* * Basic board specific setup. Pinmux has been handled already. Please fold into v2 Signed-off-by: Tom Rini tr...@ti.com Ok, thanks! There's a minor bug in what I posted, however. ti814x needs timer_init called _before_ pll_init() as setting the sata clocks (which are shared with other periphrals that we do enable right now) needs udelay(50) to settle as we go along. That also needs to be commented in the code as I had to think about it for a bit to recall exactly what was going on. Do you have an update here for me? We can have a timer_init for am33xx boards also. It doesn't harm. So keep timer_init in your common s_init Ok, fine. BTW: I just realized that I have on one of the three boards a problem, that in spl code calling the rtc32k_enable() crashes ... which votes against moving this to a common place ... I haveno real idea why ... did you heard from such a behaviour? Is there some am335x soc, which differs from the others? On which board it is giving a problem? Not in mainline yet, posting soon ... Did you make sure clocks for rtc are enabled? Yes. I posted a clean up series for am33xx today [PATCH 0/4] ARM: AM33xx: Cleanup clocks and hwinit Can you please try with this series on your board. Check the SPL log for any clock failure. If no error, then ideally registers should be accessible. (Please make sure register offsets that you are using are correct). If not there is something really bad. Thanks and regards, Lokesh I have 3 boards with an am335x, two works with the rtc32k_enable() call without problems ... the third board hang when accessing rtc registers ... no idea why ... Code on all three boards is at this point identical, all use 24MHz ... I am making a cleanup series for am33xx boards. If you don't mind can I take this patch as part of my series. I am fine with that ... but what do we do with my probem with rtc23k_enable? Thanks and regards, Lokesh You aren't using a different clock crystal rate than the reference platforms, are you? I know that's a problem that needs solving still. I am prospecting, whats going on here ... but have no real idea, why it is not possible to write this registers ... if writing this registers, cpu hang ... But I want to have a common function here ... maybe it is OK to make the rtc32k_enable() call configurable through a define? Saying CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K and document in the u-boot README this define, and why it is necessary? Would this be acceptable? bye, Heiko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] ARM: AM33xx: Cleanup dplls data
Hi Heiko,
On Tuesday 25 June 2013 12:42 AM, Heiko Schocher wrote:
Hello Lokesh,
Am 24.06.2013 15:15, schrieb Lokesh Vutla:
Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/Makefile |1 +
arch/arm/cpu/armv7/am33xx/clock.c| 116 ++
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 222 +-
arch/arm/cpu/armv7/am33xx/emif4.c|4 +
arch/arm/include/asm/arch-am33xx/clock.h | 68
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 +
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
7 files changed, 232 insertions(+), 182 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
[...]
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 000..a7f1d83
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,116 @@
[...]
+static void do_setup_dpll(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
+{
Could we have this function not only static? I posted a patch:
[U-Boot] arm, am335x: make mpu pll config configurable
http://patchwork.ozlabs.org/patch/248509/
which uses mpu_pll_config() for switching mpu pll clock
from board code ... you delete this function later in this patch,
so I think, I can switch to do_setup_pll() ... if this is not
static code ...
Yes I saw that patch. No need to make this non-static.
Please have your own struct const struct dpll_params dpll_mpu
and update your values accordingly.
Thanks and regards,
Lokesh
[...]
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index 9c4d0b4..e878b25 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -26,56 +26,53 @@
#define PRCM_FORCE_WAKEUP 0x2
#define PRCM_FUNCTL 0x0
-#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
-#define PRCM_L3_GCLK_ACTIVITY BIT(4)
-
-#define PLL_BYPASS_MODE0x4
-#define ST_MN_BYPASS 0x0100
-#define ST_DPLL_CLK0x0001
-#define CLK_SEL_MASK 0x7
-#define CLK_DIV_MASK 0x1f
-#define CLK_DIV2_MASK 0x7f
-#define CLK_SEL_SHIFT 0x8
-#define CLK_MODE_SEL 0x7
-#define CLK_MODE_MASK 0xfff8
-#define CLK_DIV_SEL0xFFE0
#define CPGMAC0_IDLE 0x3
-#define DPLL_CLKDCOLDO_GATE_CTRL0x300
-
#define OSC (V_OSCK/100)
and could we move this define then to
arch/arm/include/asm/arch-am33xx/clock.h
too?
Thnaks!
bye,
Heiko
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Re: [U-Boot] [PATCH 1/4] ARM: AM33xx: Cleanup dplls data
Hi Heiko,
On Tuesday 25 June 2013 10:24 AM, Heiko Schocher wrote:
Hello Lokesh,
Am 25.06.2013 05:48, schrieb Lokesh Vutla:
Hi Heiko,
On Tuesday 25 June 2013 12:42 AM, Heiko Schocher wrote:
Hello Lokesh,
Am 24.06.2013 15:15, schrieb Lokesh Vutla:
Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/Makefile |1 +
arch/arm/cpu/armv7/am33xx/clock.c| 116 ++
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 222
+-
arch/arm/cpu/armv7/am33xx/emif4.c|4 +
arch/arm/include/asm/arch-am33xx/clock.h | 68
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 +
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
7 files changed, 232 insertions(+), 182 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
[...]
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 000..a7f1d83
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,116 @@
[...]
+static void do_setup_dpll(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
+{
Could we have this function not only static? I posted a patch:
[U-Boot] arm, am335x: make mpu pll config configurable
http://patchwork.ozlabs.org/patch/248509/
which uses mpu_pll_config() for switching mpu pll clock
from board code ... you delete this function later in this patch,
so I think, I can switch to do_setup_pll() ... if this is not
static code ...
Yes I saw that patch. No need to make this non-static.
Please have your own struct const struct dpll_params dpll_mpu
and update your values accordingly.
Hmm.. maybe I miss something here. You call setup_dplls()
in arch/arm/cpu/armv7/am33xx/clock.c using dpll_mpu defined
in arch/arm/cpu/armv7/am33xx/clock_am33xx.c ... so how to
make here a board specific struct?
The MPUCLK is configurable through the define CONFIG_SYS_MPUCLK
which is good, but I have on this board a PMIC, which in board SPL
code change MPU and core voltage ... and after that I change
the MPU clock again ...
Ohk.
Can't we scale the voltages before calling setup_dplls()
(Why do you want to configure the MPU clocks twice?
I don't know much about your board, so I am just asking..:) )
What I meant is something like below:
void __weak scale_vcores(void)
{}
void prcm_init()
{
enable_basic_clocks();
scale_vcores();
setup_dplls();
}
have your own scale_vcores in your board file.
and for dpll_mpu have something like this:
#ifdef CONFIG_BOARD
const struct dpll_params dpll_mpu = {
M, N, 1, -1, -1, -1, -1};
#else
const struct dpll_params dpll_mpu = {
CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
#endif
I hope this should be possible on your board.
I am telling this because it will be easy for me during my next cleanup
during
which I planned to combine omap-common and am33xx code..:)
This is the exactly what is done for omap( program voltages and then
setup dplls)
You can refer to arch/arm/cpu/armv7/omap-common/clocks-common.c
prcm_init() function.
Please correct me if I am wrong..
Thanks and regards,
Lokesh
bye,
Heiko
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Re: [U-Boot] [PATCH 1/4] ARM: AM33xx: Cleanup dplls data
Hi Heiko,
On Tuesday 25 June 2013 12:35 PM, Heiko Schocher wrote:
Hello Lokesh,
Am 25.06.2013 07:39, schrieb Lokesh Vutla:
Hi Heiko,
On Tuesday 25 June 2013 10:24 AM, Heiko Schocher wrote:
Hello Lokesh,
Am 25.06.2013 05:48, schrieb Lokesh Vutla:
Hi Heiko,
On Tuesday 25 June 2013 12:42 AM, Heiko Schocher wrote:
Hello Lokesh,
Am 24.06.2013 15:15, schrieb Lokesh Vutla:
Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/Makefile |1 +
arch/arm/cpu/armv7/am33xx/clock.c| 116 ++
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 222
+-
arch/arm/cpu/armv7/am33xx/emif4.c|4 +
arch/arm/include/asm/arch-am33xx/clock.h | 68
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 +
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
7 files changed, 232 insertions(+), 182 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
[...]
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 000..a7f1d83
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,116 @@
[...]
+static void do_setup_dpll(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
+{
Could we have this function not only static? I posted a patch:
[U-Boot] arm, am335x: make mpu pll config configurable
http://patchwork.ozlabs.org/patch/248509/
which uses mpu_pll_config() for switching mpu pll clock
from board code ... you delete this function later in this patch,
so I think, I can switch to do_setup_pll() ... if this is not
static code ...
Yes I saw that patch. No need to make this non-static.
Please have your own struct const struct dpll_params dpll_mpu
and update your values accordingly.
Hmm.. maybe I miss something here. You call setup_dplls()
in arch/arm/cpu/armv7/am33xx/clock.c using dpll_mpu defined
in arch/arm/cpu/armv7/am33xx/clock_am33xx.c ... so how to
make here a board specific struct?
The MPUCLK is configurable through the define CONFIG_SYS_MPUCLK
which is good, but I have on this board a PMIC, which in board SPL
code change MPU and core voltage ... and after that I change
the MPU clock again ...
Ohk.
Can't we scale the voltages before calling setup_dplls()
(Why do you want to configure the MPU clocks twice?
I speak with the customer ...
I don't know much about your board, so I am just asking..:) )
What I meant is something like below:
void __weak scale_vcores(void)
{}
void prcm_init()
{
enable_basic_clocks();
scale_vcores();
setup_dplls();
}
have your own scale_vcores in your board file.
and for dpll_mpu have something like this:
#ifdef CONFIG_BOARD
const struct dpll_params dpll_mpu = {
M, N, 1, -1, -1, -1, -1};
#else
const struct dpll_params dpll_mpu = {
CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
#endif
No, that is not good. We should prevent such board specific
defines in common code. I think this define is not necessary,
as, if we have a scale_vcore() function, I can set
CONFIG_SYS_MPUCLK to the end value ! I try this out! Thanks!
My idea here is to populate data according to the board.
Its good if you use the same value.
I hope this should be possible on your board.
I am telling this because it will be easy for me during my next cleanup
during
which I planned to combine omap-common and am33xx code..:)
Ok, i try it ...
This is the exactly what is done for omap( program voltages and then
setup dplls)
You can refer to arch/arm/cpu/armv7/omap-common/clocks-common.c
prcm_init() function.
Please correct me if I am wrong..
Yes, that looks good. Hmm... have we access to an pmic connected
over i2c at this time?
you can do an i2c_init() here.
Thanks and regards,
Lokesh
bye,
Heiko
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Re: [U-Boot] [PATCH 0/4] ARM: AM33xx: Cleanup clocks and hwinit
Hi Tom, On Monday 24 June 2013 06:45 PM, Lokesh Vutla wrote: This series tries to cleanup code for AM33xx, inorder to ensure code reusabilty by moving the duplicated code to common place. This also helps in addition of new Soc with minimal changes. Testing: Boot tested on BeagleBone White/Black, AM35xx EVM, TI814x. Verified MAKEALL for armv7 and am33xx boards. You have any other comments on this series ? Thanks and regards, Lokesh This series is on top of u-boot merged with u-boot-arm. Heiko Schocher (1): ARM: AM33xx: Move s_init to a common place Lokesh Vutla (3): ARM: AM33xx: Cleanup dplls data ARM: AM33xx: Cleanup clocks layer musb: Disable extra prints arch/arm/cpu/armv7/am33xx/Makefile |1 + arch/arm/cpu/armv7/am33xx/board.c| 52 ++- arch/arm/cpu/armv7/am33xx/clock.c| 176 arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 497 +- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 25 +- arch/arm/cpu/armv7/am33xx/emif4.c| 11 +- arch/arm/include/asm/arch-am33xx/clock.h | 92 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |6 +- arch/arm/include/asm/arch-am33xx/sys_proto.h |6 +- board/isee/igep0033/board.c | 48 +-- board/phytec/pcm051/board.c | 48 +-- board/ti/am335x/board.c | 50 +-- board/ti/ti814x/evm.c| 65 +-- drivers/usb/musb-new/musb_core.c | 18 +- 14 files changed, 498 insertions(+), 597 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] ARM: AM33xx: Cleanup clocks and hwinit
On Wednesday 26 June 2013 05:39 PM, Tom Rini wrote: On Wed, Jun 26, 2013 at 09:54:00AM +0530, Lokesh Vutla wrote: Hi Tom, On Monday 24 June 2013 06:45 PM, Lokesh Vutla wrote: This series tries to cleanup code for AM33xx, inorder to ensure code reusabilty by moving the duplicated code to common place. This also helps in addition of new Soc with minimal changes. Testing: Boot tested on BeagleBone White/Black, AM35xx EVM, TI814x. Verified MAKEALL for armv7 and am33xx boards. You have any other comments on this series ? Looks good, I'll pick it up for u-boot-ti/next soon. Thanks Tom.!! Regards, Lokesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] Add TI816X evm board support
Hi Antoine,
On Wednesday 19 June 2013 03:38 PM, TENART Antoine wrote:
Signed-off-by: Antoine Tenart aten...@adeneo-embedded.com
---
MAINTAINERS |4 +
board/ti/ti816x/Makefile | 47
board/ti/ti816x/evm.c| 249 ++
boards.cfg |1 +
include/configs/ti816x_evm.h | 188 +++
5 files changed, 489 insertions(+)
create mode 100644 board/ti/ti816x/Makefile
create mode 100644 board/ti/ti816x/evm.c
create mode 100644 include/configs/ti816x_evm.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 7820375..38ff5c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -940,6 +940,10 @@ Lucas Stach d...@lynxeye.de
colibri_t20_irisTegra20 (ARM7 A9 Dual Core)
+Antoine Tenart aten...@adeneo-embedded.com
+
+ TI816X ARM ARMV7 (TI816x Soc)
+
Nick Thompson nick.thomp...@gefanuc.com
da830evmARM926EJS (DA830/OMAP-L137)
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
new file mode 100644
index 000..dc23d93
--- /dev/null
+++ b/board/ti/ti816x/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2013, Adeneo Embedded www.adeneo-embedded.com
+# Antoine Tenart, aten...@adeneo-embedded.com
+#
+# Based on TI-PSP-04.00.02.14 :
+#
+# Copyright (C) 2009, Texas Instruments, Incorporated
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation version 2.
+#
+# This program is distributed as is WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := evm.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
new file mode 100644
index 000..12e98d5
--- /dev/null
+++ b/board/ti/ti816x/evm.c
@@ -0,0 +1,249 @@
+/*
+ * evm.c
+ *
+ * Copyright (C) 2013, Adeneo Embedded www.adeneo-embedded.com
+ * Antoine Tenart, aten...@adeneo-embedded.com
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include common.h
+#include spl.h
+#include asm/cache.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/cpu.h
+#include asm/arch/ddr_defs.h
+#include asm/arch/hardware.h
+#include asm/arch/sys_proto.h
+#include asm/arch/mmc_host_def.h
+#include asm/arch/mem.h
+#include asm/arch/mux.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd-bd-bi_boot_params = PHYS_DRAM_1 + 0x100;
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+
+static struct module_pin_mux mmc_pin_mux[] = {
+ { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
+ { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { -1 },
+};
+
+const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+ .dmm_lisa_map_0 = 0x,
+ .dmm_lisa_map_1 = 0x,
+ .dmm_lisa_map_2 = 0x80640300,
+ .dmm_lisa_map_3 = 0xC0640320,
+};
+
+/*
+ * DDR2 related definitions
+ */
+
+static struct ddr_data ddr2_data = {
+ .datardsratio0 = ((0x4010) | (0x400)),
+ .datawdsratio0 = ((0x4A10) | (0x4A0)),
+ .datawiratio0 = ((0x010) | (0x00)),
+ .datagiratio0 = ((0x010) | (0x00)),
+ .datafwsratio0 = ((0x13A10) | (0x13A0)),
+ .datawrsratio0 = ((0x8A10) | (0x8A0)),
+ .datauserank0delay = 0x1,
+ .datadldiff0= 0x0, /* depend on cpu rev, set later */
+};
+
+static struct cmd_control ddr2_ctrl = {
+ .cmd0csratio= 0x80,
+ .cmd0dldiff = 0x04, /* reset value is 0x4 */
+ .cmd0iclkout= 0x00,
+
+ .cmd1csratio= 0x80,
+ .cmd1dldiff = 0x04,
+ .cmd1iclkout= 0x00,
+
+ .cmd2csratio= 0x80,
+
Re: [U-Boot] [PATCH] OMAP5: USB_EHCI: Enable ehci support for omap5
Hi Dan,
On Tuesday 09 July 2013 02:29 AM, Dan Murphy wrote:
From: Govindraj.R govindraj.r...@ti.com
* Enable all usb ehci related clocks.
* Add ehci support to omap5 board file and arch specific
sysc reg mask values.
* Enable config options for usb support and ethernet support
Signed-off-by: Govindraj.R govindraj.r...@ti.com
---
arch/arm/cpu/armv7/omap5/clocks.c| 20 +++---
arch/arm/include/asm/arch-omap5/clocks.h |6
arch/arm/include/asm/arch-omap5/ehci.h | 44
++
board/ti/omap5_evm/evm.c | 33 ++
include/configs/omap5_evm5430.h | 23 ++--
5 files changed, 120 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/include/asm/arch-omap5/ehci.h
Is this based on current mainline?
Most of the above files changed are not preset in mainline.
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c
b/arch/arm/cpu/armv7/omap5/clocks.c
index 7e69d2b..f914b60 100644
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -375,6 +375,8 @@ void enable_basic_clocks(void)
prcm-cm_l4per_gpio4_clkctrl,
prcm-cm_l4per_gpio5_clkctrl,
prcm-cm_l4per_gpio6_clkctrl,
+ prcm-cm_clksel_usb_60mhz,
+ prcm-cm_l3init_hsusbtll_clkctrl,
0
};
@@ -385,6 +387,7 @@ void enable_basic_clocks(void)
prcm-cm_wkup_wdtimer2_clkctrl,
prcm-cm_l4per_uart3_clkctrl,
prcm-cm_l4per_i2c1_clkctrl,
+ prcm-cm_l3init_hsusbhost_clkctrl,
0
};
@@ -408,10 +411,13 @@ void enable_basic_clocks(void)
setbits_le32(prcm-cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
+ /* Enbale all 3 usb ports enable uhh, utmi and hsic clocks*/
+ setbits_le32(prcm-cm_l3init_hsusbhost_clkctrl,
+ USB_HOST_HS_CLKCTRL_MASK);
+
+ /* Enbale all 3 usb host ports tll clocks*/
+ setbits_le32(prcm-cm_l3init_hsusbtll_clkctrl,
+ USB_TLL_HS_CLKCTRL_MASK);
Please keep this under a CONFIG_*_USB_* macro.
Thanks,
Lokesh
/* Select 384Mhz for GPU as its the POR for ES1.0 */
setbits_le32(prcm-cm_sgx_sgx_clkctrl,
@@ -429,6 +435,12 @@ void enable_basic_clocks(void)
setbits_le32(prcm-cm_coreaon_bandgap_clkctrl,
((OMAP_TS_CLK_ENABLE_MASK | OMAP_19M_TS_CLK_DIVIDER_MASK)
~OMAP_38M_TS_CLK_DIVIDER_MASK));
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+
}
void enable_basic_uboot_clocks(void)
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h
b/arch/arm/include/asm/arch-omap5/clocks.h
index c944f35..43fc5b8 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -613,6 +613,12 @@ struct omap5_prcm_regs {
/* CM_L3INIT_USBPHY_CLKCTRL */
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK8
+/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define USB_HOST_HS_CLKCTRL_MASK 0xFFC0
+
+/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define USB_TLL_HS_CLKCTRL_MASK 0x700
+
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK(1 24)
diff --git a/arch/arm/include/asm/arch-omap5/ehci.h
b/arch/arm/include/asm/arch-omap5/ehci.h
new file mode 100644
index 000..49197f2
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/ehci.h
@@ -0,0 +1,44 @@
+/*
+ * OMAP EHCI port support
+ * Based on LINUX KERNEL
+ * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com*
+ * Author: Govindraj R govindraj.r...@ti.com
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see http://www.gnu.org/licenses/.
+ */
+
+#ifndef _EHCI_H
+#define _EHCI_H
+
+#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE
+ 0x64C00)
+#define OMAP_UHH_BASE
Re: [U-Boot] [PATCH 2/3] usb: omap5-evm: Add ethernet support to the uevm
Hi Dan, On Tuesday 09 July 2013 02:29 AM, Dan Murphy wrote: Add code to configure the USB EHCI host controller. This enumerates an ethernet controller through USB3 using the HSIC lines. Signed-off-by: Dan Murphy dmur...@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 15 +++ arch/arm/include/asm/arch-omap5/clock.h |6 + arch/arm/include/asm/arch-omap5/ehci.h | 44 +++ arch/arm/include/asm/ehci-omap.h|1 + board/ti/omap5_uevm/evm.c | 35 board/ti/omap5_uevm/mux_data.h |4 ++- drivers/usb/host/ehci-omap.c|2 +- include/configs/omap5_common.h |2 -- include/configs/omap5_uevm.h| 23 9 files changed, 128 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap5/ehci.h I see a other patch from you which adds the same file. Is the previous patch sent by mistake? diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 56cf1f8..f3973ee 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -412,6 +412,8 @@ void enable_basic_clocks(void) (*prcm)-cm_l4per_gpio4_clkctrl, (*prcm)-cm_l4per_gpio5_clkctrl, (*prcm)-cm_l4per_gpio6_clkctrl, + (*prcm)-cm_clksel_usb_60mhz, + (*prcm)-cm_l3init_hsusbtll_clkctrl, 0 }; @@ -423,6 +425,7 @@ void enable_basic_clocks(void) (*prcm)-cm_wkup_wdtimer2_clkctrl, (*prcm)-cm_l4per_uart3_clkctrl, (*prcm)-cm_l4per_i2c1_clkctrl, + (*prcm)-cm_l3init_hsusbhost_clkctrl, 0 }; @@ -446,6 +449,14 @@ void enable_basic_clocks(void) setbits_le32((*prcm)-cm_wkup_gptimer1_clkctrl, GPTIMER1_CLKCTRL_CLKSEL_MASK); + /* Enbale all 3 usb ports enable uhh, utmi and hsic clocks*/ + setbits_le32((*prcm)-cm_l3init_hsusbhost_clkctrl, + USB_HOST_HS_CLKCTRL_MASK); + + /* Enbale all 3 usb host ports tll clocks*/ + setbits_le32((*prcm)-cm_l3init_hsusbtll_clkctrl, + USB_TLL_HS_CLKCTRL_MASK); Please keep this under a macro. + do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, @@ -480,6 +491,10 @@ void enable_basic_uboot_clocks(void) 0 }; + /* Enbale all 3 usb host ports tll clocks*/ + setbits_le32((*prcm)-cm_l3init_hsusbtll_clkctrl, + USB_TLL_HS_CLKCTRL_MASK); + do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 4d2765d..f98fe74 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -165,6 +165,12 @@ /* CM_L3INIT_USBPHY_CLKCTRL */ #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK8 +/* CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define USB_HOST_HS_CLKCTRL_MASK 0x7FC0 + +/* CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define USB_TLL_HS_CLKCTRL_MASK 0x700 + /* CM_MPU_MPU_CLKCTRL */ #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK(3 24) diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h new file mode 100644 index 000..49197f2 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/ehci.h @@ -0,0 +1,44 @@ +/* + * OMAP EHCI port support + * Based on LINUX KERNEL + * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com* 2013...:) Thanks Lokesh + * Author: Govindraj R govindraj.r...@ti.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 of + * the License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#ifndef _EHCI_H +#define _EHCI_H + +#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00) +#define OMAP_UHH_BASE(OMAP54XX_L4_CORE_BASE + 0x64000) +#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE
Re: [U-Boot] [PATCH 1/7] omap5: add qspi support
On Wednesday 10 July 2013 04:55 PM, Sourav Poddar wrote:
From: Matt Porter mpor...@ti.com
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter mpor...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |7 ++-
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch/arm/include/asm/arch-omap5/spl.h |1 +
arch/arm/include/asm/omap_common.h |1 +
5 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 9374c6a..046ce44 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -186,7 +186,7 @@ static const struct dpll_params
per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS]
= {
{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
- {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},/* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
@@ -423,6 +423,7 @@ void enable_basic_clocks(void)
(*prcm)-cm_wkup_wdtimer2_clkctrl,
(*prcm)-cm_l4per_uart3_clkctrl,
(*prcm)-cm_l4per_i2c1_clkctrl,
+ (*prcm)-cm_l4per_qspi_clkctrl,
Keep this also under CONFIG_TI_QSPI because we should enable QSPI clocks
only if support is available.
Thanks,
Lokesh
0
};
@@ -451,6 +452,10 @@ void enable_basic_clocks(void)
clk_modules_explicit_en_essential,
1);
+#ifdef CONFIG_TI_QSPI
+ setbits_le32((*prcm)-cm_l4per_qspi_clkctrl, (124));
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)-cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 331117c..debc56b 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -926,6 +926,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl= 0x4a009820,
.cm_l4per_mmcsd4_clkctrl= 0x4a009828,
+ .cm_l4per_qspi_clkctrl = 0x4a009838,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index e7d79fc..d2c4930 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -67,6 +67,9 @@
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x5000
+/* QSPI */
+#define QSPI_BASE0x4B30
+
/*
* Hardware Register Details
*/
diff --git a/arch/arm/include/asm/arch-omap5/spl.h
b/arch/arm/include/asm/arch-omap5/spl.h
index d4d353c..8905cb8 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -31,6 +31,7 @@
#define BOOT_DEVICE_MMC15
#define BOOT_DEVICE_MMC26
#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SPI 10
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index fa28358..c8d4619 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -279,6 +279,7 @@ struct prcm_regs {
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
___
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Re: [U-Boot] [PATCH 3/7] dra7xx_evm: add SPL API, QSPI, and serial flash support
On Wednesday 10 July 2013 04:55 PM, Sourav Poddar wrote:
From: Matt Porter mpor...@ti.com
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter mpor...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
board/ti/dra7xx/mux_data.h | 10 ++
include/configs/dra7xx_evm.h | 22 ++
2 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 338a241..2441c55 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -53,5 +53,15 @@ const struct pad_conf_entry core_padconf_array_essential[]
= {
{UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
{I2C1_SDA, (IEN | PTU | PDIS | M0)},/* I2C1_SDA */
{I2C1_SCL, (IEN | PTU | PDIS | M0)},/* I2C1_SCL */
+ {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
+ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
+ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
+ {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
+ {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A18, (IEN | PDIS | M1)}, /* QSPI1_SCLK */
+ {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
+ {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
+ {GPMC_CS2, (IEN | PTU | PDIS | M1)},/* QSPI1_CS0 */
+ {GPMC_CS3, (IEN | PTU | PDIS | M1)},/* QSPI1_CS1*/
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 6b37e1d..0583858 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -46,4 +46,26 @@
#define NON_SECURE_SRAM_END 0x4038 /* Not inclusive */
#define CONFIG_SYS_OMAP_ABE_SYSCK
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
Is it necessary to Disable caches to use QSPI?
If not please drop these two defines.
+
+#define EMIF1_EMIF2
This one too..
Thanks,
Lokesh
+
+/* SPI */
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SF_DEFAULT_SPEED 1200
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2
+
#endif /* __CONFIG_DRA7XX_EVM_H */
___
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Re: [U-Boot] [[PATCH v2 3/6] ARM: OMAP5: USB: Add OMAP5 common USB EHCI information
On Thursday 11 July 2013 01:35 AM, Dan Murphy wrote: * Enable the OMAP5 EHCI host clocks * Add OMAP5 EHCI register definitions * Add OMAP5 ES2 host revision Signed-off-by: Dan Murphy dmur...@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 13 ++ arch/arm/include/asm/arch-omap5/clock.h |6 + arch/arm/include/asm/arch-omap5/ehci.h | 43 +++ arch/arm/include/asm/ehci-omap.h|1 + drivers/usb/host/ehci-omap.c|2 +- 5 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-omap5/ehci.h diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 56cf1f8..055f058 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -412,6 +412,8 @@ void enable_basic_clocks(void) (*prcm)-cm_l4per_gpio4_clkctrl, (*prcm)-cm_l4per_gpio5_clkctrl, (*prcm)-cm_l4per_gpio6_clkctrl, + (*prcm)-cm_clksel_usb_60mhz, + (*prcm)-cm_l3init_hsusbtll_clkctrl, guard this with CONFIG_USB_EHCI please or it ll throw an error for DRA7xx boards. 0 }; @@ -423,6 +425,7 @@ void enable_basic_clocks(void) (*prcm)-cm_wkup_wdtimer2_clkctrl, (*prcm)-cm_l4per_uart3_clkctrl, (*prcm)-cm_l4per_i2c1_clkctrl, + (*prcm)-cm_l3init_hsusbhost_clkctrl, same here... Thanks, Lokesh 0 }; @@ -446,6 +449,16 @@ void enable_basic_clocks(void) setbits_le32((*prcm)-cm_wkup_gptimer1_clkctrl, GPTIMER1_CLKCTRL_CLKSEL_MASK); +#ifdef CONFIG_USB_EHCI + /* Enable port 2 and 3 clocks*/ + setbits_le32((*prcm)-cm_l3init_hsusbhost_clkctrl, + USB_HOST_HS_CLKCTRL_MASK); + + /* Enable all 3 usb host ports tll clocks*/ + setbits_le32((*prcm)-cm_l3init_hsusbtll_clkctrl, + USB_TLL_HS_CLKCTRL_MASK); +#endif + do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 4d2765d..3a58337 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -165,6 +165,12 @@ /* CM_L3INIT_USBPHY_CLKCTRL */ #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK8 +/* CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define USB_HOST_HS_CLKCTRL_MASK 0x56C0 + +/* CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define USB_TLL_HS_CLKCTRL_MASK 0x700 + /* CM_MPU_MPU_CLKCTRL */ #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK(3 24) diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h new file mode 100644 index 000..3921e4a --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/ehci.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com* + * Author: Govindraj R govindraj.r...@ti.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _EHCI_H +#define _EHCI_H + +#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00) +#define OMAP_UHH_BASE(OMAP54XX_L4_CORE_BASE + 0x64000) +#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000) + +/* TLL Register Set */ +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 1) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 8) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 + +#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE(1 2) +#define OMAP_UHH_SYSCONFIG_NOIDLE(1 2) +#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 4) + +#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ + OMAP_UHH_SYSCONFIG_NOSTDBY) + +#endif /* _EHCI_H
[U-Boot] [PATCH 4/6] ARM: OMAP: Add CONFIG_OMAP_COMMON
Adding a new CONFIG_OMAP_COMMON which is included by all boards that needs to build cpu/armv7/omap-common folder. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- Makefile|2 +- arch/arm/config.mk |2 +- arch/arm/cpu/armv7/omap-common/Makefile |2 +- include/configs/am335x_evm.h|1 + include/configs/am3517_crane.h |1 + include/configs/am3517_evm.h|1 + include/configs/cm_t35.h|1 + include/configs/devkit8000.h|1 + include/configs/dig297.h|1 + include/configs/igep0033.h |1 + include/configs/igep00x0.h |1 + include/configs/mcx.h |1 + include/configs/nokia_rx51.h|1 + include/configs/omap3_beagle.h |1 + include/configs/omap3_evm_common.h |1 + include/configs/omap3_logic.h |1 + include/configs/omap3_mvblx.h |1 + include/configs/omap3_overo.h |1 + include/configs/omap3_pandora.h |1 + include/configs/omap3_sdp3430.h |1 + include/configs/omap3_zoom1.h |1 + include/configs/omap3_zoom2.h |1 + include/configs/omap4_common.h |1 + include/configs/omap5_common.h |1 + include/configs/pcm051.h|1 + include/configs/tam3517-common.h|1 + include/configs/ti814x_evm.h|1 + include/configs/tricorder.h |1 + spl/Makefile|2 +- 29 files changed, 29 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index fdaddb9..32b6c17 100644 --- a/Makefile +++ b/Makefile @@ -337,7 +337,7 @@ LIBS-y += api/libapi.o LIBS-y += post/libpost.o LIBS-y += test/libtest.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_OMAP_COMMON),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif diff --git a/arch/arm/config.mk b/arch/arm/config.mk index e80e1ed..f0c15b4 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -24,7 +24,7 @@ CROSS_COMPILE ?= arm-linux- ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_OMAP_COMMON),) CONFIG_STANDALONE_LOAD_ADDR = 0x8030 else CONFIG_STANDALONE_LOAD_ADDR = 0xc10 diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index c4b9809..8c95253 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -37,7 +37,7 @@ COBJS += vc.o COBJS += abb.o endif -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifeq ($(CONFIG_OMAP34XX),) COBJS += boot-common.o SOBJS += lowlevel_init.o endif diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 9c3c2cd..8b2e38f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -18,6 +18,7 @@ #define CONFIG_AM33XX #define CONFIG_OMAP +#define CONFIG_OMAP_COMMON #include asm/arch/omap.h diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index bf9d63e..6abb190 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -31,6 +31,7 @@ #define CONFIG_OMAP1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ +#define CONFIG_OMAP_COMMON #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 17fe88d..df9d476 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -31,6 +31,7 @@ #define CONFIG_OMAP1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ +#define CONFIG_OMAP_COMMON #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index c6e357a..e442af7 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -39,6 +39,7 @@ #define CONFIG_OMAP34XX/* which is a 34XX */ #define CONFIG_OMAP_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ +#define CONFIG_OMAP_COMMON #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 3b74d7c..c6ce192 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -37,6 +37,7 @@ #define CONFIG_OMAP3_DEVKIT80001 /* working with DevKit8000 */ #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON /* * 1MB
[U-Boot] [PATCH 1/6] ARM: AM43xx: Add Board files
Add board specific information for AM43xx.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
board/ti/am43xx/Makefile | 46 ++
board/ti/am43xx/board.c | 55 ++
board/ti/am43xx/board.h | 25 +
board/ti/am43xx/mux.c| 35 +
4 files changed, 161 insertions(+)
create mode 100644 board/ti/am43xx/Makefile
create mode 100644 board/ti/am43xx/board.c
create mode 100644 board/ti/am43xx/board.h
create mode 100644 board/ti/am43xx/mux.c
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
new file mode 100644
index 000..b1301c8
--- /dev/null
+++ b/board/ti/am43xx/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed as is WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mux.o
+endif
+
+COBJS += board.o
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
new file mode 100644
index 000..f65347f
--- /dev/null
+++ b/board/ti/am43xx/board.c
@@ -0,0 +1,55 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM43XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include spl.h
+#include asm/arch/sys_proto.h
+#include asm/arch/mux.h
+#include board.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+}
+#endif
+
+int board_init(void)
+{
+ gd-bd-bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ return 0;
+}
+#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
new file mode 100644
index 000..f6b31d3
--- /dev/null
+++ b/board/ti/am43xx/board.h
@@ -0,0 +1,25 @@
+/*
+ * board.h
+ *
+ * TI AM437x boards information header
+ * Derived from AM335x board.
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
new file mode 100644
index 000..432ddb4
--- /dev/null
+++ b/board/ti/am43xx/mux.c
@@ -0,0 +1,35 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind
[U-Boot] [PATCH 2/6] ARM: AM43xx: Add header files
Adding the following data:
- Prcm structure
- Base addresses
- Pin mux structure.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-am33xx/cpu.h | 164 +++-
arch/arm/include/asm/arch-am33xx/hardware.h|8 +-
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |9 ++
.../{hardware_am33xx.h = hardware_am43xx.h} | 18 ++-
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |9 ++
arch/arm/include/asm/arch-am33xx/mux.h |2 +
arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 151 ++
arch/arm/include/asm/arch-am33xx/omap.h|9 +-
arch/arm/include/asm/arch-am33xx/spl.h |4 +-
9 files changed, 348 insertions(+), 26 deletions(-)
copy arch/arm/include/asm/arch-am33xx/{hardware_am33xx.h = hardware_am43xx.h}
(78%)
create mode 100644 arch/arm/include/asm/arch-am33xx/mux_am43xx.h
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 3d3a7c8..a216bc8 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -51,13 +51,6 @@
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
| BIT(3) | BIT(4))
-/* Reset control */
-#ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL(PRCM_BASE + 0x0F00)
-#elif defined(CONFIG_TI814X)
-#define PRM_RSTCTRL(PRCM_BASE + 0x00A0)
-#endif
-#define PRM_RSTST (PRM_RSTCTRL + 8)
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
@@ -116,6 +109,7 @@ struct gpmc {
/* Used for board specific gpmc initialization */
extern struct gpmc *gpmc_cfg;
+#ifndef CONFIG_AM43XX
/* Encapsulating core pll registers */
struct cm_wkuppll {
unsigned int wkclkstctrl; /* offset 0x00 */
@@ -219,6 +213,162 @@ struct cm_perpll {
unsigned int resv10[8];
unsigned int cpswclkstctrl; /* offset 0x144 */
};
+#else
+/* Encapsulating core pll registers */
+struct cm_wkuppll {
+ unsigned int resv0[136];
+ unsigned int wkl4wkclkctrl; /* offset 0x220 */
+ unsigned int resv1[55];
+ unsigned int wkclkstctrl; /* offset 0x300 */
+ unsigned int resv2[15];
+ unsigned int wkup_i2c0ctrl; /* offset 0x340 */
+ unsigned int resv3;
+ unsigned int wkup_uart0ctrl;/* offset 0x348 */
+ unsigned int resv4[5];
+ unsigned int wkctrlclkctrl; /* offset 0x360 */
+ unsigned int resv5;
+ unsigned int wkgpio0clkctrl;/* offset 0x368 */
+
+ unsigned int resv6[109];
+ unsigned int clkmoddpllcore;/* offset 0x520 */
+ unsigned int idlestdpllcore;/* offset 0x524 */
+ unsigned int resv61;
+ unsigned int clkseldpllcore;/* offset 0x52C */
+ unsigned int resv7[2];
+ unsigned int divm4dpllcore; /* offset 0x538 */
+ unsigned int divm5dpllcore; /* offset 0x53C */
+ unsigned int divm6dpllcore; /* offset 0x540 */
+
+ unsigned int resv8[7];
+ unsigned int clkmoddpllmpu; /* offset 0x560 */
+ unsigned int idlestdpllmpu; /* offset 0x564 */
+ unsigned int resv9;
+ unsigned int clkseldpllmpu; /* offset 0x56c */
+ unsigned int divm2dpllmpu; /* offset 0x570 */
+
+ unsigned int resv10[11];
+ unsigned int clkmoddpllddr; /* offset 0x5A0 */
+ unsigned int idlestdpllddr; /* offset 0x5A4 */
+ unsigned int resv11;
+ unsigned int clkseldpllddr; /* offset 0x5AC */
+ unsigned int divm2dpllddr; /* offset 0x5B0 */
+
+ unsigned int resv12[11];
+ unsigned int clkmoddpllper; /* offset 0x5E0 */
+ unsigned int idlestdpllper; /* offset 0x5E4 */
+ unsigned int resv13;
+ unsigned int clkseldpllper; /* offset 0x5EC */
+ unsigned int divm2dpllper; /* offset 0x5F0 */
+ unsigned int resv14[8];
+ unsigned int clkdcoldodpllper; /* offset 0x614 */
+
+ unsigned int resv15[2];
+ unsigned int clkmoddplldisp;/* offset 0x620 */
+ unsigned int resv16[2];
+ unsigned int clkseldplldisp;/* offset 0x62C */
+ unsigned int divm2dplldisp; /* offset 0x630 */
+};
+
+/*
+ * Encapsulating peripheral functional clocks
+ * pll registers
+ */
+struct cm_perpll {
+ unsigned int l3clkstctrl; /* offset 0x00 */
+ unsigned int resv0[7];
+ unsigned int l3clkctrl; /* Offset 0x20 */
+ unsigned int resv1[7];
+ unsigned int l3instrclkctrl;/* offset 0x40 */
+ unsigned int resv2[3];
+ unsigned int ocmcramclkctrl;/* offset 0x50 */
+ unsigned int resv3[9];
+ unsigned int tpccclkctrl; /* offset 0x78 */
+ unsigned int resv4;
+ unsigned int tptc0clkctrl; /* offset 0x80 */
+
+ unsigned int resv5[7];
+ unsigned int l4hsclkctrl
[U-Boot] [PATCH 0/6] ARM: AM43xx: Add Support for AM43xx Soc's
AM43xx is a low cost Cortex-A9 based application processor
targets higher performance applications and new specific end
equipments like Point of Sale requiring stringent security requirements.
This series add support for AM43xx Soc's.
Data for the following is not added:
- SDRAM
- DPLL Dividers and post dividers
- Pin mux data(only uart data added).
Once this data is available Ill add them.
Config file is kept minimal for now, ll add the corresponding configs when
they are validated.
This is based on top of u-boot mainline + my recent am33xx cleanup series:
http://u-boot.10912.n7.nabble.com/PATCH-0-4-ARM-AM33xx-Cleanup-clocks-and-hwinit-tt157703.html
Testing:
Tested on pre-silicon platform
verified ./MAKEALL --cpu=armv7
./MAKEALL -s omap/am33xx
Lokesh Vutla (6):
ARM: AM43xx: Add Board files
ARM: AM43xx: Add header files
ARM: AM43xx: clocks: Add dpll and clock data
ARM: OMAP: Add CONFIG_OMAP_COMMON
ARM: AM43xx: Add build support
ARM: AM43xx: Add config file
Makefile |2 +-
arch/arm/config.mk |2 +-
arch/arm/cpu/armv7/Makefile|2 +-
arch/arm/cpu/armv7/am33xx/Makefile |7 +-
arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 120 ++
arch/arm/cpu/armv7/omap-common/Makefile|2 +-
arch/arm/cpu/armv7/omap-common/boot-common.c |3 +-
arch/arm/include/asm/arch-am33xx/cpu.h | 164 +++-
arch/arm/include/asm/arch-am33xx/hardware.h|8 +-
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |9 ++
.../{hardware_am33xx.h = hardware_am43xx.h} | 18 ++-
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |9 ++
arch/arm/include/asm/arch-am33xx/mux.h |2 +
arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 151 ++
arch/arm/include/asm/arch-am33xx/omap.h|9 +-
arch/arm/include/asm/arch-am33xx/spl.h |4 +-
.../cpu/armv7/am33xx = board/ti/am43xx}/Makefile | 35 ++---
board/ti/am43xx/board.c| 55 +++
board/ti/am43xx/board.h| 25 +++
board/ti/am43xx/mux.c | 35 +
boards.cfg |1 +
drivers/serial/ns16550.c |5 +-
include/configs/am335x_evm.h |1 +
include/configs/am3517_crane.h |1 +
include/configs/am3517_evm.h |1 +
include/configs/am43xx_evm.h | 143 +
include/configs/cm_t35.h |1 +
include/configs/devkit8000.h |1 +
include/configs/dig297.h |1 +
include/configs/igep0033.h |1 +
include/configs/igep00x0.h |1 +
include/configs/mcx.h |1 +
include/configs/nokia_rx51.h |1 +
include/configs/omap3_beagle.h |1 +
include/configs/omap3_evm_common.h |1 +
include/configs/omap3_logic.h |1 +
include/configs/omap3_mvblx.h |1 +
include/configs/omap3_overo.h |1 +
include/configs/omap3_pandora.h|1 +
include/configs/omap3_sdp3430.h|1 +
include/configs/omap3_zoom1.h |1 +
include/configs/omap3_zoom2.h |1 +
include/configs/omap4_common.h |1 +
include/configs/omap5_common.h |1 +
include/configs/pcm051.h |1 +
include/configs/tam3517-common.h |1 +
include/configs/ti814x_evm.h |1 +
include/configs/tricorder.h|1 +
spl/Makefile |2 +-
49 files changed, 783 insertions(+), 55 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock_am43xx.c
copy arch/arm/include/asm/arch-am33xx/{hardware_am33xx.h = hardware_am43xx.h}
(78%)
create mode 100644 arch/arm/include/asm/arch-am33xx/mux_am43xx.h
copy {arch/arm/cpu/armv7/am33xx = board/ti/am43xx}/Makefile (55%)
create mode 100644 board/ti/am43xx/board.c
create mode 100644 board/ti/am43xx/board.h
create mode 100644 board/ti/am43xx/mux.c
create mode 100644 include/configs/am43xx_evm.h
--
1.7.9.5
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[U-Boot] [PATCH 3/6] ARM: AM43xx: clocks: Add dpll and clock data
Add dpll and clock data for AM43xx
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/Makefile |7 +-
arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 120 ++
2 files changed, 126 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock_am43xx.c
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile
b/arch/arm/cpu/armv7/am33xx/Makefile
index f4ccd2a..89d9104 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -18,7 +18,12 @@ LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
COBJS-$(CONFIG_TI814X) += clock_ti814x.o
-COBJS-$(CONFIG_AM33XX) += clock.o
+COBJS-$(CONFIG_AM43XX) += clock_am43xx.o
+
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
+COBJS += clock.o
+endif
+
COBJS += sys_info.o
COBJS += mem.o
COBJS += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
new file mode 100644
index 000..c9842b6
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -0,0 +1,120 @@
+/*
+ * clock_am43xx.c
+ *
+ * clocks for AM43XX based boards
+ * Derived from AM33XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/clock.h
+#include asm/arch/hardware.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+
+const struct dpll_regs dpll_mpu_regs = {
+ .cm_clkmode_dpll= CM_WKUP + 0x560,
+ .cm_idlest_dpll = CM_WKUP + 0x564,
+ .cm_clksel_dpll = CM_WKUP + 0x56c,
+ .cm_div_m2_dpll = CM_WKUP + 0x570,
+};
+
+const struct dpll_regs dpll_core_regs = {
+ .cm_clkmode_dpll= CM_WKUP + 0x520,
+ .cm_idlest_dpll = CM_WKUP + 0x524,
+ .cm_clksel_dpll = CM_WKUP + 0x52C,
+ .cm_div_m4_dpll = CM_WKUP + 0x538,
+ .cm_div_m5_dpll = CM_WKUP + 0x53C,
+ .cm_div_m6_dpll = CM_WKUP + 0x540,
+};
+
+const struct dpll_regs dpll_per_regs = {
+ .cm_clkmode_dpll= CM_WKUP + 0x5E0,
+ .cm_idlest_dpll = CM_WKUP + 0x5E4,
+ .cm_clksel_dpll = CM_WKUP + 0x5EC,
+ .cm_div_m2_dpll = CM_WKUP + 0x5F0,
+};
+
+const struct dpll_regs dpll_ddr_regs = {
+ .cm_clkmode_dpll= CM_WKUP + 0x5A0,
+ .cm_idlest_dpll = CM_WKUP + 0x5A4,
+ .cm_clksel_dpll = CM_WKUP + 0x5AC,
+ .cm_div_m2_dpll = CM_WKUP + 0x5B0,
+};
+
+const struct dpll_params dpll_mpu = {
+ -1, -1, -1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+ -1, -1, -1, -1, -1, -1, -1};
+const struct dpll_params dpll_per = {
+ -1, -1, -1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr = {
+ -1, -1, -1, -1, -1, -1, -1};
+
+void setup_clocks_for_console(void)
+{
+ /* Do not add any spl_debug prints in this function */
+ clrsetbits_le32(cmwkup-wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+ /* Enable UART0 */
+ clrsetbits_le32(cmwkup-wkup_uart0ctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+void enable_basic_clocks(void)
+{
+ u32 *const clk_domains[] = {
+ cmper-l3clkstctrl,
+ cmper-l3sclkstctrl,
+ cmper-l4lsclkstctrl,
+ cmwkup-wkclkstctrl,
+ cmper-emifclkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en[] = {
+ cmper-l3clkctrl,
+ cmper-l4lsclkctrl,
+ cmper-l4fwclkctrl,
+ cmwkup-wkl4wkclkctrl,
+ cmper-l3instrclkctrl,
+ cmper-l4hsclkctrl,
+ cmwkup-wkgpio0clkctrl,
+ cmwkup-wkctrlclkctrl,
+ cmper-timer2clkctrl,
+ cmper-gpmcclkctrl,
+ cmper-elmclkctrl,
+ cmper-mmc0clkctrl,
+ cmper-mmc1clkctrl,
+ cmwkup-wkup_i2c0ctrl,
+ cmper-gpio1clkctrl,
+ cmper-gpio2clkctrl,
+ cmper
[U-Boot] [PATCH 6/6] ARM: AM43xx: Add config file
Add config file
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
boards.cfg |1 +
include/configs/am43xx_evm.h | 143 ++
2 files changed, 144 insertions(+)
create mode 100644 include/configs/am43xx_evm.h
diff --git a/boards.cfg b/boards.cfg
index c0c4282..067df4d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -249,6 +249,7 @@ am335x_evm_uart3 arm armv7 am335x
ti
am335x_evm_uart4 arm armv7 am335x ti
am33xx am335x_evm:SERIAL5,CONS_INDEX=5
am335x_evm_uart5 arm armv7 am335x ti
am33xx am335x_evm:SERIAL6,CONS_INDEX=6
am335x_evm_usbsplarm armv7 am335x ti
am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
+am43xx_evm arm armv7 am43xx ti
am33xx am43xx_evm:SERIAL1,CONS_INDEX=1
ti814x_evm arm armv7 ti814x ti
am33xx
pcm051 arm armv7 pcm051
phytec am33xx pcm051
sama5d3xek_mmc arm armv7 sama5d3xek atmel
at91sama5d3xek:SAMA5D3,SYS_USE_MMC
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
new file mode 100644
index 000..602d3e7
--- /dev/null
+++ b/include/configs/am43xx_evm.h
@@ -0,0 +1,143 @@
+/*
+ * am43xx_evm.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_AM43XX_EVM_H
+#define __CONFIG_AM43XX_EVM_H
+
+#define CONFIG_AM43XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#include asm/arch/omap.h
+
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE (1 20)
+
+#define CONFIG_ENV_SIZE(128 10) /* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1024 10)
+#define CONFIG_SYS_LONGHELP/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use hush command parser */
+#define CONFIG_SYS_PROMPT U-Boot#
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* commands to include */
+#include config_cmd_default.h
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_VERSION_VARIABLE
+
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Clock Defines */
+#define V_OSCK 2400 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#define CONFIG_CMD_ECHO
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
+
+ /* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_DRAM_10x8000 /* DRAM Bank #1 */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 20)/* 1GB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
+ GENERATED_GBL_DATA_SIZE)
+/* Platform/Board specific defs */
+#define CONFIG_SYS_LOAD_ADDR 0x8100 /* Default load address */
+
+#define CONFIG_SYS_TIMERBASE 0x4804 /* Use Timer2 */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) = 8 */
+#define CONFIG_SYS_HZ 1000
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE(-4)
+#define CONFIG_SYS_NS16550_CLK (4800)
+#define CONFIG_SYS_NS16550_COM10x44e09000 /* Base EVM has
UART0 */
+
+#define CONFIG_BAUDRATE115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600
[U-Boot] [PATCH 5/6] ARM: AM43xx: Add build support
Add AM43xx support in the required places
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/Makefile |2 +-
arch/arm/cpu/armv7/omap-common/boot-common.c |3 ++-
drivers/serial/ns16550.c |5 +++--
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 7a8c2d0..17fa4e2 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
COBJS += cpu.o
COBJS += syslib.o
-ifneq
($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),)
+ifneq
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),)
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c
b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 76ae1b6..a6e4481 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -48,7 +48,8 @@ void save_omap_boot_params(void)
if ((boot_device = MMC_BOOT_DEVICES_START)
(boot_device = MMC_BOOT_DEVICES_END)) {
-#if !defined(CONFIG_AM33XX) !defined(CONFIG_TI81XX)
+#if !defined(CONFIG_AM33XX) !defined(CONFIG_TI81XX) \
+ !defined(CONFIG_AM43XX)
if ((omap_hw_init_context() ==
OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
gd-arch.omap_boot_params.omap_bootmode =
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index d77c25f..bc976ba 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -57,7 +57,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(CONFIG_SYS_NS16550_IER, com_port-ier);
#if (defined(CONFIG_OMAP) !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
+ defined(CONFIG_AM33XX) || defined(CONFIG_TI814X) || \
+ defined(CONFIG_AM43XX)
serial_out(0x7, com_port-mdr1); /* mode select reset TL16C750*/
#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, com_port-lcr);
@@ -72,7 +73,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(UART_LCRVAL, com_port-lcr);
#if (defined(CONFIG_OMAP) !defined(CONFIG_OMAP3_ZOOM2)) || \
defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
- defined(CONFIG_TI814X)
+ defined(CONFIG_TI814X) || defined(CONFIG_AM43XX)
/* /16 is proper to hit 115200 with 48MHz */
serial_out(0, com_port-mdr1);
--
1.7.9.5
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Re: [U-Boot] [PATCH] am335x:Handle worst case scenario for Errata 1.0.24
On Monday 22 July 2013 08:12 PM, Tom Rini wrote:
From: Steve Kipisz s-kipi...@ti.com
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.
Cc: Enric Balletbo i Serra eballe...@iseebcn.com
Cc: Lars Poeschel poesc...@lemonage.de
Signed-off-by: Steve Kipisz s-kipi...@ti.com
[trini: Adapt to current framework]
Signed-off-by: Tom Rini tr...@ti.com
Doesn't this patch gives a conflict with recent cleanup series
for Am33xx ?
http://patchwork.ozlabs.org/patch/253831/
Thanks,
Lokesh
---
arch/arm/cpu/armv7/am33xx/board.c|2 +
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 72
++
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |3 +
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
board/ti/am335x/board.c | 11
include/configs/pcm051.h |1 +
include/power/tps65217.h |1 +
7 files changed, 67 insertions(+), 24 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 9356501..03427da 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -158,6 +158,8 @@ int arch_misc_init(void)
*/
__weak void am33xx_spl_board_init(void)
{
+ mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+ core_pll_config(OPP_100);
}
void rtc32k_enable(void)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index 9c4d0b4..ef06814 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -50,12 +50,17 @@
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M1000
+#define COREPLL_M_OPP50 50
#define COREPLL_N(OSC-1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
+#define COREPLL_M4_OPP50 1
+#define COREPLL_M5_OPP50 1
+#define COREPLL_M6_OPP50 1
+
/*
* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
* frequency needs to be set to 960 MHZ. Hence,
@@ -274,12 +279,7 @@ void mpu_pll_config_val(int mpull_m)
;
}
-static void mpu_pll_config(void)
-{
- mpu_pll_config_val(CONFIG_SYS_MPUCLK);
-}
-
-static void core_pll_config(void)
+void core_pll_config(int opp)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;
@@ -293,29 +293,53 @@ static void core_pll_config(void)
writel(PLL_BYPASS_MODE, cmwkup-clkmoddpllcore);
while (readl(cmwkup-idlestdpllcore) != ST_MN_BYPASS)
- ;
+ ;
+ if (opp == OPP_50) {
+ clksel = clksel (~CLK_SEL_MASK);
+ clksel = clksel | ((COREPLL_M_OPP50 CLK_SEL_SHIFT)
+ | COREPLL_N);
+ writel(clksel, cmwkup-clkseldpllcore);
- clksel = clksel (~CLK_SEL_MASK);
- clksel = clksel | ((COREPLL_M CLK_SEL_SHIFT) | COREPLL_N);
- writel(clksel, cmwkup-clkseldpllcore);
+ div_m4 = div_m4 ~CLK_DIV_MASK;
+ div_m4 = div_m4 | COREPLL_M4_OPP50;
+ writel(div_m4, cmwkup-divm4dpllcore);
- div_m4 = div_m4 ~CLK_DIV_MASK;
- div_m4 = div_m4 | COREPLL_M4;
- writel(div_m4, cmwkup-divm4dpllcore);
+ div_m5 = div_m5 ~CLK_DIV_MASK;
+ div_m5 = div_m5 | COREPLL_M5_OPP50;
+ writel(div_m5, cmwkup-divm5dpllcore);
- div_m5 = div_m5 ~CLK_DIV_MASK;
- div_m5 = div_m5 | COREPLL_M5;
- writel(div_m5, cmwkup-divm5dpllcore);
+ div_m6 = div_m6 ~CLK_DIV_MASK;
+ div_m6 = div_m6 | COREPLL_M6_OPP50;
+ writel(div_m6, cmwkup-divm6dpllcore);
- div_m6 = div_m6 ~CLK_DIV_MASK;
- div_m6 = div_m6 | COREPLL_M6;
- writel(div_m6, cmwkup-divm6dpllcore);
+ clkmode = clkmode | CLK_MODE_SEL;
+ writel(clkmode, cmwkup-clkmoddpllcore);
- clkmode = clkmode | CLK_MODE_SEL;
- writel(clkmode, cmwkup-clkmoddpllcore);
+ while (readl(cmwkup-idlestdpllcore) != ST_DPLL_CLK)
+ ;
+ } else {
+ clksel = clksel (~CLK_SEL_MASK);
+ clksel = clksel | ((COREPLL_M CLK_SEL_SHIFT) | COREPLL_N);
+ writel(clksel, cmwkup-clkseldpllcore);
+
+ div_m4 = div_m4 ~CLK_DIV_MASK;
+ div_m4 = div_m4 | COREPLL_M4;
+ writel(div_m4, cmwkup-divm4dpllcore);
+
+ div_m5 = div_m5 ~CLK_DIV_MASK;
+ div_m5 = div_m5 | COREPLL_M5;
+ writel(div_m5, cmwkup-divm5dpllcore);
+
+ div_m6 = div_m6 ~CLK_DIV_MASK;
+ div_m6 =
[U-Boot] [PATCH V2 1/4] ARM: AM33xx: Cleanup dplls data
Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/Makefile |1 +
arch/arm/cpu/armv7/am33xx/clock.c| 111 +
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 220 +-
arch/arm/cpu/armv7/am33xx/emif4.c|4 +
arch/arm/include/asm/arch-am33xx/clock.h | 70
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 +
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
board/isee/igep0033/board.c | 10 ++
board/phytec/pcm051/board.c |9 ++
board/ti/am335x/board.c | 27
10 files changed, 273 insertions(+), 182 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile
b/arch/arm/cpu/armv7/am33xx/Makefile
index dbd1ec3..7fd21af 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -10,6 +10,7 @@ LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
COBJS-$(CONFIG_TI814X) += clock_ti814x.o
+COBJS-$(CONFIG_AM33XX) += clock.o
COBJS += sys_info.o
COBJS += mem.o
COBJS += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 000..15f4a2c
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,111 @@
+/*
+ * clock.c
+ *
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/clock.h
+#include asm/arch/hardware.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+const struct dpll_params *params)
+{
+ /* Setup post-dividers */
+ if (params-m2 = 0)
+ writel(params-m2, dpll_regs-cm_div_m2_dpll);
+ if (params-m3 = 0)
+ writel(params-m3, dpll_regs-cm_div_m3_dpll);
+ if (params-m4 = 0)
+ writel(params-m4, dpll_regs-cm_div_m4_dpll);
+ if (params-m5 = 0)
+ writel(params-m5, dpll_regs-cm_div_m5_dpll);
+ if (params-m6 = 0)
+ writel(params-m6, dpll_regs-cm_div_m6_dpll);
+}
+
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
+{
+ clrsetbits_le32(dpll_regs-cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_LOCK CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
+{
+ if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+ (void *)dpll_regs-cm_idlest_dpll, LDELAY)) {
+ printf(DPLL locking failed for 0x%x\n,
+ dpll_regs-cm_clkmode_dpll);
+ hang();
+ }
+}
+
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+ clrsetbits_le32(dpll_regs-cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_MN_BYPASS CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
+{
+ if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+ (void *)dpll_regs-cm_idlest_dpll, LDELAY)) {
+ printf(Bypassing DPLL failed 0x%x\n,
+ dpll_regs-cm_clkmode_dpll);
+ }
+}
+
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+ do_bypass_dpll(dpll_regs);
+ wait_for_bypass(dpll_regs);
+}
+
+void do_setup_dpll(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
+{
+ u32 temp;
+
+ if (!params)
+ return;
+
+ temp = readl(dpll_regs-cm_clksel_dpll);
+
+ bypass_dpll(dpll_regs);
+
+ /* Set M N */
+ temp = ~CM_CLKSEL_DPLL_M_MASK;
+ temp |= (params-m CM_CLKSEL_DPLL_M_SHIFT) CM_CLKSEL_DPLL_M_MASK;
+
+ temp = ~CM_CLKSEL_DPLL_N_MASK;
+ temp |= (params-n CM_CLKSEL_DPLL_N_SHIFT) CM_CLKSEL_DPLL_N_MASK;
+
+ writel(temp, dpll_regs-cm_clksel_dpll);
+
+ setup_post_dividers(dpll_regs, params);
+
+ /* Wait till the DPLL locks */
+ do_lock_dpll(dpll_regs);
+ wait_for_lock(dpll_regs);
+}
+
+void setup_dplls(void)
+{
+ const struct dpll_params *params;
+ do_setup_dpll(dpll_core_regs, dpll_core);
+ do_setup_dpll(dpll_mpu_regs, dpll_mpu);
+ do_setup_dpll(dpll_per_regs, dpll_per);
+ writel(0x300, cmwkup-clkdcoldodpllper);
+
+ params = get_dpll_ddr_params();
+ do_setup_dpll(dpll_ddr_regs, params);
+}
diff --git
[U-Boot] [PATCH V2 0/4]ARM: AM33xx: Cleanup clocks and hwinit
This series tries to cleanup code for AM33xx, inorder to ensure code reusabilty by moving the duplicated code to common place. This also helps in addition of new Soc with minimal changes. Testing: Boot tested on BeagleBone White/Black, AM35xx EVM/EVMSK. Verified ./MAKEALL -s am33xx. Changes Since V1: - Rebased on top of u-boot-ti - Created a function get_dpll_ddr_params() for getting ddr dpll params from board files. - Updated License header for newly created files. Heiko Schocher (1): ARM: AM33xx: Move s_init to a common place Lokesh Vutla (3): ARM: AM33xx: Cleanup dplls data ARM: AM33xx: Cleanup clocks layer musb: Disable extra prints arch/arm/cpu/armv7/am33xx/Makefile |1 + arch/arm/cpu/armv7/am33xx/board.c| 68 ++- arch/arm/cpu/armv7/am33xx/clock.c| 171 arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 495 +- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 25 +- arch/arm/cpu/armv7/am33xx/emif4.c|5 +- arch/arm/include/asm/arch-am33xx/clock.h | 94 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |6 +- arch/arm/include/asm/arch-am33xx/sys_proto.h |9 +- board/isee/igep0033/board.c | 55 +-- board/phytec/pcm051/board.c | 57 +-- board/ti/am335x/board.c | 102 ++--- board/ti/am335x/mux.c| 19 + board/ti/ti814x/evm.c| 65 +-- drivers/usb/musb-new/musb_core.c | 20 +- 15 files changed, 573 insertions(+), 619 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 4/4] musb: Disable extra prints
There are many musb prints in SPL and U-Boot log.
These prints are required only during musb debug.
So replacing printk with pr_debug in musb_core.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/usb/musb-new/musb_core.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index da93571..36681b6 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -1311,9 +1311,7 @@ static int __devinit ep_config_from_table(struct musb
*musb)
break;
}
- printk(KERN_DEBUG %s: setup fifo_mode %d\n,
- musb_driver_name, fifo_mode);
-
+ pr_debug(%s: setup fifo_mode %d\n, musb_driver_name, fifo_mode);
done:
offset = fifo_setup(musb, hw_ep, ep0_cfg, 0);
@@ -1341,10 +1339,9 @@ done:
musb-nr_endpoints = max(epn, musb-nr_endpoints);
}
- printk(KERN_DEBUG %s: %d/%d max ep, %d/%d memory\n,
- musb_driver_name,
- n + 1, musb-config-num_eps * 2 - 1,
- offset, (1 (musb-config-ram_bits + 2)));
+ pr_debug(%s: %d/%d max ep, %d/%d memory\n, musb_driver_name, n + 1,
+musb-config-num_eps * 2 - 1, offset,
+(1 (musb-config-ram_bits + 2)));
if (!musb-bulk_ep) {
pr_debug(%s: missing bulk\n, musb_driver_name);
@@ -1447,8 +1444,7 @@ static int __devinit musb_core_init(u16 musb_type, struct
musb *musb)
if (reg MUSB_CONFIGDATA_SOFTCONE)
strcat(aInfo, , SoftConn);
- printk(KERN_DEBUG %s: ConfigData=0x%02x (%s)\n,
- musb_driver_name, reg, aInfo);
+ pr_debug(%s:ConfigData=0x%02x (%s)\n, musb_driver_name, reg, aInfo);
aDate[0] = 0;
if (MUSB_CONTROLLER_MHDRC == musb_type) {
@@ -1469,8 +1465,8 @@ static int __devinit musb_core_init(u16 musb_type, struct
musb *musb)
snprintf(aRevision, 32, %d.%d%s, MUSB_HWVERS_MAJOR(musb-hwvers),
MUSB_HWVERS_MINOR(musb-hwvers),
(musb-hwvers MUSB_HWVERS_RC) ? RC : );
- printk(KERN_DEBUG %s: %sHDRC RTL version %s %s\n,
- musb_driver_name, type, aRevision, aDate);
+ pr_debug(%s: %sHDRC RTL version %s %s\n, musb_driver_name, type,
+aRevision, aDate);
/* configure ep0 */
musb_configure_ep0(musb);
@@ -2122,7 +2118,7 @@ musb_init_controller(struct musb_hdrc_platform_data
*plat, struct device *dev,
pm_runtime_put(musb-controller);
- dev_info(dev, USB %s mode controller at %p using %s, IRQ %d\n,
+ pr_debug(USB %s mode controller at %p using %s, IRQ %d\n,
({char *s;
switch (musb-board_mode) {
case MUSB_HOST:s = Host; break;
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
From: Heiko Schocher h...@denx.de
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Heiko Schocher h...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c| 62 +++--
arch/arm/cpu/armv7/am33xx/clock_ti814x.c |6 ++
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |6 +-
arch/arm/include/asm/arch-am33xx/sys_proto.h |8 ++-
board/isee/igep0033/board.c | 50 +++---
board/phytec/pcm051/board.c | 48 +++--
board/ti/am335x/board.c | 80 --
board/ti/am335x/mux.c| 19 +
board/ti/ti814x/evm.c| 67 +++---
9 files changed, 128 insertions(+), 218 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 64a3af7..2ea3d69 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -137,7 +137,7 @@ int arch_misc_init(void)
}
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
-void rtc32k_enable(void)
+static void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
@@ -153,11 +153,7 @@ void rtc32k_enable(void)
writel((1 3) | (1 6), rtc-osc);
}
-#define UART_RESET (0x1 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 0x3)
-
-void uart_soft_reset(void)
+static void uart_soft_reset(void)
{
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
u32 regval;
@@ -174,4 +170,58 @@ void uart_soft_reset(void)
regval |= UART_SMART_IDLE_EN;
writel(regval, uart_base-uartsyscfg);
}
+
+static void watchdog_disable(void)
+{
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ writel(0x, wdtimer-wdtwspr);
+ while (readl(wdtimer-wdtwwps) != 0x0)
+ ;
+ writel(0x, wdtimer-wdtwspr);
+ while (readl(wdtimer-wdtwwps) != 0x0)
+ ;
+}
#endif
+
+void s_init(void)
+{
+ /*
+* The ROM will only have set up sufficient pinmux to allow for the
+* first 4KiB NOR to be read, we must finish doing what we know of
+* the NOR mux in this space in order to continue.
+*/
+#ifdef CONFIG_NOR_BOOT
+ enable_norboot_pin_mux();
+#endif
+ /*
+* Save the boot parameters passed from romcode.
+* We cannot delay the saving further than this,
+* to prevent overwrites.
+*/
+#ifdef CONFIG_SPL_BUILD
+ save_omap_boot_params();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+ watchdog_disable();
+ timer_init();
+ set_uart_mux_conf();
+ setup_clocks_for_console();
+ uart_soft_reset();
+#endif
+#ifdef CONFIG_NOR_BOOT
+ gd-baudrate = CONFIG_BAUDRATE;
+ serial_init();
+ gd-have_console = 1;
+#else
+ gd = gdata;
+ preloader_console_init();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+ prcm_init();
+ set_mux_conf_regs();
+ /* Enable RTC32K clock */
+ rtc32k_enable();
+ sdram_init();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 965e875..93c7f7b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -277,6 +277,12 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, cmalwon-ethernet1clkctrl);
while ((readl(cmalwon-ethernet1clkctrl) ENET_CLKCTRL_CMPL) != 0)
;
+
+ /* RTC clocks */
+ writel(PRCM_MOD_EN, cmalwon-rtcclkstctrl);
+ writel(PRCM_MOD_EN, cmalwon-rtcclkctrl);
+ while (readl(cmalwon-rtcclkctrl) != PRCM_MOD_EN)
+ ;
}
/*
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 80e1899..140379f 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -16,8 +16,10 @@
#define CONFIG_SYS_MPUCLK 550
#endif
-extern void pll_init(void);
-extern void enable_emif_clocks(void);
+#define UART_RESET (0x1 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 0x3)
+
extern void enable_dmm_clocks(void);
#endif /* endif _CLOCKS_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h
b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index dbcede0..c6070a3 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -35,7 +35,11 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct
gpmc_cs *cs, u32 base,
u32 size
[U-Boot] [PATCH V2 2/4] ARM: AM33xx: Cleanup clocks layer
Cleaning up the clocks layer.
This helps in addition of new Soc with minimal
changes.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c |6 -
arch/arm/cpu/armv7/am33xx/clock.c | 62 +-
arch/arm/cpu/armv7/am33xx/clock_am33xx.c| 275 ---
arch/arm/cpu/armv7/am33xx/clock_ti814x.c| 19 +-
arch/arm/cpu/armv7/am33xx/emif4.c |1 -
arch/arm/include/asm/arch-am33xx/clock.h| 28 ++-
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 -
board/isee/igep0033/board.c | 11 +-
board/ti/am335x/board.c | 13 +-
board/ti/ti814x/evm.c | 12 +-
10 files changed, 193 insertions(+), 236 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index f1623db..64a3af7 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -56,12 +56,6 @@ int cpu_mmc_init(bd_t *bis)
}
#endif
-void setup_clocks_for_console(void)
-{
- /* Not yet implemented */
- return;
-}
-
/* AM33XX has two MUSB controllers which can be host or gadget */
#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) \
(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
index 15f4a2c..8e5f3c6 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -98,7 +98,7 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
wait_for_lock(dpll_regs);
}
-void setup_dplls(void)
+static void setup_dplls(void)
{
const struct dpll_params *params;
do_setup_dpll(dpll_core_regs, dpll_core);
@@ -109,3 +109,63 @@ void setup_dplls(void)
params = get_dpll_ddr_params();
do_setup_dpll(dpll_ddr_regs, params);
}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+ u32 bound = LDELAY;
+
+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl MODULE_CLKCTRL_IDLEST_MASK)
+MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf(Clock enable failed for 0x%p idlest 0x%x\n,
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32
enable_mode,
+ u32 wait_for_enable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ enable_mode MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug(Enable clock module - %p\n, clkctrl_addr);
+ if (wait_for_enable)
+ wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ enable_mode CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug(Enable clock domain - %p\n, clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+ u32 i, max = 100;
+
+ /* Put the clock domains in SW_WKUP mode */
+ for (i = 0; (i max) clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ }
+
+ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+ for (i = 0; (i max) clk_modules_explicit_en[i]; i++) {
+ enable_clock_module(clk_modules_explicit_en[i],
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+ wait_for_enable);
+ };
+}
+
+void prcm_init()
+{
+ enable_basic_clocks();
+ setup_dplls();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index d5d47ad..e5f287b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -14,17 +14,12 @@
#include asm/arch/hardware.h
#include asm/io.h
-#define PRCM_MOD_EN0x2
-#define PRCM_FORCE_WAKEUP 0x2
-#define PRCM_FUNCTL0x0
-
-#define CPGMAC0_IDLE 0x3
#define OSC(V_OSCK/100)
-const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP
[U-Boot] [PATCH V2 5/6] ARM: AM43xx: Add build support
Add AM43xx support in the required places
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/Makefile |2 +-
arch/arm/cpu/armv7/omap-common/boot-common.c |3 ++-
drivers/serial/ns16550.c |5 +++--
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 2ba88d0..8f27507 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -16,7 +16,7 @@ COBJS += cache_v7.o
COBJS += cpu.o
COBJS += syslib.o
-ifneq
($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),)
+ifneq
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),)
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c
b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 6b9ce36..6b4772b 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -40,7 +40,8 @@ void save_omap_boot_params(void)
if ((boot_device = MMC_BOOT_DEVICES_START)
(boot_device = MMC_BOOT_DEVICES_END)) {
-#if !defined(CONFIG_AM33XX) !defined(CONFIG_TI81XX)
+#if !defined(CONFIG_AM33XX) !defined(CONFIG_TI81XX) \
+ !defined(CONFIG_AM43XX)
if ((omap_hw_init_context() ==
OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
gd-arch.omap_boot_params.omap_bootmode =
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index d77c25f..bc976ba 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -57,7 +57,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(CONFIG_SYS_NS16550_IER, com_port-ier);
#if (defined(CONFIG_OMAP) !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
+ defined(CONFIG_AM33XX) || defined(CONFIG_TI814X) || \
+ defined(CONFIG_AM43XX)
serial_out(0x7, com_port-mdr1); /* mode select reset TL16C750*/
#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, com_port-lcr);
@@ -72,7 +73,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(UART_LCRVAL, com_port-lcr);
#if (defined(CONFIG_OMAP) !defined(CONFIG_OMAP3_ZOOM2)) || \
defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
- defined(CONFIG_TI814X)
+ defined(CONFIG_TI814X) || defined(CONFIG_AM43XX)
/* /16 is proper to hit 115200 with 48MHz */
serial_out(0, com_port-mdr1);
--
1.7.9.5
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[U-Boot] [PATCH V2 0/6] ARM: AM43xx: Add Support for AM43xx Soc's
AM43xx is a low cost Cortex-A9 based application processor
targets higher performance applications and new specific end
equipments like Point of Sale requiring stringent security requirements.
This series add support for AM43xx Soc's.
Data for the following is not added:
- SDRAM
- DPLL Dividers and post dividers
- Pin mux data(only uart data added).
Once this data is available Ill add them.
Config file is kept minimal for now, ll add the corresponding configs when
they are validated.
This is on top of u-boot-ti + V2 of AM33xx cleanup series.
http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-AM33xx-Cleanup-clocks-and-hwinit-tt160272.html
Testing:
Tested on pre-silicon platform
verified ./MAKEALL --cpu=armv7
./MAKEALL -s am33xx
Changes Since V1:
- Rebased on top of u-boot-ti + V2 of AM33xx Cleanup
- Updated License header for new files.
Lokesh Vutla (6):
ARM: AM43xx: Add Board files
ARM: AM43xx: Add header files
ARM: AM43xx: clocks: Add dpll and clock data
ARM: OMAP: Add CONFIG_OMAP_COMMON
ARM: AM43xx: Add build support
ARM: AM43xx: Add config file
Makefile |2 +-
arch/arm/config.mk |2 +-
arch/arm/cpu/armv7/Makefile|2 +-
arch/arm/cpu/armv7/am33xx/Makefile |7 +-
arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 110 +
arch/arm/cpu/armv7/omap-common/Makefile|2 +-
arch/arm/cpu/armv7/omap-common/boot-common.c |3 +-
arch/arm/include/asm/arch-am33xx/cpu.h | 164 +++-
arch/arm/include/asm/arch-am33xx/hardware.h|8 +-
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |9 ++
.../{hardware_am33xx.h = hardware_am43xx.h} | 18 ++-
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |9 ++
arch/arm/include/asm/arch-am33xx/mux.h |2 +
arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 143 +
arch/arm/include/asm/arch-am33xx/omap.h|9 +-
arch/arm/include/asm/arch-am33xx/spl.h |4 +-
board/ti/am43xx/Makefile | 38 +
board/ti/am43xx/board.c| 57 +++
board/ti/am43xx/board.h| 17 ++
board/ti/am43xx/mux.c | 27
boards.cfg |1 +
drivers/serial/ns16550.c |5 +-
include/configs/am335x_evm.h |1 +
include/configs/am3517_crane.h |1 +
include/configs/am3517_evm.h |1 +
include/configs/am43xx_evm.h | 135
include/configs/cm_t35.h |1 +
include/configs/devkit8000.h |1 +
include/configs/dig297.h |1 +
include/configs/igep0033.h |1 +
include/configs/igep00x0.h |1 +
include/configs/mcx.h |1 +
include/configs/nokia_rx51.h |1 +
include/configs/omap3_beagle.h |1 +
include/configs/omap3_evm_common.h |1 +
include/configs/omap3_logic.h |1 +
include/configs/omap3_mvblx.h |1 +
include/configs/omap3_overo.h |1 +
include/configs/omap3_pandora.h|1 +
include/configs/omap3_sdp3430.h|1 +
include/configs/omap3_zoom1.h |1 +
include/configs/omap3_zoom2.h |1 +
include/configs/omap4_common.h |1 +
include/configs/omap5_common.h |1 +
include/configs/pcm051.h |1 +
include/configs/tam3517-common.h |1 +
include/configs/ti814x_evm.h |1 +
include/configs/tricorder.h|1 +
spl/Makefile |2 +-
49 files changed, 766 insertions(+), 35 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock_am43xx.c
copy arch/arm/include/asm/arch-am33xx/{hardware_am33xx.h = hardware_am43xx.h}
(69%)
create mode 100644 arch/arm/include/asm/arch-am33xx/mux_am43xx.h
create mode 100644 board/ti/am43xx/Makefile
create mode 100644 board/ti/am43xx/board.c
create mode 100644 board/ti/am43xx/board.h
create mode 100644 board/ti/am43xx/mux.c
create mode 100644 include/configs/am43xx_evm.h
--
1.7.9.5
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[U-Boot] [PATCH V2 2/6] ARM: AM43xx: Add header files
Adding the following data:
- Prcm structure
- Base addresses
- Pin mux structure.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-am33xx/cpu.h | 164 +++-
arch/arm/include/asm/arch-am33xx/hardware.h|8 +-
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |9 ++
.../{hardware_am33xx.h = hardware_am43xx.h} | 18 ++-
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |9 ++
arch/arm/include/asm/arch-am33xx/mux.h |2 +
arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 143 +
arch/arm/include/asm/arch-am33xx/omap.h|9 +-
arch/arm/include/asm/arch-am33xx/spl.h |4 +-
9 files changed, 340 insertions(+), 26 deletions(-)
copy arch/arm/include/asm/arch-am33xx/{hardware_am33xx.h = hardware_am43xx.h}
(69%)
create mode 100644 arch/arm/include/asm/arch-am33xx/mux_am43xx.h
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index bcb4c50..10b56e0 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -43,13 +43,6 @@
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
| BIT(3) | BIT(4))
-/* Reset control */
-#ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL(PRCM_BASE + 0x0F00)
-#elif defined(CONFIG_TI814X)
-#define PRM_RSTCTRL(PRCM_BASE + 0x00A0)
-#endif
-#define PRM_RSTST (PRM_RSTCTRL + 8)
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
@@ -108,6 +101,7 @@ struct gpmc {
/* Used for board specific gpmc initialization */
extern struct gpmc *gpmc_cfg;
+#ifndef CONFIG_AM43XX
/* Encapsulating core pll registers */
struct cm_wkuppll {
unsigned int wkclkstctrl; /* offset 0x00 */
@@ -211,6 +205,162 @@ struct cm_perpll {
unsigned int resv10[8];
unsigned int cpswclkstctrl; /* offset 0x144 */
};
+#else
+/* Encapsulating core pll registers */
+struct cm_wkuppll {
+ unsigned int resv0[136];
+ unsigned int wkl4wkclkctrl; /* offset 0x220 */
+ unsigned int resv1[55];
+ unsigned int wkclkstctrl; /* offset 0x300 */
+ unsigned int resv2[15];
+ unsigned int wkup_i2c0ctrl; /* offset 0x340 */
+ unsigned int resv3;
+ unsigned int wkup_uart0ctrl;/* offset 0x348 */
+ unsigned int resv4[5];
+ unsigned int wkctrlclkctrl; /* offset 0x360 */
+ unsigned int resv5;
+ unsigned int wkgpio0clkctrl;/* offset 0x368 */
+
+ unsigned int resv6[109];
+ unsigned int clkmoddpllcore;/* offset 0x520 */
+ unsigned int idlestdpllcore;/* offset 0x524 */
+ unsigned int resv61;
+ unsigned int clkseldpllcore;/* offset 0x52C */
+ unsigned int resv7[2];
+ unsigned int divm4dpllcore; /* offset 0x538 */
+ unsigned int divm5dpllcore; /* offset 0x53C */
+ unsigned int divm6dpllcore; /* offset 0x540 */
+
+ unsigned int resv8[7];
+ unsigned int clkmoddpllmpu; /* offset 0x560 */
+ unsigned int idlestdpllmpu; /* offset 0x564 */
+ unsigned int resv9;
+ unsigned int clkseldpllmpu; /* offset 0x56c */
+ unsigned int divm2dpllmpu; /* offset 0x570 */
+
+ unsigned int resv10[11];
+ unsigned int clkmoddpllddr; /* offset 0x5A0 */
+ unsigned int idlestdpllddr; /* offset 0x5A4 */
+ unsigned int resv11;
+ unsigned int clkseldpllddr; /* offset 0x5AC */
+ unsigned int divm2dpllddr; /* offset 0x5B0 */
+
+ unsigned int resv12[11];
+ unsigned int clkmoddpllper; /* offset 0x5E0 */
+ unsigned int idlestdpllper; /* offset 0x5E4 */
+ unsigned int resv13;
+ unsigned int clkseldpllper; /* offset 0x5EC */
+ unsigned int divm2dpllper; /* offset 0x5F0 */
+ unsigned int resv14[8];
+ unsigned int clkdcoldodpllper; /* offset 0x614 */
+
+ unsigned int resv15[2];
+ unsigned int clkmoddplldisp;/* offset 0x620 */
+ unsigned int resv16[2];
+ unsigned int clkseldplldisp;/* offset 0x62C */
+ unsigned int divm2dplldisp; /* offset 0x630 */
+};
+
+/*
+ * Encapsulating peripheral functional clocks
+ * pll registers
+ */
+struct cm_perpll {
+ unsigned int l3clkstctrl; /* offset 0x00 */
+ unsigned int resv0[7];
+ unsigned int l3clkctrl; /* Offset 0x20 */
+ unsigned int resv1[7];
+ unsigned int l3instrclkctrl;/* offset 0x40 */
+ unsigned int resv2[3];
+ unsigned int ocmcramclkctrl;/* offset 0x50 */
+ unsigned int resv3[9];
+ unsigned int tpccclkctrl; /* offset 0x78 */
+ unsigned int resv4;
+ unsigned int tptc0clkctrl; /* offset 0x80 */
+
+ unsigned int resv5[7];
+ unsigned int l4hsclkctrl
[U-Boot] [PATCH V2 4/6] ARM: OMAP: Add CONFIG_OMAP_COMMON
Adding a new CONFIG_OMAP_COMMON which is included by all boards that needs to build cpu/armv7/omap-common folder. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- Makefile|2 +- arch/arm/config.mk |2 +- arch/arm/cpu/armv7/omap-common/Makefile |2 +- include/configs/am335x_evm.h|1 + include/configs/am3517_crane.h |1 + include/configs/am3517_evm.h|1 + include/configs/cm_t35.h|1 + include/configs/devkit8000.h|1 + include/configs/dig297.h|1 + include/configs/igep0033.h |1 + include/configs/igep00x0.h |1 + include/configs/mcx.h |1 + include/configs/nokia_rx51.h|1 + include/configs/omap3_beagle.h |1 + include/configs/omap3_evm_common.h |1 + include/configs/omap3_logic.h |1 + include/configs/omap3_mvblx.h |1 + include/configs/omap3_overo.h |1 + include/configs/omap3_pandora.h |1 + include/configs/omap3_sdp3430.h |1 + include/configs/omap3_zoom1.h |1 + include/configs/omap3_zoom2.h |1 + include/configs/omap4_common.h |1 + include/configs/omap5_common.h |1 + include/configs/pcm051.h|1 + include/configs/tam3517-common.h|1 + include/configs/ti814x_evm.h|1 + include/configs/tricorder.h |1 + spl/Makefile|2 +- 29 files changed, 29 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 7206aba..5461a21 100644 --- a/Makefile +++ b/Makefile @@ -322,7 +322,7 @@ LIBS-y += api/libapi.o LIBS-y += post/libpost.o LIBS-y += test/libtest.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_OMAP_COMMON),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 540a119..ce3903b 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -8,7 +8,7 @@ CROSS_COMPILE ?= arm-linux- ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_OMAP_COMMON),) CONFIG_STANDALONE_LOAD_ADDR = 0x8030 else CONFIG_STANDALONE_LOAD_ADDR = 0xc10 diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 98f29d4..75b3753 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -21,7 +21,7 @@ COBJS += vc.o COBJS += abb.o endif -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifeq ($(CONFIG_OMAP34XX),) COBJS += boot-common.o SOBJS += lowlevel_init.o endif diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index e32066d..dcc3d68 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -18,6 +18,7 @@ #define CONFIG_AM33XX #define CONFIG_OMAP +#define CONFIG_OMAP_COMMON #include asm/arch/omap.h diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 9bf283a..1fd2508 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -19,6 +19,7 @@ #define CONFIG_OMAP1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ +#define CONFIG_OMAP_COMMON #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 5c61697..6500878 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -19,6 +19,7 @@ #define CONFIG_OMAP1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ +#define CONFIG_OMAP_COMMON #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 39a216e..bc5b66c 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -24,6 +24,7 @@ #define CONFIG_OMAP34XX/* which is a 34XX */ #define CONFIG_OMAP_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ +#define CONFIG_OMAP_COMMON #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 513121a..cb79b4e 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -21,6 +21,7 @@ #define CONFIG_OMAP3_DEVKIT80001 /* working with DevKit8000 */ #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON /* * 1MB
[U-Boot] [PATCH V2 3/6] ARM: AM43xx: clocks: Add dpll and clock data
Add dpll and clock data for AM43xx
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/Makefile |7 +-
arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 110 ++
board/ti/am43xx/board.c |3 +-
3 files changed, 118 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock_am43xx.c
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile
b/arch/arm/cpu/armv7/am33xx/Makefile
index 7fd21af..bd8e752 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -10,7 +10,12 @@ LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
COBJS-$(CONFIG_TI814X) += clock_ti814x.o
-COBJS-$(CONFIG_AM33XX) += clock.o
+COBJS-$(CONFIG_AM43XX) += clock_am43xx.o
+
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
+COBJS += clock.o
+endif
+
COBJS += sys_info.o
COBJS += mem.o
COBJS += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
new file mode 100644
index 000..c4890f2
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -0,0 +1,110 @@
+/*
+ * clock_am43xx.c
+ *
+ * clocks for AM43XX based boards
+ * Derived from AM33XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/clock.h
+#include asm/arch/hardware.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+
+const struct dpll_regs dpll_mpu_regs = {
+ .cm_clkmode_dpll= CM_WKUP + 0x560,
+ .cm_idlest_dpll = CM_WKUP + 0x564,
+ .cm_clksel_dpll = CM_WKUP + 0x56c,
+ .cm_div_m2_dpll = CM_WKUP + 0x570,
+};
+
+const struct dpll_regs dpll_core_regs = {
+ .cm_clkmode_dpll= CM_WKUP + 0x520,
+ .cm_idlest_dpll = CM_WKUP + 0x524,
+ .cm_clksel_dpll = CM_WKUP + 0x52C,
+ .cm_div_m4_dpll = CM_WKUP + 0x538,
+ .cm_div_m5_dpll = CM_WKUP + 0x53C,
+ .cm_div_m6_dpll = CM_WKUP + 0x540,
+};
+
+const struct dpll_regs dpll_per_regs = {
+ .cm_clkmode_dpll= CM_WKUP + 0x5E0,
+ .cm_idlest_dpll = CM_WKUP + 0x5E4,
+ .cm_clksel_dpll = CM_WKUP + 0x5EC,
+ .cm_div_m2_dpll = CM_WKUP + 0x5F0,
+};
+
+const struct dpll_regs dpll_ddr_regs = {
+ .cm_clkmode_dpll= CM_WKUP + 0x5A0,
+ .cm_idlest_dpll = CM_WKUP + 0x5A4,
+ .cm_clksel_dpll = CM_WKUP + 0x5AC,
+ .cm_div_m2_dpll = CM_WKUP + 0x5B0,
+};
+
+const struct dpll_params dpll_mpu = {
+ -1, -1, -1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+ -1, -1, -1, -1, -1, -1, -1};
+const struct dpll_params dpll_per = {
+ -1, -1, -1, -1, -1, -1, -1};
+
+void setup_clocks_for_console(void)
+{
+ /* Do not add any spl_debug prints in this function */
+ clrsetbits_le32(cmwkup-wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+ /* Enable UART0 */
+ clrsetbits_le32(cmwkup-wkup_uart0ctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+void enable_basic_clocks(void)
+{
+ u32 *const clk_domains[] = {
+ cmper-l3clkstctrl,
+ cmper-l3sclkstctrl,
+ cmper-l4lsclkstctrl,
+ cmwkup-wkclkstctrl,
+ cmper-emifclkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en[] = {
+ cmper-l3clkctrl,
+ cmper-l4lsclkctrl,
+ cmper-l4fwclkctrl,
+ cmwkup-wkl4wkclkctrl,
+ cmper-l3instrclkctrl,
+ cmper-l4hsclkctrl,
+ cmwkup-wkgpio0clkctrl,
+ cmwkup-wkctrlclkctrl,
+ cmper-timer2clkctrl,
+ cmper-gpmcclkctrl,
+ cmper-elmclkctrl,
+ cmper-mmc0clkctrl,
+ cmper-mmc1clkctrl,
+ cmwkup-wkup_i2c0ctrl,
+ cmper-gpio1clkctrl,
+ cmper-gpio2clkctrl,
+ cmper-gpio3clkctrl,
+ cmper-i2c1clkctrl,
+ cmper-emiffwclkctrl,
+ cmper-emifclkctrl,
+ cmper-otfaemifclkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+}
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index f5b9100..51b2576 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -10,6 +10,7 @@
#include common.h
#include spl.h
+#include asm/arch/clock.h
#include
[U-Boot] [PATCH V2 1/6] ARM: AM43xx: Add Board files
Add board specific information for AM43xx.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
board/ti/am43xx/Makefile | 38 +++
board/ti/am43xx/board.c | 56 ++
board/ti/am43xx/board.h | 17 ++
board/ti/am43xx/mux.c| 27 ++
4 files changed, 138 insertions(+)
create mode 100644 board/ti/am43xx/Makefile
create mode 100644 board/ti/am43xx/board.c
create mode 100644 board/ti/am43xx/board.h
create mode 100644 board/ti/am43xx/mux.c
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
new file mode 100644
index 000..4a1bb7c
--- /dev/null
+++ b/board/ti/am43xx/Makefile
@@ -0,0 +1,38 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mux.o
+endif
+
+COBJS += board.o
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
new file mode 100644
index 000..f5b9100
--- /dev/null
+++ b/board/ti/am43xx/board.c
@@ -0,0 +1,56 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM43XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include spl.h
+#include asm/arch/sys_proto.h
+#include asm/arch/mux.h
+#include board.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+
+const struct dpll_params dpll_ddr = {
+ 266, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+}
+#endif
+
+int board_init(void)
+{
+ gd-bd-bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ return 0;
+}
+#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
new file mode 100644
index 000..8ca098b
--- /dev/null
+++ b/board/ti/am43xx/board.h
@@ -0,0 +1,17 @@
+/*
+ * board.h
+ *
+ * TI AM437x boards information header
+ * Derived from AM335x board.
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
new file mode 100644
index 000..700e9a7
--- /dev/null
+++ b/board/ti/am43xx/mux.c
@@ -0,0 +1,27 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/sys_proto.h
+#include asm/arch/mux.h
+#include board.h
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+}
--
1.7.9.5
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[U-Boot] [PATCH V2 6/6] ARM: AM43xx: Add config file
Add config file
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
boards.cfg |1 +
include/configs/am43xx_evm.h | 135 ++
2 files changed, 136 insertions(+)
create mode 100644 include/configs/am43xx_evm.h
diff --git a/boards.cfg b/boards.cfg
index 211ed58..8d86a1b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -252,6 +252,7 @@ am335x_evm_uart4 arm armv7 am335x
ti
am335x_evm_uart5 arm armv7 am335x ti
am33xx am335x_evm:SERIAL6,CONS_INDEX=1,NAND
am335x_evm_usbsplarm armv7 am335x ti
am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT
am335x_boneblack arm armv7 am335x ti
am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT
+am43xx_evm arm armv7 am43xx ti
am33xx am43xx_evm:SERIAL1,CONS_INDEX=1
ti814x_evm arm armv7 ti814x ti
am33xx
pcm051 arm armv7 pcm051
phytec am33xx pcm051
sama5d3xek_mmc arm armv7 sama5d3xek atmel
at91sama5d3xek:SAMA5D3,SYS_USE_MMC
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
new file mode 100644
index 000..5c802a1
--- /dev/null
+++ b/include/configs/am43xx_evm.h
@@ -0,0 +1,135 @@
+/*
+ * am43xx_evm.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_AM43XX_EVM_H
+#define __CONFIG_AM43XX_EVM_H
+
+#define CONFIG_AM43XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#include asm/arch/omap.h
+
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE (1 20)
+
+#define CONFIG_ENV_SIZE(128 10) /* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1024 10)
+#define CONFIG_SYS_LONGHELP/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use hush command parser */
+#define CONFIG_SYS_PROMPT U-Boot#
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* commands to include */
+#include config_cmd_default.h
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_VERSION_VARIABLE
+
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Clock Defines */
+#define V_OSCK 2400 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#define CONFIG_CMD_ECHO
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
+
+ /* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_DRAM_10x8000 /* DRAM Bank #1 */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 20)/* 1GB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
+ GENERATED_GBL_DATA_SIZE)
+/* Platform/Board specific defs */
+#define CONFIG_SYS_LOAD_ADDR 0x8100 /* Default load address */
+
+#define CONFIG_SYS_TIMERBASE 0x4804 /* Use Timer2 */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) = 8 */
+#define CONFIG_SYS_HZ 1000
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE(-4)
+#define CONFIG_SYS_NS16550_CLK (4800)
+#define CONFIG_SYS_NS16550_COM10x44e09000 /* Base EVM has
UART0 */
+
+#define CONFIG_BAUDRATE115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
+4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x8010 should not be used for any
Re: [U-Boot] [PATCH 3/4] ARM: OMAP4470: Add Elpida EDB8164B3PF memory configuration
Hi Taras,
On Tuesday 06 August 2013 05:48 PM, Taras Kondratiuk wrote:
From: Lubomir Popov lpo...@mm-sol.com
OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board.
This memory has 4Gb x 2CS = 8Gb configuration.
Add configuration for runtime calculation and precalculated cases.
Patch is based on a draft Lubomir's patch [1].
[1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html
Just curious to know, Have you tried SDRAM_AUTO_DETECTION ?
Rest looks fine to me.
Thanks and regards,
Lokesh
Signed-off-by: Lubomir Popov lpo...@mm-sol.com
[ta...@ti.com: cleaned up patch and fixed precalculated values]
Signed-off-by: Taras Kondratiuk ta...@ti.com
@@ -138,6 +138,9 @@ void init_omap_revision(void)
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4470_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP4470_ES1_0;
+ break;
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = OMAP4460_ES1_1;
break;
@@ -138,6 +138,9 @@ void init_omap_revision(void)
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4470_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP4470_ES1_0;
+ break;
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = OMAP4460_ES1_1;
break;
---
arch/arm/cpu/armv7/omap4/sdram_elpida.c | 41
+--
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index d76dde7..67a7926 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs
= {
.emif_ddr_phy_ctlr_1= 0x049ff418
};
+const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
+ .sdram_config_init = 0x80800eb2,
+ .sdram_config = 0x80801ab2,
+ .ref_ctrl = 0x0618,
+ .sdram_tim1 = 0x10eb0662,
+ .sdram_tim2 = 0x20370dd2,
+ .sdram_tim3 = 0x00b1c33f,
+ .read_idle_ctrl = 0x000501ff,
+ .zq_config = 0x500b3215,
+ .temp_alert_config = 0x58016893,
+ .emif_ddr_phy_ctlr_1_init = 0x0495,
+ .emif_ddr_phy_ctlr_1= 0x049ff418
+};
+
const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
.sdram_config_init = 0x8eb9,
.sdram_config = 0x80001ab9,
@@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const
struct emif_regs **regs)
*regs = emif_regs_elpida_380_mhz_1cs;
else if (omap4_rev == OMAP4430_ES2_0)
*regs = emif_regs_elpida_200_mhz_2cs;
- else
+ else if (omap4_rev OMAP4470_ES1_0)
*regs = emif_regs_elpida_400_mhz_2cs;
+ else
+ *regs = emif_regs_elpida_400_mhz_1cs;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias(emif_get_reg_dump_sdp)));
@@ -138,20 +154,31 @@ static const struct lpddr2_device_details
elpida_2G_S4_details = {
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
+static const struct lpddr2_device_details elpida_4G_S4_details = {
+ .type = LPDDR2_TYPE_S4,
+ .density= LPDDR2_DENSITY_4Gb,
@@ -138,6 +138,9 @@ void init_omap_revision(void)
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4470_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP4470_ES1_0;
+ break;
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = OMAP4460_ES1_1;
break;
+ .io_width = LPDDR2_IO_WIDTH_32,
+ .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
+};
+
struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
{
u32 omap_rev = omap_revision();
/* EMIF1 EMIF2 have identical configuration */
- if ((omap_rev == OMAP4430_ES1_0) (cs == CS1)) {
- /* Nothing connected on CS1 for ES1.0 */
+ if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
+ (cs == CS1)) {
+ /* Nothing connected on CS1 for 4430/4470 ES1.0 */
return NULL;
- } else {
- /* In all other cases Elpida 2G device */
+ } else if (omap_rev OMAP4470_ES1_0) {
+ /* In all other 4430/4460
Re: [U-Boot] [PATCH 3/4] ARM: OMAP4470: Add Elpida EDB8164B3PF memory configuration
Hi, On Tuesday 06 August 2013 09:27 PM, Taras Kondratiuk wrote: On 08/06/2013 05:21 PM, Lokesh Vutla wrote: Hi Taras, On Tuesday 06 August 2013 05:48 PM, Taras Kondratiuk wrote: From: Lubomir Popov lpo...@mm-sol.com OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. This memory has 4Gb x 2CS = 8Gb configuration. Add configuration for runtime calculation and precalculated cases. Patch is based on a draft Lubomir's patch [1]. [1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html Just curious to know, Have you tried SDRAM_AUTO_DETECTION ? Rest looks fine to me. If you mean SYS_AUTOMATIC_SDRAM_DETECTION then yes I've tried it and it works. Cool, thats fine...!! Thanks and regards, Lokesh The only minor issue is that detection is called twice during boot: for dmm_init() and for do_sdram_init(). In case you need additional details I've put boot log with debug enabled below. U-Boot SPL 2013.07-00116-gd7325e5-dirty (Aug 06 2013 - 18:20:56) OMAP4470 ES1.0 sdram_init() in_sdram = 0 get_mr: EMIF1 cs 0 mr val 0x0 get_mr: EMIF1 cs 0 mr 0004 val 0x3 get_mr: EMIF1 cs 0 mr 0005 val 0x3 get_mr: EMIF1 cs 0 mr 0006 val 0x0 get_mr: EMIF1 cs 0 mr 0007 val 0x0 get_mr: EMIF1 cs 0 mr 0008 val 0x18 EMIF1 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF1 cs 1 mr 8000 val 0x3 get_mr: EMIF2 cs 0 mr val 0x0 get_mr: EMIF2 cs 0 mr 0004 val 0x3 get_mr: EMIF2 cs 0 mr 0005 val 0x3 get_mr: EMIF2 cs 0 mr 0006 val 0x0 get_mr: EMIF2 cs 0 mr 0007 val 0x0 get_mr: EMIF2 cs 0 mr 0008 val 0x18 EMIF2 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF2 cs 1 mr 8000 val 0x3 emif1_size 0x2000 emif2_size 0x2000 do_sdram_init() 4c00 get_mr: EMIF1 cs 0 mr val 0x0 get_mr: EMIF1 cs 0 mr 0004 val 0x3 get_mr: EMIF1 cs 0 mr 0005 val 0x3 get_mr: EMIF1 cs 0 mr 0006 val 0x0 get_mr: EMIF1 cs 0 mr 0007 val 0x0 get_mr: EMIF1 cs 0 mr 0008 val 0x18 EMIF1 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF1 cs 1 mr 8000 val 0x3 emif: timings table: 4 emif: addressing table index 6 regs-sdram_config_init - 0x8eb2 regs-sdram_config - 0x80001ab2 regs-ref_ctrl - 0x0618 regs-sdram_tim1 - 0x10eb0662 regs-sdram_tim2 - 0x20370dd2 regs-sdram_tim3 - 0x00b1c33f regs-read_idle_ctrl - 0x000501ff regs-temp_alert_config - 0x58016893 regs-zq_config - 0x500b3214 regs-emif_ddr_phy_ctlr_1 - 0x049ff418 regs-emif_ddr_phy_ctlr_1_init - 0x0495 get_mr: EMIF1 cs 0 mr val 0x0 do_sdram_init() 4c00 do_sdram_init() 4d00 get_mr: EMIF2 cs 0 mr val 0x0 get_mr: EMIF2 cs 0 mr 0004 val 0x3 get_mr: EMIF2 cs 0 mr 0005 val 0x3 get_mr: EMIF2 cs 0 mr 0006 val 0x0 get_mr: EMIF2 cs 0 mr 0007 val 0x0 get_mr: EMIF2 cs 0 mr 0008 val 0x18 EMIF2 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF2 cs 1 mr 8000 val 0x3 emif: timings table: 4 emif: addressing table index 6 regs-sdram_config_init - 0x8eb2 regs-sdram_config - 0x80001ab2 regs-ref_ctrl - 0x0618 regs-sdram_tim1 - 0x10eb0662 regs-sdram_tim2 - 0x20370dd2 regs-sdram_tim3 - 0x00b1c33f regs-read_idle_ctrl - 0x000501ff regs-temp_alert_config - 0x58016893 regs-zq_config - 0x500b3214 regs-emif_ddr_phy_ctlr_1 - 0x049ff418 regs-emif_ddr_phy_ctlr_1_init - 0x0495 get_mr: EMIF2 cs 0 mr val 0x0 do_sdram_init() 4d00 get_ram_size() successfulsdram_init() OMAP SD/MMC: 0 reading u-boot.img reading u-boot.img ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
Hi Mark,
On Friday 23 August 2013 02:58 PM, Mark Jackson wrote:
On 30/07/13 06:18, Lokesh Vutla wrote:
From: Heiko Schocher h...@denx.de
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Heiko Schocher h...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
snip
This patch introduces the following new function call ...
+void s_init(void)
+{
+/*
+ * The ROM will only have set up sufficient pinmux to allow for the
+ * first 4KiB NOR to be read, we must finish doing what we know of
+ * the NOR mux in this space in order to continue.
+ */
+#ifdef CONFIG_NOR_BOOT
+enable_norboot_pin_mux();
+#endif
... which replaces the old code ...
-/*
- * The ROM will only have set up sufficient pinmux to allow for the
- * first 4KiB NOR to be read, we must finish doing what we know of
- * the NOR mux in this space in order to continue.
- */
-#ifdef CONFIG_NOR_BOOT
-asm(stmfd sp!, {r2 - r4});
-asm(movw r4, #0x8A4);
-asm(movw r3, #0x44E1);
-asm(orrr4, r4, r3, lsl #16);
-asm(movr2, #9);
-asm(movr3, #8);
-asm(gpmc_mux: str r2, [r4], #4);
-asm(subs r3, r3, #1);
-asm(bnegpmc_mux);
-asm(ldmfd sp!, {r2 - r4});
-#endif
Now (for the TI boards) enable_norboot_pin_mux() is defined as:-
+#if defined(CONFIG_NOR_BOOT)
+static struct module_pin_mux norboot_pin_mux[] = {
+{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
+{-1},
+};
Is this configuration not working for you?
+
+void enable_norboot_pin_mux(void)
+{
+configure_module_pin_mux(norboot_pin_mux);
+}
+#endif
Firstly, this pinmux code seems wrong, since lcd_data pin map:-
lcd_data1 (mode 1) = gpmc_a1_mux1
lcd_data2 (mode 1) = gpmc_a2_mux1
lcd_data3 (mode 1) = gpmc_a3_mux1
lcd_data4 (mode 1) = gpmc_a4_mux1
lcd_data5 (mode 1) = gpmc_a5_mux1
lcd_data6 (mode 1) = gpmc_a6_mux1
lcd_data7 (mode 1) = gpmc_a7_mux1
lcd_data8 (mode 1) = gpmc_a12_mux1
lcd_data9 (mode 1) = gpmc_a13_mux1
Doesn't this leave gpmc_a[8..11] unconfigured ?
Shouldn't we configure lcd_vsync, lcd_hsync and lcd_pclk ?
Secondly, I've modded our Nanobone code to match this new setup, as follows:-
static struct module_pin_mux norboot_pin_mux[] = {
{OFFSET(lcd_data1), (MODE(1) | PULLUDDIS)}, /* GPMC A17 */
{OFFSET(lcd_data2), (MODE(1) | PULLUDDIS)}, /* GPMC A18 */
{OFFSET(lcd_data3), (MODE(1) | PULLUDDIS)}, /* GPMC A19 */
{OFFSET(lcd_data4), (MODE(1) | PULLUDDIS)}, /* GPMC A20 */
{OFFSET(lcd_data5), (MODE(1) | PULLUDDIS)}, /* GPMC A21 */
{OFFSET(lcd_data6), (MODE(1) | PULLUDDIS)}, /* GPMC A22 */
{OFFSET(lcd_data7), (MODE(1) | PULLUDDIS)}, /* GPMC A23 */
{OFFSET(lcd_vsync), (MODE(1) | PULLUDDIS)}, /* GPMC A24 */
{OFFSET(lcd_hsync), (MODE(1) | PULLUDDIS)}, /* GPMC A25 */
{OFFSET(lcd_pclk), (MODE(1) | PULLUDDIS)}, /* GPMC A26 */
{-1},
};
void enable_norboot_pin_mux(void)
{
configure_module_pin_mux(norboot_pin_mux);
}
But this fails to boot. However, if I use the old ASM code:-
void enable_norboot_pin_mux(void)
{
asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4);
asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16);
asm(movr2, #9);
asm(movr3, #8);
asm(gpmc_mux: str r2, [r4], #4);
asm(subs r3, r3, #1);
asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4});
}
This code writes 0x9 into 8 continuous registers starting from
0x44e108a4, this is what done in module_pin_mux norboot_pin_mux
except that it has 9 registers(i guess 9th register was added by mistake..:( )
Correct me if I am wrong.
So you are telling this is wrong but boots properly ?
Steve in CC can comment more on this configuration.
Thanks and regards,
Lokesh
... this now boots correctly !!
Anyone care to comment ?
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