Re: [U-Boot] [PATCH] ventana: Add Gateworks Ventana family support
On Mon, Jan 27, 2014 at 3:57 AM, Fabio Estevam feste...@gmail.com wrote:
On Tue, Jan 21, 2014 at 4:41 PM, Tim Harvey thar...@gateworks.com wrote:
+static int setup_pmic_voltages(void)
+{
+ int ret;
+ unsigned char value, rev_id = 0;
+
+ ret = i2c_set_bus_num(1);
+ if (ret)
+ return ret;
+ if (!i2c_probe(0x8)) {
+ if (i2c_read(0x8, 0, 1, value, 1)) {
+ printf(Read device ID error!\n);
+ return -1;
Please use the PMIC API to read/write to the PMIC.
Fabio,
Thanks for the review! I see include/power/pmic.h and will take a look.
Tim
Regards,
Fabio Estevam
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Re: [U-Boot] [PATCH] ventana: Add Gateworks Ventana family support
On Tue, Jan 28, 2014 at 2:20 AM, Stefano Babic sba...@denx.de wrote:
Hi Tim,
On 28/01/2014 00:36, Tim Harvey wrote:
snip
diff --git a/board/gateworks/gw_ventana/README
b/board/gateworks/gw_ventana/README
new file mode 100644
index 000..9de55ba
--- /dev/null
+++ b/board/gateworks/gw_ventana/README
@@ -0,0 +1,49 @@
+U-Boot for the Gateworks Ventana Product Family boards
+
+This file contains information for the port of U-Boot to the Gateworks
+Ventana Product family boards.
+
+1. Boot source, boot from NAND
+--
+
+The i.MX6 BOOT ROM expects some headers that provide details of NAND
layout
+and bad block information (referred to as 'bootstreams') which are
replicated
+multiple times in NAND.
The number of replications is configurable through
+board strapping options and eFUSE settings. The Freescale 'kobs-ng'
+application from the Freescale LTIB BSP, which runs under Linux, must be
used
+to program the bootstream in order to setup the replicated headers
correctly.
The behavior is quite different as we have currently in mainline. With
kobs-ng you flash u-boot.bin, while the result image for i.MXes in
mailine is u-boot.imx (u-boot.bin with imx header).
I'm not familiar with the IMX family other than IMX6 but for IMX6
kobs-ng does use u-boot.imx and not u-boot.bin. kobs needs the
headers which are not part of u-boot.bin. Are you sure you are not
mistaken here? Can you point me to some references?
I think there is a misunderstanding due to the usage of headers. What
do you mean with headers here ? As you talk about BOOT ROM, the only
header that the ROM understands is the i.MX image header, that is the
description of the image itself with the DCD and all that stuff. When
you say that kobs-ng needs headers, it seems you are talking about .h
files,
I should not have used the word 'header'.
I _am_ talking about the Image Vector Table (IVT) and Device
Configuration Data (DCD) data structures that the IMX6 BOOT ROM needs
to boot and which are present in u-boot.imx. The kobs-ng (at least
for IMX6) needs u-boot.imx because it contains these structures built
from imximage and it must flash them onto the boot media.
As far as I know, kobs-ng is a flasher - a utility to install u-boot on
the target. It is not the only method to install the binary. I think you
should rework the text making the statements more clearer.
Can you re-read the README instructions? Other than the bad link I
feel they are very clear. I think perhaps your thinking that I was in
error specifying that kobs-ng needing u-boot.imx added to some
confusion?
Regardless of what is loading the next level (u-boot.bin) the initial
flashing of NAND is still currently handled only by kobs-ng so I'm not
sure how this differs in this respect. I plan to look at adding the
functionality of kobs-ng to u-boot at some point.
If as I think kobs-ng is only a flasher, it does not take part to the
build of U-Boot binaries. IMHO it should be not part of U-Boot sources,
but maybe there are some features that can be interesting.
I was not referring to making the code a part of uboot sources but
adding the functionality that it provides such that one could use
uboot to update itself on an IMX NAND device. I'm actually surprised
nobody has done this before for IMX in general as its a bit
inconvenient to boot to a linux based OS in order to run kobs-ng to
flash the bootloader. Regardless, this would be functionality added
later.
It appears the only other mainlined IMX6 bootloader to support NAND is
the Titanium and there is no README for it at all. If there were, I
would expect it to say pretty much the same thing that my proposed
Ventana README states. There was a comment by Fabio on original
titanium patch to include a README explaining how to flash and boot
from NAND but it apparently didn't make it in:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/158436/focus=158441
I've added Stefan Roese and Fabio to the cc to hear their thoughts.
+ * retries.
+ */
+int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int retry = 3;
+ int n = 0;
+ int ret;
+
+ while (n++ retry) {
+ ret = i2c_read(chip, addr, alen, buf, len);
+ if (!ret)
+ break;
+ printf(%s: 0x%02x 0x%02x retry%d: %d\n, __func__, chip,
addr,
+n, ret);
+ if (ret != -ENODEV)
+ break;
+ mdelay(10);
+ }
Whcih is the benefit of trying three times ?
it provides a little more redundancy than 2 times, and a little less than 4
;)
As there is no guarantee that works, but it is only statistics, it looks
more a workaround as a solution.
Our GSC can occasionally be 'busy' and NAK (every 1Hz it does some
internal processing).
ok - but is there no way to understand that the component is busy ?
No - the only
[U-Boot] recommended action for bootloaders regarding modifying device-tree nodes
Greetings, I develop the boot-loader and kernel for a family of boards that have an on-board EEPROM which contains information as to what options are physically loaded on the board such as memory size/config, and peripheral IC's. We allow customers to create special builds of our standard products with sub-loaded components and while each combination of options ends up with a unique model number, it seems silly to create a different static device-trees for each possible option (not to mention we don't create the unique model number until an order is placed). My approach has been to define a per-baseboard device-tree in Linux for a 'fully loaded' board, then remove nodes which the EEPROM claims are not present in the bootloader before it passes the DTB to the kernel. I do this by defining aliases in the device-tree for the peripherals that are 'optional' so that the bootloader itself does not need to know the details about how the device is connected. Is it more appropriate for the bootloader to 'remove' nodes for devices that are not physically present or should I be setting their status property to 'disabled' instead? I'm not clear if either option really has any pros or cons. Thanks for any suggestions or comments, Tim Tim Harvey - Principal Software Engineer Gateworks Corporation 3026 S. Higuera St. San Luis Obispo CA 93401 805-781-2000 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] recommended action for bootloaders regarding modifying device-tree nodes
On Thu, Jan 30, 2014 at 12:45 PM, Jason Cooper ja...@lakedaemon.net wrote: Hi Tim, On Thu, Jan 30, 2014 at 01:11:18AM -0800, Tim Harvey wrote: My approach has been to define a per-baseboard device-tree in Linux for a 'fully loaded' board, then remove nodes which the EEPROM claims are not present in the bootloader before it passes the DTB to the kernel. I do this by defining aliases in the device-tree for the peripherals that are 'optional' so that the bootloader itself does not need to know the details about how the device is connected. This is more of a process question: Is there any information captured in your EEPROM that can't be represented in the dtb? iow, at the point when you write the EEPROM, why not write the dtb to it as configured? You could have pre-configured dtsi fragments for each config option, and then dynamically create the board dts from the order. I only ask because it would solve the problem below. However, there's a lot more to changing a manufacturing process than meets the eye. :) our eeprom config section is only 40 bytes. It contains a SKU string, mac addrs, and some bitwise fields for the various optional components that we can subload. Is it more appropriate for the bootloader to 'remove' nodes for devices that are not physically present or should I be setting their status property to 'disabled' instead? I'm not clear if either option really has any pros or cons. That depends on how you have it structured. Is it a valid dtb? Meaning, do you have four nodes all at the same register address? Perhaps you could provide an example dts? yes its a valid dtb - it is just the superset of everything the baseboard (ie schematic design) can support. A good example is a custom SKU of a baseboard with ethernet subloaded. If the EEPROM says there is no ethernet mac or phy, I would want to remove or disable the ethernet node from the devicetree. Another example would be a node for 'gpio-pps' (GPIO based pulse-per-second) support. A baseboard design that has a GPS with its PPS signal tied to a GPIO would define this in the device-tree, but if the EEPROM says the GPS isn't loaded, I would want to remove or disable the gps-pps node. Tim thx, Jason. Tim Harvey - Principal Software Engineer Gateworks Corporation btw - one of my first embedded projects was on one of your boards. An ixp425 with 4 mini-pci slots. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] recommended action for bootloaders regarding modifying device-tree nodes
On Thu, Jan 30, 2014 at 1:15 PM, Jason Gunthorpe
jguntho...@obsidianresearch.com wrote:
On Thu, Jan 30, 2014 at 03:45:58PM -0500, Jason Cooper wrote:
This is more of a process question: Is there any information captured
in your EEPROM that can't be represented in the dtb? iow, at the point
when you write the EEPROM, why not write the dtb to it as configured?
I can share what we do here.. In our systems the serial EEPROM is only
256 bytes, so storing things in DT format would be challenging.
What we do is have a master DTB that has the union of all our
configurations. The boot process has a very simple bit of code that
runs down the DTB in binary format and replaces entire
OF_DT_BEGIN_NODE-OF_DT_END_NODE regions with OF_DT_NOP.
The NOP approach is very simple, no other changes (eg offset
recalculation) needs to be done to the DT, so we can do this process
with a very small code footprint and without libfdt.
Choosing which sections to drop is done with some combination of
hardwired code and searching for specific property patterns. There are
also a few places where placeholder sections are directly fixed up, eg
a mac address is written into a placeholder of 0s, etc.
So an example might be
optional_peripheral@1 {
orc,board-style = 1;
[..]
}
Eg The board-style number comes from the EEPROM and if board-style !=
1 then the entire stanza is replaced with NOP.
Jason
Jason,
Sounds pretty much like what we are doing. I am using u-boot and my
current code looks like this:
/*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the
* peripheral is not loaded on the board.
*/
if (!test_bit(EECONFIG_ETH0, info-config))
fdt_del_node_and_alias(blob, ethernet0);
if (!test_bit(EECONFIG_ETH1, info-config))
fdt_del_node_and_alias(blob, ethernet1);
if (!test_bit(EECONFIG_HDMI_OUT, info-config))
fdt_del_node_and_alias(blob, hdmi_out);
if (!test_bit(EECONFIG_SATA, info-config))
fdt_del_node_and_alias(blob, ahci0);
if (!test_bit(EECONFIG_PCIE, info-config))
fdt_del_node_and_alias(blob, pcie);
if (!test_bit(EECONFIG_SSI0, info-config))
fdt_del_node_and_alias(blob, ssi0);
if (!test_bit(EECONFIG_SSI1, info-config))
fdt_del_node_and_alias(blob, ssi1);
...
I've submitted my code to u-boot and have been asked if its more
appropriate to remove nodes as I'm doing above or to mark them as
'disabled'. From what I can tell there really isn't a rule or
recommendation for this so I think I'll keep doing what I'm doing
above.
Thanks!
Tim
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Re: [U-Boot] [PATCH] pci: mx6: Implement reset callback
On Fri, Jan 24, 2014 at 7:25 AM, Marek Vasut ma...@denx.de wrote:
Add a callback so that a board can implement it's own specific routine to
toggle the port's nRESET line.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Stefano Babic sba...@denx.de
---
drivers/pci/pcie_imx.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 0a74867..b554075 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -450,6 +450,13 @@ static int imx6_pcie_init_phy(void)
return 0;
}
+__weak int imx6_pcie_toggle_reset(void)
+{
+ /* This function ought to be overridden ! */
+ puts(WARNING: Make sure the PCIe nRESET line is connected!\n);
+ return 0;
+}
+
static int imx6_pcie_deassert_core_reset(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -466,10 +473,9 @@ static int imx6_pcie_deassert_core_reset(void)
* Wait for the clock to settle a bit, when the clock are sourced
* from the CPU, we need about 30mS to settle.
*/
- mdelay(30);
+ mdelay(50);
- /* FIXME: GPIO reset goes here */
- mdelay(100);
+ imx6_pcie_toggle_reset();
return 0;
}
Tested-by: Tim Harvey thar...@gateworks.com
Acked-by: Tim Harvey thar...@gateworks.com
Tested on a Gateworks Ventana GW54xx board with a PLX PEX8609 switch
on the RC with 2 devices behind it:
00:01.0 - 16c3:abcd - Bridge device
01:00.0- 10b5:8609 - Bridge device
02:01.0 - 10b5:8609 - Bridge device
02:04.0 - 10b5:8609 - Bridge device
02:05.0 - 10b5:8609 - Bridge device
02:06.0 - 10b5:8609 - Bridge device
02:07.0 - 10b5:8609 - Bridge device
02:08.0 - 10b5:8609 - Bridge device
08:00.0 - 11ab:4380 - Network controller
02:09.0 - 10b5:8609 - Bridge device
01:00.1- 10b5:8609 - Base system peripheral
I would love to see this merged as the PCI driver won't really work
without it for boards that have a proper PCI_RST#.
Thanks Merek!
Tim
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[U-Boot] [PATCH 0/2] IMX6: Add Gateworks Ventana support
Signed-off-by: Tim Harvey thar...@gateworks.com Cc: Stefano Babic sba...@denx.de Cc: Stefan Roese s...@denx.de Cc: Fabio Estevam fabio.este...@freescale.com --- v2: - rebase on top of u-boot-imx - use switch..case for model specific init instead of strcmps - move checkboard to late init allowing i2c_setup to be moved to board_init() eeprom reading to be done after relocation, and move eeprom struct from data segment - move SPI/I2C init to board_init() - update README - remove unnecessary console overwrite function - fix multiline comment style and eliminate 80 char lines - eliminate unnecessary loop in board_mmc_init() - add missing copyright to clocks.cfg - avoid duplicating cfg files where no changes exist - added missing SPDX header to ventana_eeprom.h - use puts() instead of printf() for constant strings - remove messages regarding /dev/i2c-n - use get_ram_size() for determing ram_size - cleanup gpio configuration using tables for baseboard pinmux combinations - remove phy init errata as it doesn't pertain to use case (it is for 802.3az which IMX6 MAC does not support) - added pfuze100_pmic driver using PMIC API - moved GSC code (gsc command and i2c_read/i2c_write wrappers into own file) - allow user to quiet down some of the data displayed - remove display support for now - will revisit later - remove display of boot mode info - may revisit later - replace bitwise fields in eeprom structure with bit definitions Tim Harvey (2): power: add PFUZE100 PMIC driver ventana: Add Gateworks Ventana family support board/gateworks/gw_ventana/Makefile | 10 + board/gateworks/gw_ventana/README | 56 ++ board/gateworks/gw_ventana/clocks.cfg | 42 + board/gateworks/gw_ventana/gsc.c| 129 +++ board/gateworks/gw_ventana/gsc.h|9 + board/gateworks/gw_ventana/gw_ventana.c | 1200 +++ board/gateworks/gw_ventana/gw_ventana.cfg | 42 + board/gateworks/gw_ventana/ventana_eeprom.h | 103 +++ boards.cfg |5 + drivers/power/pmic/Makefile |1 + drivers/power/pmic/pmic_pfuze100.c | 42 + include/configs/gw_ventana.h| 418 ++ include/power/pfuze100_pmic.h | 96 +++ 13 files changed, 2153 insertions(+) create mode 100644 board/gateworks/gw_ventana/Makefile create mode 100644 board/gateworks/gw_ventana/README create mode 100644 board/gateworks/gw_ventana/clocks.cfg create mode 100644 board/gateworks/gw_ventana/gsc.c create mode 100644 board/gateworks/gw_ventana/gsc.h create mode 100644 board/gateworks/gw_ventana/gw_ventana.c create mode 100644 board/gateworks/gw_ventana/gw_ventana.cfg create mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h create mode 100644 drivers/power/pmic/pmic_pfuze100.c create mode 100644 include/configs/gw_ventana.h create mode 100644 include/power/pfuze100_pmic.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] power: add PFUZE100 PMIC driver
Signed-off-by: Tim Harvey thar...@gateworks.com
---
drivers/power/pmic/Makefile| 1 +
drivers/power/pmic/pmic_pfuze100.c | 42 +
include/power/pfuze100_pmic.h | 96 ++
3 files changed, 139 insertions(+)
create mode 100644 drivers/power/pmic/pmic_pfuze100.c
create mode 100644 include/power/pfuze100_pmic.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 0b45ffa..4129bda 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_pfuze100.c
b/drivers/power/pmic/pmic_pfuze100.c
new file mode 100644
index 000..c382921
--- /dev/null
+++ b/drivers/power/pmic/pmic_pfuze100.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include i2c.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
+
+int pmic_init(unsigned char bus)
+{
+ static const char name[] = PFUZE100_PMIC;
+ int ret;
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf(%s: POWER allocation error!\n, __func__);
+ return -ENOMEM;
+ }
+
+ p-name = name;
+ p-interface = PMIC_I2C;
+ p-number_of_regs = PMIC_NUM_OF_REGS;
+ p-hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR;
+ p-hw.i2c.tx_num = 1;
+ p-bus = bus;
+
+ ret = i2c_set_bus_num(p-bus);
+ if (ret)
+ return ret;
+ if (!i2c_probe(p-hw.i2c.addr)) {
+ unsigned char dev_id, rev_id;
+ i2c_read(p-hw.i2c.addr, PFUZE100_DEVICEID, 1, dev_id, 1);
+ i2c_read(p-hw.i2c.addr, PFUZE100_REVID, 1, rev_id, 1);
+ printf(PMIC: PFUZE100 0x%02x/0x%02x\n, dev_id, rev_id);
+ }
+ return 0;
+}
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
new file mode 100644
index 000..2a9032a
--- /dev/null
+++ b/include/power/pfuze100_pmic.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFUZE100_PMIC_H_
+#define __PFUZE100_PMIC_H_
+
+/* PFUZE100 registers */
+enum {
+ PFUZE100_DEVICEID = 0x00,
+ PFUZE100_REVID = 0x03,
+ PFUZE100_FABID = 0x04,
+
+ PFUZE100_SW1ABVOL = 0x20,
+ PFUZE100_SW1CVOL= 0x2e,
+ PFUZE100_SW2VOL = 0x35,
+ PFUZE100_SW3AVOL= 0x3c,
+ PFUZE100_SW3BVOL= 0x43,
+ PFUZE100_SW4VOL = 0x4a,
+ PFUZE100_SWBSTCON1 = 0x66,
+ PFUZE100_VREFDDRCON = 0x6a,
+ PFUZE100_VSNVSVOL = 0x6b,
+ PFUZE100_VGEN1VOL = 0x6c,
+ PFUZE100_VGEN2VOL = 0x6d,
+ PFUZE100_VGEN3VOL = 0x6e,
+ PFUZE100_VGEN4VOL = 0x6f,
+ PFUZE100_VGEN5VOL = 0x70,
+ PFUZE100_VGEN6VOL = 0x71,
+
+ PMIC_NUM_OF_REGS= 0x7f,
+};
+
+/*
+ * LDO Configuration
+ */
+
+/* VGEN1/2 Voltage Configuration */
+#define LDOA_0_80V 0
+#define LDOA_0_85V 1
+#define LDOA_0_90V 2
+#define LDOA_0_95V 3
+#define LDOA_1_00V 4
+#define LDOA_1_05V 5
+#define LDOA_1_10V 6
+#define LDOA_1_15V 7
+#define LDOA_1_20V 8
+#define LDOA_1_25V 9
+#define LDOA_1_30V 10
+#define LDOA_1_35V 11
+#define LDOA_1_40V 12
+#define LDOA_1_45V 13
+#define LDOA_1_50V 14
+#define LDOA_1_55V 15
+
+/* VGEN3/4/5/6 Voltage Configuration */
+#define LDOB_1_80V 0
+#define LDOB_1_90V 1
+#define LDOB_2_00V 2
+#define LDOB_2_10V 3
+#define LDOB_2_20V 4
+#define LDOB_2_30V 5
+#define LDOB_2_40V 6
+#define LDOB_2_50V 7
+#define LDOB_2_60V 8
+#define LDOB_2_70V 9
+#define LDOB_2_80V 10
+#define LDOB_2_90V 11
+#define LDOB_3_00V 12
+#define LDOB_3_10V 13
+#define LDOB_3_20V 14
+#define LDOB_3_30V 15
+
+#define LDO_VOL_MASK 0xf
+#define LDO_EN 4
+
+/*
+ * Boost Regulator
+ */
+
+/* SWBST Output Voltage */
+#define SWBST_5_00V0
+#define SWBST_5_05V1
+#define SWBST_5_10V2
+#define SWBST_5_15V3
+
+#define SWBST_VOL_MASK 0x3
+#define SWBST_MODE_MASK0x6
+#define SWBST_MODE_OFF (2 0)
+#define SWBST_MODE_PFM (2 1)
+#define SWBST_MODE_AUTO(2 2)
+#define SWBST_MODE_APS (2 3)
+
+#endif
--
1.8.3.2
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Re: [U-Boot] [PATCH 1/2] power: add PFUZE100 PMIC driver
On Mon, Feb 3, 2014 at 4:05 AM, Stefano Babic sba...@denx.de wrote:
Hi Tim,
On 01/02/2014 20:49, Tim Harvey wrote:
Signed-off-by: Tim Harvey thar...@gateworks.com
---
drivers/power/pmic/Makefile| 1 +
drivers/power/pmic/pmic_pfuze100.c | 42 +
include/power/pfuze100_pmic.h | 96
++
3 files changed, 139 insertions(+)
create mode 100644 drivers/power/pmic/pmic_pfuze100.c
create mode 100644 include/power/pfuze100_pmic.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 0b45ffa..4129bda 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_pfuze100.c
b/drivers/power/pmic/pmic_pfuze100.c
new file mode 100644
index 000..c382921
--- /dev/null
+++ b/drivers/power/pmic/pmic_pfuze100.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include i2c.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
+
+int pmic_init(unsigned char bus)
+{
+ static const char name[] = PFUZE100_PMIC;
+ int ret;
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf(%s: POWER allocation error!\n, __func__);
+ return -ENOMEM;
+ }
+
+ p-name = name;
+ p-interface = PMIC_I2C;
+ p-number_of_regs = PMIC_NUM_OF_REGS;
+ p-hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR;
+ p-hw.i2c.tx_num = 1;
+ p-bus = bus;
+
+ ret = i2c_set_bus_num(p-bus);
+ if (ret)
+ return ret;
+ if (!i2c_probe(p-hw.i2c.addr)) {
+ unsigned char dev_id, rev_id;
+ i2c_read(p-hw.i2c.addr, PFUZE100_DEVICEID, 1, dev_id, 1);
+ i2c_read(p-hw.i2c.addr, PFUZE100_REVID, 1, rev_id, 1);
+ printf(PMIC: PFUZE100 0x%02x/0x%02x\n, dev_id, rev_id);
This is always printed, not only on your board - even from other board,
if any, that will use this pmic. If you want that your board always
prints the pmic revision, move this output to your board file - maybe in
checkboard().
I noticed that all the pmic drivers in drivers/power/pmic print
something very generic in their pmic_init such as 'Board PMIC init'
(even though no initialization or communication with the pmic has
occurred). I thought I would be a bit more specific and display
exactly which PMIC init has been called and provide some details about
the PMIC version.
I would agree that this can go into checkboard()
Is there value in adding the 'puts(Board PMIC init\n)? I didn't
want to display that if the pmic isn't present (as this PMIC isn't
present on some Ventana boards).
+ }
+ return 0;
If i2c_probe() returns with error, why does this function returns with
zero (= no error) ?
oops! If displaying the version info shouldn't go in pmic_init, then
I'm not sure the value of even doing the probe here either so I will
remove.
Thanks for the review!
Tim
Best regards,
Stefano Babic
--
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Re: [U-Boot] [PATCH 2/2] ventana: Add Gateworks Ventana family support
On Mon, Feb 3, 2014 at 9:39 AM, Stefano Babic sba...@denx.de wrote: Hi Tim, On 01/02/2014 20:49, Tim Harvey wrote: Gateworks Ventana is a product family based on the i.MX6. This patch adds support for all boards in the Ventana family. Where possible, data from the boards EEPROM is used to determine various details about the board at runtime. Signed-off-by: Tim Harvey thar...@gateworks.com --- board/gateworks/gw_ventana/Makefile | 10 + board/gateworks/gw_ventana/README | 56 ++ board/gateworks/gw_ventana/clocks.cfg | 42 + board/gateworks/gw_ventana/gsc.c| 129 +++ board/gateworks/gw_ventana/gsc.h|9 + board/gateworks/gw_ventana/gw_ventana.c | 1200 +++ board/gateworks/gw_ventana/gw_ventana.cfg | 42 + board/gateworks/gw_ventana/ventana_eeprom.h | 103 +++ boards.cfg |5 + include/configs/gw_ventana.h| 418 ++ 10 files changed, 2014 insertions(+) create mode 100644 board/gateworks/gw_ventana/Makefile create mode 100644 board/gateworks/gw_ventana/README create mode 100644 board/gateworks/gw_ventana/clocks.cfg create mode 100644 board/gateworks/gw_ventana/gsc.c create mode 100644 board/gateworks/gw_ventana/gsc.h create mode 100644 board/gateworks/gw_ventana/gw_ventana.c create mode 100644 board/gateworks/gw_ventana/gw_ventana.cfg create mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h create mode 100644 include/configs/gw_ventana.h diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile new file mode 100644 index 000..e8dab89 --- /dev/null +++ b/board/gateworks/gw_ventana/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski l...@denx.de +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Gateworks Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := gw_ventana.o gsc.o + diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README new file mode 100644 index 000..f744a4a --- /dev/null +++ b/board/gateworks/gw_ventana/README @@ -0,0 +1,56 @@ +U-Boot for the Gateworks Ventana Product Family boards + +This file contains information for the port of U-Boot to the Gateworks +Ventana Product family boards. + +1. Boot source, boot from NAND +-- + +The i.MX6 BOOT ROM expects some structures that provide details of NAND layout +and bad block information (referred to as 'bootstreams') which are replicated +multiple times in NAND. The number of replications is configurable through +board strapping options and eFUSE settings. The Freescale 'kobs-ng' +application from the Freescale LTIB BSP, which runs under Linux, must be used +to program the bootstream in order to setup the replicated headers correctly. + +The Gateworks Ventana boards with NAND flash have been factory programmed +such that their eFUSE settings expect 2 copies of the boostream (this is +specified by providing kobs-ng with the --search_exponent=1 argument). Once in +Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream +with: + +kobs-ng init -v -x --search_exponent=1 u-boot.imx + +The kobs-ng application users an imximage (u-boot.imx) which contains the ^-- spelling, uses will fix +Image Vector Table (IVT) and Device Configuration Data (DCD) structures that +the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware +Configuration Block (FCB) and Discovered Bad Block Table (DBBT). + +This information is taken from: + http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH + +More details about the i.MX6 BOOT ROM can be found at: + http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf Why cache.freescale ? I think you can simply write that more information are in the User Manual. Freescale moves sometimes the location of the documentation. will replace with: More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manuals. diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c new file mode 100644 index 000..72eec38 --- /dev/null +++ b/board/gateworks/gw_ventana/gsc.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey thar...@gateworks.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include asm/errno.h +#include common.h +#include i2c.h +#include linux/ctype.h + +/* + * The Gateworks System Controller will fail to ACK a master transaction if + * it is busy, which can occur during its 1HZ timer tick while reading ADC's. + * When this does occur, it will never be busy long enough to fail more than + * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with + * 3 retries. + */ +int gsc_i2c_read(uchar chip
[U-Boot] [PATCH v3 0/2] IMX6: Add Gateworks Ventana support
Changes in v3: - update README fixing typo and removing Freescale document link - use debug() instead of printf() - be more explicit with hwmon error output and use macro for min/max percent - use #defines for GSC slave address and registers - remove extern from function prototype - moved gpio config into structure for better readability - use enum for eeprom bit configs and array to map to fdt property alias - add SATA regardless of cpu type - add FIT support regardless of flash type - display PMIC and device id in misc_init_r() instead of pmic driver Changes in v2: - rebase on top of u-boot-imx - use switch..case for model specific init instead of strcmps - move checkboard to late init allowing i2c_setup to be moved to board_init() eeprom reading to be done after relocation, and move eeprom struct from data segment - move SPI/I2C init to board_init() - update README - remove unnecessary console overwrite function - fix multiline comment style and eliminate 80 char lines - eliminate unnecessary loop in board_mmc_init() - add missing copyright to clocks.cfg - avoid duplicating cfg files where no changes exist - added missing SPDX header to ventana_eeprom.h - use puts() instead of printf() for constant strings - remove messages regarding /dev/i2c-n - use get_ram_size() for determing ram_size - cleanup gpio configuration using tables for baseboard pinmux combinations - remove phy init errata as it doesn't pertain to use case (it is for 802.3az which IMX6 MAC does not support) - added pfuze100_pmic driver using PMIC API - moved GSC code (gsc command and i2c_read/i2c_write wrappers into own file) - allow user to quiet down some of the data displayed - remove display support for now - will revisit later - remove display of boot mode info - may revisit later - replace bitwise fields in eeprom structure with bit definitions Tim Harvey (2): power: add PFUZE100 PMIC driver ventana: Add Gateworks Ventana family support board/gateworks/gw_ventana/Makefile | 10 + board/gateworks/gw_ventana/README | 55 ++ board/gateworks/gw_ventana/clocks.cfg | 42 + board/gateworks/gw_ventana/gsc.c| 129 +++ board/gateworks/gw_ventana/gsc.h| 30 + board/gateworks/gw_ventana/gw_ventana.c | 1240 +++ board/gateworks/gw_ventana/gw_ventana.cfg | 42 + board/gateworks/gw_ventana/ventana_eeprom.h | 106 +++ boards.cfg |5 + drivers/power/pmic/Makefile |1 + drivers/power/pmic/pmic_pfuze100.c | 33 + include/configs/gw_ventana.h| 415 + include/power/pfuze100_pmic.h | 96 +++ 13 files changed, 2204 insertions(+) create mode 100644 board/gateworks/gw_ventana/Makefile create mode 100644 board/gateworks/gw_ventana/README create mode 100644 board/gateworks/gw_ventana/clocks.cfg create mode 100644 board/gateworks/gw_ventana/gsc.c create mode 100644 board/gateworks/gw_ventana/gsc.h create mode 100644 board/gateworks/gw_ventana/gw_ventana.c create mode 100644 board/gateworks/gw_ventana/gw_ventana.cfg create mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h create mode 100644 drivers/power/pmic/pmic_pfuze100.c create mode 100644 include/configs/gw_ventana.h create mode 100644 include/power/pfuze100_pmic.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/2] power: add PFUZE100 PMIC driver
Signed-off-by: Tim Harvey thar...@gateworks.com
Cc: Stefano Babic sba...@denx.de
---
Changes in v2:
- remove detect and device_id display from pmic_init()
drivers/power/pmic/Makefile| 1 +
drivers/power/pmic/pmic_pfuze100.c | 33 +
include/power/pfuze100_pmic.h | 96 ++
3 files changed, 130 insertions(+)
create mode 100644 drivers/power/pmic/pmic_pfuze100.c
create mode 100644 include/power/pfuze100_pmic.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 0b45ffa..4129bda 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_pfuze100.c
b/drivers/power/pmic/pmic_pfuze100.c
new file mode 100644
index 000..3962bb7
--- /dev/null
+++ b/drivers/power/pmic/pmic_pfuze100.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include i2c.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
+
+int pmic_init(unsigned char bus)
+{
+ static const char name[] = PFUZE100_PMIC;
+ int ret;
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf(%s: POWER allocation error!\n, __func__);
+ return -ENOMEM;
+ }
+
+ p-name = name;
+ p-interface = PMIC_I2C;
+ p-number_of_regs = PMIC_NUM_OF_REGS;
+ p-hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR;
+ p-hw.i2c.tx_num = 1;
+ p-bus = bus;
+
+ return 0;
+}
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
new file mode 100644
index 000..2a9032a
--- /dev/null
+++ b/include/power/pfuze100_pmic.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFUZE100_PMIC_H_
+#define __PFUZE100_PMIC_H_
+
+/* PFUZE100 registers */
+enum {
+ PFUZE100_DEVICEID = 0x00,
+ PFUZE100_REVID = 0x03,
+ PFUZE100_FABID = 0x04,
+
+ PFUZE100_SW1ABVOL = 0x20,
+ PFUZE100_SW1CVOL= 0x2e,
+ PFUZE100_SW2VOL = 0x35,
+ PFUZE100_SW3AVOL= 0x3c,
+ PFUZE100_SW3BVOL= 0x43,
+ PFUZE100_SW4VOL = 0x4a,
+ PFUZE100_SWBSTCON1 = 0x66,
+ PFUZE100_VREFDDRCON = 0x6a,
+ PFUZE100_VSNVSVOL = 0x6b,
+ PFUZE100_VGEN1VOL = 0x6c,
+ PFUZE100_VGEN2VOL = 0x6d,
+ PFUZE100_VGEN3VOL = 0x6e,
+ PFUZE100_VGEN4VOL = 0x6f,
+ PFUZE100_VGEN5VOL = 0x70,
+ PFUZE100_VGEN6VOL = 0x71,
+
+ PMIC_NUM_OF_REGS= 0x7f,
+};
+
+/*
+ * LDO Configuration
+ */
+
+/* VGEN1/2 Voltage Configuration */
+#define LDOA_0_80V 0
+#define LDOA_0_85V 1
+#define LDOA_0_90V 2
+#define LDOA_0_95V 3
+#define LDOA_1_00V 4
+#define LDOA_1_05V 5
+#define LDOA_1_10V 6
+#define LDOA_1_15V 7
+#define LDOA_1_20V 8
+#define LDOA_1_25V 9
+#define LDOA_1_30V 10
+#define LDOA_1_35V 11
+#define LDOA_1_40V 12
+#define LDOA_1_45V 13
+#define LDOA_1_50V 14
+#define LDOA_1_55V 15
+
+/* VGEN3/4/5/6 Voltage Configuration */
+#define LDOB_1_80V 0
+#define LDOB_1_90V 1
+#define LDOB_2_00V 2
+#define LDOB_2_10V 3
+#define LDOB_2_20V 4
+#define LDOB_2_30V 5
+#define LDOB_2_40V 6
+#define LDOB_2_50V 7
+#define LDOB_2_60V 8
+#define LDOB_2_70V 9
+#define LDOB_2_80V 10
+#define LDOB_2_90V 11
+#define LDOB_3_00V 12
+#define LDOB_3_10V 13
+#define LDOB_3_20V 14
+#define LDOB_3_30V 15
+
+#define LDO_VOL_MASK 0xf
+#define LDO_EN 4
+
+/*
+ * Boost Regulator
+ */
+
+/* SWBST Output Voltage */
+#define SWBST_5_00V0
+#define SWBST_5_05V1
+#define SWBST_5_10V2
+#define SWBST_5_15V3
+
+#define SWBST_VOL_MASK 0x3
+#define SWBST_MODE_MASK0x6
+#define SWBST_MODE_OFF (2 0)
+#define SWBST_MODE_PFM (2 1)
+#define SWBST_MODE_AUTO(2 2)
+#define SWBST_MODE_APS (2 3)
+
+#endif
--
1.8.3.2
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[U-Boot] [PATCH v3 1/2] power: add PFUZE100 PMIC driver
Signed-off-by: Tim Harvey thar...@gateworks.com
Cc: Stefano Babic sbabic at denx.de
---
Changes in v2:
- remove detect and device_id display from pmic_init()
drivers/power/pmic/Makefile| 1 +
drivers/power/pmic/pmic_pfuze100.c | 33 +
include/power/pfuze100_pmic.h | 96 ++
3 files changed, 130 insertions(+)
create mode 100644 drivers/power/pmic/pmic_pfuze100.c
create mode 100644 include/power/pfuze100_pmic.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 0b45ffa..4129bda 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_pfuze100.c
b/drivers/power/pmic/pmic_pfuze100.c
new file mode 100644
index 000..3962bb7
--- /dev/null
+++ b/drivers/power/pmic/pmic_pfuze100.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include i2c.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
+
+int pmic_init(unsigned char bus)
+{
+ static const char name[] = PFUZE100_PMIC;
+ int ret;
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf(%s: POWER allocation error!\n, __func__);
+ return -ENOMEM;
+ }
+
+ p-name = name;
+ p-interface = PMIC_I2C;
+ p-number_of_regs = PMIC_NUM_OF_REGS;
+ p-hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR;
+ p-hw.i2c.tx_num = 1;
+ p-bus = bus;
+
+ return 0;
+}
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
new file mode 100644
index 000..2a9032a
--- /dev/null
+++ b/include/power/pfuze100_pmic.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFUZE100_PMIC_H_
+#define __PFUZE100_PMIC_H_
+
+/* PFUZE100 registers */
+enum {
+ PFUZE100_DEVICEID = 0x00,
+ PFUZE100_REVID = 0x03,
+ PFUZE100_FABID = 0x04,
+
+ PFUZE100_SW1ABVOL = 0x20,
+ PFUZE100_SW1CVOL= 0x2e,
+ PFUZE100_SW2VOL = 0x35,
+ PFUZE100_SW3AVOL= 0x3c,
+ PFUZE100_SW3BVOL= 0x43,
+ PFUZE100_SW4VOL = 0x4a,
+ PFUZE100_SWBSTCON1 = 0x66,
+ PFUZE100_VREFDDRCON = 0x6a,
+ PFUZE100_VSNVSVOL = 0x6b,
+ PFUZE100_VGEN1VOL = 0x6c,
+ PFUZE100_VGEN2VOL = 0x6d,
+ PFUZE100_VGEN3VOL = 0x6e,
+ PFUZE100_VGEN4VOL = 0x6f,
+ PFUZE100_VGEN5VOL = 0x70,
+ PFUZE100_VGEN6VOL = 0x71,
+
+ PMIC_NUM_OF_REGS= 0x7f,
+};
+
+/*
+ * LDO Configuration
+ */
+
+/* VGEN1/2 Voltage Configuration */
+#define LDOA_0_80V 0
+#define LDOA_0_85V 1
+#define LDOA_0_90V 2
+#define LDOA_0_95V 3
+#define LDOA_1_00V 4
+#define LDOA_1_05V 5
+#define LDOA_1_10V 6
+#define LDOA_1_15V 7
+#define LDOA_1_20V 8
+#define LDOA_1_25V 9
+#define LDOA_1_30V 10
+#define LDOA_1_35V 11
+#define LDOA_1_40V 12
+#define LDOA_1_45V 13
+#define LDOA_1_50V 14
+#define LDOA_1_55V 15
+
+/* VGEN3/4/5/6 Voltage Configuration */
+#define LDOB_1_80V 0
+#define LDOB_1_90V 1
+#define LDOB_2_00V 2
+#define LDOB_2_10V 3
+#define LDOB_2_20V 4
+#define LDOB_2_30V 5
+#define LDOB_2_40V 6
+#define LDOB_2_50V 7
+#define LDOB_2_60V 8
+#define LDOB_2_70V 9
+#define LDOB_2_80V 10
+#define LDOB_2_90V 11
+#define LDOB_3_00V 12
+#define LDOB_3_10V 13
+#define LDOB_3_20V 14
+#define LDOB_3_30V 15
+
+#define LDO_VOL_MASK 0xf
+#define LDO_EN 4
+
+/*
+ * Boost Regulator
+ */
+
+/* SWBST Output Voltage */
+#define SWBST_5_00V0
+#define SWBST_5_05V1
+#define SWBST_5_10V2
+#define SWBST_5_15V3
+
+#define SWBST_VOL_MASK 0x3
+#define SWBST_MODE_MASK0x6
+#define SWBST_MODE_OFF (2 0)
+#define SWBST_MODE_PFM (2 1)
+#define SWBST_MODE_AUTO(2 2)
+#define SWBST_MODE_APS (2 3)
+
+#endif
--
1.8.3.2
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Re: [U-Boot] [PATCH v3 2/2] ventana: Add Gateworks Ventana family support
On Wed, Feb 5, 2014 at 3:43 PM, Wolfgang Denk w...@denx.de wrote: Dear Tim Harvey, In message 1391642553-25778-1-git-send-email-thar...@gateworks.com you wrote: Gateworks Ventana is a product family based on the i.MX6. This patch adds support for all boards in the Ventana family. Where possible, data from the boards EEPROM is used to determine various details about the board at runtime. ... +#define MINMAX(n, percent) n*(1.0-percent/100), n*(1.0+percent/100) U-Boot is integer arithmetics only. You must not use any FP calculations in the code. ok +/* + * Hardware Monitor + */ +#define GSC_HWMON_TEMP 0x00 +#define GSC_HWMON_VIN0x02 +#define GSC_HWMON_VDD_3P30x05 +#define GSC_HWMON_VBATT 0x08 +#define GSC_HWMON_VDD_5P00x0b +#define GSC_HWMON_VDD_CORE 0x0e +#define GSC_HWMON_VDD_HIGH 0x14 +#define GSC_HWMON_VDD_DDR0x17 +#define GSC_HWMON_VDD_SOC0x11 +#define GSC_HWMON_VDD_1P80x1d +#define GSC_HWMON_VDD_2P50x23 +#define GSC_HWMON_VDD_1P00x20 I'd really like to see a C struct here to describe the register layout... you mean enum right? I see that some include/power/*.h use enums for regs, others use #defines. I would agree that enums save some text at least and seem preferable. diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h new file mode 100644 index 000..1a18d93 ... + #define CONFIG_SPI_FLASH_WINBOND_ERASESIZE 64*1024 /* 4,32,64K for W26Q256 */ This causes a checkpatch error: ERROR: Macros with complex values should be enclosed in parenthesis Please fix! what args do you run checkpatch.pl with? The default args does not check COMPLEX_MACRO it would seem which is why I missed that. Thanks, Tim Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The use of anthropomorphic terminology when dealing with computing systems is a symptom of professional immaturity. -- Edsger Dijkstra ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/2] ventana: Add Gateworks Ventana family support
On Thu, Feb 6, 2014 at 4:07 AM, Wolfgang Denk w...@denx.de wrote: Dear Tim, In message caj+vnu2udv1yeujh79uznf01jtamde7p8u-g_x1hendg7mk...@mail.gmail.com you wrote: +/* + * Hardware Monitor + */ +#define GSC_HWMON_TEMP 0x00 +#define GSC_HWMON_VIN0x02 +#define GSC_HWMON_VDD_3P30x05 +#define GSC_HWMON_VBATT 0x08 +#define GSC_HWMON_VDD_5P00x0b +#define GSC_HWMON_VDD_CORE 0x0e +#define GSC_HWMON_VDD_HIGH 0x14 +#define GSC_HWMON_VDD_DDR0x17 +#define GSC_HWMON_VDD_SOC0x11 +#define GSC_HWMON_VDD_1P80x1d +#define GSC_HWMON_VDD_2P50x23 +#define GSC_HWMON_VDD_1P00x20 I'd really like to see a C struct here to describe the register layout... you mean enum right? No, actually I mean a struct - but on closer look I am not really sure if these numbers are offsets against a device base address or actually I2C addresses? These are register offsets, not i2c addresses. An enum makes sense to me. Can you point me to an example of a struct your talking about? Thanks, Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 1/2] power: add PFUZE100 PMIC driver
Signed-off-by: Tim Harvey thar...@gateworks.com
Acked-by: Stefano Babic sba...@denx.de
---
Changes in v3:
- no changes
Changes in v2:
- remove detect and device_id display from pmic_init()
Signed-off-by: Tim Harvey thar...@gateworks.com
---
drivers/power/pmic/Makefile| 1 +
drivers/power/pmic/pmic_pfuze100.c | 32 +
include/power/pfuze100_pmic.h | 96 ++
3 files changed, 129 insertions(+)
create mode 100644 drivers/power/pmic/pmic_pfuze100.c
create mode 100644 include/power/pfuze100_pmic.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 0b45ffa..4129bda 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_pfuze100.c
b/drivers/power/pmic/pmic_pfuze100.c
new file mode 100644
index 000..22c1f15
--- /dev/null
+++ b/drivers/power/pmic/pmic_pfuze100.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include i2c.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
+
+int pmic_init(unsigned char bus)
+{
+ static const char name[] = PFUZE100_PMIC;
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf(%s: POWER allocation error!\n, __func__);
+ return -ENOMEM;
+ }
+
+ p-name = name;
+ p-interface = PMIC_I2C;
+ p-number_of_regs = PMIC_NUM_OF_REGS;
+ p-hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR;
+ p-hw.i2c.tx_num = 1;
+ p-bus = bus;
+
+ return 0;
+}
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
new file mode 100644
index 000..2a9032a
--- /dev/null
+++ b/include/power/pfuze100_pmic.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFUZE100_PMIC_H_
+#define __PFUZE100_PMIC_H_
+
+/* PFUZE100 registers */
+enum {
+ PFUZE100_DEVICEID = 0x00,
+ PFUZE100_REVID = 0x03,
+ PFUZE100_FABID = 0x04,
+
+ PFUZE100_SW1ABVOL = 0x20,
+ PFUZE100_SW1CVOL= 0x2e,
+ PFUZE100_SW2VOL = 0x35,
+ PFUZE100_SW3AVOL= 0x3c,
+ PFUZE100_SW3BVOL= 0x43,
+ PFUZE100_SW4VOL = 0x4a,
+ PFUZE100_SWBSTCON1 = 0x66,
+ PFUZE100_VREFDDRCON = 0x6a,
+ PFUZE100_VSNVSVOL = 0x6b,
+ PFUZE100_VGEN1VOL = 0x6c,
+ PFUZE100_VGEN2VOL = 0x6d,
+ PFUZE100_VGEN3VOL = 0x6e,
+ PFUZE100_VGEN4VOL = 0x6f,
+ PFUZE100_VGEN5VOL = 0x70,
+ PFUZE100_VGEN6VOL = 0x71,
+
+ PMIC_NUM_OF_REGS= 0x7f,
+};
+
+/*
+ * LDO Configuration
+ */
+
+/* VGEN1/2 Voltage Configuration */
+#define LDOA_0_80V 0
+#define LDOA_0_85V 1
+#define LDOA_0_90V 2
+#define LDOA_0_95V 3
+#define LDOA_1_00V 4
+#define LDOA_1_05V 5
+#define LDOA_1_10V 6
+#define LDOA_1_15V 7
+#define LDOA_1_20V 8
+#define LDOA_1_25V 9
+#define LDOA_1_30V 10
+#define LDOA_1_35V 11
+#define LDOA_1_40V 12
+#define LDOA_1_45V 13
+#define LDOA_1_50V 14
+#define LDOA_1_55V 15
+
+/* VGEN3/4/5/6 Voltage Configuration */
+#define LDOB_1_80V 0
+#define LDOB_1_90V 1
+#define LDOB_2_00V 2
+#define LDOB_2_10V 3
+#define LDOB_2_20V 4
+#define LDOB_2_30V 5
+#define LDOB_2_40V 6
+#define LDOB_2_50V 7
+#define LDOB_2_60V 8
+#define LDOB_2_70V 9
+#define LDOB_2_80V 10
+#define LDOB_2_90V 11
+#define LDOB_3_00V 12
+#define LDOB_3_10V 13
+#define LDOB_3_20V 14
+#define LDOB_3_30V 15
+
+#define LDO_VOL_MASK 0xf
+#define LDO_EN 4
+
+/*
+ * Boost Regulator
+ */
+
+/* SWBST Output Voltage */
+#define SWBST_5_00V0
+#define SWBST_5_05V1
+#define SWBST_5_10V2
+#define SWBST_5_15V3
+
+#define SWBST_VOL_MASK 0x3
+#define SWBST_MODE_MASK0x6
+#define SWBST_MODE_OFF (2 0)
+#define SWBST_MODE_PFM (2 1)
+#define SWBST_MODE_AUTO(2 2)
+#define SWBST_MODE_APS (2 3)
+
+#endif
--
1.8.3.2
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[U-Boot] [PATCH v4 0/2] IMX6: Add Gateworks Ventana support
Changes in v4: - fixed FP calculation - fixed invalid return type for read_eeprom() - use enum and defines for GSC HWMON registers/bits - removed unused CONFIG_SPI_FLASH_WINBOND_ERASESIZE - use defines for I2C bus numbers - added PCIE support - moved board-specific gpio iomux to board_init as imx6_pcie_toggle_reset needs it Changes in v3: - update README fixing typo and removing Freescale document link - use debug() instead of printf() - be more explicit with hwmon error output and use macro for min/max percent - use #defines for GSC slave address and registers - remove extern from function prototype - moved gpio config into structure for better readability - use enum for eeprom bit configs and array to map to fdt property alias - add SATA regardless of cpu type - add FIT support regardless of flash type - display PMIC and device id in misc_init_r() instead of pmic driver Changes in v2: - rebase on top of u-boot-imx - use switch..case for model specific init instead of strcmps - move checkboard to late init allowing i2c_setup to be moved to board_init() eeprom reading to be done after relocation, and move eeprom struct from data segment - move SPI/I2C init to board_init() - update README - remove unnecessary console overwrite function - fix multiline comment style and eliminate 80 char lines - eliminate unnecessary loop in board_mmc_init() - add missing copyright to clocks.cfg - avoid duplicating cfg files where no changes exist - added missing SPDX header to ventana_eeprom.h - use puts() instead of printf() for constant strings - remove messages regarding /dev/i2c-n - use get_ram_size() for determing ram_size - cleanup gpio configuration using tables for baseboard pinmux combinations - remove phy init errata as it doesn't pertain to use case (it is for 802.3az which IMX6 MAC does not support) - added pfuze100_pmic driver using PMIC API - moved GSC code (gsc command and i2c_read/i2c_write wrappers into own file) - allow user to quiet down some of the data displayed - remove display support for now - will revisit later - remove display of boot mode info - may revisit later - replace bitwise fields in eeprom structure with bit definitions Tim Harvey (2): power: add PFUZE100 PMIC driver ventana: Add Gateworks Ventana family support board/gateworks/gw_ventana/Makefile | 10 + board/gateworks/gw_ventana/README | 55 ++ board/gateworks/gw_ventana/clocks.cfg | 42 + board/gateworks/gw_ventana/gsc.c| 129 +++ board/gateworks/gw_ventana/gsc.h| 64 ++ board/gateworks/gw_ventana/gw_ventana.c | 1262 +++ board/gateworks/gw_ventana/gw_ventana.cfg | 42 + board/gateworks/gw_ventana/ventana_eeprom.h | 106 +++ boards.cfg |5 + drivers/power/pmic/Makefile |1 + drivers/power/pmic/pmic_pfuze100.c | 32 + include/configs/gw_ventana.h| 425 + include/power/pfuze100_pmic.h | 96 ++ 13 files changed, 2269 insertions(+) create mode 100644 board/gateworks/gw_ventana/Makefile create mode 100644 board/gateworks/gw_ventana/README create mode 100644 board/gateworks/gw_ventana/clocks.cfg create mode 100644 board/gateworks/gw_ventana/gsc.c create mode 100644 board/gateworks/gw_ventana/gsc.h create mode 100644 board/gateworks/gw_ventana/gw_ventana.c create mode 100644 board/gateworks/gw_ventana/gw_ventana.cfg create mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h create mode 100644 drivers/power/pmic/pmic_pfuze100.c create mode 100644 include/configs/gw_ventana.h create mode 100644 include/power/pfuze100_pmic.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/2] ventana: Add Gateworks Ventana family support
On Wed, Mar 5, 2014 at 3:22 AM, Stefano Babic sba...@denx.de wrote: Hi Tim, On 05/03/2014 12:06, Stefano Babic wrote: On 13/02/2014 08:48, Tim Harvey wrote: Gateworks Ventana is a product family based on the i.MX6. This patch adds support for all boards in the Ventana family. Where possible, data from the boards EEPROM is used to determine various details about the board at runtime. Signed-off-by: Tim Harvey thar...@gateworks.com Cc: Stefano Babic sba...@denx.de --- Applied to u-boot-imx, thanks ! I merged but not yet pushed to the server. I have found an issue: gwventanaq cannot be compiled. In fact, the combination quad + 512MB RAM is not covered in /gw_ventana.cfg: /home/stefano/Projects/imx/u-boot-imx/board/gateworks/gw_ventana/gw_ventana.cfg:40:4: error: #error Unsupported CPU/Memory configuration Can you fix and resubmit ? Thanks ! Stefano, Sorry about that - yes I realized that issue as well a few days back. I posted a v5 patch yesterday. Let me know if there is anything else needed. Thanks, Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/18] i2c: imx: add macros to setup pads for multiple SoC types
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nik...@compulab.co.il wrote:
Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.
Cc: Stefano Babic sba...@denx.de
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
arch/arm/include/asm/imx-common/mxc_i2c.h | 33
+++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h
b/arch/arm/include/asm/imx-common/mxc_i2c.h
index 47a9edc..182c2f3 100644
--- a/arch/arm/include/asm/imx-common/mxc_i2c.h
+++ b/arch/arm/include/asm/imx-common/mxc_i2c.h
@@ -19,6 +19,39 @@ struct i2c_pads_info {
struct i2c_pin_ctrl sda;
};
+#if defined(CONFIG_MX6QDL)
+#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp)
\
+ struct i2c_pads_info mx6q_##name = {\
+ .scl = {\
+ .i2c_mode = MX6Q_##scl_i2c, \
+ .gpio_mode = MX6Q_##scl_gpio, \
+ .gp = scl_gp, \
+ }, \
+ .sda = {\
+ .i2c_mode = MX6Q_##sda_i2c, \
+ .gpio_mode = MX6Q_##sda_gpio, \
+ .gp = sda_gp, \
+ } \
+ }; \
+ struct i2c_pads_info mx6s_##name = {\
+ .scl = {\
+ .i2c_mode = MX6DL_##scl_i2c,\
+ .gpio_mode = MX6DL_##scl_gpio, \
+ .gp = scl_gp, \
+ }, \
+ .sda = {\
+ .i2c_mode = MX6DL_##sda_i2c,\
+ .gpio_mode = MX6DL_##sda_gpio, \
+ .gp = sda_gp, \
+ } \
+ };
+
+
+#define I2C_PADS_INFO(name)\
+ (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
+ mx6q_##name : mx6s_##name
+#endif
+
void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
struct i2c_pads_info *p);
void bus_i2c_init(void *base, int speed, int slave_addr,
--
1.9.1
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Hi Nikita,
Very nice cleanup!
Acked-by: Tim Harvey thar...@gateworks.com
Tim
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Re: [U-Boot] [PATCH 2/4] ARM: mx6: Prevent overflow in DRAM size detection
On Sun, Aug 3, 2014 at 4:47 PM, Marek Vasut ma...@denx.de wrote: The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but only 3840 MiB of that can be really used. In case the controller is configured to operate a 4GiB module, the imx_ddr_size() function will correctly compute that there is 4GiB of DRAM in the system. Firstly, the return value is 32-bit, so the function will effectively return zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB of all that. Thus, clamp the returned size to 3840MiB in such case. Signed-off-by: Marek Vasut ma...@denx.de --- arch/arm/imx-common/cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 5a09107..0ec8b18 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -93,6 +93,11 @@ unsigned imx_ddr_size(void) bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; bits += ESD_MMDC_CTL_GET_WIDTH(ctl); bits += ESD_MMDC_CTL_GET_CS1(ctl); + + /* The MX6 can do only 3840 MiB of DRAM */ + if (bits == 32) + return 0xf000; + return 1 bits; } #endif -- 2.0.1 Acked-by: Tim Harvey thar...@gateworks.com Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/18] arm: mx6: add support for Compulab cm-fx6 CoM
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nik...@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
snip
+
+static void spl_mx6s_dram_init(enum ddr_config dram_config, int reset)
+{
+ struct mx6_mmdc_calibration calib;
+ struct mx6_ddr_sysinfo sysinfo;
+ struct mx6_ddr3_cfg ddr3_cfg;
+
+ if (reset)
+ ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)-mdmisc = 2;
+
+ calib.p0_mpwldectrl0= 0x005B0061;
+ calib.p0_mpwldectrl1= 0x004F0055;
+ calib.p0_mpdgctrl0 = 0x0314030C;
+ calib.p0_mpdgctrl1 = 0x025C0268;
+ calib.p0_mprddlctl = 0x42464646;
+ calib.p0_mpwrdlctl = 0x36322C34;
+ ddr3_cfg.mem_speed = 800;
+ ddr3_cfg.density= 4;
+ ddr3_cfg.rowaddr= 14;
+ ddr3_cfg.coladdr= 10;
+ ddr3_cfg.pagesz = 2;
+ ddr3_cfg.trcd = 1800;
+ ddr3_cfg.trcmin = 5200;
+ ddr3_cfg.trasmin= 3600;
+ ddr3_cfg.SRT= 0;
+ sysinfo.cs1_mirror = 1;
+ sysinfo.cs_density = 16;
+ sysinfo.bi_on = 1;
+ sysinfo.rtt_nom = 1;
+ sysinfo.rtt_wr = 0;
+ sysinfo.ralat = 5;
+ sysinfo.walat = 1;
+ sysinfo.mif3_mode = 3;
+ sysinfo.rst_to_cke = 0x23;
+ sysinfo.sde_to_rst = 0x10;
+ switch (dram_config) {
+ case DDR_16BIT_256MB:
+ sysinfo.dsize = 0;
+ sysinfo.ncs = 1;
+ break;
+ case DDR_32BIT_512MB:
+ sysinfo.dsize = 1;
+ sysinfo.ncs = 1;
+ break;
+ case DDR_32BIT_1GB:
+ sysinfo.dsize = 1;
+ sysinfo.ncs = 2;
+ break;
+ default:
+ puts(Tried to setup invalid DDR configuration\n);
+ hang();
+ }
+
+ mx6_dram_cfg(sysinfo, calib, ddr3_cfg);
+ udelay(100);
+}
Nikita,
I'm curious why you add an extra udelay(100) here? There is an
mdelay(1) before the return of mx6_dram_cfg() to wait for auto-ZQ
calibration to complete (I never found a way to determine when it was
complete via registers).
Regards,
Tim
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Re: [U-Boot] [PATCH 08/18] arm: mx6: ddr: cleanup
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nik...@compulab.co.il wrote:
No functional changes.
Cc: Stefano Babic sba...@denx.de
Cc: Tim Harvey thar...@gateworks.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
arch/arm/cpu/armv7/mx6/ddr.c | 272
+--
1 file changed, 134 insertions(+), 138 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 0434211..af91314 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width,
*/
#define MR(val, ba, cmd, cs1) \
((val 16) | (1 15) | (cmd 4) | (cs1 3) | ba)
-void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
- const struct mx6_mmdc_calibration *c,
- const struct mx6_ddr3_cfg *m)
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+ const struct mx6_mmdc_calibration *calib,
+ const struct mx6_ddr3_cfg *ddr3_cfg)
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
- u32 reg;
+ u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
- u16 CS0_END;
+ u16 cs0_end;
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
int clkper; /* clock period in picoseconds */
int clock; /* clock freq in mHz */
@@ -214,13 +214,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
clock = 400;
tcwl = 3;
}
- clkper = (1000*1000)/clock; /* ps */
+ clkper = (1000 * 1000) / clock; /* pico seconds */
todtlon = tcwl;
taxpd = tcwl;
tanpd = tcwl;
- tcwl = tcwl;
- switch (m-density) {
+ switch (ddr3_cfg-density) {
case 1: /* 1Gb per chip */
trfc = DIV_ROUND_UP(11, clkper) - 1;
txs = DIV_ROUND_UP(12, clkper) - 1;
@@ -239,80 +238,84 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
break;
default:
/* invalid density */
- printf(invalid chip density\n);
+ puts(invalid chip density\n);
hang();
break;
}
txpr = txs;
- switch (m-mem_speed) {
+ switch (ddr3_cfg-mem_speed) {
case 800:
- txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
- if (m-pagesz == 1) {
+ txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+ if (ddr3_cfg-pagesz == 1) {
tfaw = DIV_ROUND_UP(4, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 1), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 1), clkper) -
1;
} else {
tfaw = DIV_ROUND_UP(5, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 1), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 1), clkper) -
1;
}
break;
case 1066:
- txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
- if (m-pagesz == 1) {
+ txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+ if (ddr3_cfg-pagesz == 1) {
tfaw = DIV_ROUND_UP(37500, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) -
1;
} else {
tfaw = DIV_ROUND_UP(5, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 1), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 1), clkper) -
1;
}
break;
case 1333:
- txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
- if (m-pagesz == 1) {
+ txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+ if (ddr3_cfg-pagesz == 1) {
tfaw = DIV_ROUND_UP(3, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1
Re: [U-Boot] [PATCH 09/18] arm: mx6: ddr: do not write into reserved bit
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nik...@compulab.co.il wrote: Bit 16 in mapsr register is in a reserved field. Don't write to it. Cc: Stefano Babic sba...@denx.de Cc: Tim Harvey thar...@gateworks.com Signed-off-by: Nikita Kiryanov nik...@compulab.co.il --- arch/arm/cpu/armv7/mx6/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index af91314..70ce38f 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -466,7 +466,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, 1 6 | /* BOTH_CS_PD */ (tcksrx 0x7) 3 | (tcksre 0x7); - mmdc0-mapsr = 0x00011006; /* ADOPT power down enabled */ + mmdc0-mapsr = 0x1006; /* ADOPT power down enabled */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ val = 0xa1390003; -- 1.9.1 Nikita, This makes sense per the reference manual, but does not agree with the i.Mx6DQSDL DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917). I'm curious if you found any other explanation of this or anything else that makes you feel the spreadsheet is in error (vs the RM's). I've asked our Freescale FAE to clarify. Regards, Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/18] arm: mx6: ddr: configure MMDC for slow_pd
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nik...@compulab.co.il wrote: According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd, and the DRAM for slow pd. Nikita, I'm inclined to agree with you. A glance at some of the existing non-spl board config's show this same discrepancy which probably comes form an error in the IMX DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917). I would at least add to the description the fact that the precharge pd is MR0 bit12 for DRAM and the current value of 0 indicates 'Slow exit (DLL off)'. I've asked our Freescale FAE for clarification to see if the spreadsheet is in error. Regards, Tim Configure MMDC for slow pd. Cc: Stefano Babic sba...@denx.de Cc: Tim Harvey thar...@gateworks.com Signed-off-by: Nikita Kiryanov nik...@compulab.co.il --- arch/arm/cpu/armv7/mx6/ddr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 70ce38f..c0fb749 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -463,6 +463,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0-mdpdc = (tcke 0x7) 16 | 5 12 | /* PWDT_1: 256 cycles */ 5 8 | /* PWDT_0: 256 cycles */ + 1 7 | /* SLOW_PD */ 1 6 | /* BOTH_CS_PD */ (tcksrx 0x7) 3 | (tcksre 0x7); -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/18] arm: mx6: add support for Compulab cm-fx6 CoM
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nik...@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
snip
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
new file mode 100644
index 000..285af33
--- /dev/null
+++ b/include/configs/cm_fx6.h
@@ -0,0 +1,227 @@
+/*
+ * Config file for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov nik...@compulab.co.il
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_FX6_H
+#define __CONFIG_CM_FX6_H
+
+#include asm/arch/imx-regs.h
+#include config_distro_defaults.h
+
+#define CONFIG_SYS_L2CACHE_OFF
+#include mx6_common.h
+
+/* Machine config */
+#define CONFIG_MX6
+#define CONFIG_MX6QDL
+#define CONFIG_CM_FX6
+#define CONFIG_SYS_LITTLE_ENDIAN
+#define CONFIG_MACH_TYPE 4273
+#define CONFIG_SYS_HZ 1000
+
+/* Display information on boot */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIMESTAMP
+
+/* CMD */
+#include config_cmd_default.h
+#define CONFIG_CMD_GREPENV
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+
+/* RAM */
+#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_MEMTEST_START 0x1000
+#define CONFIG_SYS_MEMTEST_END 0x1001
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Serial console */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART4_BASE
+#define CONFIG_BAUDRATE115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/* Shell */
+#define CONFIG_SYS_PROMPT CM-FX6 #
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 *
1024)
+
+/* SPI flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED2500
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MODECONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE(8 * 1024)
+#define CONFIG_ENV_OFFSET (768 * 1024)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ kernel=uImage-cm-fx6\0 \
+ autoload=no\0 \
+ loadaddr=0x1080\0 \
+ fdtaddr=0x1100\0 \
+ console=ttymxc3,115200\0 \
+ ethprime=FEC0\0 \
+ bootscr=boot.scr\0 \
+ bootm_low=1800\0 \
+ video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0 \
+ video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0 \
+ fdtfile=cm-fx6.dtb\0 \
+ doboot=bootm ${loadaddr}\0 \
+ loadfdt=false\0 \
+ setboottypez=setenv kernel zImage-cm-fx6; \
+ setenv doboot bootz ${loadaddr} - ${fdtaddr}; \
+ setenv loadfdt true;\0 \
+ setboottypem=setenv kernel uImage-cm-fx6; \
+ setenv doboot bootm ${loadaddr}; \
+ setenv loadfdt false;\0\
+ run_eboot=echo Starting EBOOT ...; \
+ mmc dev ${mmcdev} \
+ mmc rescan mmc read 10042000 a 400 go 10042000\0 \
+ mmcdev=2\0 \
+ mmcroot=/dev/mmcblk0p2 rw rootwait\0 \
+ loadmmcbootscript=fatload mmc ${mmcdev} ${loadaddr} ${bootscr}\0 \
+ mmcbootscript=echo Running bootscript from mmc ...; \
+ source ${loadaddr}\0 \
+ mmcargs=setenv bootargs
Re: [U-Boot] [PATCH 09/18] arm: mx6: ddr: do not write into reserved bit
On Mon, Aug 4, 2014 at 5:49 AM, Nikita Kiryanov nik...@compulab.co.il wrote: Hi Tim, On 04/08/14 08:43, Tim Harvey wrote: On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nik...@compulab.co.il wrote: Bit 16 in mapsr register is in a reserved field. Don't write to it. Cc: Stefano Babic sba...@denx.de Cc: Tim Harvey thar...@gateworks.com Signed-off-by: Nikita Kiryanov nik...@compulab.co.il --- arch/arm/cpu/armv7/mx6/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index af91314..70ce38f 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -466,7 +466,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, 1 6 | /* BOTH_CS_PD */ (tcksrx 0x7) 3 | (tcksre 0x7); - mmdc0-mapsr = 0x00011006; /* ADOPT power down enabled */ + mmdc0-mapsr = 0x1006; /* ADOPT power down enabled */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ val = 0xa1390003; -- 1.9.1 Nikita, This makes sense per the reference manual, but does not agree with the i.Mx6DQSDL DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917). I'm curious if you found any other explanation of this or anything else that makes you feel the spreadsheet is in error (vs the RM's). Nothing specific, I just don't like to use undocumented features. It's probably benign, but still... I've asked our Freescale FAE to clarify. Looking forward to that... Regards, Nikita Kiryanov Nikita, Freescale confirmed its an error in their spreadsheet (https://community.freescale.com/docs/DOC-94917#comment-12921), so: Acked-by: Tim Harvey thar...@gateworks.com Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] ARM: mx6: Enable Thumb build for SPL
On Sun, Aug 3, 2014 at 4:47 PM, Marek Vasut ma...@denx.de wrote: Building the SPL in Thumb mode saves roughly 30% in size of the resulting SPL binary. As the size of SPL it limited on the MX6, this helps a lot. Signed-off-by: Marek Vasut ma...@denx.de --- include/configs/imx6_spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 6fdc438..970460d 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -24,6 +24,7 @@ *and some padding thus 'our' max size is really 0x00908000 - 0x00918000 *or 64KB */ +#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SPL_LDSCRIPT arch/arm/cpu/armv7/omap-common/u-boot-spl.lds #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE(64 * 1024) -- 2.0.1 Marek, Thanks for pointing this out - this indeed is a great space savings where it matters. Acked-by: Tim Harvey thar...@gateworks.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/11] imx: ventana: add iomux for PCISKT_WDIS# gpio
The PCISKT_WDIS# gpio allows for asserting WDIS# going to the various PCIe
sockets on the Ventana board.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index d57ede4..1c24e4b 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -581,6 +581,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
@@ -603,6 +605,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
@@ -625,6 +629,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
@@ -650,6 +656,8 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* VID_EN */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
};
/*
@@ -680,6 +688,7 @@ struct ventana {
int dioi2c_en;
int pcie_sson;
int usb_sel;
+ int wdis;
};
struct ventana gpio_cfg[] = {
@@ -765,6 +774,7 @@ struct ventana gpio_cfg[] = {
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 2),
.vidin_en = IMX_GPIO_NR(5, 20),
+ .wdis = IMX_GPIO_NR(7, 12),
},
/* GW52xx */
@@ -808,6 +818,7 @@ struct ventana gpio_cfg[] = {
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
.usb_sel = IMX_GPIO_NR(1, 2),
+ .wdis = IMX_GPIO_NR(7, 12),
},
/* GW53xx */
@@ -850,6 +861,7 @@ struct ventana gpio_cfg[] = {
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
+ .wdis = IMX_GPIO_NR(7, 12),
},
/* GW54xx */
@@ -894,6 +906,7 @@ struct ventana gpio_cfg[] = {
.vidin_en = IMX_GPIO_NR(3, 31),
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
+ .wdis = IMX_GPIO_NR(5, 17),
},
};
@@ -1019,6 +1032,10 @@ static void setup_board_gpio(int board)
if (gpio_cfg[board].usb_sel)
gpio_direction_output(gpio_cfg[board].usb_sel, 0);
+ /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
+ if (gpio_cfg[board].wdis)
+ gpio_direction_output(gpio_cfg[board].wdis, 1);
+
/*
* Configure DIO pinmux/padctl registers
* see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
--
1.8.3.2
___
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[U-Boot] [PATCH 09/11] imx: ventana: enable SION bit on gpio outputs
Enable the SION bit on gpio outputs that we wish to be able to read the
value of.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 133 +---
1 file changed, 70 insertions(+), 63 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 98ee9df..d57ede4 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -74,6 +74,13 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
+
+
/*
* EEPROM board info struct populated by read_eeprom so that we only have to
* read it once.
@@ -183,7 +190,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* CD */
- IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
};
/* ENET */
@@ -207,7 +214,7 @@ iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* PHY nRST */
- IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
};
/* NAND */
@@ -277,10 +284,10 @@ static void setup_iomux_uart(void)
#ifdef CONFIG_USB_EHCI_MX6
iomux_v3_cfg_t const usb_pads[] = {
- IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
+ IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
/* OTG PWR */
- IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
};
int board_ehci_hcd_init(int port)
@@ -292,15 +299,13 @@ int board_ehci_hcd_init(int port)
/* Reset USB HUB (present on GW54xx/GW53xx) */
switch (info-model[3]) {
case '3': /* GW53xx */
- SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(1, 9), 1);
break;
case '4': /* GW54xx */
- SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(1, 16), 1);
@@ -422,7 +427,7 @@ static void enable_lvds(struct display_info_t const *dev)
writel(reg, iomux-gpr[2]);
/* Enable Backlight */
- SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
}
@@ -519,7 +524,7 @@ static void setup_display(void)
writel(reg, iomux-gpr[3]);
/* Backlight CABEN on LVDS connector */
- SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
@@ -531,120 +536,120 @@ static void setup_display(void)
/* common to add baseboards */
static iomux_v3_cfg_t const gw_gpio_pads[] = {
/* MSATA_EN */
- IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* RS232_EN# */
- IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
};
/* prototype */
static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
/* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* RS485_EN */
- IOMUX_PADS
[U-Boot] [PATCH 05/11] imx: ventana: add econfig command
The Gateworks Ventana EEPROM contains a set of configuration bits that
affect the removal of device-tree nodes that support peripherals that do not
exist on sub-loaded boards. This patch adds:
- a structure to define a config bit name, dt node alias, bit position
- an array of supported configuration items
- an econfig command to get/set/list configuration bits
- use of the array when adjusting the FDT prior to boot
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/eeprom.c | 168 +++-
board/gateworks/gw_ventana/gw_ventana.c | 100 +++--
board/gateworks/gw_ventana/ventana_eeprom.h | 11 ++
include/configs/gw_ventana.h| 5 +-
4 files changed, 198 insertions(+), 86 deletions(-)
diff --git a/board/gateworks/gw_ventana/eeprom.c
b/board/gateworks/gw_ventana/eeprom.c
index e90186e..3edc915 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -6,7 +6,10 @@
*/
#include common.h
+#include errno.h
#include i2c.h
+#include malloc.h
+#include asm/bitops.h
#include gsc.h
#include ventana_eeprom.h
@@ -38,14 +41,12 @@ read_eeprom(int bus, struct ventana_board_info *info)
/* read eeprom config section */
if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
puts(EEPROM: Failed to read EEPROM\n);
- info-model[0] = 0;
return GW_UNKNOWN;
}
/* sanity checks */
if (info-model[0] != 'G' || info-model[1] != 'W') {
puts(EEPROM: Invalid Model in EEPROM\n);
- info-model[0] = 0;
return GW_UNKNOWN;
}
@@ -55,7 +56,6 @@ read_eeprom(int bus, struct ventana_board_info *info)
if ((info-chksum[0] != chksum8) ||
(info-chksum[1] != (chksum0xff))) {
puts(EEPROM: Failed EEPROM checksum\n);
- info-model[0] = 0;
return GW_UNKNOWN;
}
@@ -87,3 +87,165 @@ read_eeprom(int bus, struct ventana_board_info *info)
}
return type;
}
+
+/* list of config bits that the bootloader will remove from dtb if not set */
+struct ventana_eeprom_config econfig[] = {
+ { eth0, ethernet0, EECONFIG_ETH0 },
+ { eth1, ethernet1, EECONFIG_ETH1 },
+ { sata, ahci0, EECONFIG_SATA },
+ { pcie, NULL, EECONFIG_PCIE},
+ { lvds0, NULL, EECONFIG_LVDS0 },
+ { lvds1, NULL, EECONFIG_LVDS1 },
+ { usb0, NULL, EECONFIG_USB0 },
+ { usb1, NULL, EECONFIG_USB1 },
+ { mmc0, NULL, EECONFIG_SD0 },
+ { mmc1, NULL, EECONFIG_SD1 },
+ { mmc2, NULL, EECONFIG_SD2 },
+ { mmc3, NULL, EECONFIG_SD3 },
+ { uart0, NULL, EECONFIG_UART0 },
+ { uart1, NULL, EECONFIG_UART1 },
+ { uart2, NULL, EECONFIG_UART2 },
+ { uart3, NULL, EECONFIG_UART3 },
+ { uart4, NULL, EECONFIG_UART4 },
+ { ipu0, NULL, EECONFIG_IPU0 },
+ { ipu1, NULL, EECONFIG_IPU1 },
+ { can0, NULL, EECONFIG_FLEXCAN },
+ { i2c0, NULL, EECONFIG_I2C0 },
+ { i2c1, NULL, EECONFIG_I2C1 },
+ { i2c2, NULL, EECONFIG_I2C2 },
+ { vpu, NULL, EECONFIG_VPU },
+ { csi0, NULL, EECONFIG_CSI0 },
+ { csi1, NULL, EECONFIG_CSI1 },
+ { spi0, NULL, EECONFIG_ESPCI0 },
+ { spi1, NULL, EECONFIG_ESPCI1 },
+ { spi2, NULL, EECONFIG_ESPCI2 },
+ { spi3, NULL, EECONFIG_ESPCI3 },
+ { spi4, NULL, EECONFIG_ESPCI4 },
+ { spi5, NULL, EECONFIG_ESPCI5 },
+ { gps, pps, EECONFIG_GPS },
+ { hdmi_in, NULL, EECONFIG_HDMI_IN },
+ { hdmi_out, NULL, EECONFIG_HDMI_OUT },
+ { cvbs_in, NULL, EECONFIG_VID_IN },
+ { cvbs_out, NULL, EECONFIG_VID_OUT },
+ { nand, NULL, EECONFIG_NAND },
+ { /* Sentinel */ }
+};
+
+#ifdef CONFIG_CMD_EECONFIG
+static struct ventana_eeprom_config *get_config(const char *name)
+{
+ struct ventana_eeprom_config *cfg = econfig;
+
+ while (cfg-name) {
+ if (0 == strcmp(name, cfg-name))
+ return cfg;
+ cfg++;
+ }
+ return NULL;
+}
+
+static u8 econfig_bytes[sizeof(ventana_info.config)];
+static int econfig_init = -1;
+
+int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct ventana_eeprom_config *cfg;
+ struct ventana_board_info *info = ventana_info;
+ int i;
+
+ if (argc 2)
+ return CMD_RET_USAGE;
+
+ /* initialize */
+ if (econfig_init != 1) {
+ memcpy(econfig_bytes, info-config, sizeof(econfig_bytes));
+ econfig_init = 1;
+ }
+
+ /* list configs */
+ if ((strncmp(argv[1], list, 4) == 0)) {
+ cfg = econfig;
+ while (cfg-name) {
+ printf(%s: %d\n, cfg-name,
+ test_bit(cfg-bit, econfig_bytes) ? 1 : 0);
+ cfg
[U-Boot] [PATCH 03/11] imx: ventana: remove caam disable per eeprom bit
During manufacturing this bit is not getting enabled when it should be, so
we will ignore it.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index de2336e..b35fe5a 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -1388,7 +1388,7 @@ const char *fdt_aliases[] = {
vpu,
csi0,
csi1,
- caam,
+ NULL,
NULL,
NULL,
NULL,
--
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[U-Boot] [PATCH 06/11] imx: ventana: add video enable gpio pinmux for GW54xx
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 9857a05..07d5e2d 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -643,6 +643,8 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* VID_EN */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
/*
--
1.8.3.2
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[U-Boot] [PATCH 04/11] imx: ventana: add appropriate delay following GSC i2c write
The Gateworks System Controller EEPROM config is flash based. Add a delay following writes to avoid errors on back-to-back writes. Signed-off-by: Tim Harvey thar...@gateworks.com --- board/gateworks/gw_ventana/gsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index 37966ab..1cf38d4 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -57,7 +57,7 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) break; mdelay(10); } - mdelay(1); + mdelay(100); return ret; } -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/11] imx: ventana: leave PCI reset de-asserted if PCI enabled
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 1c24e4b..70b90d8 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -991,12 +991,10 @@ static void setup_board_gpio(int board)
gpio_direction_output(GP_MSATA_SEL, 0);
}
- /*
-* assert PCI_RST# (released by OS when clock is valid)
-* TODO: figure out why leaving this de-asserted from PCI scan on boot
-* causes linux pcie driver to hang during enumeration
-*/
+#if !defined(CONFIG_CMD_PCI)
+ /* assert PCI_RST# (released by OS when clock is valid) */
gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
+#endif
/* turn off (active-high) user LED's */
for (i = 0; i 4; i++) {
--
1.8.3.2
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[U-Boot] [PATCH 02/11] imx: ventana: added cputype env var
There are many similarities between the IMX6QUAD/IMX6DUAL and there are many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env variable that tells you which type you have. Signed-off-by: Tim Harvey thar...@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index a8fcb5d..de2336e 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1264,6 +1264,7 @@ int misc_init_r(void) else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) cputype = imx6dl; + setenv(soctype, cputype); if (8 (ventana_info.nand_flash_size-1) = 2048) setenv(flash_layout, large); else -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/11] imx: ventana: add missing crlf to print
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 07d5e2d..54e582b 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -1339,7 +1339,7 @@ int misc_init_r(void)
}
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, reg, 1)) {
if (reg (1 GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
- puts(GSC boot watchdog timeout detected);
+ puts(GSC boot watchdog timeout detected\n);
reg = ~(1 GSC_SC_IRQ_WATCHDOG); /* clear flag */
gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, reg, 1);
}
--
1.8.3.2
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[U-Boot] [PATCH 08/11] imx: ventana: configure i2c_dis# pin properly for gw53xx
The i2c_dis# pinmux/padconf was missing for the GW53xx (this feature was
added to the GW53xx on revB PCB's). Additionally, remove the duplicate
config for GW54xx.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 54e582b..98ee9df 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -609,6 +609,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* DIOI2C_DIS# */
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
@@ -637,8 +639,6 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* DIOI2C_DIS# */
- IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCICK_SSON */
IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCI_RST# */
--
1.8.3.2
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[U-Boot] [PATCH 01/11] imx: ventana: set dynamic env var for flash layout
NAND devices have differing layouts with respect to page size and pages per block. These parameters affect the parameters that need to be passed to mkfs.ubifs and ubinize used to create UBI images. The various NAND chips supported by Gateworks Ventana fall into two different layouts which we refer to as 'normal' and 'large'. This layout is useful when referencing ubi files to download and flash so we create a dynamic env variable for it. Signed-off-by: Tim Harvey thar...@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 4 1 file changed, 4 insertions(+) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 9d2651f..a8fcb5d 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1264,6 +1264,10 @@ int misc_init_r(void) else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) cputype = imx6dl; + if (8 (ventana_info.nand_flash_size-1) = 2048) + setenv(flash_layout, large); + else + setenv(flash_layout, normal); memset(str, 0, sizeof(str)); for (i = 0; i (sizeof(str)-1) info-model[i]; i++) str[i] = tolower(info-model[i]); -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 00/11] imx: ventana: misc patches
This is a series of patches in my queue for the Gateworks Ventana family of boards. Tim Harvey (11): imx: ventana: set dynamic env var for flash layout imx: ventana: added cputype env var imx: ventana: remove caam disable per eeprom bit imx: ventana: add appropriate delay following GSC i2c write imx: ventana: add econfig command imx: ventana: add video enable gpio pinmux for GW54xx imx: ventana: add missing crlf to print imx: ventana: configure i2c_dis# pin properly for gw53xx imx: ventana: enable SION bit on gpio outputs imx: ventana: add iomux for PCISKT_WDIS# gpio imx: ventana: leave PCI reset de-asserted if PCI enabled board/gateworks/gw_ventana/eeprom.c | 168 - board/gateworks/gw_ventana/gsc.c| 2 +- board/gateworks/gw_ventana/gw_ventana.c | 267 board/gateworks/gw_ventana/ventana_eeprom.h | 11 ++ include/configs/gw_ventana.h| 5 +- 5 files changed, 297 insertions(+), 156 deletions(-) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] pci: add support for board_pci_fixup_dev function
Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey thar...@gateworks.com --- drivers/pci/pci.c | 4 include/pci.h | 7 +++ 2 files changed, 11 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ed113bf..e269468 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -648,6 +648,10 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, device); pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, class); +#ifdef CONFIG_PCI_FIXUP_DEV + board_pci_fixup_dev(hose, dev, vendor, device, class); +#endif + #ifdef CONFIG_PCI_SCAN_SHOW indent++; diff --git a/include/pci.h b/include/pci.h index 461f17c..2ff7365 100644 --- a/include/pci.h +++ b/include/pci.h @@ -659,6 +659,13 @@ extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap); +#ifdef CONFIG_PCI_FIXUP_DEV +extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, + unsigned short vendor, + unsigned short device, + unsigned short class); +#endif + const char * pci_class_str(u8 class); int pci_last_busno(void); -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] imx: ventana: Add pci fixup for PLX switch
Many of the Gateworks Ventana boards have a PLX PCIe switch where GPIO on the switch is used as the PERST# of the downstream ports. In the Linux kernel there is a PCI fixup that asserts these properly when the upstream port is enumerated. The first patch in this serial adds a board_pci_fixup_dev function define to allow hooking similarly to the kernel pci fixup functionality. The second patch uses the board_pci_fixup_dev function to perform the GPIO configuration on the switch for the downstream ports. Tim Harvey (2): pci: add support for board_pci_fixup_dev function imx: ventana: add pci fixup for PLX PEX860x switch GPIO board/gateworks/gw_ventana/gw_ventana.c | 30 ++ drivers/pci/pci.c | 4 include/configs/gw_ventana.h| 1 + include/pci.h | 7 +++ 4 files changed, 42 insertions(+) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] imx: ventana: add pci fixup for PLX PEX860x switch GPIO
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion.
These boards use GPIO on the PLX device as PERST# for the downstream ports
thus we assert this when the PLX is enumerated.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 30 ++
include/configs/gw_ventana.h| 1 +
2 files changed, 31 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 70b90d8..186cd38 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -31,6 +31,7 @@
#include mmc.h
#include mtd_node.h
#include netdev.h
+#include pci.h
#include power/pmic.h
#include power/ltc3676_pmic.h
#include power/pfuze100_pmic.h
@@ -1092,6 +1093,35 @@ int imx6_pcie_toggle_reset(void)
}
return 0;
}
+
+/*
+ * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
+ * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
+ * properly and assert reset for 100ms.
+ */
+void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
+unsigned short vendor, unsigned short device,
+unsigned short class)
+{
+ u32 dw;
+
+ debug(%s: %02d:%02d.%02d: %04x:%04x\n, __func__,
+ PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
+ if (vendor == PCI_VENDOR_ID_PLX
+ (device 0xfff0) == 0x8600
+ PCI_DEV(dev) == 0 PCI_FUNC(dev) == 0) {
+ debug(configuring PLX 860X downstream PERST#\n);
+ pci_hose_read_config_dword(hose, dev, 0x62c, dw);
+ dw |= 0xaaa8; /* GPIO1-7 outputs */
+ pci_hose_write_config_dword(hose, dev, 0x62c, dw);
+
+ pci_hose_read_config_dword(hose, dev, 0x644, dw);
+ dw |= 0xfe; /* GPIO1-7 output high */
+ pci_hose_write_config_dword(hose, dev, 0x644, dw);
+
+ mdelay(100);
+ }
+}
#endif /* CONFIG_CMD_PCI */
#ifdef CONFIG_SERIAL_TAG
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index b991b09..0e5c200 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -141,6 +141,7 @@
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCI_FIXUP_DEV
#define CONFIG_PCIE_IMX
#endif
--
1.8.3.2
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[U-Boot] [PATCH] pci: mx6: fix occasional link failures
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey thar...@gateworks.com --- drivers/pci/pcie_imx.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c48737e..a3982c4 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -509,10 +509,6 @@ static int imx6_pcie_deassert_core_reset(void) imx6_pcie_toggle_power(); - /* Enable PCIe */ - clrbits_le32(iomuxc_regs-gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); - setbits_le32(iomuxc_regs-gpr[1], IOMUXC_GPR1_REF_SSP_EN); - enable_pcie_clock(); /* @@ -521,6 +517,10 @@ static int imx6_pcie_deassert_core_reset(void) */ mdelay(50); + /* Enable PCIe */ + clrbits_le32(iomuxc_regs-gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(iomuxc_regs-gpr[1], IOMUXC_GPR1_REF_SSP_EN); + imx6_pcie_toggle_reset(); return 0; -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/18] arm: mx6: add support for Compulab cm-fx6 CoM
On Wed, Aug 6, 2014 at 10:29 AM, Nikita Kiryanov nik...@compulab.co.il wrote:
On 04/08/14 16:36, Nikita Kiryanov wrote:
On 04/08/14 07:45, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov
nik...@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
snip
+
+static void spl_mx6s_dram_init(enum ddr_config dram_config, int reset)
+{
+ struct mx6_mmdc_calibration calib;
+ struct mx6_ddr_sysinfo sysinfo;
+ struct mx6_ddr3_cfg ddr3_cfg;
+
+ if (reset)
+ ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)-mdmisc = 2;
+
+ calib.p0_mpwldectrl0= 0x005B0061;
+ calib.p0_mpwldectrl1= 0x004F0055;
+ calib.p0_mpdgctrl0 = 0x0314030C;
+ calib.p0_mpdgctrl1 = 0x025C0268;
+ calib.p0_mprddlctl = 0x42464646;
+ calib.p0_mpwrdlctl = 0x36322C34;
+ ddr3_cfg.mem_speed = 800;
+ ddr3_cfg.density= 4;
+ ddr3_cfg.rowaddr= 14;
+ ddr3_cfg.coladdr= 10;
+ ddr3_cfg.pagesz = 2;
+ ddr3_cfg.trcd = 1800;
+ ddr3_cfg.trcmin = 5200;
+ ddr3_cfg.trasmin= 3600;
+ ddr3_cfg.SRT= 0;
+ sysinfo.cs1_mirror = 1;
+ sysinfo.cs_density = 16;
+ sysinfo.bi_on = 1;
+ sysinfo.rtt_nom = 1;
+ sysinfo.rtt_wr = 0;
+ sysinfo.ralat = 5;
+ sysinfo.walat = 1;
+ sysinfo.mif3_mode = 3;
+ sysinfo.rst_to_cke = 0x23;
+ sysinfo.sde_to_rst = 0x10;
+ switch (dram_config) {
+ case DDR_16BIT_256MB:
+ sysinfo.dsize = 0;
+ sysinfo.ncs = 1;
+ break;
+ case DDR_32BIT_512MB:
+ sysinfo.dsize = 1;
+ sysinfo.ncs = 1;
+ break;
+ case DDR_32BIT_1GB:
+ sysinfo.dsize = 1;
+ sysinfo.ncs = 2;
+ break;
+ default:
+ puts(Tried to setup invalid DDR configuration\n);
+ hang();
+ }
+
+ mx6_dram_cfg(sysinfo, calib, ddr3_cfg);
+ udelay(100);
+}
Nikita,
I'm curious why you add an extra udelay(100) here? There is an
mdelay(1) before the return of mx6_dram_cfg() to wait for auto-ZQ
calibration to complete (I never found a way to determine when it was
complete via registers).
Yes you're right. This udelay can probably be removed (unless I catch
the board misbehaving during multiple resets).
Caught the DRAM config failing during multiple resets when udelay(100)
is removed, so I guess they stay..
Nikita,
What exactly was failing? Was the subsequent to get_ram_size()
failing? If the extra delay is really needed we should add it to the
mx6_dram_cfg() function. The issue I ran into before I added the
mdelay(1) there to wait for auto-ZQ calib to complete was that SDRAM
operations immediately following the call to mx6_dram_cfg() would be
un-reliable, specifically a memset to 0 would fail to clear memory
where GD was which caused some interesting failures down the line.
Maybe I'll open up an issue with Freescale and ask them if there is a
way to know when auto-ZQ calibration is complete because it isn't
clear to me how to do that. The 1ms delay was because the 0 value we
set to MPZQHWCTRL ZQ_HW_PER configures it for a 1ms ZQ calibration
cycle maybe we simply need a little more headroom.
Tim
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[U-Boot] [PATCH 0/2] e1000: add i210 support
Two patches to add Intel i210 support to the e1000 driver. Marek Vasut (2): e1000: Implement dcache support e1000: add i210 support drivers/net/e1000.c | 266 ++-- drivers/net/e1000.h | 12 +++ include/pci_ids.h | 7 ++ 3 files changed, 236 insertions(+), 49 deletions(-) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] e1000: Implement dcache support
From: Marek Vasut ma...@denx.de
Implement proper support for cache flushing and invalidation into the
Intel e1000 NIC driver.
Signed-off-by: Marek Vasut ma...@denx.de
Acked-by: Tim Harvey thar...@gateworks.com
---
drivers/net/e1000.c | 71 -
1 file changed, 49 insertions(+), 22 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 9d9b259..0441a4f 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -41,12 +41,12 @@ tested on both gig copper and gig fiber boards
/* NIC specific static variables go here */
-static char tx_pool[128 + 16];
-static char rx_pool[128 + 16];
-static char packet[2096];
+/* Intel i210 needs the DMA descriptor rings aligned to 128b */
+#define E1000_BUFFER_ALIGN 128
-static struct e1000_tx_desc *tx_base;
-static struct e1000_rx_desc *rx_base;
+DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
+DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
+DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
static int tx_tail;
static int rx_tail, rx_last;
@@ -4803,12 +4803,25 @@ void
fill_rx(struct e1000_hw *hw)
{
struct e1000_rx_desc *rd;
+ uint32_t flush_start, flush_end;
rx_last = rx_tail;
rd = rx_base + rx_tail;
rx_tail = (rx_tail + 1) % 8;
memset(rd, 0, 16);
- rd-buffer_addr = cpu_to_le64((u32) packet);
+ rd-buffer_addr = cpu_to_le64((u32)packet);
+
+ /*
+* Make sure there are no stale data in WB over this area, which
+* might get written into the memory while the e1000 also writes
+* into the same memory area.
+*/
+ invalidate_dcache_range((u32)packet, (u32)packet + 4096);
+ /* Dump the DMA descriptor into RAM. */
+ flush_start = ((u32)rd) ~(ARCH_DMA_MINALIGN - 1);
+ flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
+ flush_dcache_range(flush_start, flush_end);
+
E1000_WRITE_REG(hw, RDT, rx_tail);
}
@@ -4822,17 +4835,10 @@ fill_rx(struct e1000_hw *hw)
static void
e1000_configure_tx(struct e1000_hw *hw)
{
- unsigned long ptr;
unsigned long tctl;
unsigned long tipg, tarc;
uint32_t ipgr1, ipgr2;
- ptr = (u32) tx_pool;
- if (ptr 0xf)
- ptr = (ptr + 0x10) (~0xf);
-
- tx_base = (typeof(tx_base)) ptr;
-
E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
E1000_WRITE_REG(hw, TDBAH, 0);
@@ -4941,7 +4947,6 @@ e1000_setup_rctl(struct e1000_hw *hw)
static void
e1000_configure_rx(struct e1000_hw *hw)
{
- unsigned long ptr;
unsigned long rctl, ctrl_ext;
rx_tail = 0;
/* make sure receives are disabled while setting up the descriptors */
@@ -4963,10 +4968,6 @@ e1000_configure_rx(struct e1000_hw *hw)
E1000_WRITE_FLUSH(hw);
}
/* Setup the Base and Length of the Rx Descriptor Ring */
- ptr = (u32) rx_pool;
- if (ptr 0xf)
- ptr = (ptr + 0x10) (~0xf);
- rx_base = (typeof(rx_base)) ptr;
E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
E1000_WRITE_REG(hw, RDBAH, 0);
@@ -4989,12 +4990,25 @@ e1000_poll(struct eth_device *nic)
{
struct e1000_hw *hw = nic-priv;
struct e1000_rx_desc *rd;
+ uint32_t inval_start, inval_end;
+ uint32_t len;
+
/* return true if there's an ethernet packet ready to read */
rd = rx_base + rx_last;
+
+ /* Re-load the descriptor from RAM. */
+ inval_start = ((u32)rd) ~(ARCH_DMA_MINALIGN - 1);
+ inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(inval_start, inval_end);
+
if (!(le32_to_cpu(rd-status)) E1000_RXD_STAT_DD)
return 0;
/*DEBUGOUT(recv: packet len=%d \n, rd-length); */
- NetReceive((uchar *)packet, le32_to_cpu(rd-length));
+ /* Packet received, make sure the data are re-loaded from RAM. */
+ len = le32_to_cpu(rd-length);
+ invalidate_dcache_range((u32)packet,
+ (u32)packet + roundup(len, ARCH_DMA_MINALIGN));
+ NetReceive((uchar *)packet, len);
fill_rx(hw);
return 1;
}
@@ -5002,12 +5016,13 @@ e1000_poll(struct eth_device *nic)
/**
TRANSMIT - Transmit a frame
***/
-static int e1000_transmit(struct eth_device *nic, void *packet, int length)
+static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
{
- void *nv_packet = (void *)packet;
+ void *nv_packet = (void *)txpacket;
struct e1000_hw *hw = nic-priv;
struct e1000_tx_desc *txp;
int i = 0;
+ uint32_t flush_start, flush_end;
txp = tx_base + tx_tail;
tx_tail = (tx_tail + 1) % 8
[U-Boot] [PATCH 2/2] e1000: add i210 support
From: Marek Vasut ma...@denx.de
Add i210 support to the e1000 driver.
Signed-off-by: Marek Vasut ma...@denx.de
Acked-by: Tim Harvey thar...@gateworks.com
---
drivers/net/e1000.c | 195
drivers/net/e1000.h | 12
include/pci_ids.h | 7 ++
3 files changed, 187 insertions(+), 27 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 0441a4f..0eba57c 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -92,6 +92,12 @@ static struct pci_device_id e1000_supported[] = {
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX},
+
{}
};
@@ -340,7 +346,7 @@ int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
return -E1000_ERR_SWFW_SYNC;
eecd = E1000_READ_REG(hw, EECD);
- if (hw-mac_type != e1000_82573 || hw-mac_type != e1000_82574) {
+ if (hw-mac_type != e1000_82573 hw-mac_type != e1000_82574) {
/* Request EEPROM Access */
if (hw-mac_type e1000_82544) {
eecd |= E1000_EECD_REQ;
@@ -391,10 +397,15 @@ int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
{
struct e1000_eeprom_info *eeprom = hw-eeprom;
- uint32_t eecd = E1000_READ_REG(hw, EECD);
+ uint32_t eecd;
int32_t ret_val = E1000_SUCCESS;
uint16_t eeprom_size;
+ if (hw-mac_type == e1000_igb)
+ eecd = E1000_READ_REG(hw, I210_EECD);
+ else
+ eecd = E1000_READ_REG(hw, EECD);
+
DEBUGFUNC();
switch (hw-mac_type) {
@@ -485,9 +496,10 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw
*hw)
eeprom-page_size = 8;
eeprom-address_bits = 8;
}
- eeprom-use_eerd = true;
- eeprom-use_eewr = true;
if (e1000_is_onboard_nvm_eeprom(hw) == false) {
+ eeprom-use_eerd = true;
+ eeprom-use_eewr = true;
+
eeprom-type = e1000_eeprom_flash;
eeprom-word_size = 2048;
@@ -511,6 +523,16 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw
*hw)
eeprom-use_eerd = true;
eeprom-use_eewr = false;
break;
+ case e1000_igb:
+ /* i210 has 4k of iNVM mapped as EEPROM */
+ eeprom-type = e1000_eeprom_invm;
+ eeprom-opcode_bits = 8;
+ eeprom-delay_usec = 1;
+ eeprom-page_size = 32;
+ eeprom-address_bits = 16;
+ eeprom-use_eerd = true;
+ eeprom-use_eewr = false;
+ break;
/* ich8lan does not support currently. if needed, please
* add corresponding code and functions.
@@ -552,7 +574,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
break;
}
- if (eeprom-type == e1000_eeprom_spi) {
+ if (eeprom-type == e1000_eeprom_spi ||
+ eeprom-type == e1000_eeprom_invm) {
/* eeprom_size will be an enum [0..8] that maps
* to eeprom sizes 128B to
* 32KB (incremented by powers of 2).
@@ -596,10 +619,17 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
int32_t done = E1000_ERR_EEPROM;
for (i = 0; i attempts; i++) {
- if (eerd == E1000_EEPROM_POLL_READ)
- reg = E1000_READ_REG(hw, EERD);
- else
- reg = E1000_READ_REG(hw, EEWR);
+ if (eerd == E1000_EEPROM_POLL_READ) {
+ if (hw-mac_type == e1000_igb)
+ reg = E1000_READ_REG(hw, I210_EERD);
+ else
+ reg = E1000_READ_REG(hw, EERD);
+ } else {
+ if (hw-mac_type == e1000_igb)
+ reg = E1000_READ_REG(hw, I210_EEWR);
+ else
+ reg = E1000_READ_REG(hw, EEWR);
+ }
if (reg E1000_EEPROM_RW_REG_DONE) {
done = E1000_SUCCESS;
@@ -632,13 +662,23 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw,
eerd = ((offset+i) E1000_EEPROM_RW_ADDR_SHIFT) +
E1000_EEPROM_RW_REG_START;
- E1000_WRITE_REG(hw
Re: [U-Boot] mx6: spl: Rename ncs as ranks and move it to mx6_ddr3_cfg
On Sat, Aug 9, 2014 at 7:08 AM, Nikolay Dimitrov picmas...@mail.bg wrote:
Hi guys,
I'm working on adding SO-DIMM SPL support on a custom imx6 board, so I'm
thinking on the idea of which DDR3 settings belong to the controller and
which belong to the DDR3 memory module/chips.
My proposal is to rename the struct member ncs to ranks (as per JEDEC)
and to move it as part of the DDR3 module description (be it an external
so-dimm module or on-board DDR ICs), and not part of the MMDC description.
This way the ranks value can be loaded from the SO-DIMM SPD or hard-coded
as in Tim's case for the Ventana board.
The code for my board is out of the official tree, so I'm showing my idea on
Tim's Ventana SPL code:
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 0434211..0d3580b 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -340,7 +340,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
debug(trrd=%d\n, trrd);
debug(txpr=%d\n, txpr);
debug(CS0_END=%d\n, CS0_END);
- debug(ncs=%d\n, i-ncs);
+ debug(ranks=%d\n, m-ranks);
debug(Rtt_wr=%d\n, i-rtt_wr);
debug(Rtt_nom=%d\n, i-rtt_nom);
debug(SRT=%d\n, m-SRT);
@@ -437,11 +437,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
/* Step 7: Enable MMDC with desired chip select */
reg = mmdc0-mdctl |
(1 31) | /* SDE_0 for CS0 */
- ((i-ncs == 2) ? 1 : 0) 30;/* SDE_1 for CS1 */
+ ((m-ranks == 2) ? 1 : 0) 30; /* SDE_1 for CS1 */
mmdc0-mdctl = reg;
/* Step 8: Write Mode Registers to Init DDR3 devices */
- for (cs = 0; cs i-ncs; cs++) {
+ for (cs = 0; cs m-ranks; cs++) {
/* MR2 */
reg = (i-rtt_wr 3) 9 | (m-SRT 1) 7 |
((tcwl - 3) 3) 3;
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 5ebabfa..2b9649c 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -191,13 +191,13 @@ struct mx6_ddr3_cfg {
u16 trcmin; /* tRC min (ns*100) */
u16 trasmin;/* tRAS min (ns*100) */
u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
+ u8 ranks; /* ranks (chip-selects) of the DDR3 memory (1,2) */
};
/* System Information: Varies per board design, layout, and term choices */
struct mx6_ddr_sysinfo {
u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit)
*/
u8 cs_density; /* density per chip select (Gb) */
- u8 ncs; /* number chip selects used (1|2) */
char cs1_mirror;/* enable address mirror (0|1) */
char bi_on; /* Bank interleaving enable */
u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c
b/board/gateworks/gw_ventana/gw_ventana_spl.c
index e943879..93be270 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -199,6 +199,7 @@ static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
+ .ranks = 1
};
/* GW54xx specific calibration */
@@ -309,8 +310,6 @@ static void spl_dram_init(int width, int size, int
board_model)
.dsize = width/32,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
- /* single chip select */
- .ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,/* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
Please excuse me if this way to show ideas is not the appropriate one, just
tell me how to do it better and I'll do my best.
Kind regards,
Nikolay
Hi Nikolay,
The ncs field is a 'system' property detailing how many chip selects
your board supports. I suppose in your case you are saying you have a
SO-DIMM that you route both chip selects to and the SO-DIMM SPD tells
you whether it uses 1 or 2 of them.
Nikita may have comments on this as he's using board configurations
with multiple chip selects - I haven't needed that myself yet (but
will soon) so I've cc'd him.
Tim
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[U-Boot] [PATCH 4/4] [PATCH] ventana: Add support for the LTC3676 PMIC
The LTC3676 PMIC is used instead of the PFUZE100 PMIC on the
GW51xx/GW52xx/GW53xx Ventana baseboards. In order to support the IMX6Q SoC
at 1GHz on those baseboards, we need to adjust the voltage scaling for the SW1
and SW3 DC/DC converters on the LTC3676 for 1225mV. Note that the scalar
values for the LTC3676 are board-specific as they relate to a resistor devider
chosen by the board design.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 78 +++--
include/configs/gw_ventana.h| 2 +
2 files changed, 57 insertions(+), 23 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 48e90e0..cf42fcf 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -30,6 +30,7 @@
#include mtd_node.h
#include netdev.h
#include power/pmic.h
+#include power/ltc3676_pmic.h
#include power/pfuze100_pmic.h
#include i2c.h
#include fdt_support.h
@@ -733,6 +734,60 @@ struct ventana gpio_cfg[] = {
},
};
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+ u32 reg;
+
+ /* configure PFUZE100 PMIC */
+ if (board_type == GW54xx || board_type == GW54proto) {
+ power_pfuze100_init(I2C_PMIC);
+ p = pmic_get(PFUZE100_PMIC);
+ if (p !pmic_probe(p)) {
+ pmic_reg_read(p, PFUZE100_DEVICEID, reg);
+ printf(PMIC: PFUZE100 ID=0x%02x\n, reg);
+
+ /* Set VGEN1 to 1.5V and enable */
+ pmic_reg_read(p, PFUZE100_VGEN1VOL, reg);
+ reg = ~(LDO_VOL_MASK);
+ reg |= (LDOA_1_50V | LDO_EN);
+ pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
+
+ /* Set SWBST to 5.0V and enable */
+ pmic_reg_read(p, PFUZE100_SWBSTCON1, reg);
+ reg = ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+ reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
+ pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+ }
+ }
+
+ /* configure LTC3676 PMIC */
+ else {
+ power_ltc3676_init(I2C_PMIC);
+ p = pmic_get(LTC3676_PMIC);
+ if (p !pmic_probe(p)) {
+ puts(PMIC: LTC3676\n);
+ /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
+ if (is_cpu_type(MXC_CPU_MX6Q)) {
+ /* mask PGOOD during SW1 transition */
+ reg = 0x1d | LTC3676_PGOOD_MASK;
+ pmic_reg_write(p, LTC3676_DVB1B, reg);
+ /* set SW1 (VDD_SOC) to 1259mV */
+ reg = 0x1d;
+ pmic_reg_write(p, LTC3676_DVB1A, reg);
+
+ /* mask PGOOD during SW3 transition */
+ reg = 0x1d | LTC3676_PGOOD_MASK;
+ pmic_reg_write(p, LTC3676_DVB3B, reg);
+ /*set SW3 (VDD_ARM) to 1259mV */
+ reg = 0x1d;
+ pmic_reg_write(p, LTC3676_DVB3A, reg);
+ }
+ }
+ }
+}
+
/* setup GPIO pinmux and default configuration per baseboard */
static void setup_board_gpio(int board)
{
@@ -1076,29 +1131,6 @@ int misc_init_r(void)
setenv(serial#, str);
}
- /* configure PFUZE100 PMIC (not used on all Ventana baseboards) */
- power_pfuze100_init(I2C_PMIC);
- if (board_type == GW54xx || board_type == GW54proto) {
- struct pmic *p = pmic_get(PFUZE100_PMIC);
- u32 reg;
-
- if (p !pmic_probe(p)) {
- pmic_reg_read(p, PFUZE100_DEVICEID, reg);
- printf(PMIC: PFUZE100 ID=0x%02x\n, reg);
-
- /* Set VGEN1 to 1.5V and enable */
- pmic_reg_read(p, PFUZE100_VGEN1VOL, reg);
- reg = ~(LDO_VOL_MASK);
- reg |= (LDOA_1_50V | LDO_EN);
- pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
-
- /* Set SWBST to 5.0V and enable */
- pmic_reg_read(p, PFUZE100_SWBSTCON1, reg);
- reg = ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
- reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
- pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
- }
- }
/* setup baseboard specific GPIO pinmux and config */
setup_board_gpio(board_type);
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 3398390..b984f27 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
Re: [U-Boot] [PATCH] mx6sabred: Add PFUZE100 PMIC support
On Mon, May 5, 2014 at 7:29 AM, Stefano Babic sba...@denx.de wrote:
Hi Fabio,
just a minor question:
On 04/05/2014 21:14, Fabio Estevam wrote:
snip
+int misc_init_r(void)
+{
Do we need misc_init ? Why not to use power_init_board() ? It is already
defined as weak.
OT: I confess I am quite losing which functions are already foreseen.
Most of them have the prefix board_, and they are easier to find.
However, power_init_board() does not follow the same rule.
Hi Fabio,
Yes, I think Stefano is correct in that power_init_board() is the
right place to put pmic init. He asked me to do that to my recent
series as well and it worked fine. Note that in that series I do have
a patch that will rename pmic_init() for the PFUZE100 to
power_pfuze100_init() [1]. I'm hoping that will make it in soon.
Tim
[1] - http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/184853/focus=184851
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Re: [U-Boot] [PATCH 05/12] MX6: add boot device support for SPL
+cc Edward Lin
On Mon, May 5, 2014 at 2:14 AM, Stefano Babic sba...@denx.de wrote:
Hi Tim,
On 28/04/2014 22:17, Tim Harvey wrote:
Add a common spl.c file to support boot device functions needed for SPL
such as detecting the boot device.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v2:
- re-base on top of Masahiro Yamada's consolidation patch:
http://patchwork.ozlabs.org/patch/341817/
- moved spl_boot_device() and get_boot_mode() into own common imx spl.c file
- use mem-mapped structure for smbr reg access
---
arch/arm/imx-common/Makefile | 1 +
arch/arm/imx-common/spl.c| 79
2 files changed, 80 insertions(+)
create mode 100644 arch/arm/imx-common/spl.c
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index b04dfbb..c97ea48 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y+= misc.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
new file mode 100644
index 000..5c1667c
--- /dev/null
+++ b/arch/arm/imx-common/spl.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
Just a little remark. Do you have written the function on your own or
have you ported it from Freescale's 2009.08 ? Apart names, it looks similar.
If this is the case, you should also add Freescale's Copyright to the
header.
Hi Stefano,
I've never looked at Freescales 2009.08 code myself (I have an
aversion to vendor specific forks of u-boot almost 5 years old heh),
but its likely bits of the function came from there originally but my
inspiration likely came from Edward Lin's patch a while back. A
switch/case seems the logical approach given the bitfield from the
IMX6 reference manual with several don't-cares spread around and I
felt that was much easier to read than trying to convert it all the
shifts and masks.
I can add additional copyright's if anyone feels its necessary - I've
added Edward to the cc to see if he feels its necessary.
Tim
+#include common.h
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/spl.h
+#include spl.h
+
+#if defined(CONFIG_MX6)
+/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+u32 spl_boot_device(void)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(psrc-sbmr1);
+
+ /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
+ switch ((reg 0x00FF) 4) {
+ /* EIM: See 8.5.1, Table 8-9 */
+ case 0x0:
+ /* BOOT_CFG1[3]: NOR/OneNAND Selection */
+ if ((reg 0x0008) 3)
+ return BOOT_DEVICE_ONENAND;
+ else
+ return BOOT_DEVICE_NOR;
+ break;
+ /* SATA: See 8.5.4, Table 8-20 */
+ case 0x2:
+ return BOOT_DEVICE_SATA;
+ /* Serial ROM: See 8.5.5.1, Table 8-22 */
+ case 0x3:
+ /* BOOT_CFG4[2:0] */
+ switch ((reg 0x0700) 24) {
+ case 0x0 ... 0x4:
+ return BOOT_DEVICE_SPI;
+ case 0x5 ... 0x7:
+ return BOOT_DEVICE_I2C;
+ }
+ break;
+ /* SD/eSD: 8.5.3, Table 8-15 */
+ case 0x4:
+ case 0x5:
+ return BOOT_DEVICE_MMC1;
+ /* MMC/eMMC: 8.5.3 */
+ case 0x6:
+ case 0x7:
+ return BOOT_DEVICE_MMC1;
+ /* NAND Flash: 8.5.2 */
+ case 0x8 ... 0xf:
+ return BOOT_DEVICE_NAND;
+ }
+ return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ /* for MMC return either RAW or FAT mode */
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ break;
+ default:
+ puts(spl: ERROR: unsupported device\n);
+ hang();
+ }
+}
+#endif
Best regards,
Stefano Babic
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Re: [U-Boot] [PATCH 07/12] MX6: add structs for mmdc and ddr iomux registers
On Mon, May 5, 2014 at 3:34 AM, Stefano Babic sba...@denx.de wrote:
Hi Tim,
On 28/04/2014 22:17, Tim Harvey wrote:
Add memory-mapped structures for MMDC iomux and configuration. Note that
while
the MMDC configuration registers are common between the IMX6DQ
(IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux
registers differ. This requires two sets of structures.
Add structures to describe DDR3 device information, system information
(memory layout, etc), and MMDC calibration regitsers that can be used to
configure the MMDC dynamically.
We define these structures for SPL builds instead of including mx6q-ddr.h and
mx6dl-ddr.h which use the same namespace and are only useful for imximage cfg
files.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v2:
- split out from original mmdc configuration patch
- only define for SPL build
- do not include mx6q-ddr.h and mx6dl-ddr.h for SPL build - these use the
same namespace and are only useful for imximage cfg files
---
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 231
1 file changed, 231 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 43d377a..d544d2e 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -6,6 +6,7 @@
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_MX6Q
#include mx6q-ddr.h
#else
@@ -15,6 +16,236 @@
#error Please select cpu
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
+#else
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
+ u32 mdscr;
+ u32 mdref;
+ u32 res1[2];
+ u32 mdrwd;
+ u32 mdor;
+ u32 res2[3];
+ u32 mdasp;
+ u32 res3[240];
+ u32 mapsr;
+ u32 res4[254];
+ u32 mpzqhwctrl;
+ u32 res5[2];
+ u32 mpwldectrl0;
+ u32 mpwldectrl1;
+ u32 res6;
+ u32 mpodtctrl;
+ u32 mprddqby0dl;
+ u32 mprddqby1dl;
+ u32 mprddqby2dl;
+ u32 mprddqby3dl;
+ u32 res7[4];
+ u32 mpdgctrl0;
+ u32 mpdgctrl1;
+ u32 res8;
+ u32 mprddlctl;
+ u32 res9;
+ u32 mpwrdlctl;
+ u32 res10[25];
+ u32 mpmur0;
+};
+
+/*
+ * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
+ */
+#define MX6DQ_IOM_DDR_BASE 0x020e0500
It is only a question - having the value here let us know where the
registers are located. Anyway, registers' offsets are stored in the
imx-regs.h file of the SOC. Which is the reason to set them here ?
I felt they belonged with the ddr structures themselves. I can move
them but then will someone claim that the ddr structures should also
be moved?
Tim
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Re: [U-Boot] [PATCH 02/12] SPL: NAND: add support for mxs nand
On Fri, May 2, 2014 at 1:56 PM, Scott Wood scottw...@freescale.com wrote:
Hi Scott,
On Mon, 2014-04-28 at 13:17 -0700, Tim Harvey wrote:
+static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ register struct nand_chip *chip = mtd-priv;
+ int ctrl = NAND_NCE | NAND_CTRL_CLE | NAND_CTRL_CHANGE;
+ u32 timeo, time_start;
+
+ /* write out the command to the device */
+ chip-cmd_ctrl(mtd, command, ctrl);
+
+ /* Address cycle, when necessary */
+ ctrl = NAND_NCE | NAND_CTRL_ALE | NAND_CTRL_CHANGE;
+ /* Serially input address */
+ if (column != -1) {
+ ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
What happened to NAND_NCE?
It looks like the cmd_ctrl in nand_mxs.c doesn't care about NAND_MCE at
all, so there's no functional impact, but either use it consistently or
don't use it at all.
+ chip-cmd_ctrl(mtd, column, ctrl);
+ ctrl = ~NAND_CTRL_CHANGE;
+ chip-cmd_ctrl(mtd, column 8, ctrl);
+ }
Why not pass the ctrl flags directly to cmd_ctrl as you do in most of
the rest of the function? nand_mxs.c doesn't even look at NAND_CTRL_CHANGE.
I'll simplify using only what nand_mxs.c pays attention to (NAND_ALE,
NAND_CLE), remove the ctrl var and repost
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
+{
+ register struct nand_chip *chip;
Why register?
cut-n-paste code from nand_base.c - will remove
+ if (!(page % nand_page_per_block)) {
+ /*
+ * Yes, new block. See if this block is good. If not,
+ * loop until we find a good block.
+ */
+ while (is_badblock(mtd, offs, 1)) {
+ page = page + nand_page_per_block;
+ /* Check i we've reached the end of flash. */
+ if (page = mtd.size chip-page_shift)
+ return -1;
Why -1 rather than a real error value?
probably from the example I used from drivers/mtd/nand/mxc_nand_spl.c.
The calling functions don't appear to do any error checking, but I'll
replace it with -ENOMEM and -ENODEV if mxs_nand_init() fails.
Thanks for the review!
Tim
-Scott
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Re: [U-Boot] [PATCH 09/12] IMX: add additional function for pinmux using an array
On Tue, Apr 29, 2014 at 8:22 AM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
Hi Tim,
Hi Eric,
On 04/28/2014 01:17 PM, Tim Harvey wrote:
Add new function that can take an array of iomux configs, an index, and
a stride to allow a multi-dimentional array of pinmux values to be used
to define pinmux values per cpu-type.
This takes a different approach to previously proposed solutions which
used
multiple arrays of pad lists. The goal is to eliminate having these
multiple
arrays such as 'mx6q_uart1_pads' and 'mx6dl_uart1_pads' which are almost
identical copies of each other except for the MX6Q/MX6DL prefix on the
PAD.
I don't think a blind reference to the previously proposed solution
helps in understanding this patch, and an example would be more helpful.
agreed - will remove
snip
-void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
- unsigned count)
I think 'start_offs' would be clearer than 'list'.
agreed - will change to 'start_offs'
The function name ..._array() also doesn't really capture what's
going on here. Naming is hard though, and I'm not coming up
with something else.
Perhaps 'sparse', 'skip', or alternate?
ya, I'm not sure anything else is more explanatory when we are doing
something like this. Its bad enough that its likely difficult for
someone to understand their first time through that we are doing this
to eliminate multiple structs.
snip
+/* macros for declaring and using pinmux array */
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
In a similar vein to my comment about Patch 8, I do wonder if a
minor extension of this will allow use with a single-variant
board though.
for a single-variant one would just use the original
IOMUX_PAD/imx_iomux_v3_setup_pad/imx_iomux_v3_setup_pad right?
We have some custom designs that really only function with
one variant (usually i.MX6DQ) and it seems wrong to have
the other variant included.
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def);\
+}
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads_array(x, \
+ ARRAY_SIZE(x)/2, is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1, 2)
+
#endif/* __MACH_IOMUX_V3_H__*/
Please don't mis-interpret my comments as any form of Nack.
This patch moves the ball forward, and the approach of building
two lists into one prevents duplication of tables quite nicely.
Regards,
Eric
Thanks for the review!
Tim
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[U-Boot] [PATCH] dwc_ahsata: return failure for MX6 if not IMX6Q
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return an error
indicating no such port instead of attempting a memory access that results
in a data abort and reset. This dynamic detection is necessary for bootloaders
that support multiple variants of the IMX6 SoC.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
drivers/block/dwc_ahsata.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 3569214..638a585 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -17,6 +17,7 @@
#include asm/io.h
#include linux/bitops.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
#include dwc_ahsata.h
struct sata_port_regs {
@@ -558,6 +559,12 @@ int init_sata(int dev)
u32 linkmap;
struct ahci_probe_ent *probe_ent = NULL;
+#if defined(CONFIG_MX6)
+ if (!is_cpu_type(MXC_CPU_MX6Q)) {
+ printf(No device detected!\n);
+ return 1;
+ }
+#endif
if (dev 0 || dev (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
printf(The sata index %d is out of ranges\n\r, dev);
return -1;
--
1.8.3.2
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Re: [U-Boot] [PATCH 05/12] MX6: add boot device support for SPL
On Tue, May 6, 2014 at 12:55 AM, Stefano Babic sba...@denx.de wrote: Hi Tim, On 06/05/2014 08:36, Tapani Utriainen wrote: Tim, Stefano, that piece of code indeed originates from Freescale's 2009.08 u-boot. (Edward has changed jobs, so the CC:d address is of no use.) I supposed this. Tim, please add Freescale's Copyright, too. Thanks, Stefano Babic ok - will do. Thanks for the heads-up Tapani. Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On Mon, Apr 28, 2014 at 1:17 PM, Tim Harvey thar...@gateworks.com wrote:
Switch to an SPL image. The SPL for Ventana does the following:
- setup i2c and read the factory programmed EEPROM to obtain DRAM config
and model for board-specific calibration data
- configure DRAM per CPU/size/layout/devices/calibration
- load u-boot.img from NAND or MTD depending on boot device and jump to it
This allows for a single SPL+u-boot.img to replace the previous multiple board
configurations.
snip
+
+static void i2c_setup_iomux(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, mx6q_i2c_pad_info0);
+ else
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f,
mx6dl_i2c_pad_info0);
+}
+
snip
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+ struct ventana_board_info ventana_info;
+ int board_model;
+
+ /* iomux and setup of i2c */
+ i2c_setup_iomux();
+ timer_init();
+ board_model = read_eeprom(I2C_GSC, ventana_info);
+
+ /* provide some some default: 32bit 128MB */
+ if (GW_UNKNOWN == board_model) {
+ ventana_info.sdram_width = 2;
+ ventana_info.sdram_size = 3;
+ }
+ spl_dram_init(8 ventana_info.sdram_width,
+ 16 ventana_info.sdram_size,
+ board_model);
+
+ arch_cpu_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Set global data pointer. */
+ gd = gdata;
+
+ board_early_init_f();
+
+ preloader_console_init();
+
+ board_init_r(NULL, 0);
+}
Stefano / York,
While preparing for a v3 patch series of my IMX6 SPL bootloader, I
find that commit dec1861be90c948ea9fb771927d3d26a994d2e20 [1] breaks
the above code because gd is now needed within setup_i2c.
I've always been a bit fuzzy on the order of the above calls so I dug
through the code and I think I understand things better. Please
correct any wrong assumptions I'm making below:
- assignment to gd should 'always' be first (before anything needs
it, so why not do it first)
- arch_cpu_init() should go next as this sets up very low level
CPU/SoC resources (in this case AIPS config and watchdog disable)
- board_early_init_f() should be next as that sets up any board-specific iomux
- any additional iomux necessary for SPL should go next (I take care
of i2c iomux and setup here)
- timer_init() next as you need a timer for UART and mxc i2c (for
delays and busy checks)
- preloader_console_init() next as we are now able to send something
over the UART (this gives me early debug for sdram config now too!)
- sdram setup goes next
- after sdram is setup, the bss can be cleared
- board_init_r - pass over to generic SPL code which will load/call
an image based on boot device
So, if the above is correct, I should rework the above function as follows:
void board_init_f(ulong dummy)
{
struct ventana_board_info ventana_info;
int board_model;
/* Set global data pointer. */
gd = gdata;
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* read/validate EEPROM info to determine board model and SDRAM cfg */
board_model = read_eeprom(I2C_GSC, ventana_info);
/* provide some some default: 32bit 128MB */
if (GW_UNKNOWN == board_model) {
ventana_info.sdram_width = 2;
ventana_info.sdram_size = 3;
}
/* configure MMDC for SDRAM width/size and per-model calibration */
spl_dram_init(8 ventana_info.sdram_width,
16 ventana_info.sdram_size,
board_model);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
Does this make sense?
Thanks,
Tim
[1] -
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=dec1861be90c948ea9fb771927d3d26a994d2e20
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/boards.cfg b/boards.cfg
index c83aff3..9119e24 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -322,11 +322,7 @@ Active arm armv7 mx6 freescale
mx6qsabreauto
Active arm armv7 mx6 freescale mx6sabresd
mx6dlsabresd
mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL
Fabio
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On Tue, May 6, 2014 at 12:11 PM, Jeroen Hofstee dasub...@myspectrum.nl wrote:
Hello Tim,
On di, 2014-05-06 at 11:18 -0700, Tim Harvey wrote:
On Mon, Apr 28, 2014 at 1:17 PM, Tim Harvey thar...@gateworks.com wrote:
void board_init_f(ulong dummy)
{
struct ventana_board_info ventana_info;
int board_model;
/* Set global data pointer. */
gd = gdata;
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* read/validate EEPROM info to determine board model and SDRAM cfg
*/
board_model = read_eeprom(I2C_GSC, ventana_info);
/* provide some some default: 32bit 128MB */
if (GW_UNKNOWN == board_model) {
ventana_info.sdram_width = 2;
ventana_info.sdram_size = 3;
}
/* configure MMDC for SDRAM width/size and per-model calibration */
spl_dram_init(8 ventana_info.sdram_width,
16 ventana_info.sdram_size,
board_model);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
Does this make sense?
Since Crt0.S already created gd on the stack before calling
board_init_f, can't the assignment of gd not simply be removed?
Is there anything special about gdata?
Regards,
Jeroen
Jeroen,
That does make sense, but what I find is that York's ocmmit
dec1861be90c948ea9fb771927d3d26a994d2e20 requires that gd be blanked
and its not. This causes bus_i2c_init to skip its initialization
because p-base is not zero.
York, does this make sense? Your patch creates a dependence on
gd-srdata being blank which isn't the case with the SRAM when booting
from the IMX6 boot rom.
Tim
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Re: [U-Boot] [PATCH] dwc_ahsata: return failure for MX6 if not IMX6Q
On Tue, May 6, 2014 at 12:55 PM, Troy Kisky
troy.ki...@boundarydevices.com wrote:
On 5/5/2014 10:22 PM, Tim Harvey wrote:
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return an error
indicating no such port instead of attempting a memory access that results
in a data abort and reset. This dynamic detection is necessary for
bootloaders
that support multiple variants of the IMX6 SoC.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
drivers/block/dwc_ahsata.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 3569214..638a585 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -17,6 +17,7 @@
#include asm/io.h
#include linux/bitops.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
#include dwc_ahsata.h
struct sata_port_regs {
@@ -558,6 +559,12 @@ int init_sata(int dev)
u32 linkmap;
struct ahci_probe_ent *probe_ent = NULL;
+#if defined(CONFIG_MX6)
+ if (!is_cpu_type(MXC_CPU_MX6Q)) {
!is_cpu_type(MXC_CPU_MX6D)
is needed too ?
Troy
Troy,
Indeed - thanks for the reminder!
Tim
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Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On Wed, May 7, 2014 at 9:14 AM, York Sun york...@freescale.com wrote: On 05/06/2014 04:35 PM, Tim Harvey wrote: On Tue, May 6, 2014 at 12:11 PM, Jeroen Hofstee dasub...@myspectrum.nl wrote: Hello Tim, snip Since Crt0.S already created gd on the stack before calling board_init_f, can't the assignment of gd not simply be removed? Is there anything special about gdata? Regards, Jeroen Jeroen, That does make sense, but what I find is that York's ocmmit dec1861be90c948ea9fb771927d3d26a994d2e20 requires that gd be blanked and its not. This causes bus_i2c_init to skip its initialization because p-base is not zero. York, does this make sense? Your patch creates a dependence on gd-srdata being blank which isn't the case with the SRAM when booting from the IMX6 boot rom. GD should be cleared (zeroed). Then we don't have this problem. Whoever sets up gd (board_int_f, cpu_init_f, or others) should make sure gd is cleared. Why isn't it the case for IMX6 boot rom? York York, crt0.S is mapping gd to where the SPL stack pointer is defined, which is where Freescale says its stack pointer is for its firmware BOOT ROM, so its initial data will be dependent on what the BOOT ROM did. I think the right solution is to have crt0.S zero it out. Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On Wed, May 7, 2014 at 1:29 PM, York Sun york...@freescale.com wrote: On 05/07/2014 01:27 PM, Tim Harvey wrote: On Wed, May 7, 2014 at 9:14 AM, York Sun york...@freescale.com wrote: On 05/06/2014 04:35 PM, Tim Harvey wrote: On Tue, May 6, 2014 at 12:11 PM, Jeroen Hofstee dasub...@myspectrum.nl wrote: Hello Tim, snip Since Crt0.S already created gd on the stack before calling board_init_f, can't the assignment of gd not simply be removed? Is there anything special about gdata? Regards, Jeroen Jeroen, That does make sense, but what I find is that York's ocmmit dec1861be90c948ea9fb771927d3d26a994d2e20 requires that gd be blanked and its not. This causes bus_i2c_init to skip its initialization because p-base is not zero. York, does this make sense? Your patch creates a dependence on gd-srdata being blank which isn't the case with the SRAM when booting from the IMX6 boot rom. GD should be cleared (zeroed). Then we don't have this problem. Whoever sets up gd (board_int_f, cpu_init_f, or others) should make sure gd is cleared. Why isn't it the case for IMX6 boot rom? York York, crt0.S is mapping gd to where the SPL stack pointer is defined, which is where Freescale says its stack pointer is for its firmware BOOT ROM, so its initial data will be dependent on what the BOOT ROM did. I think the right solution is to have crt0.S zero it out. Either crt0.S, or somewhere before gd is used for the first time. Can it be done in board_init_f()? York It makes more sense to do it in crt0.S so that all boards don't have to do it and can make the assumption that it is cleared. Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/12] IMX: add additional function for pinmux using an array
On Wed, May 7, 2014 at 9:59 AM, Nikita Kiryanov nik...@compulab.co.il wrote: On 06/05/14 07:35, Tim Harvey wrote: On Tue, Apr 29, 2014 at 8:22 AM, Eric Nelson eric.nel...@boundarydevices.com wrote: snip The function name ..._array() also doesn't really capture what's going on here. Naming is hard though, and I'm not coming up with something else. Perhaps 'sparse', 'skip', or alternate? ya, I'm not sure anything else is more explanatory when we are doing something like this. Its bad enough that its likely difficult for someone to understand their first time through that we are doing this to eliminate multiple structs. Come to think of it, I don't think we need an _array() function at all. The list selection and stride size are IOMUX_PADS implementation details. It's not something we should expose to the function user. is_cpu_type() and ifdef(CONFIG_MX6QDL) can be used to decide the list and stride values inside imx_iomux_v3_setup_multiple_pads(), and then this function could be used for both single and multi cpu type situations. snip +/* macros for declaring and using pinmux array */ +#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x) In a similar vein to my comment about Patch 8, I do wonder if a minor extension of this will allow use with a single-variant board though. for a single-variant one would just use the original IOMUX_PAD/imx_iomux_v3_setup_pad/imx_iomux_v3_setup_pad right? They can, but then we don't get to use the same code for both situations. If we define two versions of IOMUX_PADS: one for multi cpu type, and one for single cpu type, then the pinmux arrays for both situations will be syntactically similar. When combined with my other suggestion, it will be very easy to take a U-Boot configured for one CPU type, and reconfigure it to support both CPU types. Nikita, Excellent idea - I've merged that idea into my new patchset that I will post shortly. Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 01/11] nand: remove CONFIG_SYS_NAND_PAGE_SIZE
We only need to read in the size of struct image_header and thus don't need to know the page size of the nand device. Cc: Scott Wood scottw...@freescale.com Signed-off-by: Tim Harvey thar...@gateworks.com Acked-by: Stefano Babic sba...@denx.de Acked-by: Scott Wood scottw...@freescale.com --- v3: - no changes v2: - cc Scott Wood scottw...@freescale.com on this - Acked-by: Stefano Babic sba...@denx.de - Acked-by: Scott Wood scottw...@freescale.com --- common/spl/spl_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 9da0218..062461b 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -76,7 +76,7 @@ void spl_nand_load_image(void) #endif /* Load u-boot */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + sizeof(*header), (void *)header); spl_parse_image_header(header); nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, spl_image.size, (void *)spl_image.load_addr); -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 00/11] mx6: SPL NAND support
This series adds some necessary framework for IMX6 SPL support. The series includes support for NAND SPL and has been tested with MMC as well. I have tested this on five differing Ventana baseboards with a variety of memory (32bit 512MB, 32bit 1024MB, 64bit 1024MB) and CPU configurations (IMX6Q, IMX6DL, IMX6S). This is based on top of Mashahiro Yamada's patch that consolidates arch/arm/include/asm/arch-*/spl.h [1] v3: - re-ordered calls in board_init_f - replace imx_iomux_v3_setup_multiple_pads_array with additional intelligence in imx_iomux_v3_setup_multiple_pads - added ifdef's around cpu specific mmdc iocfg functions for code-reduction with single-variant board configs - added checks for IMX6D - added Freescale copyright to boot device support function - fixed typo s/IMX6SLD/IMX6SDL - encorporated cleanups in mxs_nand_spl.c per feedback v2: - use compatible linker script instead of creating new one - remove structure passing data from SPL to u-boot - remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base and nand_bbt to bring SPL down in size. This reduced codesize by about 32k where now mxs_spl_nand is about 12k total - adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD - move boot dev detection into imx-common/spl.c - move macros for using pinmux array into iomux-v3.h - remove missing/unnecessary include - revert mtdparts change - use get_ram_size() to detect memory - add support for MX6SOLO and MX6DUAL - set CS0_END for 4GB so get_ram_size() works - updated DDR3 calibration values for ventana boards - fixed build issue - only compile spl if doing spl build - fixed line length issue in README - remove CONFIG_SPL* conditions and conditionally compile instead - removed prints for CPU type and DRAM size/width - uboot will print these l - removed unused gw_ventana_spl.cfg - use common read_eeprom function - added MMC support to SPL - added Masahiro Yamada's boot mode consolidation patch http://patchwork.ozlabs.org/patch/341817 and rebase on top of it [1] http://patchwork.ozlabs.org/patch/341817/ Tim Harvey (11): SPL: NAND: remove CONFIG_SYS_NAND_PAGE_SIZE SPL: NAND: add support for mxs nand MX6: add common SPL configuration MX6: add boot device support for SPL IMX: add comments and remove unused struct fields MX6: add structs for mmdc and ddr iomux registers MX6: add mmdc configuration for MX6Q/MX6DL IMX: iomux: add macros to setup iomux for multiple SoC types IMX: ventana: split read_eeprom into standalone file IMX: ventana: auto-configure for IMX6Q vs IMX6DL IMX: ventana: switch to SPL arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/ddr.c| 473 ++ arch/arm/imx-common/Makefile| 1 + arch/arm/imx-common/cpu.c | 16 +- arch/arm/imx-common/iomux-v3.c | 16 +- arch/arm/imx-common/spl.c | 81 arch/arm/include/asm/arch-mx6/mx6-ddr.h | 231 +++ arch/arm/include/asm/imx-common/iomux-v3.h | 25 ++ board/gateworks/gw_ventana/Makefile | 3 +- board/gateworks/gw_ventana/README | 92 +++-- board/gateworks/gw_ventana/eeprom.c | 89 + board/gateworks/gw_ventana/gw_ventana.c | 591 +++- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 419 board/gateworks/gw_ventana/ventana_eeprom.h | 11 + boards.cfg | 6 +- common/spl/spl_nand.c | 2 +- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand_spl.c | 231 +++ include/configs/gw_ventana.h| 11 + include/configs/imx6_spl.h | 71 21 files changed, 2047 insertions(+), 339 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c create mode 100644 arch/arm/imx-common/spl.c create mode 100644 board/gateworks/gw_ventana/eeprom.c create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c create mode 100644 drivers/mtd/nand/mxs_nand_spl.c create mode 100644 include/configs/imx6_spl.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 05/11] imx: add comments and remove unused struct fields
Add comment block for the imx_ddr_size function and remove the extra unused
fields from struct esd_mmdc_regs which are also not common between IMX53 and
IMX6.
Signed-off-by: Tim Harvey thar...@gateworks.com
Acked-by: Stefano Babic sba...@denx.de
---
v3:
- fixed doxygen-style comment block
- added Stefano's Ack
v2:
- new patch in series
---
arch/arm/imx-common/cpu.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index a77c4de..5a09107 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -58,6 +58,7 @@ char *get_reset_cause(void)
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};
+/* these MMDC registers are common to the IMX53 and IMX6 */
struct esd_mmdc_regs {
uint32_tctl;
uint32_tpdc;
@@ -66,15 +67,6 @@ struct esd_mmdc_regs {
uint32_tcfg1;
uint32_tcfg2;
uint32_tmisc;
- uint32_tscr;
- uint32_tref;
- uint32_trsvd1;
- uint32_trsvd2;
- uint32_trwd;
- uint32_tor;
- uint32_tmrr;
- uint32_tcfg3lp;
- uint32_tmr4;
};
#define ESD_MMDC_CTL_GET_ROW(mdctl)((ctl 24) 7)
@@ -83,6 +75,12 @@ struct esd_mmdc_regs {
#define ESD_MMDC_CTL_GET_CS1(mdctl)((ctl 30) 1)
#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc 5) 1)
+/*
+ * imx_ddr_size - return size in bytes of DRAM according MMDC config
+ * The MMDC MDCTL register holds the number of bits for row, col, and data
+ * width and the MMDC MDMISC register holds the number of banks. Combine
+ * all these bits to determine the meme size the MMDC has been configured for
+ */
unsigned imx_ddr_size(void)
{
struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
--
1.8.3.2
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[U-Boot] [PATCH v3 04/11] mx6: add boot device support for SPL
Add a common spl.c file to support boot device functions needed for SPL
such as detecting the boot device.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- added Freescale copyright
v2:
- re-base on top of Masahiro Yamada's consolidation patch:
http://patchwork.ozlabs.org/patch/341817/
- moved spl_boot_device() and get_boot_mode() into own common imx spl.c file
- use mem-mapped structure for smbr reg access
---
arch/arm/imx-common/Makefile | 1 +
arch/arm/imx-common/spl.c| 81
2 files changed, 82 insertions(+)
create mode 100644 arch/arm/imx-common/spl.c
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index b04dfbb..c97ea48 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y += misc.o
+obj-$(CONFIG_SPL_BUILD)+= spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
new file mode 100644
index 000..9a02a64
--- /dev/null
+++ b/arch/arm/imx-common/spl.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/spl.h
+#include spl.h
+
+#if defined(CONFIG_MX6)
+/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+u32 spl_boot_device(void)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(psrc-sbmr1);
+
+ /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
+ switch ((reg 0x00FF) 4) {
+/* EIM: See 8.5.1, Table 8-9 */
+ case 0x0:
+ /* BOOT_CFG1[3]: NOR/OneNAND Selection */
+ if ((reg 0x0008) 3)
+ return BOOT_DEVICE_ONENAND;
+ else
+ return BOOT_DEVICE_NOR;
+ break;
+ /* SATA: See 8.5.4, Table 8-20 */
+ case 0x2:
+ return BOOT_DEVICE_SATA;
+ /* Serial ROM: See 8.5.5.1, Table 8-22 */
+ case 0x3:
+ /* BOOT_CFG4[2:0] */
+ switch ((reg 0x0700) 24) {
+ case 0x0 ... 0x4:
+ return BOOT_DEVICE_SPI;
+ case 0x5 ... 0x7:
+ return BOOT_DEVICE_I2C;
+ }
+ break;
+ /* SD/eSD: 8.5.3, Table 8-15 */
+ case 0x4:
+ case 0x5:
+ return BOOT_DEVICE_MMC1;
+ /* MMC/eMMC: 8.5.3 */
+ case 0x6:
+ case 0x7:
+ return BOOT_DEVICE_MMC1;
+ /* NAND Flash: 8.5.2 */
+ case 0x8 ... 0xf:
+ return BOOT_DEVICE_NAND;
+ }
+ return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ /* for MMC return either RAW or FAT mode */
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ break;
+ default:
+ puts(spl: ERROR: unsupported device\n);
+ hang();
+ }
+}
+#endif
--
1.8.3.2
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[U-Boot] [PATCH v3 02/11] spl: nand: add support for mxs nand
This utilizes existing mxs_nand support layer to provide a method to load an
image off nand for SPL. The flash device will be detected in order to support
multiple flash devices instead of having layout hard coded at build time.
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- removed NAND_NCE and NAND_CTRL_CHANGE unused by mxc_nand.c
- return specific error types on errors
- remove register keyword - let compiler do optimizations
v2:
- remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base
and nand_bbt to bring SPL down in size. This reduced codesize by about 32k
where now mxs_spl_nand is about 12k total.
---
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/mxs_nand_spl.c | 231
2 files changed, 232 insertions(+)
create mode 100644 drivers/mtd/nand/mxs_nand_spl.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 02b149c..de5b461 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -65,5 +65,6 @@ else # minimal SPL drivers
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
+obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
endif # drivers
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
new file mode 100644
index 000..78ca32c
--- /dev/null
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include nand.h
+#include malloc.h
+
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
+int column, int page_addr)
+{
+ register struct nand_chip *chip = mtd-priv;
+ u32 timeo, time_start;
+
+ /* write out the command to the device */
+ chip-cmd_ctrl(mtd, command, NAND_CLE);
+
+ /* Serially input address */
+ if (column != -1) {
+ chip-cmd_ctrl(mtd, column, NAND_ALE);
+ chip-cmd_ctrl(mtd, column 8, NAND_ALE);
+ }
+ if (page_addr != -1) {
+ chip-cmd_ctrl(mtd, page_addr, NAND_ALE);
+ chip-cmd_ctrl(mtd, page_addr 8, NAND_ALE);
+ /* One more address cycle for devices 128MiB */
+ if (chip-chipsize (128 20))
+ chip-cmd_ctrl(mtd, page_addr 16, NAND_ALE);
+ }
+ chip-cmd_ctrl(mtd, NAND_CMD_NONE, 0);
+
+ if (command == NAND_CMD_READ0) {
+ chip-cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE);
+ chip-cmd_ctrl(mtd, NAND_CMD_NONE, 0);
+ }
+
+ /* wait for nand ready */
+ ndelay(100);
+ timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ time_start = get_timer(0);
+ while (get_timer(time_start) timeo) {
+ if (chip-dev_ready(mtd))
+ break;
+ }
+}
+
+static int mxs_flash_ident(struct mtd_info *mtd)
+{
+ register struct nand_chip *chip = mtd-priv;
+ int i;
+ u8 mfg_id, dev_id;
+ u8 id_data[8];
+ struct nand_onfi_params *p = chip-onfi_params;
+
+ /* Reset the chip */
+ chip-cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+ /* Send the command for reading device ID */
+ chip-cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+ /* Read manufacturer and device IDs */
+ mfg_id = chip-read_byte(mtd);
+ dev_id = chip-read_byte(mtd);
+
+ /* Try again to make sure */
+ chip-cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+ for (i = 0; i 8; i++)
+ id_data[i] = chip-read_byte(mtd);
+ if (id_data[0] != mfg_id || id_data[1] != dev_id) {
+ printf(second ID read did not match);
+ return -1;
+ }
+ debug(0x%02x:0x%02x , mfg_id, dev_id);
+
+ /* read ONFI */
+ chip-onfi_version = 0;
+ chip-cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+ if (chip-read_byte(mtd) != 'O' || chip-read_byte(mtd) != 'N' ||
+ chip-read_byte(mtd) != 'F' || chip-read_byte(mtd) != 'I') {
+ return -2;
+ }
+
+ /* we have ONFI, probe it */
+ chip-cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+ chip-read_buf(mtd, (uint8_t *)p, sizeof(*p));
+ mtd-name = p-model;
+ mtd-writesize = le32_to_cpu(p-byte_per_page);
+ mtd-erasesize = le32_to_cpu(p-pages_per_block) * mtd-writesize;
+ mtd-oobsize = le16_to_cpu(p-spare_bytes_per_page);
+ chip-chipsize = le32_to_cpu(p-blocks_per_lun);
+ chip-chipsize *= (uint64_t)mtd-erasesize * p-lun_count;
+ /* Calculate the address shift from the page size */
+ chip-page_shift = ffs(mtd-writesize) - 1;
+ chip-phys_erase_shift = ffs(mtd-erasesize) - 1;
+ /* Convert chipsize to number of pages
[U-Boot] [PATCH v3 03/11] mx6: add common SPL configuration
Add a common header which can hopefully be shared amon imx6 SPL users Signed-off-by: Tim Harvey thar...@gateworks.com Acked-by: Stefano Babic sba...@denx.de Acked-by: Nikita Kiryanov nik...@compulab.co.il --- v3: - fixed typo s/IMX6SLD/IMX6SDL - add acks from Stefano and Nikita v2: - adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD --- include/configs/imx6_spl.h | 71 ++ 1 file changed, 71 insertions(+) create mode 100644 include/configs/imx6_spl.h diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h new file mode 100644 index 000..6fdc438 --- /dev/null +++ b/include/configs/imx6_spl.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey thar...@gateworks.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __IMX6_SPL_CONFIG_H +#define __IMX6_SPL_CONFIG_H + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_FRAMEWORK + +/* + * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: + * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091 + * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well + * - BOOT ROM stack is at 0x0091FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + *IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to + *fit between 0x00907000 and 0x00918000. + * - Additionally the BOOT ROM loads what they consider the firmware image + *which consists of a 4K header in front of us that contains the IVT, DCD + *and some padding thus 'our' max size is really 0x00908000 - 0x00918000 + *or 64KB + */ +#define CONFIG_SPL_LDSCRIPTarch/arm/cpu/armv7/omap-common/u-boot-spl.lds +#define CONFIG_SPL_TEXT_BASE 0x00908000 +#define CONFIG_SPL_MAX_SIZE(64 * 1024) +#define CONFIG_SPL_START_S_PATHarch/arm/cpu/armv7 +#define CONFIG_SPL_STACK 0x0091FFB8 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* NAND support */ +#if defined(CONFIG_SPL_NAND_SUPPORT) +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_DMA_SUPPORT +#endif + +/* MMC support */ +#if defined(CONFIG_SPL_MMC_SUPPORT) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR138 /* offset 69KB */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) +#endif + +/* SATA support */ +#if defined(CONFIG_SPL_SATA_SUPPORT) +#define CONFIG_SPL_SATA_BOOT_DEVICE0 +#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 +#endif + +/* Define the payload for FAT/EXT support */ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME u-boot.img +#define CONFIG_SPL_LIBDISK_SUPPORT +#endif + +#define CONFIG_SPL_BSS_START_ADDR 0x1820 +#define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START0x1830 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB */ +#define CONFIG_SYS_TEXT_BASE 0x1780 +#endif + +#endif -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 06/11] mx6: add structs for mmdc and ddr iomux registers
Add memory-mapped structures for MMDC iomux and configuration. Note that
the MMDC configuration registers are common between the IMX6DQ
(IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) the iomux
register addresses differ. This requires two sets of structures.
Add structures to describe DDR3 device information, system information
(memory layout, etc), and MMDC calibration regitsers that can be used to
configure the MMDC dynamically.
We define these structures for SPL builds instead of including mx6q-ddr.h an
mx6dl-ddr.h which use the same namespace and are only useful for imximage cf
files.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- moved portions into following patch
v2:
- split out from original mmdc configuration patch
- only define for SPL build
- do not include mx6q-ddr.h and mx6dl-ddr.h for SPL build - these use the
same namespace and are only useful for imximage cfg files
---
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 159
1 file changed, 159 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 43d377a..c2a31d2 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -6,6 +6,7 @@
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_MX6Q
#include mx6q-ddr.h
#else
@@ -15,6 +16,164 @@
#error Please select cpu
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
+#else
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
+ u32 mdscr;
+ u32 mdref;
+ u32 res1[2];
+ u32 mdrwd;
+ u32 mdor;
+ u32 res2[3];
+ u32 mdasp;
+ u32 res3[240];
+ u32 mapsr;
+ u32 res4[254];
+ u32 mpzqhwctrl;
+ u32 res5[2];
+ u32 mpwldectrl0;
+ u32 mpwldectrl1;
+ u32 res6;
+ u32 mpodtctrl;
+ u32 mprddqby0dl;
+ u32 mprddqby1dl;
+ u32 mprddqby2dl;
+ u32 mprddqby3dl;
+ u32 res7[4];
+ u32 mpdgctrl0;
+ u32 mpdgctrl1;
+ u32 res8;
+ u32 mprddlctl;
+ u32 res9;
+ u32 mpwrdlctl;
+ u32 res10[25];
+ u32 mpmur0;
+};
+
+/*
+ * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
+ */
+#define MX6DQ_IOM_DDR_BASE 0x020e0500
+struct mx6dq_iomux_ddr_regs {
+ u32 res1[3];
+ u32 dram_sdqs5;
+ u32 dram_dqm5;
+ u32 dram_dqm4;
+ u32 dram_sdqs4;
+ u32 dram_sdqs3;
+ u32 dram_dqm3;
+ u32 dram_sdqs2;
+ u32 dram_dqm2;
+ u32 res2[16];
+ u32 dram_cas;
+ u32 res3[2];
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res4[2];
+ u32 dram_sdclk_0;
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdclk_1;
+ u32 dram_sdcke1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 res5;
+ u32 dram_sdqs0;
+ u32 dram_dqm0;
+ u32 dram_sdqs1;
+ u32 dram_dqm1;
+ u32 dram_sdqs6;
+ u32 dram_dqm6;
+ u32 dram_sdqs7;
+ u32 dram_dqm7;
+};
+
+#define MX6DQ_IOM_GRP_BASE 0x020e0700
+struct mx6dq_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 res2;
+ u32 grp_ddrpke;
+ u32 res3[6];
+ u32 grp_ddrmode;
+ u32 res4[3];
+ u32 grp_b0ds;
+ u32 grp_b1ds;
+ u32 grp_ctlds;
+ u32 res5;
+ u32 grp_b2ds;
+ u32 grp_ddr_type;
+ u32 grp_b3ds;
+ u32 grp_b4ds;
+ u32 grp_b5ds;
+ u32 grp_b6ds;
+};
+
+#define MX6SDL_IOM_DDR_BASE 0x020e0400
+struct mx6sdl_iomux_ddr_regs {
+ u32 res1[25];
+ u32 dram_cas;
+ u32 res2[2];
+ u32 dram_dqm0;
+ u32 dram_dqm1;
+ u32 dram_dqm2;
+ u32 dram_dqm3;
+ u32 dram_dqm4;
+ u32 dram_dqm5;
+ u32 dram_dqm6;
+ u32 dram_dqm7;
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res3[2];
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdcke1;
+ u32 dram_sdclk_0;
+ u32 dram_sdclk_1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 dram_sdqs0;
+ u32 dram_sdqs1;
+ u32 dram_sdqs2;
+ u32 dram_sdqs3;
+ u32 dram_sdqs4;
+ u32 dram_sdqs5;
+ u32 dram_sdqs6;
+ u32 dram_sdqs7;
+};
+
+#define MX6SDL_IOM_GRP_BASE 0x020e0700
+struct mx6sdl_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 grp_ddrpke;
+ u32 res2[2];
+ u32 grp_ddrmode;
+ u32 grp_b0ds;
+ u32 res3;
+ u32 grp_ctlds;
+ u32 grp_b1ds;
+ u32 grp_ddr_type;
+ u32 grp_b2ds;
+ u32 grp_b3ds;
+ u32 grp_b4ds;
+ u32 grp_b5ds;
+ u32 res4;
+ u32
[U-Boot] [PATCH v3 07/11] mx6: add mmdc configuration for MX6Q/MX6DL
Add functions for configuring iomux based on board-specific regs and
for configuring mmdc based on board-specific and chip-specific data.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- added ifdef's around cpu specific iocfg functions for code-reduction with
single-variant board configs
- moved portions from previous patch here
- added check for IMX6D
v2:
- split out mmdc and iomux structs into separate patch
---
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/ddr.c| 473
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 72 +
3 files changed, 546 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..6dc9f8e 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -8,4 +8,5 @@
#
obj-y := soc.o clock.o
+obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
new file mode 100644
index 000..e64fa91
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -0,0 +1,473 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/types.h
+#include asm/arch/mx6-ddr.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+#include asm/types.h
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+/* Configure MX6DQ mmdc iomux */
+void mx6dq_dram_iocfg(unsigned width,
+ const struct mx6dq_iomux_ddr_regs *ddr,
+ const struct mx6dq_iomux_grp_regs *grp)
+{
+ volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
+
+ /* DDR IO Type */
+ mx6_grp_iomux-grp_ddr_type = grp-grp_ddr_type;
+ mx6_grp_iomux-grp_ddrpke = grp-grp_ddrpke;
+
+ /* Clock */
+ mx6_ddr_iomux-dram_sdclk_0 = ddr-dram_sdclk_0;
+ mx6_ddr_iomux-dram_sdclk_1 = ddr-dram_sdclk_1;
+
+ /* Address */
+ mx6_ddr_iomux-dram_cas = ddr-dram_cas;
+ mx6_ddr_iomux-dram_ras = ddr-dram_ras;
+ mx6_grp_iomux-grp_addds = grp-grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux-dram_reset = ddr-dram_reset;
+ mx6_ddr_iomux-dram_sdcke0 = ddr-dram_sdcke0;
+ mx6_ddr_iomux-dram_sdcke1 = ddr-dram_sdcke1;
+ mx6_ddr_iomux-dram_sdba2 = ddr-dram_sdba2;
+ mx6_ddr_iomux-dram_sdodt0 = ddr-dram_sdodt0;
+ mx6_ddr_iomux-dram_sdodt1 = ddr-dram_sdodt1;
+ mx6_grp_iomux-grp_ctlds = grp-grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux-grp_ddrmode_ctl = grp-grp_ddrmode_ctl;
+ mx6_ddr_iomux-dram_sdqs0 = ddr-dram_sdqs0;
+ mx6_ddr_iomux-dram_sdqs1 = ddr-dram_sdqs1;
+ if (width = 32) {
+ mx6_ddr_iomux-dram_sdqs2 = ddr-dram_sdqs2;
+ mx6_ddr_iomux-dram_sdqs3 = ddr-dram_sdqs3;
+ }
+ if (width = 64) {
+ mx6_ddr_iomux-dram_sdqs4 = ddr-dram_sdqs4;
+ mx6_ddr_iomux-dram_sdqs5 = ddr-dram_sdqs5;
+ mx6_ddr_iomux-dram_sdqs6 = ddr-dram_sdqs6;
+ mx6_ddr_iomux-dram_sdqs7 = ddr-dram_sdqs7;
+ }
+
+ /* Data */
+ mx6_grp_iomux-grp_ddrmode = grp-grp_ddrmode;
+ mx6_grp_iomux-grp_b0ds = grp-grp_b0ds;
+ mx6_grp_iomux-grp_b1ds = grp-grp_b1ds;
+ if (width = 32) {
+ mx6_grp_iomux-grp_b2ds = grp-grp_b2ds;
+ mx6_grp_iomux-grp_b3ds = grp-grp_b3ds;
+ }
+ if (width = 64) {
+ mx6_grp_iomux-grp_b4ds = grp-grp_b4ds;
+ mx6_grp_iomux-grp_b5ds = grp-grp_b5ds;
+ mx6_grp_iomux-grp_b6ds = grp-grp_b6ds;
+ mx6_grp_iomux-grp_b7ds = grp-grp_b7ds;
+ }
+ mx6_ddr_iomux-dram_dqm0 = ddr-dram_dqm0;
+ mx6_ddr_iomux-dram_dqm1 = ddr-dram_dqm1;
+ if (width = 32) {
+ mx6_ddr_iomux-dram_dqm2 = ddr-dram_dqm2;
+ mx6_ddr_iomux-dram_dqm3 = ddr-dram_dqm3;
+ }
+ if (width = 64) {
+ mx6_ddr_iomux-dram_dqm4 = ddr-dram_dqm4;
+ mx6_ddr_iomux-dram_dqm5 = ddr-dram_dqm5;
+ mx6_ddr_iomux-dram_dqm6 = ddr-dram_dqm6;
+ mx6_ddr_iomux-dram_dqm7 = ddr-dram_dqm7;
+ }
+}
+#endif
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+/* Configure MX6SDL mmdc iomux */
+void mx6sdl_dram_iocfg(unsigned width,
+ const struct mx6sdl_iomux_ddr_regs *ddr,
+ const struct mx6sdl_iomux_grp_regs *grp)
+{
+ volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux
[U-Boot] [PATCH v3 11/11] imx: ventana: switch to SPL
Switch to an SPL image. The SPL for Ventana does the following: - setup i2c and read the factory programmed EEPROM to obtain DRAM config and model for board-specific calibration data - configure DRAM per CPU/size/layout/devices/calibration - load u-boot.img from NAND and jump to it This allows for a single SPL+u-boot.img to replace the previous multiple boa configurations. Signed-off-by: Tim Harvey thar...@gateworks.com --- v3: - re-ordered calls in board_init_f v2: - remove missing/unnecessary include - revert mtdparts change - use imx_ddr_size() which uses MMDC configuration to determine mem size explicitly - add support for MX6SOLO and MX6DUAL - set CS0_END for 4GB so get_ram_size() works - updated DDR3 calibration values for ventana boards - fixed build issue - only compile spl if doing spl build - fixed line length issue in README - remove CONFIG_SPL* conditions and conditionally compile instead - removed prints for CPU type and DRAM size/width - uboot will print these later - removed unused gw_ventana_spl.cfg - use common read_eeprom function - added MMC support to SPL --- board/gateworks/gw_ventana/Makefile | 1 + board/gateworks/gw_ventana/README | 92 +++--- board/gateworks/gw_ventana/gw_ventana.c | 10 +- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 419 boards.cfg | 6 +- include/configs/gw_ventana.h| 11 + 7 files changed, 498 insertions(+), 56 deletions(-) create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile index 03bd1fd..33a1788 100644 --- a/board/gateworks/gw_ventana/Makefile +++ b/board/gateworks/gw_ventana/Makefile @@ -7,4 +7,5 @@ # obj-y := gw_ventana.o gsc.o eeprom.o +obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README index 9e697d6..888657c 100644 --- a/board/gateworks/gw_ventana/README +++ b/board/gateworks/gw_ventana/README @@ -3,53 +3,81 @@ U-Boot for the Gateworks Ventana Product Family boards This file contains information for the port of U-Boot to the Gateworks Ventana Product family boards. -1. Boot source, boot from NAND +1. Secondary Program Loader (SPL) +- + +The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading +an executable image from various boot devices. + +The Gateworks Ventana board config uses an SPL build configuration. This +will build the following artifacts from u-boot source: + - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program + Loader) boots. This detects CPU/DRAM configuration, configures + The DRAM controller, loads u-boot.img from the detected boot device, + and jumps to it. As this is booted from the PPL, it has an IVT/DCD + table. + - u-boot.img - The main u-boot core which is u-boot.bin with a image header. + + +2. Build + + +To build U-Boot for the Gateworks Ventana product family: + + make gwventana_config + make + + +3. Boot source, boot from NAND -- The i.MX6 BOOT ROM expects some structures that provide details of NAND layout and bad block information (referred to as 'bootstreams') which are replicated -multiple times in NAND. The number of replications is configurable through -board strapping options and eFUSE settings. The Freescale 'kobs-ng' -application from the Freescale LTIB BSP, which runs under Linux, must be used -to program the bootstream in order to setup the replicated headers correctly. +multiple times in NAND. The number of replications and their spacing (referred +to as search stride) is configurable through board strapping options and/or +eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In +addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two +copies of a bootloader in flash in the case that a bad block has corrupted one. +The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs +under Linux and operates on an MTD partition, must be used to program the +bootstream in order to setup this flash structure correctly. The Gateworks Ventana boards with NAND flash have been factory programmed such that their eFUSE settings expect 2 copies of the boostream (this is specified by providing kobs-ng with the --search_exponent=1 argument). Once in -Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream +Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL with: -kobs-ng init -v -x --search_exponent=1 u-boot.imx +kobs-ng init -v -x --search_exponent=1 SPL -The kobs-ng application uses an imximage (u-boot.imx) which contains the -Image Vector Table (IVT) and Device Configuration Data (DCD) structures that -the i.MX6
[U-Boot] [PATCH v3 09/11] imx: ventana: split read_eeprom into standalone file
Split the read_eeprom function out so that it can be shared (ie with SPL)
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- no changes
v2:
- new patch in series
---
board/gateworks/gw_ventana/Makefile | 2 +-
board/gateworks/gw_ventana/eeprom.c | 89 +
board/gateworks/gw_ventana/gw_ventana.c | 89 +
board/gateworks/gw_ventana/ventana_eeprom.h | 11
4 files changed, 102 insertions(+), 89 deletions(-)
create mode 100644 board/gateworks/gw_ventana/eeprom.c
diff --git a/board/gateworks/gw_ventana/Makefile
b/board/gateworks/gw_ventana/Makefile
index e8dab89..03bd1fd 100644
--- a/board/gateworks/gw_ventana/Makefile
+++ b/board/gateworks/gw_ventana/Makefile
@@ -6,5 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := gw_ventana.o gsc.o
+obj-y := gw_ventana.o gsc.o eeprom.o
diff --git a/board/gateworks/gw_ventana/eeprom.c
b/board/gateworks/gw_ventana/eeprom.c
new file mode 100644
index 000..e90186e
--- /dev/null
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+
+#include gsc.h
+#include ventana_eeprom.h
+
+/* read ventana EEPROM, check for validity, and return baseboard type */
+int
+read_eeprom(int bus, struct ventana_board_info *info)
+{
+ int i;
+ int chksum;
+ char baseboard;
+ int type;
+ unsigned char *buf = (unsigned char *)info;
+
+ memset(info, 0, sizeof(*info));
+
+ /*
+* On a board with a missing/depleted backup battery for GSC, the
+* board may be ready to probe the GSC before its firmware is
+* running. We will wait here indefinately for the GSC/EEPROM.
+*/
+ while (1) {
+ if (0 == i2c_set_bus_num(bus)
+ 0 == i2c_probe(GSC_EEPROM_ADDR))
+ break;
+ mdelay(1);
+ }
+
+ /* read eeprom config section */
+ if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
+ puts(EEPROM: Failed to read EEPROM\n);
+ info-model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* sanity checks */
+ if (info-model[0] != 'G' || info-model[1] != 'W') {
+ puts(EEPROM: Invalid Model in EEPROM\n);
+ info-model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* validate checksum */
+ for (chksum = 0, i = 0; i sizeof(*info)-2; i++)
+ chksum += buf[i];
+ if ((info-chksum[0] != chksum8) ||
+ (info-chksum[1] != (chksum0xff))) {
+ puts(EEPROM: Failed EEPROM checksum\n);
+ info-model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* original GW5400-A prototype */
+ baseboard = info-model[3];
+ if (strncasecmp((const char *)info-model, GW5400-A, 8) == 0)
+ baseboard = '0';
+
+ switch (baseboard) {
+ case '0': /* original GW5400-A prototype */
+ type = GW54proto;
+ break;
+ case '1':
+ type = GW51xx;
+ break;
+ case '2':
+ type = GW52xx;
+ break;
+ case '3':
+ type = GW53xx;
+ break;
+ case '4':
+ type = GW54xx;
+ break;
+ default:
+ printf(EEPROM: Unknown model in EEPROM: %s\n, info-model);
+ type = GW_UNKNOWN;
+ break;
+ }
+ return type;
+}
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 2113740..3b6bc01 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -81,15 +81,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static struct ventana_board_info ventana_info;
-enum {
- GW54proto, /* original GW5400-A prototype */
- GW51xx,
- GW52xx,
- GW53xx,
- GW54xx,
- GW_UNKNOWN,
-};
-
int board_type;
/* UART1: Function varies per baseboard */
@@ -368,84 +359,6 @@ int board_eth_init(bd_t *bis)
return 0;
}
-/* read ventana EEPROM, check for validity, and return baseboard type */
-static int
-read_eeprom(void)
-{
- int i;
- int chksum;
- char baseboard;
- int type;
- struct ventana_board_info *info = ventana_info;
- unsigned char *buf = (unsigned char *)ventana_info;
-
- memset(info, 0, sizeof(ventana_info));
-
- /*
-* On a board with a missing/depleted backup battery for GSC, the
-* board may be ready to probe the GSC before its firmware is
-* running. We will wait here indefinately for the GSC/EEPROM.
-*/
- while (1) {
- if (0 == i2c_set_bus_num(I2C_GSC)
- 0 == i2c_probe(GSC_EEPROM_ADDR
[U-Boot] [PATCH v3 08/11] imx: iomux: add macros to setup iomux for multiple SoC types
Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list
and add macros for declaring the pad_list that take into account the
SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL
iomux).
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- remove commit msg 2nd paragrap about prior approaches
- re-work to avoid needing to add a new function by making
imx_iomux_v3_setup_multiple_pads more intelligent and adding macros
that depend on SoC type support
v2:
- moved macros for declaring and using structs for array variant
- removed non-related whitespace cleanup
---
arch/arm/imx-common/iomux-v3.c | 16 ++--
arch/arm/include/asm/imx-common/iomux-v3.h | 25 +
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b59b802..9bd8dfb 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -11,6 +11,7 @@
#include common.h
#include asm/io.h
#include asm/arch/imx-regs.h
+#include asm/arch/sys_proto.h
#include asm/imx-common/iomux-v3.h
static void *base = (void *)IOMUXC_BASE_ADDR;
@@ -46,12 +47,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
#endif
}
+/* configures a list of pads within declared with IOMUX_PADS macro */
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count)
{
iomux_v3_cfg_t const *p = pad_list;
+ int stride;
int i;
- for (i = 0; i count; i++)
- imx_iomux_v3_setup_pad(*p++);
+#if defined(CONFIG_MX6QDL)
+ stride = 2;
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ p += 1;
+#else
+ stride = 1;
+#endif
+ for (i = 0; i count; i++) {
+ imx_iomux_v3_setup_pad(*p);
+ p += stride;
+ }
}
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
b/arch/arm/include/asm/imx-common/iomux-v3.h
index dec11a1..3b0759a 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -170,4 +170,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def);\
+}
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
+
#endif /* __MACH_IOMUX_V3_H__*/
--
1.8.3.2
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[U-Boot] [PATCH v3 10/11] imx: ventana: auto-configure for IMX6Q vs IMX6DL
use the new iomux function and a macros to create a multi-dimensional array
of iomux values without duplicating the defintions.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- replace use of imx_iomux_v3_setup_multiple_pads_array with
imx_iomux_v3_setup_multiple_pads
v2:
- use macros that have been moved to iomux-v3.h
---
board/gateworks/gw_ventana/gw_ventana.c | 492
1 file changed, 310 insertions(+), 182 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 3b6bc01..4ae458f 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -85,109 +85,149 @@ int board_type;
/* UART1: Function varies per baseboard */
iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
/* UART2: Serial Console */
iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1: GSC */
-struct i2c_pads_info i2c_pad_info0 = {
+struct i2c_pads_info mx6q_i2c_pad_info0 = {
.scl = {
- .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
- .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
-struct i2c_pads_info i2c_pad_info1 = {
+struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
/* I2C3: Misc/Expansion */
-struct i2c_pads_info i2c_pad_info2 = {
+struct i2c_pads_info mx6q_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info2 = {
.scl = {
- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC
[U-Boot] [PATCH v2] dwc_ahsata: return failure for MX6 if not IMX6Q/IMX6D
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure
instead of attempting a memory access that results in a data abort and reset.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v2:
- remove print as this condition isn't really an error just something not
possible
---
drivers/block/dwc_ahsata.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 3569214..15d65d7 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -17,6 +17,7 @@
#include asm/io.h
#include linux/bitops.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
#include dwc_ahsata.h
struct sata_port_regs {
@@ -558,6 +559,10 @@ int init_sata(int dev)
u32 linkmap;
struct ahci_probe_ent *probe_ent = NULL;
+#if defined(CONFIG_MX6)
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+#endif
if (dev 0 || dev (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
printf(The sata index %d is out of ranges\n\r, dev);
return -1;
--
1.8.3.2
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[U-Boot] [PATCH] imx: sata: return failure if not IMX6Q/IMX6D
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return
instead of configuring the SATA clock and GPR13 registers.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
arch/arm/imx-common/sata.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index 2e69486..c10dd28 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -8,13 +8,18 @@
#include asm/arch/iomux.h
#include asm/io.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ int ret;
- int ret = enable_sata_clock();
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+
+ ret = enable_sata_clock();
if (ret)
return ret;
--
1.8.3.2
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Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On Wed, May 7, 2014 at 2:29 AM, Stefano Babic sba...@denx.de wrote:
Hi Tim,
On 06/05/2014 20:18, Tim Harvey wrote:
Stefano / York,
While preparing for a v3 patch series of my IMX6 SPL bootloader, I
find that commit dec1861be90c948ea9fb771927d3d26a994d2e20 [1] breaks
the above code because gd is now needed within setup_i2c.
I've always been a bit fuzzy on the order of the above calls so I dug
through the code and I think I understand things better. Please
correct any wrong assumptions I'm making below:
- assignment to gd should 'always' be first (before anything needs
it, so why not do it first)
- arch_cpu_init() should go next as this sets up very low level
CPU/SoC resources (in this case AIPS config and watchdog disable)
- board_early_init_f() should be next as that sets up any board-specific
iomux
- any additional iomux necessary for SPL should go next (I take care
of i2c iomux and setup here)
- timer_init() next as you need a timer for UART and mxc i2c (for
delays and busy checks)
- preloader_console_init() next as we are now able to send something
over the UART (this gives me early debug for sdram config now too!)
- sdram setup goes next
- after sdram is setup, the bss can be cleared
- board_init_r - pass over to generic SPL code which will load/call
an image based on boot device
I think your analyses is correct.
So, if the above is correct, I should rework the above function as follows:
void board_init_f(ulong dummy)
{
struct ventana_board_info ventana_info;
int board_model;
/* Set global data pointer. */
gd = gdata;
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* read/validate EEPROM info to determine board model and SDRAM cfg
*/
board_model = read_eeprom(I2C_GSC, ventana_info);
/* provide some some default: 32bit 128MB */
if (GW_UNKNOWN == board_model) {
ventana_info.sdram_width = 2;
ventana_info.sdram_size = 3;
}
/* configure MMDC for SDRAM width/size and per-model calibration */
spl_dram_init(8 ventana_info.sdram_width,
16 ventana_info.sdram_size,
board_model);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
It seems reasonable, go on this way.
Regards,
Stefano
Stefano,
I've just found that one of my boards fails with the above re-org.
Strangely a board which has the same mem layout, mem width/size, CPU
and nand does not fail.
If I make the following change:
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Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On Tue, May 13, 2014 at 9:58 PM, Tim Harvey thar...@gateworks.com wrote:
On Wed, May 7, 2014 at 2:29 AM, Stefano Babic sba...@denx.de wrote:
Hi Tim,
On 06/05/2014 20:18, Tim Harvey wrote:
Stefano / York,
While preparing for a v3 patch series of my IMX6 SPL bootloader, I
find that commit dec1861be90c948ea9fb771927d3d26a994d2e20 [1] breaks
the above code because gd is now needed within setup_i2c.
I've always been a bit fuzzy on the order of the above calls so I dug
through the code and I think I understand things better. Please
correct any wrong assumptions I'm making below:
- assignment to gd should 'always' be first (before anything needs
it, so why not do it first)
- arch_cpu_init() should go next as this sets up very low level
CPU/SoC resources (in this case AIPS config and watchdog disable)
- board_early_init_f() should be next as that sets up any board-specific
iomux
- any additional iomux necessary for SPL should go next (I take care
of i2c iomux and setup here)
- timer_init() next as you need a timer for UART and mxc i2c (for
delays and busy checks)
- preloader_console_init() next as we are now able to send something
over the UART (this gives me early debug for sdram config now too!)
- sdram setup goes next
- after sdram is setup, the bss can be cleared
- board_init_r - pass over to generic SPL code which will load/call
an image based on boot device
I think your analyses is correct.
So, if the above is correct, I should rework the above function as follows:
void board_init_f(ulong dummy)
{
struct ventana_board_info ventana_info;
int board_model;
/* Set global data pointer. */
gd = gdata;
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* read/validate EEPROM info to determine board model and SDRAM cfg
*/
board_model = read_eeprom(I2C_GSC, ventana_info);
/* provide some some default: 32bit 128MB */
if (GW_UNKNOWN == board_model) {
ventana_info.sdram_width = 2;
ventana_info.sdram_size = 3;
}
/* configure MMDC for SDRAM width/size and per-model calibration */
spl_dram_init(8 ventana_info.sdram_width,
16 ventana_info.sdram_size,
board_model);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
It seems reasonable, go on this way.
Regards,
Stefano
Stefano,
I've just found that one of my boards fails with the above re-org.
Strangely a board which has the same mem layout, mem width/size, CPU
and nand does not fail.
If I make the following change:
(sorry, accidentally fat fingered and sent instead of pasting). I'll continue:
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -380,9 +380,6 @@ void board_init_f(ulong dummy)
*/
memset((void *)gd, 0, sizeof(struct global_data));
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
@@ -407,6 +404,9 @@ void board_init_f(ulong dummy)
16 ventana_info.sdram_size,
board_model);
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
Things start to work properly. I took a look at arch_cpu_init() and
the call that really needs to be moved (or just duplicated here) is
mxs_dma_init() to start APBH DMA. The failure mode of the one board is
that apparently it hangs while loading u-boot.img from NAND (which of
course uses mxs_nand and thus APBH DMA).
Anyone know what's going on here and why mxs_dma_init() needs to be
called after MMDC setup, and before clearing the BSS? I don't like
having magic placement of functions without understanding why.
Thanks,
Tim
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Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On Tue, May 13, 2014 at 10:03 PM, Tim Harvey thar...@gateworks.com wrote:
On Tue, May 13, 2014 at 9:58 PM, Tim Harvey thar...@gateworks.com wrote:
On Wed, May 7, 2014 at 2:29 AM, Stefano Babic sba...@denx.de wrote:
Hi Tim,
On 06/05/2014 20:18, Tim Harvey wrote:
Stefano / York,
While preparing for a v3 patch series of my IMX6 SPL bootloader, I
find that commit dec1861be90c948ea9fb771927d3d26a994d2e20 [1] breaks
the above code because gd is now needed within setup_i2c.
I've always been a bit fuzzy on the order of the above calls so I dug
through the code and I think I understand things better. Please
correct any wrong assumptions I'm making below:
- assignment to gd should 'always' be first (before anything needs
it, so why not do it first)
- arch_cpu_init() should go next as this sets up very low level
CPU/SoC resources (in this case AIPS config and watchdog disable)
- board_early_init_f() should be next as that sets up any board-specific
iomux
- any additional iomux necessary for SPL should go next (I take care
of i2c iomux and setup here)
- timer_init() next as you need a timer for UART and mxc i2c (for
delays and busy checks)
- preloader_console_init() next as we are now able to send something
over the UART (this gives me early debug for sdram config now too!)
- sdram setup goes next
- after sdram is setup, the bss can be cleared
- board_init_r - pass over to generic SPL code which will load/call
an image based on boot device
I think your analyses is correct.
So, if the above is correct, I should rework the above function as
follows:
void board_init_f(ulong dummy)
{
struct ventana_board_info ventana_info;
int board_model;
/* Set global data pointer. */
gd = gdata;
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* read/validate EEPROM info to determine board model and SDRAM
cfg */
board_model = read_eeprom(I2C_GSC, ventana_info);
/* provide some some default: 32bit 128MB */
if (GW_UNKNOWN == board_model) {
ventana_info.sdram_width = 2;
ventana_info.sdram_size = 3;
}
/* configure MMDC for SDRAM width/size and per-model calibration
*/
spl_dram_init(8 ventana_info.sdram_width,
16 ventana_info.sdram_size,
board_model);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
It seems reasonable, go on this way.
Regards,
Stefano
Stefano,
I've just found that one of my boards fails with the above re-org.
Strangely a board which has the same mem layout, mem width/size, CPU
and nand does not fail.
If I make the following change:
(sorry, accidentally fat fingered and sent instead of pasting). I'll
continue:
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -380,9 +380,6 @@ void board_init_f(ulong dummy)
*/
memset((void *)gd, 0, sizeof(struct global_data));
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
@@ -407,6 +404,9 @@ void board_init_f(ulong dummy)
16 ventana_info.sdram_size,
board_model);
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
Things start to work properly. I took a look at arch_cpu_init() and
the call that really needs to be moved (or just duplicated here) is
mxs_dma_init() to start APBH DMA. The failure mode of the one board is
that apparently it hangs while loading u-boot.img from NAND (which of
course uses mxs_nand and thus APBH DMA).
Anyone know what's going on here and why mxs_dma_init() needs to be
called after MMDC setup, and before clearing the BSS? I don't like
having magic placement of functions without understanding why.
Thanks,
Tim
I figured this one out - it has nothing to do with the order of
calling arch_cpu_init() its that the MMDC isn't always 'ready' by the
time the BSS is cleared and thus in my failure case the BSS isn't
getting entirely cleared which causes the spl_image global var to not
be cleared as expected and triggers an invalid codepath. I will update
the mmdc config patch when I find the right solution.
Sorry for the noise.
Tim
Re: [U-Boot] [PATCH] spl: consolidate arch/arm/include/asm/arch-*/spl.h
On Mon, Apr 28, 2014 at 1:16 AM, Masahiro Yamada
yamad...@jp.panasonic.com wrote:
Hi Tom,
On Fri, 25 Apr 2014 14:52:06 -0400
Tom Rini tr...@ti.com wrote:
On Wed, Apr 16, 2014 at 03:44:36PM +0900, Masahiro Yamada wrote:
arch/arm/include/asm/spl.h requires all SoCs to have
arch/arm/include/asm/arch-*/spl.h.
But many of them just define BOOT_DEVICE_* macros.
Those macros are used in the switch (boot_device) { ... }
statement in common/spl/spl.c.
So they should not be archtecture specific, but described as
a simpile enumeration.
This commit merge most of arch/arm/include/asm/arch-*/spl.h
into arch/arm/include/asm/spl.h.
With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h
will be merged, while I am not sure about OMAP and Exynos.
The problem is that on TI platforms these values have meaning defined by
ROM (which changes occasionally). When ROM starts us up, we get a
little bit of info that says I found and loaded you on So while
we could move towards moving BOOT_DEVICE_FOO into spl.h we'd need in
arch/arm/cpu/armv7/omap-common/boot-common.c some logic to translate
from ROM numbers to U-Boot numbers.
Could you apply my patch first and fix the OMAP translation logic lator?
I want to stop duplication of similar spl.h headers.
Best Regards
Masahiro Yamada
Tom / Masahiro,
Any update on this? This is a very useful cleanup and there is at
least one pending patch series that depend on it.
Regards,
Tim
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Re: [U-Boot] [PATCH v3 00/11] mx6: SPL NAND support
On Wed, May 7, 2014 at 10:16 PM, Tim Harvey thar...@gateworks.com wrote: This series adds some necessary framework for IMX6 SPL support. The series includes support for NAND SPL and has been tested with MMC as well. I have tested this on five differing Ventana baseboards with a variety of memory (32bit 512MB, 32bit 1024MB, 64bit 1024MB) and CPU configurations (IMX6Q, IMX6DL, IMX6S). This is based on top of Mashahiro Yamada's patch that consolidates arch/arm/include/asm/arch-*/spl.h [1] v3: - re-ordered calls in board_init_f - replace imx_iomux_v3_setup_multiple_pads_array with additional intelligence in imx_iomux_v3_setup_multiple_pads - added ifdef's around cpu specific mmdc iocfg functions for code-reduction with single-variant board configs - added checks for IMX6D - added Freescale copyright to boot device support function - fixed typo s/IMX6SLD/IMX6SDL - encorporated cleanups in mxs_nand_spl.c per feedback v2: - use compatible linker script instead of creating new one - remove structure passing data from SPL to u-boot - remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base and nand_bbt to bring SPL down in size. This reduced codesize by about 32k where now mxs_spl_nand is about 12k total - adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD - move boot dev detection into imx-common/spl.c - move macros for using pinmux array into iomux-v3.h - remove missing/unnecessary include - revert mtdparts change - use get_ram_size() to detect memory - add support for MX6SOLO and MX6DUAL - set CS0_END for 4GB so get_ram_size() works - updated DDR3 calibration values for ventana boards - fixed build issue - only compile spl if doing spl build - fixed line length issue in README - remove CONFIG_SPL* conditions and conditionally compile instead - removed prints for CPU type and DRAM size/width - uboot will print these l - removed unused gw_ventana_spl.cfg - use common read_eeprom function - added MMC support to SPL - added Masahiro Yamada's boot mode consolidation patch http://patchwork.ozlabs.org/patch/341817 and rebase on top of it [1] http://patchwork.ozlabs.org/patch/341817/ Tim Harvey (11): SPL: NAND: remove CONFIG_SYS_NAND_PAGE_SIZE SPL: NAND: add support for mxs nand MX6: add common SPL configuration MX6: add boot device support for SPL IMX: add comments and remove unused struct fields MX6: add structs for mmdc and ddr iomux registers MX6: add mmdc configuration for MX6Q/MX6DL IMX: iomux: add macros to setup iomux for multiple SoC types IMX: ventana: split read_eeprom into standalone file IMX: ventana: auto-configure for IMX6Q vs IMX6DL IMX: ventana: switch to SPL arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/ddr.c| 473 ++ arch/arm/imx-common/Makefile| 1 + arch/arm/imx-common/cpu.c | 16 +- arch/arm/imx-common/iomux-v3.c | 16 +- arch/arm/imx-common/spl.c | 81 arch/arm/include/asm/arch-mx6/mx6-ddr.h | 231 +++ arch/arm/include/asm/imx-common/iomux-v3.h | 25 ++ board/gateworks/gw_ventana/Makefile | 3 +- board/gateworks/gw_ventana/README | 92 +++-- board/gateworks/gw_ventana/eeprom.c | 89 + board/gateworks/gw_ventana/gw_ventana.c | 591 +++- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 419 board/gateworks/gw_ventana/ventana_eeprom.h | 11 + boards.cfg | 6 +- common/spl/spl_nand.c | 2 +- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand_spl.c | 231 +++ include/configs/gw_ventana.h| 11 + include/configs/imx6_spl.h | 71 21 files changed, 2047 insertions(+), 339 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c create mode 100644 arch/arm/imx-common/spl.c create mode 100644 board/gateworks/gw_ventana/eeprom.c create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c create mode 100644 drivers/mtd/nand/mxs_nand_spl.c create mode 100644 include/configs/imx6_spl.h -- 1.8.3.2 Stefano, Any comments on this series? I realize you've applied the first one and I'll remove that from any subsequent posts. Regards, Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/11] mx6: SPL NAND support
On Wed, May 21, 2014 at 11:34 PM, Stefano Babic sba...@denx.de wrote: Hi Tim, On 22/05/2014 08:14, Tim Harvey wrote: Stefano, Any comments on this series? I realize you've applied the first one and I'll remove that from any subsequent posts. Right. I think we have a very good point (nice work !) and we are near to merge the patchset. If I am not wrong, you want to post an update for the MMDC config patch, do you ? Yes, I do have an update for that particular patch, but I don't think anyone has commented on that patch either way. I'll go ahead and respond to that thread with my update as that is the only non-submitted change I have. Thanks, Tim Patch 2 should be acked by Scott because it belongs to his area of competence. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 07/11] mx6: add mmdc configuration for MX6Q/MX6DL
- add function for configuring iomux based on board-specific regs
- add function for configuring mmdc based on board-specific and
chip-specific data
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v4:
- added delay following configure to allow ZQ calibration to complete
- update MMDC configuration to match Freescale RM
v3:
- added ifdef's around cpu specific iocfg functions for code-reduction with
single-variant board configs
- moved portions from previous patch here
- added check for IMX6D
v2:
- split out mmdc and iomux structs into separate patch
---
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/ddr.c| 490
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 72 +
3 files changed, 563 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..6dc9f8e 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -8,4 +8,5 @@
#
obj-y := soc.o clock.o
+obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
new file mode 100644
index 000..0434211
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/types.h
+#include asm/arch/mx6-ddr.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+#include asm/types.h
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+/* Configure MX6DQ mmdc iomux */
+void mx6dq_dram_iocfg(unsigned width,
+ const struct mx6dq_iomux_ddr_regs *ddr,
+ const struct mx6dq_iomux_grp_regs *grp)
+{
+ volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
+
+ /* DDR IO Type */
+ mx6_grp_iomux-grp_ddr_type = grp-grp_ddr_type;
+ mx6_grp_iomux-grp_ddrpke = grp-grp_ddrpke;
+
+ /* Clock */
+ mx6_ddr_iomux-dram_sdclk_0 = ddr-dram_sdclk_0;
+ mx6_ddr_iomux-dram_sdclk_1 = ddr-dram_sdclk_1;
+
+ /* Address */
+ mx6_ddr_iomux-dram_cas = ddr-dram_cas;
+ mx6_ddr_iomux-dram_ras = ddr-dram_ras;
+ mx6_grp_iomux-grp_addds = grp-grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux-dram_reset = ddr-dram_reset;
+ mx6_ddr_iomux-dram_sdcke0 = ddr-dram_sdcke0;
+ mx6_ddr_iomux-dram_sdcke1 = ddr-dram_sdcke1;
+ mx6_ddr_iomux-dram_sdba2 = ddr-dram_sdba2;
+ mx6_ddr_iomux-dram_sdodt0 = ddr-dram_sdodt0;
+ mx6_ddr_iomux-dram_sdodt1 = ddr-dram_sdodt1;
+ mx6_grp_iomux-grp_ctlds = grp-grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux-grp_ddrmode_ctl = grp-grp_ddrmode_ctl;
+ mx6_ddr_iomux-dram_sdqs0 = ddr-dram_sdqs0;
+ mx6_ddr_iomux-dram_sdqs1 = ddr-dram_sdqs1;
+ if (width = 32) {
+ mx6_ddr_iomux-dram_sdqs2 = ddr-dram_sdqs2;
+ mx6_ddr_iomux-dram_sdqs3 = ddr-dram_sdqs3;
+ }
+ if (width = 64) {
+ mx6_ddr_iomux-dram_sdqs4 = ddr-dram_sdqs4;
+ mx6_ddr_iomux-dram_sdqs5 = ddr-dram_sdqs5;
+ mx6_ddr_iomux-dram_sdqs6 = ddr-dram_sdqs6;
+ mx6_ddr_iomux-dram_sdqs7 = ddr-dram_sdqs7;
+ }
+
+ /* Data */
+ mx6_grp_iomux-grp_ddrmode = grp-grp_ddrmode;
+ mx6_grp_iomux-grp_b0ds = grp-grp_b0ds;
+ mx6_grp_iomux-grp_b1ds = grp-grp_b1ds;
+ if (width = 32) {
+ mx6_grp_iomux-grp_b2ds = grp-grp_b2ds;
+ mx6_grp_iomux-grp_b3ds = grp-grp_b3ds;
+ }
+ if (width = 64) {
+ mx6_grp_iomux-grp_b4ds = grp-grp_b4ds;
+ mx6_grp_iomux-grp_b5ds = grp-grp_b5ds;
+ mx6_grp_iomux-grp_b6ds = grp-grp_b6ds;
+ mx6_grp_iomux-grp_b7ds = grp-grp_b7ds;
+ }
+ mx6_ddr_iomux-dram_dqm0 = ddr-dram_dqm0;
+ mx6_ddr_iomux-dram_dqm1 = ddr-dram_dqm1;
+ if (width = 32) {
+ mx6_ddr_iomux-dram_dqm2 = ddr-dram_dqm2;
+ mx6_ddr_iomux-dram_dqm3 = ddr-dram_dqm3;
+ }
+ if (width = 64) {
+ mx6_ddr_iomux-dram_dqm4 = ddr-dram_dqm4;
+ mx6_ddr_iomux-dram_dqm5 = ddr-dram_dqm5;
+ mx6_ddr_iomux-dram_dqm6 = ddr-dram_dqm6;
+ mx6_ddr_iomux-dram_dqm7 = ddr-dram_dqm7;
+ }
+}
+#endif
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+/* Configure MX6SDL mmdc iomux */
+void mx6sdl_dram_iocfg(unsigned width,
+ const struct mx6sdl_iomux_ddr_regs *ddr,
+ const struct mx6sdl_iomux_grp_regs *grp
Re: [U-Boot] [PATCH v3 06/11] mx6: add structs for mmdc and ddr iomux registers
On Wed, May 28, 2014 at 10:06 AM, Nikita Kiryanov nik...@compulab.co.il wrote: Hi Tim, On 08/05/14 08:16, Tim Harvey wrote: Add memory-mapped structures for MMDC iomux and configuration. Note that the MMDC configuration registers are common between the IMX6DQ (IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) the iomux register addresses differ. This requires two sets of structures. Add structures to describe DDR3 device information, system information (memory layout, etc), and MMDC calibration regitsers that can be used to configure the MMDC dynamically. s/regitsers/registers thanks - will address in the next revision or in a following the commit if we can ever get this series committed. We define these structures for SPL builds instead of including mx6q-ddr.h an mx6dl-ddr.h which use the same namespace and are only useful for imximage cf files. What about the usefulness of the structs for U-Boot code? For example, it might be necessary for U-Boot code to query the MMDC registers to setup memory related variables like gd-ram_size and gd-bd-bi_dram[i].size. Sure this can be done using the #defines in the header files, but we lose nothing by making the structs available to U-Boot as well. perhaps, but I would assume if anyone needs these in u-boot they can broaden the scope when needed. There is an imx_ddr_size() function in spl/arch/arm/imx-common/cpu.c that returns dram size based on MMDC configuration already, yet it uses a subset of this structure that is common to imx in general. Regards, Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 04/11] mx6: add boot device support for SPL
On Wed, May 28, 2014 at 9:38 AM, Nikita Kiryanov nik...@compulab.co.il wrote:
Hi Tim,
Sorry for the late reply.
no worries - your the only review of this revision thus far ;)
On 08/05/14 08:16, Tim Harvey wrote:
Add a common spl.c file to support boot device functions needed for SPL
such as detecting the boot device.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- added Freescale copyright
v2:
- re-base on top of Masahiro Yamada's consolidation patch:
http://patchwork.ozlabs.org/patch/341817/
- moved spl_boot_device() and get_boot_mode() into own common imx spl.c
file
- use mem-mapped structure for smbr reg access
---
[..snip..]
+ }
+ break;
+ /* SD/eSD: 8.5.3, Table 8-15 */
+ case 0x4:
+ case 0x5:
+ return BOOT_DEVICE_MMC1;
+ /* MMC/eMMC: 8.5.3 */
+ case 0x6:
+ case 0x7:
+ return BOOT_DEVICE_MMC1;
+ /* NAND Flash: 8.5.2 */
+ case 0x8 ... 0xf:
+ return BOOT_DEVICE_NAND;
+ }
+ return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT)
*/
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ /* for MMC return either RAW or FAT mode */
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
spl_boot_device() returns only BOOT_DEVICE_MMC1. Was the MMC/eMMC case
supposed to return a BOOT_DEVICE_MMC2?
Its hard to say - I think the use of BOOT_DEVICE_* is very
implementation specific. I don't quite understand why there is a
BOOT_DEVICE_MMC{1,2,2_2} defined in arch/arm/include/asm/spl.h - the
BOOT_DEVICE_MMC2_2 is certainly quite odd. In uboot/common/spl/spl.c
they are all treated the same and spl_mmc_load_image() always assumes
the 'first' mmc device anyway.
In the IMX6 case I'm not sure an SD/uSD card would be treated any
different than an MMC card so it would come down to which specific
device is flagged as the boot device, of which there are 4 sdhc's. So
eventually, one might need to add more BOOT_DEVICE_MMC enums if that
is to be supported. For now, I'm keeping it simple and there is an
issue with IMX6 spl_mmc_load_image() anyway which I plan on addressing
later.
Tim
Aside from this nitpick,
Acked-by: Nikita Kiryanov nik...@compulab.co.il
___
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Re: [U-Boot] [PATCH v3 11/11] imx: ventana: switch to SPL
On Thu, May 29, 2014 at 12:02 AM, Stefano Babic sba...@denx.de wrote: Hi Tim, I cannot build with this version. A setup for a couple of pins is not yet replaces. In fact, I have: /* Enable Backlight */ imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 | and it should be: SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | The same some lines later: /* Backlight CABEN on LVDS connector */ - imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 | + SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | Can you check and fix it ? Thanks ! Regarding your patchset: I had no remarkable comments and, as I have not seen any comments from other developers, your patchset is ready to be merged. I am also waiting for Masahiro's patch to be applied. Best regards, Stefano Babic Stefano, Those should be patched from patch 10. However, I can't seem to get patch 9 to apply cleanly from current u-boot-imx/master so perhaps I should just rebase the whole series and post again? Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] imx6 booting from NAND with bad block 0
On Mon, Jun 2, 2014 at 4:03 AM, Andy Ng andreas2...@gmail.com wrote: I have an imx6 solo system and currently I am using the SD card to boot the u-boot. I would like to make it boot from NAND, but my first Block in NAND is a bad one. Do I need u-boot with NAND SPL support? Best regards Andy Andy, You only need NAND SPL support if the board you are booting uses an SPL bootloader. The benefit of using SPL is really to allow mutliple board configurations to be supported in a single bootloader (mostly by configuring pinmux and SDRAM controller dynamically for IMX6DQ vs IMX6SDL SoCs). In general to 'boot' from NAND on IMX6 you need to use the kobs-ng tool (source distributed with Freescales IMX BSP) to flash the bootstream to the NAND in a way that is compatible with the internal IMX BOOT ROM. Note that this also depends on eFUSE configuration and/or board strappings specifing that the BOOT ROM should boot from NAND. If all this is done, then having a bad block at the beginning is not an issue, as the IMX BOOT ROM and kobs-ng allow for some redundancy there. What board are you working with and what bootloader tree? Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 00/10] mx6: SPL NAND support
This series adds some necessary framework for IMX6 SPL support. The series includes support for NAND SPL and has been tested with MMC as well. I have tested this on five differing Ventana baseboards with a variety of memory (32bit 512MB, 32bit 1024MB, 64bit 1024MB) and CPU configurations (IMX6Q, IMX6DL, IMX6S). This is based on top of Mashahiro Yamada's patch that consolidates arch/arm/include/asm/arch-*/spl.h [1] v4: - removed unnecessary parens from a return - removed patch 1 as it has been merged upstream v3: - re-ordered calls in board_init_f - replace imx_iomux_v3_setup_multiple_pads_array with additional intelligence in imx_iomux_v3_setup_multiple_pads - added ifdef's around cpu specific mmdc iocfg functions for code-reduction with single-variant board configs - added checks for IMX6D - added Freescale copyright to boot device support function - fixed typo s/IMX6SLD/IMX6SDL - encorporated cleanups in mxs_nand_spl.c per feedback v2: - use compatible linker script instead of creating new one - remove structure passing data from SPL to u-boot - remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base and nand_bbt to bring SPL down in size. This reduced codesize by about 32k where now mxs_spl_nand is about 12k total - adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD - move boot dev detection into imx-common/spl.c - move macros for using pinmux array into iomux-v3.h - remove missing/unnecessary include - revert mtdparts change - use get_ram_size() to detect memory - add support for MX6SOLO and MX6DUAL - set CS0_END for 4GB so get_ram_size() works - updated DDR3 calibration values for ventana boards - fixed build issue - only compile spl if doing spl build - fixed line length issue in README - remove CONFIG_SPL* conditions and conditionally compile instead - removed prints for CPU type and DRAM size/width - uboot will print these l - removed unused gw_ventana_spl.cfg - use common read_eeprom function - added MMC support to SPL - added Masahiro Yamada's boot mode consolidation patch http://patchwork.ozlabs.org/patch/341817 and rebase on top of it [1] http://patchwork.ozlabs.org/patch/341817/ Tim Harvey (10): spl: nand: add support for mxs nand mx6: add common SPL configuration mx6: add boot device support for SPL imx: add comments and remove unused struct fields mx6: add structs for mmdc and ddr iomux registers mx6: add mmdc configuration for MX6Q/MX6DL imx: iomux: add macros to setup iomux for multiple SoC types imx: ventana: split read_eeprom into standalone file imx: ventana: auto-configure for IMX6Q vs IMX6DL imx: ventana: switch to SPL arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/ddr.c| 490 +++ arch/arm/imx-common/Makefile| 1 + arch/arm/imx-common/cpu.c | 16 +- arch/arm/imx-common/iomux-v3.c | 16 +- arch/arm/imx-common/spl.c | 81 arch/arm/include/asm/arch-mx6/mx6-ddr.h | 231 +++ arch/arm/include/asm/imx-common/iomux-v3.h | 25 ++ board/gateworks/gw_ventana/Makefile | 3 +- board/gateworks/gw_ventana/README | 92 +++-- board/gateworks/gw_ventana/eeprom.c | 89 + board/gateworks/gw_ventana/gw_ventana.c | 597 +++- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 419 +++ board/gateworks/gw_ventana/ventana_eeprom.h | 11 + boards.cfg | 6 +- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand_spl.c | 231 +++ include/configs/gw_ventana.h| 11 + include/configs/imx6_spl.h | 71 20 files changed, 2065 insertions(+), 342 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c create mode 100644 arch/arm/imx-common/spl.c create mode 100644 board/gateworks/gw_ventana/eeprom.c create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c create mode 100644 drivers/mtd/nand/mxs_nand_spl.c create mode 100644 include/configs/imx6_spl.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 01/10] spl: nand: add support for mxs nand
This utilizes existing mxs_nand support layer to provide a method to load an
image off nand for SPL. The flash device will be detected in order to support
multiple flash devices instead of having layout hard coded at build time.
Cc: Stefan Roese s...@denx.de
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Andy Ng andreas2...@gmail.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Tapani Utriainen tap...@technexion.com
Cc: Tom Rini tr...@ti.com
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v4:
- removed unnecessary parens from return
v3:
- removed NAND_NCE and NAND_CTRL_CHANGE unused by mxc_nand.c
- return specific error types on errors
- remove register keyword - let compiler do optimizations
v2:
- remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base
and nand_bbt to bring SPL down in size. This reduced codesize by about 32k
where now mxs_spl_nand is about 12k total.
---
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/mxs_nand_spl.c | 231
2 files changed, 232 insertions(+)
create mode 100644 drivers/mtd/nand/mxs_nand_spl.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 4eb354d..bf1312a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -68,5 +68,6 @@ else # minimal SPL drivers
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
+obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
endif # drivers
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
new file mode 100644
index 000..0e7c364
--- /dev/null
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include nand.h
+#include malloc.h
+
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
+int column, int page_addr)
+{
+ register struct nand_chip *chip = mtd-priv;
+ u32 timeo, time_start;
+
+ /* write out the command to the device */
+ chip-cmd_ctrl(mtd, command, NAND_CLE);
+
+ /* Serially input address */
+ if (column != -1) {
+ chip-cmd_ctrl(mtd, column, NAND_ALE);
+ chip-cmd_ctrl(mtd, column 8, NAND_ALE);
+ }
+ if (page_addr != -1) {
+ chip-cmd_ctrl(mtd, page_addr, NAND_ALE);
+ chip-cmd_ctrl(mtd, page_addr 8, NAND_ALE);
+ /* One more address cycle for devices 128MiB */
+ if (chip-chipsize (128 20))
+ chip-cmd_ctrl(mtd, page_addr 16, NAND_ALE);
+ }
+ chip-cmd_ctrl(mtd, NAND_CMD_NONE, 0);
+
+ if (command == NAND_CMD_READ0) {
+ chip-cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE);
+ chip-cmd_ctrl(mtd, NAND_CMD_NONE, 0);
+ }
+
+ /* wait for nand ready */
+ ndelay(100);
+ timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ time_start = get_timer(0);
+ while (get_timer(time_start) timeo) {
+ if (chip-dev_ready(mtd))
+ break;
+ }
+}
+
+static int mxs_flash_ident(struct mtd_info *mtd)
+{
+ register struct nand_chip *chip = mtd-priv;
+ int i;
+ u8 mfg_id, dev_id;
+ u8 id_data[8];
+ struct nand_onfi_params *p = chip-onfi_params;
+
+ /* Reset the chip */
+ chip-cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+ /* Send the command for reading device ID */
+ chip-cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+ /* Read manufacturer and device IDs */
+ mfg_id = chip-read_byte(mtd);
+ dev_id = chip-read_byte(mtd);
+
+ /* Try again to make sure */
+ chip-cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+ for (i = 0; i 8; i++)
+ id_data[i] = chip-read_byte(mtd);
+ if (id_data[0] != mfg_id || id_data[1] != dev_id) {
+ printf(second ID read did not match);
+ return -1;
+ }
+ debug(0x%02x:0x%02x , mfg_id, dev_id);
+
+ /* read ONFI */
+ chip-onfi_version = 0;
+ chip-cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+ if (chip-read_byte(mtd) != 'O' || chip-read_byte(mtd) != 'N' ||
+ chip-read_byte(mtd) != 'F' || chip-read_byte(mtd) != 'I') {
+ return -2;
+ }
+
+ /* we have ONFI, probe it */
+ chip-cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+ chip-read_buf(mtd, (uint8_t *)p, sizeof(*p));
+ mtd-name = p-model;
+ mtd-writesize = le32_to_cpu(p-byte_per_page);
+ mtd-erasesize = le32_to_cpu(p-pages_per_block) * mtd-writesize;
+ mtd-oobsize = le16_to_cpu(p-spare_bytes_per_page);
+ chip-chipsize = le32_to_cpu(p-blocks_per_lun
[U-Boot] [PATCH v4 05/10] mx6: add structs for mmdc and ddr iomux registers
Add memory-mapped structures for MMDC iomux and configuration. Note that whi
the MMDC configuration registers are common between the IMX6DQ
(IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux
registers differ. This requires two sets of structures.
Add structures to describe DDR3 device information, system information
(memory layout, etc), and MMDC calibration registers that can be used to
configure the MMDC dynamically.
We define these structures for SPL builds instead of including mx6q-ddr.h an
mx6dl-ddr.h which use the same namespace and are only useful for imximage cf
files.
Cc: Stefan Roese s...@denx.de
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Andy Ng andreas2...@gmail.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Tapani Utriainen tap...@technexion.com
Cc: Tom Rini tr...@ti.com
Signed-off-by: Tim Harvey thar...@gateworks.com
Acked-by: Nikita Kiryanov nik...@compulab.co.il
---
v4:
- added Nikita's Ack
v3:
- moved portions into following patch
v2:
- split out from original mmdc configuration patch
- only define for SPL build
- do not include mx6q-ddr.h and mx6dl-ddr.h for SPL build - these use the
same namespace and are only useful for imximage cfg files
---
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 159
1 file changed, 159 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 43d377a..c2a31d2 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -6,6 +6,7 @@
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_MX6Q
#include mx6q-ddr.h
#else
@@ -15,6 +16,164 @@
#error Please select cpu
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
+#else
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
+ u32 mdscr;
+ u32 mdref;
+ u32 res1[2];
+ u32 mdrwd;
+ u32 mdor;
+ u32 res2[3];
+ u32 mdasp;
+ u32 res3[240];
+ u32 mapsr;
+ u32 res4[254];
+ u32 mpzqhwctrl;
+ u32 res5[2];
+ u32 mpwldectrl0;
+ u32 mpwldectrl1;
+ u32 res6;
+ u32 mpodtctrl;
+ u32 mprddqby0dl;
+ u32 mprddqby1dl;
+ u32 mprddqby2dl;
+ u32 mprddqby3dl;
+ u32 res7[4];
+ u32 mpdgctrl0;
+ u32 mpdgctrl1;
+ u32 res8;
+ u32 mprddlctl;
+ u32 res9;
+ u32 mpwrdlctl;
+ u32 res10[25];
+ u32 mpmur0;
+};
+
+/*
+ * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
+ */
+#define MX6DQ_IOM_DDR_BASE 0x020e0500
+struct mx6dq_iomux_ddr_regs {
+ u32 res1[3];
+ u32 dram_sdqs5;
+ u32 dram_dqm5;
+ u32 dram_dqm4;
+ u32 dram_sdqs4;
+ u32 dram_sdqs3;
+ u32 dram_dqm3;
+ u32 dram_sdqs2;
+ u32 dram_dqm2;
+ u32 res2[16];
+ u32 dram_cas;
+ u32 res3[2];
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res4[2];
+ u32 dram_sdclk_0;
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdclk_1;
+ u32 dram_sdcke1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 res5;
+ u32 dram_sdqs0;
+ u32 dram_dqm0;
+ u32 dram_sdqs1;
+ u32 dram_dqm1;
+ u32 dram_sdqs6;
+ u32 dram_dqm6;
+ u32 dram_sdqs7;
+ u32 dram_dqm7;
+};
+
+#define MX6DQ_IOM_GRP_BASE 0x020e0700
+struct mx6dq_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 res2;
+ u32 grp_ddrpke;
+ u32 res3[6];
+ u32 grp_ddrmode;
+ u32 res4[3];
+ u32 grp_b0ds;
+ u32 grp_b1ds;
+ u32 grp_ctlds;
+ u32 res5;
+ u32 grp_b2ds;
+ u32 grp_ddr_type;
+ u32 grp_b3ds;
+ u32 grp_b4ds;
+ u32 grp_b5ds;
+ u32 grp_b6ds;
+};
+
+#define MX6SDL_IOM_DDR_BASE 0x020e0400
+struct mx6sdl_iomux_ddr_regs {
+ u32 res1[25];
+ u32 dram_cas;
+ u32 res2[2];
+ u32 dram_dqm0;
+ u32 dram_dqm1;
+ u32 dram_dqm2;
+ u32 dram_dqm3;
+ u32 dram_dqm4;
+ u32 dram_dqm5;
+ u32 dram_dqm6;
+ u32 dram_dqm7;
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res3[2];
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdcke1;
+ u32 dram_sdclk_0;
+ u32 dram_sdclk_1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 dram_sdqs0;
+ u32 dram_sdqs1;
+ u32 dram_sdqs2;
+ u32 dram_sdqs3;
+ u32 dram_sdqs4;
+ u32 dram_sdqs5;
+ u32 dram_sdqs6;
+ u32 dram_sdqs7;
+};
+
+#define MX6SDL_IOM_GRP_BASE 0x020e0700
+struct mx6sdl_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32
[U-Boot] [PATCH v4 02/10] mx6: add common SPL configuration
Add a common header which can hopefully be shared amon imx6 SPL users Cc: Stefan Roese s...@denx.de Cc: Otavio Salvador ota...@ossystems.com.br Cc: Andy Ng andreas2...@gmail.com Cc: Eric Nelson eric.nel...@boundarydevices.com Cc: Tapani Utriainen tap...@technexion.com Cc: Tom Rini tr...@ti.com Signed-off-by: Tim Harvey thar...@gateworks.com Acked-by: Stefano Babic sba...@denx.de Acked-by: Nikita Kiryanov nik...@compulab.co.il --- v4: - no changes v3: - fixed typo s/IMX6SLD/IMX6SDL - add acks from Stefano and Nikita v2: - adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD --- include/configs/imx6_spl.h | 71 ++ 1 file changed, 71 insertions(+) create mode 100644 include/configs/imx6_spl.h diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h new file mode 100644 index 000..6fdc438 --- /dev/null +++ b/include/configs/imx6_spl.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey thar...@gateworks.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __IMX6_SPL_CONFIG_H +#define __IMX6_SPL_CONFIG_H + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_FRAMEWORK + +/* + * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: + * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091 + * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well + * - BOOT ROM stack is at 0x0091FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + *IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to + *fit between 0x00907000 and 0x00918000. + * - Additionally the BOOT ROM loads what they consider the firmware image + *which consists of a 4K header in front of us that contains the IVT, DCD + *and some padding thus 'our' max size is really 0x00908000 - 0x00918000 + *or 64KB + */ +#define CONFIG_SPL_LDSCRIPTarch/arm/cpu/armv7/omap-common/u-boot-spl.lds +#define CONFIG_SPL_TEXT_BASE 0x00908000 +#define CONFIG_SPL_MAX_SIZE(64 * 1024) +#define CONFIG_SPL_START_S_PATHarch/arm/cpu/armv7 +#define CONFIG_SPL_STACK 0x0091FFB8 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* NAND support */ +#if defined(CONFIG_SPL_NAND_SUPPORT) +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_DMA_SUPPORT +#endif + +/* MMC support */ +#if defined(CONFIG_SPL_MMC_SUPPORT) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR138 /* offset 69KB */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) +#endif + +/* SATA support */ +#if defined(CONFIG_SPL_SATA_SUPPORT) +#define CONFIG_SPL_SATA_BOOT_DEVICE0 +#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 +#endif + +/* Define the payload for FAT/EXT support */ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME u-boot.img +#define CONFIG_SPL_LIBDISK_SUPPORT +#endif + +#define CONFIG_SPL_BSS_START_ADDR 0x1820 +#define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START0x1830 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB */ +#define CONFIG_SYS_TEXT_BASE 0x1780 +#endif + +#endif -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 04/10] imx: add comments and remove unused struct fields
Add comment block for the imx_ddr_size function and remove the extra unused
fields from struct esd_mmdc_regs which are also not common between IMX53 and
IMX6.
Cc: Stefan Roese s...@denx.de
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Andy Ng andreas2...@gmail.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Tapani Utriainen tap...@technexion.com
Cc: Tom Rini tr...@ti.com
Signed-off-by: Tim Harvey thar...@gateworks.com
Acked-by: Stefano Babic sba...@denx.de
Acked-by: Nikita Kiryanov nik...@compulab.co.il
---
v4:
- added Nikita's Ack
v3:
- fixed doxygen-style comment block
- added Stefano's Ack
v2:
- new patch in series
---
arch/arm/imx-common/cpu.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index a77c4de..5a09107 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -58,6 +58,7 @@ char *get_reset_cause(void)
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};
+/* these MMDC registers are common to the IMX53 and IMX6 */
struct esd_mmdc_regs {
uint32_tctl;
uint32_tpdc;
@@ -66,15 +67,6 @@ struct esd_mmdc_regs {
uint32_tcfg1;
uint32_tcfg2;
uint32_tmisc;
- uint32_tscr;
- uint32_tref;
- uint32_trsvd1;
- uint32_trsvd2;
- uint32_trwd;
- uint32_tor;
- uint32_tmrr;
- uint32_tcfg3lp;
- uint32_tmr4;
};
#define ESD_MMDC_CTL_GET_ROW(mdctl)((ctl 24) 7)
@@ -83,6 +75,12 @@ struct esd_mmdc_regs {
#define ESD_MMDC_CTL_GET_CS1(mdctl)((ctl 30) 1)
#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc 5) 1)
+/*
+ * imx_ddr_size - return size in bytes of DRAM according MMDC config
+ * The MMDC MDCTL register holds the number of bits for row, col, and data
+ * width and the MMDC MDMISC register holds the number of banks. Combine
+ * all these bits to determine the meme size the MMDC has been configured for
+ */
unsigned imx_ddr_size(void)
{
struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
--
1.8.3.2
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[U-Boot] [PATCH v4 03/10] mx6: add boot device support for SPL
Add a common spl.c file to support boot device functions needed for SPL
such as detecting the boot device.
Cc: Stefan Roese s...@denx.de
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Andy Ng andreas2...@gmail.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Tapani Utriainen tap...@technexion.com
Cc: Tom Rini tr...@ti.com
Signed-off-by: Tim Harvey thar...@gateworks.com
Acked-by: Nikita Kiryanov nik...@compulab.co.il
---
v4:
- added Nikita's Ack
v3:
- added Freescale copyright
v2:
- re-base on top of Masahiro Yamada's consolidation patch:
http://patchwork.ozlabs.org/patch/341817/
- moved spl_boot_device() and get_boot_mode() into own common imx spl.c file
- use mem-mapped structure for smbr reg access
---
arch/arm/imx-common/Makefile | 1 +
arch/arm/imx-common/spl.c| 81
2 files changed, 82 insertions(+)
create mode 100644 arch/arm/imx-common/spl.c
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 0e71395..d4799e7 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y += misc.o
+obj-$(CONFIG_SPL_BUILD)+= spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
new file mode 100644
index 000..9a02a64
--- /dev/null
+++ b/arch/arm/imx-common/spl.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/spl.h
+#include spl.h
+
+#if defined(CONFIG_MX6)
+/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+u32 spl_boot_device(void)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(psrc-sbmr1);
+
+ /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
+ switch ((reg 0x00FF) 4) {
+/* EIM: See 8.5.1, Table 8-9 */
+ case 0x0:
+ /* BOOT_CFG1[3]: NOR/OneNAND Selection */
+ if ((reg 0x0008) 3)
+ return BOOT_DEVICE_ONENAND;
+ else
+ return BOOT_DEVICE_NOR;
+ break;
+ /* SATA: See 8.5.4, Table 8-20 */
+ case 0x2:
+ return BOOT_DEVICE_SATA;
+ /* Serial ROM: See 8.5.5.1, Table 8-22 */
+ case 0x3:
+ /* BOOT_CFG4[2:0] */
+ switch ((reg 0x0700) 24) {
+ case 0x0 ... 0x4:
+ return BOOT_DEVICE_SPI;
+ case 0x5 ... 0x7:
+ return BOOT_DEVICE_I2C;
+ }
+ break;
+ /* SD/eSD: 8.5.3, Table 8-15 */
+ case 0x4:
+ case 0x5:
+ return BOOT_DEVICE_MMC1;
+ /* MMC/eMMC: 8.5.3 */
+ case 0x6:
+ case 0x7:
+ return BOOT_DEVICE_MMC1;
+ /* NAND Flash: 8.5.2 */
+ case 0x8 ... 0xf:
+ return BOOT_DEVICE_NAND;
+ }
+ return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ /* for MMC return either RAW or FAT mode */
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ break;
+ default:
+ puts(spl: ERROR: unsupported device\n);
+ hang();
+ }
+}
+#endif
--
1.8.3.2
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[U-Boot] [PATCH v4 07/10] imx: iomux: add macros to setup iomux for multiple SoC types
Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list
and add macros for declaring the pad_list that take into account the
SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL
iomux).
Cc: Stefan Roese s...@denx.de
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Andy Ng andreas2...@gmail.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Tapani Utriainen tap...@technexion.com
Cc: Tom Rini tr...@ti.com
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v4:
- no changes
v3:
- remove commit msg 2nd paragrap about prior approaches
- re-work to avoid needing to add a new function by making
imx_iomux_v3_setup_multiple_pads more intelligent and adding macros
that depend on SoC type support
v2:
- moved macros for declaring and using structs for array variant
- removed non-related whitespace cleanup
---
arch/arm/imx-common/iomux-v3.c | 16 ++--
arch/arm/include/asm/imx-common/iomux-v3.h | 25 +
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 6e46ea8..306183a 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -11,6 +11,7 @@
#include common.h
#include asm/io.h
#include asm/arch/imx-regs.h
+#include asm/arch/sys_proto.h
#include asm/imx-common/iomux-v3.h
static void *base = (void *)IOMUXC_BASE_ADDR;
@@ -54,12 +55,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
#endif
}
+/* configures a list of pads within declared with IOMUX_PADS macro */
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count)
{
iomux_v3_cfg_t const *p = pad_list;
+ int stride;
int i;
- for (i = 0; i count; i++)
- imx_iomux_v3_setup_pad(*p++);
+#if defined(CONFIG_MX6QDL)
+ stride = 2;
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ p += 1;
+#else
+ stride = 1;
+#endif
+ for (i = 0; i count; i++) {
+ imx_iomux_v3_setup_pad(*p);
+ p += stride;
+ }
}
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
b/arch/arm/include/asm/imx-common/iomux-v3.h
index cca920b..dfe1ebf 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -175,4 +175,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def);\
+}
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
+
#endif /* __MACH_IOMUX_V3_H__*/
--
1.8.3.2
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[U-Boot] [PATCH v4 06/10] mx6: add mmdc configuration for MX6Q/MX6DL
- add function for configuring iomux based on board-specific regs
- add function for configuring mmdc based on board-specific and
chip-specific data
Cc: Stefan Roese s...@denx.de
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Andy Ng andreas2...@gmail.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Tapani Utriainen tap...@technexion.com
Cc: Tom Rini tr...@ti.com
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v4:
- added delay following configure to allow ZQ calibration to complete
- update MMDC configuration to match Freescale RM
v3:
- added ifdef's around cpu specific iocfg functions for code-reduction with
single-variant board configs
- moved portions from previous patch here
- added check for IMX6D
v2:
- split out mmdc and iomux structs into separate patch
---
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/ddr.c| 490
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 72 +
3 files changed, 563 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..6dc9f8e 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -8,4 +8,5 @@
#
obj-y := soc.o clock.o
+obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
new file mode 100644
index 000..0434211
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/types.h
+#include asm/arch/mx6-ddr.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+#include asm/types.h
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+/* Configure MX6DQ mmdc iomux */
+void mx6dq_dram_iocfg(unsigned width,
+ const struct mx6dq_iomux_ddr_regs *ddr,
+ const struct mx6dq_iomux_grp_regs *grp)
+{
+ volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
+
+ /* DDR IO Type */
+ mx6_grp_iomux-grp_ddr_type = grp-grp_ddr_type;
+ mx6_grp_iomux-grp_ddrpke = grp-grp_ddrpke;
+
+ /* Clock */
+ mx6_ddr_iomux-dram_sdclk_0 = ddr-dram_sdclk_0;
+ mx6_ddr_iomux-dram_sdclk_1 = ddr-dram_sdclk_1;
+
+ /* Address */
+ mx6_ddr_iomux-dram_cas = ddr-dram_cas;
+ mx6_ddr_iomux-dram_ras = ddr-dram_ras;
+ mx6_grp_iomux-grp_addds = grp-grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux-dram_reset = ddr-dram_reset;
+ mx6_ddr_iomux-dram_sdcke0 = ddr-dram_sdcke0;
+ mx6_ddr_iomux-dram_sdcke1 = ddr-dram_sdcke1;
+ mx6_ddr_iomux-dram_sdba2 = ddr-dram_sdba2;
+ mx6_ddr_iomux-dram_sdodt0 = ddr-dram_sdodt0;
+ mx6_ddr_iomux-dram_sdodt1 = ddr-dram_sdodt1;
+ mx6_grp_iomux-grp_ctlds = grp-grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux-grp_ddrmode_ctl = grp-grp_ddrmode_ctl;
+ mx6_ddr_iomux-dram_sdqs0 = ddr-dram_sdqs0;
+ mx6_ddr_iomux-dram_sdqs1 = ddr-dram_sdqs1;
+ if (width = 32) {
+ mx6_ddr_iomux-dram_sdqs2 = ddr-dram_sdqs2;
+ mx6_ddr_iomux-dram_sdqs3 = ddr-dram_sdqs3;
+ }
+ if (width = 64) {
+ mx6_ddr_iomux-dram_sdqs4 = ddr-dram_sdqs4;
+ mx6_ddr_iomux-dram_sdqs5 = ddr-dram_sdqs5;
+ mx6_ddr_iomux-dram_sdqs6 = ddr-dram_sdqs6;
+ mx6_ddr_iomux-dram_sdqs7 = ddr-dram_sdqs7;
+ }
+
+ /* Data */
+ mx6_grp_iomux-grp_ddrmode = grp-grp_ddrmode;
+ mx6_grp_iomux-grp_b0ds = grp-grp_b0ds;
+ mx6_grp_iomux-grp_b1ds = grp-grp_b1ds;
+ if (width = 32) {
+ mx6_grp_iomux-grp_b2ds = grp-grp_b2ds;
+ mx6_grp_iomux-grp_b3ds = grp-grp_b3ds;
+ }
+ if (width = 64) {
+ mx6_grp_iomux-grp_b4ds = grp-grp_b4ds;
+ mx6_grp_iomux-grp_b5ds = grp-grp_b5ds;
+ mx6_grp_iomux-grp_b6ds = grp-grp_b6ds;
+ mx6_grp_iomux-grp_b7ds = grp-grp_b7ds;
+ }
+ mx6_ddr_iomux-dram_dqm0 = ddr-dram_dqm0;
+ mx6_ddr_iomux-dram_dqm1 = ddr-dram_dqm1;
+ if (width = 32) {
+ mx6_ddr_iomux-dram_dqm2 = ddr-dram_dqm2;
+ mx6_ddr_iomux-dram_dqm3 = ddr-dram_dqm3;
+ }
+ if (width = 64) {
+ mx6_ddr_iomux-dram_dqm4 = ddr-dram_dqm4;
+ mx6_ddr_iomux-dram_dqm5 = ddr-dram_dqm5;
+ mx6_ddr_iomux-dram_dqm6 = ddr-dram_dqm6;
+ mx6_ddr_iomux-dram_dqm7 = ddr-dram_dqm7;
+ }
+}
+#endif
+
+#if defined(CONFIG_MX6QDL) || defined
[U-Boot] [PATCH v4 09/10] imx: ventana: auto-configure for IMX6Q vs IMX6DL
use the new iomux function and a macros to create a multi-dimensional array
of iomux values without duplicating the defintions.
Cc: Stefan Roese s...@denx.de
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Andy Ng andreas2...@gmail.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Tapani Utriainen tap...@technexion.com
Cc: Tom Rini tr...@ti.com
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v4:
- no changes
v3:
- replace use of imx_iomux_v3_setup_multiple_pads_array with
imx_iomux_v3_setup_multiple_pads
v2:
- use macros that have been moved to iomux-v3.h
---
board/gateworks/gw_ventana/gw_ventana.c | 498
1 file changed, 312 insertions(+), 186 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index a39374d..a33cb71 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -88,109 +88,149 @@ int board_type;
/* UART1: Function varies per baseboard */
iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
/* UART2: Serial Console */
iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1: GSC */
-struct i2c_pads_info i2c_pad_info0 = {
+struct i2c_pads_info mx6q_i2c_pad_info0 = {
.scl = {
- .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
- .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
-struct i2c_pads_info i2c_pad_info1 = {
+struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
/* I2C3: Misc/Expansion */
-struct i2c_pads_info i2c_pad_info2 = {
+struct i2c_pads_info mx6q_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info2 = {
.scl = {
- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC
[U-Boot] [PATCH v4 10/10] imx: ventana: switch to SPL
Switch to an SPL image. The SPL for Ventana does the following: - setup i2c and read the factory programmed EEPROM to obtain DRAM config and model for board-specific calibration data - configure DRAM per CPU/size/layout/devices/calibration - load u-boot.img from NAND and jump to it This allows for a single SPL+u-boot.img to replace the previous multiple boa configurations. Cc: Stefan Roese s...@denx.de Cc: Otavio Salvador ota...@ossystems.com.br Cc: Andy Ng andreas2...@gmail.com Cc: Eric Nelson eric.nel...@boundarydevices.com Cc: Tapani Utriainen tap...@technexion.com Cc: Tom Rini tr...@ti.com Signed-off-by: Tim Harvey thar...@gateworks.com --- v4: - no changes v3: - re-ordered calls in board_init_f v2: - remove missing/unnecessary include - revert mtdparts change - use imx_ddr_size() which uses MMDC configuration to determine mem size explicitly - add support for MX6SOLO and MX6DUAL - set CS0_END for 4GB so get_ram_size() works - updated DDR3 calibration values for ventana boards - fixed build issue - only compile spl if doing spl build - fixed line length issue in README - remove CONFIG_SPL* conditions and conditionally compile instead - removed prints for CPU type and DRAM size/width - uboot will print these later - removed unused gw_ventana_spl.cfg - use common read_eeprom function - added MMC support to SPL --- board/gateworks/gw_ventana/Makefile | 1 + board/gateworks/gw_ventana/README | 92 +++--- board/gateworks/gw_ventana/gw_ventana.c | 10 +- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 419 boards.cfg | 6 +- include/configs/gw_ventana.h| 11 + 7 files changed, 498 insertions(+), 56 deletions(-) create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile index 03bd1fd..33a1788 100644 --- a/board/gateworks/gw_ventana/Makefile +++ b/board/gateworks/gw_ventana/Makefile @@ -7,4 +7,5 @@ # obj-y := gw_ventana.o gsc.o eeprom.o +obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README index 9e697d6..888657c 100644 --- a/board/gateworks/gw_ventana/README +++ b/board/gateworks/gw_ventana/README @@ -3,53 +3,81 @@ U-Boot for the Gateworks Ventana Product Family boards This file contains information for the port of U-Boot to the Gateworks Ventana Product family boards. -1. Boot source, boot from NAND +1. Secondary Program Loader (SPL) +- + +The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading +an executable image from various boot devices. + +The Gateworks Ventana board config uses an SPL build configuration. This +will build the following artifacts from u-boot source: + - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program + Loader) boots. This detects CPU/DRAM configuration, configures + The DRAM controller, loads u-boot.img from the detected boot device, + and jumps to it. As this is booted from the PPL, it has an IVT/DCD + table. + - u-boot.img - The main u-boot core which is u-boot.bin with a image header. + + +2. Build + + +To build U-Boot for the Gateworks Ventana product family: + + make gwventana_config + make + + +3. Boot source, boot from NAND -- The i.MX6 BOOT ROM expects some structures that provide details of NAND layout and bad block information (referred to as 'bootstreams') which are replicated -multiple times in NAND. The number of replications is configurable through -board strapping options and eFUSE settings. The Freescale 'kobs-ng' -application from the Freescale LTIB BSP, which runs under Linux, must be used -to program the bootstream in order to setup the replicated headers correctly. +multiple times in NAND. The number of replications and their spacing (referred +to as search stride) is configurable through board strapping options and/or +eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In +addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two +copies of a bootloader in flash in the case that a bad block has corrupted one. +The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs +under Linux and operates on an MTD partition, must be used to program the +bootstream in order to setup this flash structure correctly. The Gateworks Ventana boards with NAND flash have been factory programmed such that their eFUSE settings expect 2 copies of the boostream (this is specified by providing kobs-ng with the --search_exponent=1 argument). Once in -Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream +Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL with: -kobs-ng init
[U-Boot] [PATCH v4 08/10] imx: ventana: split read_eeprom into standalone file
Split the read_eeprom function out so that it can be shared (ie with SPL)
Cc: Stefan Roese s...@denx.de
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Andy Ng andreas2...@gmail.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Tapani Utriainen tap...@technexion.com
Cc: Tom Rini tr...@ti.com
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v4:
- no changes
v3:
- no changes
v2:
- new patch in series
---
board/gateworks/gw_ventana/Makefile | 2 +-
board/gateworks/gw_ventana/eeprom.c | 89 +
board/gateworks/gw_ventana/gw_ventana.c | 89 +
board/gateworks/gw_ventana/ventana_eeprom.h | 11
4 files changed, 102 insertions(+), 89 deletions(-)
create mode 100644 board/gateworks/gw_ventana/eeprom.c
diff --git a/board/gateworks/gw_ventana/Makefile
b/board/gateworks/gw_ventana/Makefile
index e8dab89..03bd1fd 100644
--- a/board/gateworks/gw_ventana/Makefile
+++ b/board/gateworks/gw_ventana/Makefile
@@ -6,5 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := gw_ventana.o gsc.o
+obj-y := gw_ventana.o gsc.o eeprom.o
diff --git a/board/gateworks/gw_ventana/eeprom.c
b/board/gateworks/gw_ventana/eeprom.c
new file mode 100644
index 000..e90186e
--- /dev/null
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+
+#include gsc.h
+#include ventana_eeprom.h
+
+/* read ventana EEPROM, check for validity, and return baseboard type */
+int
+read_eeprom(int bus, struct ventana_board_info *info)
+{
+ int i;
+ int chksum;
+ char baseboard;
+ int type;
+ unsigned char *buf = (unsigned char *)info;
+
+ memset(info, 0, sizeof(*info));
+
+ /*
+* On a board with a missing/depleted backup battery for GSC, the
+* board may be ready to probe the GSC before its firmware is
+* running. We will wait here indefinately for the GSC/EEPROM.
+*/
+ while (1) {
+ if (0 == i2c_set_bus_num(bus)
+ 0 == i2c_probe(GSC_EEPROM_ADDR))
+ break;
+ mdelay(1);
+ }
+
+ /* read eeprom config section */
+ if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
+ puts(EEPROM: Failed to read EEPROM\n);
+ info-model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* sanity checks */
+ if (info-model[0] != 'G' || info-model[1] != 'W') {
+ puts(EEPROM: Invalid Model in EEPROM\n);
+ info-model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* validate checksum */
+ for (chksum = 0, i = 0; i sizeof(*info)-2; i++)
+ chksum += buf[i];
+ if ((info-chksum[0] != chksum8) ||
+ (info-chksum[1] != (chksum0xff))) {
+ puts(EEPROM: Failed EEPROM checksum\n);
+ info-model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* original GW5400-A prototype */
+ baseboard = info-model[3];
+ if (strncasecmp((const char *)info-model, GW5400-A, 8) == 0)
+ baseboard = '0';
+
+ switch (baseboard) {
+ case '0': /* original GW5400-A prototype */
+ type = GW54proto;
+ break;
+ case '1':
+ type = GW51xx;
+ break;
+ case '2':
+ type = GW52xx;
+ break;
+ case '3':
+ type = GW53xx;
+ break;
+ case '4':
+ type = GW54xx;
+ break;
+ default:
+ printf(EEPROM: Unknown model in EEPROM: %s\n, info-model);
+ type = GW_UNKNOWN;
+ break;
+ }
+ return type;
+}
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 031367d..a39374d 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -84,15 +84,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static struct ventana_board_info ventana_info;
-enum {
- GW54proto, /* original GW5400-A prototype */
- GW51xx,
- GW52xx,
- GW53xx,
- GW54xx,
- GW_UNKNOWN,
-};
-
int board_type;
/* UART1: Function varies per baseboard */
@@ -499,84 +490,6 @@ static void setup_display(void)
}
#endif /* CONFIG_VIDEO_IPUV3 */
-/* read ventana EEPROM, check for validity, and return baseboard type */
-static int
-read_eeprom(void)
-{
- int i;
- int chksum;
- char baseboard;
- int type;
- struct ventana_board_info *info = ventana_info;
- unsigned char *buf = (unsigned char *)ventana_info;
-
- memset(info, 0, sizeof(ventana_info));
-
- /*
-* On a board with a missing/depleted backup battery for GSC
Re: [U-Boot] [RFC 01/10] ARM: crt0.S: clear the global data
On Sat, May 31, 2014 at 1:32 PM, Jeroen Hofstee jer...@myspectrum.nl wrote: NOTE: smdk5420 snow smdkv310 apf27 arndale origen vpac270_ond_256 smdk5250 don't have a memset available. --- arch/arm/lib/crt0.S | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index dfc2de9..52b6f74 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -70,6 +70,12 @@ ENTRY(_main) sub sp, sp, #GD_SIZE/* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ mov r9, sp /* GD is above SP */ + + mov r0, r9 /* Clear the global data */ + mov r1, #0 + mov r2, #GENERATED_GBL_DATA_SIZE + bl memset + mov r0, #0 bl board_init_f -- Acked-by: Tim Harvey thar...@gateworks.com This resolves the issue I encountered and reported with IMX6 SPL. Thanks, Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC 05/10] ARM: SPL: do not set gd again
On Sat, May 31, 2014 at 1:32 PM, Jeroen Hofstee jer...@myspectrum.nl wrote: --- arch/arm/lib/spl.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index dfcc596..75ab546 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -28,9 +28,6 @@ void __weak board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); - /* Set global data pointer. */ - gd = gdata; - board_init_r(NULL, 0); } Agree with Simon's comment otherwise Acked-by: Tim Harvey thar...@gateworks.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
