[linux-linus test] 184214: tolerable FAIL - PUSHED
flight 184214 linux-linus real [real] http://logs.test-lab.xenproject.org/osstest/logs/184214/ Failures :-/ but no regressions. Tests which did not succeed, but are not blocking: test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stopfail like 184212 test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stopfail like 184212 test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stopfail like 184212 test-armhf-armhf-libvirt-qcow2 15 saverestore-support-check fail like 184212 test-armhf-armhf-libvirt 16 saverestore-support-checkfail like 184212 test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stopfail like 184212 test-armhf-armhf-libvirt-raw 15 saverestore-support-checkfail like 184212 test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 184212 test-amd64-amd64-libvirt 15 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-xl-credit2 15 migrate-support-checkfail never pass test-arm64-arm64-xl-credit2 16 saverestore-support-checkfail never pass test-arm64-arm64-libvirt-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-xl-thunderx 15 migrate-support-checkfail never pass test-arm64-arm64-libvirt-xsm 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-thunderx 16 saverestore-support-checkfail never pass test-arm64-arm64-xl 15 migrate-support-checkfail never pass test-arm64-arm64-xl 16 saverestore-support-checkfail never pass test-armhf-armhf-xl 15 migrate-support-checkfail never pass test-armhf-armhf-xl 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-rtds 15 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-arndale 15 migrate-support-checkfail never pass test-armhf-armhf-xl-arndale 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit1 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit1 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-credit1 15 migrate-support-checkfail never pass test-arm64-arm64-xl-credit1 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-xl-xsm 16 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-qcow2 14 migrate-support-checkfail never pass test-amd64-amd64-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-raw 15 saverestore-support-checkfail never pass test-arm64-arm64-xl-vhd 14 migrate-support-checkfail never pass test-arm64-arm64-xl-vhd 15 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-qcow2 14 migrate-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass test-armhf-armhf-xl-vhd 14 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 15 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 15 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 16 saverestore-support-checkfail never pass test-armhf-armhf-libvirt 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 16 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-raw 14 migrate-support-checkfail never pass version targeted for testing: linuxc0f65a7c112b3cfa691cead54bcf24d6cc2182b5 baseline version: linux24e0d2e527a39f64caeb2e6be39ad5396fb2da5e Last test of basis 184212 2023-12-22 11:03:10 Z0 days Testing same since 184214 2023-12-22 23:12:10 Z0 days1 attempts People who touched revisions under test: Alex Deucher Alvin Lee Alyssa Ross Ankit Nautiyal Anshuman Gupta Arnd Bergmann Bartosz Golaszewski Charlene Liu Charles Keepax Clément Villeret Curtis Malainey Daniel Wheeler Dave Airlie Dominique Martinet Fedor Pchelkin Gergo Koteles Ghanshyam Agrawal Hamza Mahfooz Hans de Goede Herve Codina Imre Deak Jani Nikula Jensen Huang Jeremie Knuesel Jerome Brunet Josip Pavic JP Kobryn Juergen Gross Karthik Poosa Kent Gibson Linus Torvalds Mark Brown Petr Mladek Philip Yang Pierre-Louis Bossart Quan Nguyen Ricardo Rivera-Matos Richard Fitzgerald Riwen Lu Serge Semin Shengjiu Wang
Re: hvmloader - allow_memory_relocate overlaps
On Fri, Dec 22, 2023 at 12:35:57PM +0100, Jan Beulich wrote:
> On 21.12.2023 19:08, Neowutran wrote:
> > On 2023-12-19 17:12, Jan Beulich wrote:
> >> On 16.12.2023 08:01, Neowutran wrote:
> >>> I am wondering if the variable "allow_memory_relocate" is still
> >>> relevant today and if its default value is still relevant.
> >>> Should it be defined to 0 by default instead of 1 (it seems to be a
> >>> workaround for qemu-traditional, so maybe an outdated default value ? ) ?
> >>
> >> So are you saying you use qemu-trad?
> > No, I am using "qemu_xen" ( from
> > xenstore-read -> 'device-model =
> > "qemu_xen"'
> >
> >> Otherwise isn't libxl suppressing this behavior anyway?
> > If by "isn't libxl suppressing this behavior" you means if libxl is setting
> > the value of "allow_memory_relocate", then the answer is no.
> >
> > Following this lead, I checked in what code path
> > "allow_memory_relocate" could be defined.
> >
> > It is only defined in one code path,
> >
> > In the file "tools/libs/light/libxl_dm.c",
> > in the function "void libxl__spawn_local_dm(libxl__egc *egc,
> > libxl__dm_spawn_state *dmss)":
> >
> > '''
> > // ...
> > if (b_info->type == LIBXL_DOMAIN_TYPE_HVM) {
> > // ...
> >
> > libxl__xs_printf(gc, XBT_NULL,
> > GCSPRINTF("%s/hvmloader/allow-memory-relocate",
> > path),
> > "%d",
> >
> > b_info->device_model_version==LIBXL_DEVICE_MODEL_VERSION_QEMU_XEN_TRADITIONAL
> > &&
> > !libxl__vnuma_configured(b_info));
> > // ...
> > '''
> >
> > However, on QubesOS (my system), "local_dm" is never used, "stub_dm"
> > is always used.
> >
> > In the function "void lib
> > xl__spawn_stub_dm(libxl__egc *egc, libxl__stub_dm_spawn_state *sdss)",
> > the value of "allow_memory_relocate" is never defined.
> >
> > I tried to patch the code to define "allow_memory_relocate" in
> > "libxl__spawn_stub_dm":
> >
> > '''
> > --- a/tools/libs/light/libxl_dm.c
> > +++ b/tools/libs/light/libxl_dm.c
> > @@ -2431,6 +2431,10 @@ void libxl__spawn_stub_dm(libxl__egc *egc,
> > libxl__stub_dm_spawn_state *sdss)
> > libxl__xs_get_dompath(gc,
> > guest_domid)),
> > "%s",
> >
> > libxl_bios_type_to_string(guest_config->b_info.u.hvm.bios));
> > +libxl__xs_printf(gc, XBT_NULL,
> > + libxl__sprintf(gc,
> > "%s/hvmloader/allow-memory-relocate", libxl__xs_get_dompath(gc,
> > guest_domid)),
> > + "%d",
> > + 0);
> > }
> > ret = xc_domain_set_target(ctx->xch, dm_domid, guest_domid);
> > if (ret<0) {
> > '''
> >
> > And it is indeed another way to solve my issue.
> > However I do not understand the xen hypervisor enough to known i
> > f
> > "allow-memory-relocate" should have been defined in
> > "libxl__spawn_stub_dm" or if the real issue is somewhere else.
>
> I think it should be done the same no matter where qemu runs. Back at the
> time iirc only qemu-trad could run in a stubdom, which may explain the
> omission. Cc-ing the two guys who are likely in the best position to tell
> for sure.
This indeed looks like a missing piece of qemu-xen support in
stubdomain.
But also, As Jan pointed out, this would be better fixed at the qemu
side so memory relocation could be re-enabled.
--
Best Regards,
Marek Marczykowski-Górecki
Invisible Things Lab
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[linux-linus test] 184212: tolerable FAIL - PUSHED
flight 184212 linux-linus real [real] http://logs.test-lab.xenproject.org/osstest/logs/184212/ Failures :-/ but no regressions. Tests which did not succeed, but are not blocking: test-armhf-armhf-libvirt-qcow2 15 saverestore-support-check fail blocked in 184206 test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stopfail like 184206 test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stopfail like 184206 test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stopfail like 184206 test-armhf-armhf-libvirt 16 saverestore-support-checkfail like 184206 test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stopfail like 184206 test-armhf-armhf-libvirt-raw 15 saverestore-support-checkfail like 184206 test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 184206 test-amd64-amd64-libvirt 15 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-libvirt-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-xl-thunderx 15 migrate-support-checkfail never pass test-arm64-arm64-libvirt-xsm 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-thunderx 16 saverestore-support-checkfail never pass test-arm64-arm64-xl 15 migrate-support-checkfail never pass test-arm64-arm64-xl 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-credit2 15 migrate-support-checkfail never pass test-arm64-arm64-xl-credit2 16 saverestore-support-checkfail never pass test-armhf-armhf-xl 15 migrate-support-checkfail never pass test-armhf-armhf-xl 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-rtds 15 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-arndale 15 migrate-support-checkfail never pass test-armhf-armhf-xl-arndale 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit1 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit1 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-credit1 15 migrate-support-checkfail never pass test-arm64-arm64-xl-credit1 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-xl-xsm 16 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-qcow2 14 migrate-support-checkfail never pass test-amd64-amd64-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-raw 15 saverestore-support-checkfail never pass test-arm64-arm64-xl-vhd 14 migrate-support-checkfail never pass test-arm64-arm64-xl-vhd 15 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-qcow2 14 migrate-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass test-armhf-armhf-xl-vhd 14 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 15 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 15 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 16 saverestore-support-checkfail never pass test-armhf-armhf-libvirt 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 16 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-raw 14 migrate-support-checkfail never pass version targeted for testing: linux24e0d2e527a39f64caeb2e6be39ad5396fb2da5e baseline version: linux9a6b294ab496650e9f270123730df37030911b55 Last test of basis 184206 2023-12-21 22:43:55 Z1 days Testing same since 184212 2023-12-22 11:03:10 Z0 days1 attempts People who touched revisions under test: Alexis Lothoré Linus Torvalds Linus Walleij Mario Limonciello Nam Cao Patrick Rudolph jobs: build-amd64-xsm pass build-arm64-xsm pass build-i386-xsm pass build-amd64 pass build-arm64 pass build-armhf pass build-i386 pass build-amd64-libvirt pass build-arm64-libvirt
[PATCH] xen/livepatch: Make check_for_livepatch_work() faster in the common case
When livepatching is enabled, this function is used all the time. Really do check the fastpath first, and annotate it likely() as this is the right answer 100% of the time (to many significant figures). This cuts out 3 pointer dereferences in the "nothing to do path", and it seems the optimiser has an easier time too. Bloat-o-meter reports: add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-57 (-57) Function old new delta check_for_livepatch_work.cold 12011183 -18 check_for_livepatch_work1021 982 -39 which isn't too shabby for no logical change. Signed-off-by: Andrew Cooper --- CC: Konrad Rzeszutek Wilk CC: Ross Lagerwall CC: Jan Beulich CC: Roger Pau Monné CC: Wei Liu I'm still a little disappointed with the code generation. GCC still chooses to set up the full stack frame (6 regs, +3 more slots) intermixed with the per-cpu calculations. In isolation, GCC can check the boolean without creating a stack frame: : 48 89 e2mov%rsp,%rdx 48 8d 05 de e1 37 00lea0x37e1de(%rip),%rax# 82d0405b6068 48 81 ca ff 7f 00 00or $0x7fff,%rdx 8b 4a c1mov-0x3f(%rdx),%ecx 48 8d 15 45 aa 39 00lea0x39aa45(%rip),%rdx# 82d0405d28e0 <__per_cpu_offset> 48 8b 14 ca mov(%rdx,%rcx,8),%rdx 0f b6 04 02 movzbl (%rdx,%rax,1),%eax c3 retq but I can't find a way to convince GCC that it would be worth not setting up a stack frame in in the common case, and having a few extra mov reg/reg's later in the uncommon case. I haven't tried manually splitting the function into a check() and a do() function. Views on whether that might be acceptable? At a guess, do() would need to be a static noinline to avoid it turning back into what it currently is. --- xen/common/livepatch.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/common/livepatch.c b/xen/common/livepatch.c index 1209fea2566c..b6275339f663 100644 --- a/xen/common/livepatch.c +++ b/xen/common/livepatch.c @@ -1706,15 +1706,15 @@ void check_for_livepatch_work(void) s_time_t timeout; unsigned long flags; +/* Fast path: no work to do. */ +if ( likely(!per_cpu(work_to_do, cpu)) ) +return; + /* Only do any work when invoked in truly idle state. */ if ( system_state != SYS_STATE_active || !is_idle_domain(current->sched_unit->domain) ) return; -/* Fast path: no work to do. */ -if ( !per_cpu(work_to_do, cpu ) ) -return; - smp_rmb(); /* In case we aborted, other CPUs can skip right away. */ if ( !livepatch_work.do_work ) base-commit: 49818cde637b5ec20383e46b71f93b2e7d867686 -- 2.30.2
Re: [PATCH v3 31/34] xen/riscv: add minimal stuff to mm.h to build full Xen
On Fri, 2023-12-22 at 18:32 +0200, Oleksii wrote:
> > +
> > +struct page_info
> > +{
> > + /* Each frame can be threaded onto a doubly-linked list. */
> > + struct page_list_entry list;
> > +
> > + /* Reference count and various PGC_xxx flags and fields. */
> > + unsigned long count_info;
> > +
> > + /* Context-dependent fields follow... */
> > + union {
> > + /* Page is in use: ((count_info & PGC_count_mask) != 0).
> > */
> > + struct {
> > + /* Type reference count and various PGT_xxx flags and
> > fields. */
> > + unsigned long type_info;
> > + } inuse;
> > + /* Page is on a free list: ((count_info & PGC_count_mask)
> > ==
> > 0). */
> > + union {
> > + struct {
> > + /*
> > + * Index of the first *possibly* unscrubbed page
> > in
> > the buddy.
> > + * One more bit than maximum possible order to
> > accommodate
> > + * INVALID_DIRTY_IDX.
> > + */
> > +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1)
> > + unsigned long first_dirty:MAX_ORDER + 1;
> > +
> > + /* Do TLBs need flushing for safety before next
> > page
> > use? */
> > + bool need_tlbflush:1;
> > +
> > +#define BUDDY_NOT_SCRUBBING 0
> > +#define BUDDY_SCRUBBING 1
> > +#define BUDDY_SCRUB_ABORT 2
> > + unsigned long scrub_state:2;
> > + };
> > +
> > + unsigned long val;
> > + } free;
> > +
> > + } u;
> > +
> > + union {
> > + /* Page is in use, but not as a shadow. */
> > + struct {
> > + /* Owner of this page (zero if page is anonymous). */
> > + struct domain *domain;
> > + } inuse;
> > +
> > + /* Page is on a free list. */
> > + struct {
> > + /* Order-size of the free chunk this page is the head
> > of. */
> > + unsigned int order;
> > + } free;
> > +
> > + } v;
> > +
> > + union {
> > + /*
> > + * Timestamp from 'TLB clock', used to avoid extra safety
> > flushes.
> > + * Only valid for: a) free pages, and b) pages with zero
> > type count
> > + */
> > + uint32_t tlbflush_timestamp;
> > + };
> > + uint64_t pad;
I think it can be removed too. The changes weren't saved. ( Just
another one reminder for me ).
Sorry for the convenience.
~ Oleksii
>
[xen-unstable test] 184209: tolerable FAIL - PUSHED
flight 184209 xen-unstable real [real] flight 184213 xen-unstable real-retest [real] http://logs.test-lab.xenproject.org/osstest/logs/184209/ http://logs.test-lab.xenproject.org/osstest/logs/184213/ Failures :-/ but no regressions. Tests which are failing intermittently (not blocking): test-amd64-amd64-xl-qemuu-win7-amd64 12 windows-install fail pass in 184213-retest Tests which did not succeed, but are not blocking: test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stop fail in 184213 like 184204 test-armhf-armhf-libvirt 16 saverestore-support-checkfail like 184204 test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stopfail like 184204 test-amd64-i386-xl-qemuu-win7-amd64 19 guest-stop fail like 184204 test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stopfail like 184204 test-armhf-armhf-libvirt-qcow2 15 saverestore-support-check fail like 184204 test-amd64-i386-xl-qemut-ws16-amd64 19 guest-stop fail like 184204 test-armhf-armhf-libvirt-raw 15 saverestore-support-checkfail like 184204 test-amd64-i386-xl-qemut-win7-amd64 19 guest-stop fail like 184204 test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stopfail like 184204 test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 184204 test-amd64-i386-xl-qemuu-ws16-amd64 19 guest-stop fail like 184204 test-amd64-i386-libvirt-xsm 15 migrate-support-checkfail never pass test-amd64-amd64-libvirt 15 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 15 migrate-support-checkfail never pass test-amd64-i386-libvirt 15 migrate-support-checkfail never pass test-amd64-i386-xl-pvshim14 guest-start fail never pass test-arm64-arm64-xl 15 migrate-support-checkfail never pass test-arm64-arm64-xl-thunderx 15 migrate-support-checkfail never pass test-arm64-arm64-xl-thunderx 16 saverestore-support-checkfail never pass test-arm64-arm64-xl 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-xl-xsm 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-credit2 15 migrate-support-checkfail never pass test-arm64-arm64-xl-credit2 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-credit1 15 migrate-support-checkfail never pass test-arm64-arm64-xl-credit1 16 saverestore-support-checkfail never pass test-arm64-arm64-libvirt-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-libvirt-xsm 16 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass test-armhf-armhf-xl-credit2 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 15 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-rtds 15 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 16 saverestore-support-checkfail never pass test-armhf-armhf-libvirt 15 migrate-support-checkfail never pass test-armhf-armhf-xl-arndale 15 migrate-support-checkfail never pass test-armhf-armhf-xl-arndale 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit1 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit1 16 saverestore-support-checkfail never pass test-amd64-i386-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-raw 15 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-vhd 14 migrate-support-checkfail never pass test-arm64-arm64-xl-vhd 14 migrate-support-checkfail never pass test-arm64-arm64-xl-vhd 15 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-qcow2 14 migrate-support-checkfail never pass test-armhf-armhf-libvirt-raw 14 migrate-support-checkfail never pass test-armhf-armhf-xl 15 migrate-support-checkfail never pass test-armhf-armhf-xl 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-vhd 14 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 15 saverestore-support-checkfail never pass version targeted for testing: xen 49818cde637b5ec20383e46b71f93b2e7d867686 baseline version: xen 3909fb4692dfbf7e46c0bcc37b0a3b943a034da9 Last test of basis 184204 2023-12-21 14:58:45
Re: [GIT PULL] xen: branch for v6.7-rc7
The pull request you sent on Fri, 22 Dec 2023 07:34:15 +0100: > git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git > for-linus-6.7a-rc7-tag has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/b7bc7bce88bdf52ec2b47c576fb51269a521bd9a Thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/prtracker.html
Re: [PATCH v3 31/34] xen/riscv: add minimal stuff to mm.h to build full Xen
On Fri, 2023-12-22 at 17:13 +0200, Oleksii Kurochko wrote:
> Signed-off-by: Oleksii Kurochko
> ---
> Changes in V3:
> - update the commit message
> - introduce DIRECTMAP_VIRT_START.
> - drop changes related pfn_to_paddr() and paddr_to_pfn as they were
> remvoe in
> [PATCH v2 32/39] xen/riscv: add minimal stuff to asm/page.h to
> build full Xen
> - code style fixes.
> - drop get_page_nr and put_page_nr as they don't need for time
> being
> - drop CONFIG_STATIC_MEMORY related things
> - code style fixes
> ---
> Changes in V2:
> - define stub for arch_get_dma_bitsize(void)
> ---
> xen/arch/riscv/include/asm/config.h | 2 +
> xen/arch/riscv/include/asm/mm.h | 248
>
> 2 files changed, 250 insertions(+)
>
> diff --git a/xen/arch/riscv/include/asm/config.h
> b/xen/arch/riscv/include/asm/config.h
> index fb9fc9daaa..400309f4ef 100644
> --- a/xen/arch/riscv/include/asm/config.h
> +++ b/xen/arch/riscv/include/asm/config.h
> @@ -67,6 +67,8 @@
>
> #define XEN_VIRT_START 0xC000 /* (_AC(-1, UL) + 1 -
> GB(1)) */
>
> +#define DIRECTMAP_VIRT_START SLOTN(200)
> +
> #define FRAMETABLE_VIRT_START SLOTN(196)
> #define FRAMETABLE_SIZE GB(3)
> #define FRAMETABLE_NR (FRAMETABLE_SIZE /
> sizeof(*frame_table))
> diff --git a/xen/arch/riscv/include/asm/mm.h
> b/xen/arch/riscv/include/asm/mm.h
> index 57026e134d..14fce72fde 100644
> --- a/xen/arch/riscv/include/asm/mm.h
> +++ b/xen/arch/riscv/include/asm/mm.h
> @@ -3,8 +3,251 @@
> #ifndef _ASM_RISCV_MM_H
> #define _ASM_RISCV_MM_H
>
> +#include
> +#include
> +#include
> +
> +#include
> #include
>
> +#define paddr_to_pdx(pa) mfn_to_pdx(maddr_to_mfn(pa))
> +#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn))
> +#define gaddr_to_gfn(ga) _gfn(paddr_to_pfn(ga))
> +#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn))
> +#define maddr_to_mfn(ma) _mfn(paddr_to_pfn(ma))
> +#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)va))
> +#define vmap_to_page(va) mfn_to_page(vmap_to_mfn(va))
> +#define paddr_to_pdx(pa) mfn_to_pdx(maddr_to_mfn(pa))
> +#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn))
> +#define gaddr_to_gfn(ga) _gfn(paddr_to_pfn(ga))
> +#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn))
> +#define maddr_to_mfn(ma) _mfn(paddr_to_pfn(ma))
> +#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)va))
> +#define vmap_to_page(va) mfn_to_page(vmap_to_mfn(va))
> +
> +#define virt_to_maddr(va) ((paddr_t)((vaddr_t)(va) & PADDR_MASK))
> +#define maddr_to_virt(pa) ((void *)((paddr_t)(pa) |
> DIRECTMAP_VIRT_START))
> +
> +/* Convert between Xen-heap virtual addresses and machine frame
> numbers. */
> +#define __virt_to_mfn(va) (virt_to_maddr(va) >> PAGE_SHIFT)
> +#define __mfn_to_virt(mfn) maddr_to_virt((paddr_t)(mfn) <<
> PAGE_SHIFT)
> +
> +/* Convert between Xen-heap virtual addresses and page-info
> structures. */
> +static inline struct page_info *virt_to_page(const void *v)
> +{
> + BUG();
> + return NULL;
> +}
> +
> +/*
> + * We define non-underscored wrappers for above conversion
> functions.
> + * These are overriden in various source files while underscored
> version
> + * remain intact.
> + */
> +#define virt_to_mfn(va) __virt_to_mfn(va)
> +#define mfn_to_virt(mfn) __mfn_to_virt(mfn)
> +
> +struct page_info
> +{
> + /* Each frame can be threaded onto a doubly-linked list. */
> + struct page_list_entry list;
> +
> + /* Reference count and various PGC_xxx flags and fields. */
> + unsigned long count_info;
> +
> + /* Context-dependent fields follow... */
> + union {
> + /* Page is in use: ((count_info & PGC_count_mask) != 0). */
> + struct {
> + /* Type reference count and various PGT_xxx flags and
> fields. */
> + unsigned long type_info;
> + } inuse;
> + /* Page is on a free list: ((count_info & PGC_count_mask) ==
> 0). */
> + union {
> + struct {
> + /*
> + * Index of the first *possibly* unscrubbed page in
> the buddy.
> + * One more bit than maximum possible order to
> accommodate
> + * INVALID_DIRTY_IDX.
> + */
> +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1)
> + unsigned long first_dirty:MAX_ORDER + 1;
> +
> + /* Do TLBs need flushing for safety before next page
> use? */
> + bool need_tlbflush:1;
> +
> +#define BUDDY_NOT_SCRUBBING 0
> +#define BUDDY_SCRUBBING 1
> +#define BUDDY_SCRUB_ABORT 2
> + unsigned long scrub_state:2;
> + };
> +
> + unsigned long val;
> + } free;
> +
> + } u;
> +
> + union {
> + /* Page is in use, but not as a shadow. */
> + struct {
> + /* Owner of this page (zero if page is anonymous). */
> + struct domain *domain;
> + } inuse;
> +
> + /* Page is on
Re: [PATCH v6 9/9] xen/asm-generic: introduce generic device.h
> > > Generally, > > I think it's okay not to use #ifdef DEVICE_PCI_HOSTBRIDGE to keep > > the Arm code cleaner. > > > > Does it make sense? > > I don't quite understand your last sentence. Are you saying you would > be > ok to remove #ifdef CONFIG_HAS_PCI around DEVICE_PCI_HOSTBRIDGE? Yes, that is what I meant. ~ Oleksii
Re: hvmloader - allow_memory_relocate overlaps
> > ''' > > > > And the associated result is: > > > > (d22) NEOWUTRAN pci.c: pci_mem_end: -67108864 > > (d22) NEOWUTRAN pci.c: pci_mem_start: -268435456 > > (d22) NEOWUTRAN pci.c: allow_memory_relocate: 0 > > (d22) NEOWUTRAN pci.c:�� hvm_info->low_mem_pgend: 983040 > > (d22) NEOWUTRAN pci.c: HVM_LOADER would have tried to relocate guest memory > > (d22) NEOWUTRAN pci.c: pci_mem_start: -268435456 > > > > So if "allow_memory_relocate" was not defined to 0, the hvmloader > > would have tried to overlaps guest memory, and it seems that is > > something that qemu_xen cannot handle. > > Well, memory addresses printed in decimal are pretty hard to work with. > But I'd like to ask anyway that you supply all of the log messages for > such a guest starting, to be able to correlate what you've added with > other items also logged. Full logs with my patch to set allow-memory-relocate (https://github.com/neowutran/qubes-vmm-xen/commit/819705bc346cad14836fd523195ad2b0445330ac) https://pastebin.com/9kQgvraK (GPU passthrough work, hvmloader doesn't overlaps with guest memory) Full logs without my patch to set allow-memory-relocate (https://github.com/neowutran/qubes-vmm-xen/blob/allowmemoryrelocate/ALLOWMEMORYRELOCATE.patch) https://pastebin.com/g�� QGg55WZ (GPU passthrough doesn't work, hvmloader overlaps with guest memory) > > Jan Thanks, Neowutran ��
[PATCH v3 32/34] xen/rirscv: add minimal amount of stubs to build full Xen
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- code style fixes.
- update attribute for frametable_base_pdx and frametable_virt_end to
__ro_after_init.
insteaf of read_mostly.
- use BUG() instead of assert_failed/WARN for newly introduced stubs.
- drop "#include " in stubs.c and use forward declaration
instead.
- drop ack_node() and end_node() as they aren't used now.
---
Changes in V2:
- define udelay stub
- remove 'select HAS_PDX' from RISC-V Kconfig because of
https://lore.kernel.org/xen-devel/20231006144405.1078260-1-andrew.coop...@citrix.com/
---
xen/arch/riscv/Makefile | 1 +
xen/arch/riscv/early_printk.c | 168 --
xen/arch/riscv/mm.c | 52 -
xen/arch/riscv/setup.c| 9 +-
xen/arch/riscv/stubs.c| 422 ++
xen/arch/riscv/traps.c| 25 ++
6 files changed, 507 insertions(+), 170 deletions(-)
create mode 100644 xen/arch/riscv/stubs.c
diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile
index 2fefe14e7c..5523191bb7 100644
--- a/xen/arch/riscv/Makefile
+++ b/xen/arch/riscv/Makefile
@@ -4,6 +4,7 @@ obj-y += mm.o
obj-$(CONFIG_RISCV_64) += riscv64/
obj-y += sbi.o
obj-y += setup.o
+obj-y += stubs.o
obj-y += traps.o
$(TARGET): $(TARGET)-syms
diff --git a/xen/arch/riscv/early_printk.c b/xen/arch/riscv/early_printk.c
index 60742a042d..610c814f54 100644
--- a/xen/arch/riscv/early_printk.c
+++ b/xen/arch/riscv/early_printk.c
@@ -40,171 +40,3 @@ void early_printk(const char *str)
str++;
}
}
-
-/*
- * The following #if 1 ... #endif should be removed after printk
- * and related stuff are ready.
- */
-#if 1
-
-#include
-#include
-
-/**
- * strlen - Find the length of a string
- * @s: The string to be sized
- */
-size_t (strlen)(const char * s)
-{
-const char *sc;
-
-for (sc = s; *sc != '\0'; ++sc)
-/* nothing */;
-return sc - s;
-}
-
-/**
- * memcpy - Copy one area of memory to another
- * @dest: Where to copy to
- * @src: Where to copy from
- * @count: The size of the area.
- *
- * You should not use this function to access IO space, use memcpy_toio()
- * or memcpy_fromio() instead.
- */
-void *(memcpy)(void *dest, const void *src, size_t count)
-{
-char *tmp = (char *) dest, *s = (char *) src;
-
-while (count--)
-*tmp++ = *s++;
-
-return dest;
-}
-
-int vsnprintf(char* str, size_t size, const char* format, va_list args)
-{
-size_t i = 0; /* Current position in the output string */
-size_t written = 0; /* Total number of characters written */
-char* dest = str;
-
-while ( format[i] != '\0' && written < size - 1 )
-{
-if ( format[i] == '%' )
-{
-i++;
-
-if ( format[i] == '\0' )
-break;
-
-if ( format[i] == '%' )
-{
-if ( written < size - 1 )
-{
-dest[written] = '%';
-written++;
-}
-i++;
-continue;
-}
-
-/*
- * Handle format specifiers.
- * For simplicity, only %s and %d are implemented here.
- */
-
-if ( format[i] == 's' )
-{
-char* arg = va_arg(args, char*);
-size_t arglen = strlen(arg);
-
-size_t remaining = size - written - 1;
-
-if ( arglen > remaining )
-arglen = remaining;
-
-memcpy(dest + written, arg, arglen);
-
-written += arglen;
-i++;
-}
-else if ( format[i] == 'd' )
-{
-int arg = va_arg(args, int);
-
-/* Convert the integer to string representation */
-char numstr[32]; /* Assumes a maximum of 32 digits */
-int numlen = 0;
-int num = arg;
-size_t remaining;
-
-if ( arg < 0 )
-{
-if ( written < size - 1 )
-{
-dest[written] = '-';
-written++;
-}
-
-num = -arg;
-}
-
-do
-{
-numstr[numlen] = '0' + num % 10;
-num = num / 10;
-numlen++;
-} while ( num > 0 );
-
-/* Reverse the string */
-for (int j = 0; j < numlen / 2; j++)
-{
-char tmp = numstr[j];
-numstr[j] = numstr[numlen - 1 - j];
-numstr[numlen - 1 - j] = tmp;
-}
-
-remaining = size - written - 1;
-
-if ( numlen > remaining )
-numlen = remaining;
-
-memcpy(dest + written, numstr, numlen);
-
-written += numlen;
-
[PATCH v3 29/34] xen/riscv: add minimal stuff to page.h to build full Xen
Signed-off-by: Oleksii Kurochko
Acked-by: Jan Beulich
---
Changes in V3:
- update the commit message
- add implemetation of PAGE_HYPERVISOR macros
- add Acked-by: Jan Beulich
- drop definition of pfn_to_addr, and paddr_to_pfn in
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/mm.h | 3 ---
xen/arch/riscv/include/asm/page.h | 22 ++
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h
index 07c7a0abba..57026e134d 100644
--- a/xen/arch/riscv/include/asm/mm.h
+++ b/xen/arch/riscv/include/asm/mm.h
@@ -5,9 +5,6 @@
#include
-#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT)
-#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT))
-
extern unsigned char cpu0_boot_stack[];
void setup_initial_pagetables(void);
diff --git a/xen/arch/riscv/include/asm/page.h
b/xen/arch/riscv/include/asm/page.h
index 95074e29b3..85176702d5 100644
--- a/xen/arch/riscv/include/asm/page.h
+++ b/xen/arch/riscv/include/asm/page.h
@@ -6,6 +6,7 @@
#ifndef __ASSEMBLY__
#include
+#include
#include
#include
@@ -32,6 +33,10 @@
#define PTE_LEAF_DEFAULT(PTE_VALID | PTE_READABLE | PTE_WRITABLE)
#define PTE_TABLE (PTE_VALID)
+#define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITABLE)
+
+#define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW
+
/* Calculate the offsets into the pagetables for a given VA */
#define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl))
@@ -46,6 +51,9 @@ typedef struct {
#endif
} pte_t;
+#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT)
+#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT))
+
static inline pte_t paddr_to_pte(paddr_t paddr,
unsigned int permissions)
{
@@ -62,6 +70,20 @@ static inline bool pte_is_valid(pte_t p)
return p.pte & PTE_VALID;
}
+static inline void invalidate_icache(void)
+{
+BUG();
+}
+
+#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
+#define copy_page(dp, sp) memcpy(dp, sp, PAGE_SIZE)
+
+/* TODO: Flush the dcache for an entire page. */
+static inline void flush_page_to_ram(unsigned long mfn, bool sync_icache)
+{
+BUG();
+}
+
#endif /* __ASSEMBLY__ */
#endif /* _ASM_RISCV_PAGE_H */
--
2.43.0
[PATCH v3 28/34] xen/riscv: add required things to current.h
Add minimal requied things to be able to build full Xen.
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- add SPDX
- drop a forward declaration of struct vcpu;
- update guest_cpu_user_regs() macros
- replace get_processor_id with smp_processor_id
- update the commit message
- code style fixes
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/current.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/xen/arch/riscv/include/asm/current.h
b/xen/arch/riscv/include/asm/current.h
index d84f15dc50..1694f68c6f 100644
--- a/xen/arch/riscv/include/asm/current.h
+++ b/xen/arch/riscv/include/asm/current.h
@@ -3,6 +3,21 @@
#ifndef __ASM_CURRENT_H
#define __ASM_CURRENT_H
+#include
+#include
+#include
+
+#ifndef __ASSEMBLY__
+
+/* Which VCPU is "current" on this PCPU. */
+DECLARE_PER_CPU(struct vcpu *, curr_vcpu);
+
+#define currentthis_cpu(curr_vcpu)
+#define set_current(vcpu) do { current = (vcpu); } while (0)
+#define get_cpu_current(cpu) per_cpu(curr_vcpu, cpu)
+
+#define guest_cpu_user_regs() ({ BUG(); NULL; })
+
#define switch_stack_and_jump(stack, fn) do { \
asm volatile ( \
"mv sp, %0\n" \
@@ -10,4 +25,8 @@
unreachable(); \
} while ( false )
+#define get_per_cpu_offset() __per_cpu_offset[smp_processor_id()]
+
+#endif /* __ASSEMBLY__ */
+
#endif /* __ASM_CURRENT_H */
--
2.43.0
[PATCH v3 13/34] xen/riscv: introduce cmpxchg.h
The header was taken from Linux kernl 6.4.0-rc1.
Addionally, were updated:
* add emulation of {cmp}xchg for 1/2 byte types
* replace tabs with spaces
* replace __* varialbed with *__
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- update the commit message
- add emulation of {cmp}xchg_... for 1 and 2 bytes types
---
Changes in V2:
- update the comment at the top of the header.
- change xen/lib.h to xen/bug.h.
- sort inclusion of headers properly.
---
xen/arch/riscv/include/asm/cmpxchg.h | 496 +++
1 file changed, 496 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/cmpxchg.h
diff --git a/xen/arch/riscv/include/asm/cmpxchg.h
b/xen/arch/riscv/include/asm/cmpxchg.h
new file mode 100644
index 00..916776c403
--- /dev/null
+++ b/xen/arch/riscv/include/asm/cmpxchg.h
@@ -0,0 +1,496 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2014 Regents of the University of California */
+
+#ifndef _ASM_RISCV_CMPXCHG_H
+#define _ASM_RISCV_CMPXCHG_H
+
+#include
+#include
+
+#include
+#include
+#include
+
+#define __xchg_relaxed(ptr, new, size) \
+({ \
+__typeof__(ptr) ptr__ = (ptr); \
+__typeof__(new) new__ = (new); \
+__typeof__(*(ptr)) ret__; \
+switch (size) \
+ { \
+case 4: \
+asm volatile( \
+" amoswap.w %0, %2, %1\n" \
+: "=r" (ret__), "+A" (*ptr__) \
+: "r" (new__) \
+: "memory" ); \
+break; \
+case 8: \
+asm volatile( \
+" amoswap.d %0, %2, %1\n" \
+: "=r" (ret__), "+A" (*ptr__) \
+: "r" (new__) \
+: "memory" ); \
+break; \
+default: \
+ASSERT_UNREACHABLE(); \
+} \
+ret__; \
+})
+
+#define xchg_relaxed(ptr, x) \
+({ \
+__typeof__(*(ptr)) x_ = (x); \
+(__typeof__(*(ptr))) __xchg_relaxed((ptr), x_, sizeof(*(ptr))); \
+})
+
+#define __xchg_acquire(ptr, new, size) \
+({ \
+__typeof__(ptr) ptr__ = (ptr); \
+__typeof__(new) new__ = (new); \
+__typeof__(*(ptr)) ret__; \
+switch (size) \
+ { \
+case 4: \
+asm volatile( \
+" amoswap.w %0, %2, %1\n" \
+RISCV_ACQUIRE_BARRIER \
+: "=r" (ret__), "+A" (*ptr__) \
+: "r" (new__) \
+: "memory" ); \
+break; \
+case 8: \
+asm volatile( \
+" amoswap.d %0, %2, %1\n" \
+RISCV_ACQUIRE_BARRIER \
+: "=r" (ret__), "+A" (*ptr__) \
+: "r" (new__) \
+: "memory" ); \
+break; \
+default: \
+ASSERT_UNREACHABLE(); \
+} \
+ret__; \
+})
+
+#define xchg_acquire(ptr, x) \
+({ \
+__typeof__(*(ptr)) x_ = (x); \
+(__typeof__(*(ptr))) __xchg_acquire((ptr), x_, sizeof(*(ptr))); \
+})
+
+#define __xchg_release(ptr, new, size) \
+({ \
+__typeof__(ptr) ptr__ = (ptr); \
+__typeof__(new) new__ = (new); \
+__typeof__(*(ptr)) ret__; \
+switch (size) \
+ { \
+case 4: \
+asm volatile ( \
+RISCV_RELEASE_BARRIER \
+" amoswap.w %0, %2, %1\n" \
+: "=r" (ret__), "+A" (*ptr__) \
+: "r" (new__) \
+: "memory"); \
+break; \
+case 8: \
+asm volatile ( \
+RISCV_RELEASE_BARRIER \
+" amoswap.d %0, %2, %1\n" \
+: "=r" (ret__), "+A" (*ptr__) \
+: "r" (new__) \
+: "memory"); \
+break; \
+default: \
+ASSERT_UNREACHABLE(); \
+} \
+ret__; \
+})
+
+#define xchg_release(ptr, x) \
+({ \
+__typeof__(*(ptr)) x_ = (x); \
+(__typeof__(*(ptr))) __xchg_release((ptr), x_, sizeof(*(ptr))); \
+})
+
+static always_inline uint32_t __xchg_case_4(volatile uint32_t *ptr,
+uint32_t new)
+{
+__typeof__(*(ptr)) ret;
+
+asm volatile (
+" amoswap.w.aqrl %0, %2, %1\n"
+: "=r" (ret), "+A" (*ptr)
+: "r" (new)
+: "memory" );
+
+return ret;
+}
+
+static always_inline uint64_t __xchg_case_8(volatile uint64_t *ptr,
+uint64_t new)
+{
+__typeof__(*(ptr)) ret;
+
+asm volatile( \
+" amoswap.d.aqrl %0, %2, %1\n" \
+: "=r" (ret), "+A" (*ptr) \
+: "r" (new) \
+: "memory" ); \
+
+return ret;
+}
+
+static always_inline unsigned short __cmpxchg_case_2(volatile uint32_t *ptr,
+ uint32_t old,
+ uint32_t new);
+
+static always_inline unsigned short __cmpxchg_case_1(volatile uint32_t *ptr,
+ uint32_t old,
+ uint32_t new);
+
+static inline unsigned long __xchg(volatile void *ptr, unsigned long x, int
size)
+{
+switch (size) {
+case 1:
+return __cmpxchg_case_1(ptr, (uint32_t)-1,
[PATCH v3 14/34] xen/riscv: introduce io.h
The header taken form Linux 6.4.0-rc1 and is based on
arch/riscv/include/asm/mmio.h.
Addionally, to the header was added definions of ioremap_*().
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- re-sync with linux kernel
- update the commit message
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/io.h | 142
1 file changed, 142 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/io.h
diff --git a/xen/arch/riscv/include/asm/io.h b/xen/arch/riscv/include/asm/io.h
new file mode 100644
index 00..ead466eb2d
--- /dev/null
+++ b/xen/arch/riscv/include/asm/io.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
+ * which was based on arch/arm/include/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ * Copyright (C) 2014 Regents of the University of California
+ */
+
+
+#ifndef _ASM_RISCV_IO_H
+#define _ASM_RISCV_IO_H
+
+#include
+
+/*
+ * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
+ * change the properties of memory regions. This should be fixed by the
+ * upcoming platform spec.
+ */
+#define ioremap_nocache(addr, size) ioremap((addr), (size))
+#define ioremap_wc(addr, size) ioremap((addr), (size))
+#define ioremap_wt(addr, size) ioremap((addr), (size))
+
+/* Generic IO read/write. These perform native-endian accesses. */
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+ asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+ asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+ asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
+}
+
+#ifdef CONFIG_64BIT
+#define __raw_writeq __raw_writeq
+static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
+{
+ asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
+}
+#endif
+
+#define __raw_readb __raw_readb
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+ u8 val;
+
+ asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+#define __raw_readw __raw_readw
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+ u16 val;
+
+ asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+#define __raw_readl __raw_readl
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+ u32 val;
+
+ asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+#ifdef CONFIG_64BIT
+#define __raw_readq __raw_readq
+static inline u64 __raw_readq(const volatile void __iomem *addr)
+{
+ u64 val;
+
+ asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
+ return val;
+}
+#endif
+
+/*
+ * Unordered I/O memory access primitives. These are even more relaxed than
+ * the relaxed versions, as they don't even order accesses between successive
+ * operations to the I/O regions.
+ */
+#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
+#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force
__le16)__raw_readw(c)); __r; })
+#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force
__le32)__raw_readl(c)); __r; })
+
+#define writeb_cpu(v,c)((void)__raw_writeb((v),(c)))
+#define writew_cpu(v,c)((void)__raw_writew((__force
u16)cpu_to_le16(v),(c)))
+#define writel_cpu(v,c)((void)__raw_writel((__force
u32)cpu_to_le32(v),(c)))
+
+#ifdef CONFIG_64BIT
+#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force
__le64)__raw_readq(c)); __r; })
+#define writeq_cpu(v,c)((void)__raw_writeq((__force
u64)cpu_to_le64(v),(c)))
+#endif
+
+/*
+ * I/O memory access primitives. Reads are ordered relative to any
+ * following Normal memory access. Writes are ordered relative to any prior
+ * Normal memory access. The memory barriers here are necessary as RISC-V
+ * doesn't define any ordering between the memory space and the I/O space.
+ */
+#define __io_br() do {} while (0)
+#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory");
+#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
+#define __io_aw() do { } while (0)
+
+#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c);
__io_ar(__v); __v; })
+#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c);
__io_ar(__v); __v; })
+#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c);
__io_ar(__v); __v; })
+
+#define writeb(v,c)({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); })
+#define writew(v,c)({ __io_bw(); writew_cpu((v),(c));
[PATCH v3 17/34] xen/riscv: add compilation of generic find-next-bit.c
Signed-off-by: Oleksii Kurochko --- Changes in V3: - new patch --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/configs/tiny64_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index f382b36f6c..b8f8c083dc 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -4,6 +4,7 @@ config RISCV config RISCV_64 def_bool y select 64BIT + select GENERIC_FIND_NEXT_BIT config ARCH_DEFCONFIG string diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig index 35915255e6..399128be02 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -29,3 +29,4 @@ CONFIG_RISCV_64=y CONFIG_DEBUG=y CONFIG_DEBUG_INFO=y CONFIG_EXPERT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y -- 2.43.0
[PATCH v3 16/34] xen/lib: introduce generic find next bit operations
find-next-bit.c is common for Arm64 and RISC-V64 so it is moved
to xen/lib.
Suggested-by: Jan Beulich
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- new patch.
---
xen/arch/riscv/include/asm/fence.h | 11 +-
xen/common/Kconfig | 3 +
xen/lib/Makefile | 1 +
xen/lib/find-next-bit.c| 281 +
4 files changed, 295 insertions(+), 1 deletion(-)
create mode 100644 xen/lib/find-next-bit.c
diff --git a/xen/arch/riscv/include/asm/fence.h
b/xen/arch/riscv/include/asm/fence.h
index b3f6b1c20a..5d9a851ae8 100644
--- a/xen/arch/riscv/include/asm/fence.h
+++ b/xen/arch/riscv/include/asm/fence.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _ASM_RISCV_FENCE_H
#define _ASM_RISCV_FENCE_H
@@ -11,3 +11,12 @@
#endif
#endif /* _ASM_RISCV_FENCE_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/common/Kconfig b/xen/common/Kconfig
index 310ad4229c..56ce34ffd4 100644
--- a/xen/common/Kconfig
+++ b/xen/common/Kconfig
@@ -47,6 +47,9 @@ config ARCH_MAP_DOMAIN_PAGE
config GENERIC_BUG_FRAME
bool
+config GENERIC_FIND_NEXT_BIT
+ bool
+
config HAS_ALTERNATIVE
bool
diff --git a/xen/lib/Makefile b/xen/lib/Makefile
index 2d9ebb945f..66237a45c5 100644
--- a/xen/lib/Makefile
+++ b/xen/lib/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_X86) += x86/
lib-y += bsearch.o
lib-y += ctors.o
lib-y += ctype.o
+lib-$(CONFIG_GENERIC_FIND_NEXT_BIT) += find-next-bit.o
lib-y += list-sort.o
lib-y += memchr.o
lib-y += memchr_inv.o
diff --git a/xen/lib/find-next-bit.c b/xen/lib/find-next-bit.c
new file mode 100644
index 00..ca6f82277e
--- /dev/null
+++ b/xen/lib/find-next-bit.c
@@ -0,0 +1,281 @@
+/* find_next_bit.c: fallback find next bit implementation
+ *
+ * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowe...@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include
+
+#include
+
+#ifndef find_next_bit
+/*
+ * Find the next set bit in a memory region.
+ */
+unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
+ unsigned long offset)
+{
+ const unsigned long *p = addr + BIT_WORD(offset);
+ unsigned long result = offset & ~(BITS_PER_LONG-1);
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset %= BITS_PER_LONG;
+ if (offset) {
+ tmp = *(p++);
+ tmp &= (~0UL << offset);
+ if (size < BITS_PER_LONG)
+ goto found_first;
+ if (tmp)
+ goto found_middle;
+ size -= BITS_PER_LONG;
+ result += BITS_PER_LONG;
+ }
+ while (size & ~(BITS_PER_LONG-1)) {
+ if ((tmp = *(p++)))
+ goto found_middle;
+ result += BITS_PER_LONG;
+ size -= BITS_PER_LONG;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+found_first:
+ tmp &= (~0UL >> (BITS_PER_LONG - size));
+ if (tmp == 0UL) /* Are any bits set? */
+ return result + size; /* Nope. */
+found_middle:
+ return result + __ffs(tmp);
+}
+EXPORT_SYMBOL(find_next_bit);
+#endif
+
+#ifndef find_next_zero_bit
+/*
+ * This implementation of find_{first,next}_zero_bit was stolen from
+ * Linus' asm-alpha/bitops.h.
+ */
+unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size,
+unsigned long offset)
+{
+ const unsigned long *p = addr + BIT_WORD(offset);
+ unsigned long result = offset & ~(BITS_PER_LONG-1);
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset %= BITS_PER_LONG;
+ if (offset) {
+ tmp = *(p++);
+ tmp |= ~0UL >> (BITS_PER_LONG - offset);
+ if (size < BITS_PER_LONG)
+ goto found_first;
+ if (~tmp)
+ goto found_middle;
+ size -= BITS_PER_LONG;
+ result += BITS_PER_LONG;
+ }
+ while (size & ~(BITS_PER_LONG-1)) {
+ if (~(tmp = *(p++)))
+ goto found_middle;
+ result += BITS_PER_LONG;
+ size -= BITS_PER_LONG;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+found_first:
+ tmp |= ~0UL << size;
+ if (tmp == ~0UL)/* Are any bits zero? */
+ return result + size;
[PATCH v3 15/34] xen/riscv: introduce atomic.h
From: Bobby Eshleman
Additionally, this patch introduces macros in fence.h,
which are utilized in atomic.h.
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- update the commit message
- add SPDX for fence.h
- code style fixes
- Remove /* TODO: ... */ for add_sized macros. It looks correct to me.
- re-order the patch
- merge to this patch fence.h
---
Changes in V2:
- Change an author of commit. I got this header from Bobby's old repo.
---
xen/arch/riscv/include/asm/atomic.h | 384
xen/arch/riscv/include/asm/fence.h | 13 +
2 files changed, 397 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/atomic.h
create mode 100644 xen/arch/riscv/include/asm/fence.h
diff --git a/xen/arch/riscv/include/asm/atomic.h
b/xen/arch/riscv/include/asm/atomic.h
new file mode 100644
index 00..725326a9d1
--- /dev/null
+++ b/xen/arch/riscv/include/asm/atomic.h
@@ -0,0 +1,384 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Taken and modified from Linux.
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Copyright (C) 2012 Regents of the University of California
+ * Copyright (C) 2017 SiFive
+ * Copyright (C) 2021 Vates SAS
+ */
+
+#ifndef _ASM_RISCV_ATOMIC_H
+#define _ASM_RISCV_ATOMIC_H
+
+#include
+#include
+#include
+#include
+#include
+
+void __bad_atomic_size(void);
+
+static always_inline void read_atomic_size(const volatile void *p,
+ void *res,
+ unsigned int size)
+{
+switch ( size )
+{
+case 1: *(uint8_t *)res = readb((const uint8_t *)p); break;
+case 2: *(uint16_t *)res = readw((const uint16_t *)p); break;
+case 4: *(uint32_t *)res = readl((const uint32_t *)p); break;
+case 8: *(uint32_t *)res = readq((const uint64_t *)p); break;
+default: __bad_atomic_size(); break;
+}
+}
+
+#define read_atomic(p) ({ \
+union { typeof(*p) val; char c[0]; } x_;\
+read_atomic_size(p, x_.c, sizeof(*p)); \
+x_.val; \
+})
+
+
+#define write_atomic(p, x) ({ \
+typeof(*p) x__ = (x); \
+switch ( sizeof(*p) )
\
+{
\
+case 1: writeb((uint8_t)x__, (uint8_t *) p); break;
\
+case 2: writew((uint16_t)x__, (uint16_t *) p); break;
\
+case 4: writel((uint32_t)x__, (uint32_t *) p); break;
\
+case 8: writeq((uint64_t)x__, (uint64_t *) p); break;
\
+default: __bad_atomic_size(); break;\
+} \
+x__;\
+})
+
+#define add_sized(p, x) ({ \
+typeof(*(p)) x__ = (x); \
+switch ( sizeof(*(p)) ) \
+{ \
+case 1: writeb(read_atomic(p) + x__, (uint8_t *)(p)); break;\
+case 2: writew(read_atomic(p) + x__, (uint16_t *)(p)); break; \
+case 4: writel(read_atomic(p) + x__, (uint32_t *)(p)); break; \
+default: __bad_atomic_size(); break;\
+} \
+})
+
+/*
+ * __unqual_scalar_typeof(x) - Declare an unqualified scalar type, leaving
+ * non-scalar types unchanged.
+ *
+ * Prefer C11 _Generic for better compile-times and simpler code. Note: 'char'
+ * is not type-compatible with 'signed char', and we define a separate case.
+ */
+#define __scalar_type_to_expr_cases(type) \
+unsigned type: (unsigned type)0, \
+signed type:(signed type)0
+
+#define __unqual_scalar_typeof(x) typeof( \
+_Generic((x), \
+char: (char)0, \
+__scalar_type_to_expr_cases(char), \
+__scalar_type_to_expr_cases(short), \
+__scalar_type_to_expr_cases(int), \
+__scalar_type_to_expr_cases(long), \
+__scalar_type_to_expr_cases(long long), \
+default: (x)))
+
+#define READ_ONCE(x) (*(const volatile __unqual_scalar_typeof(x) *)&(x))
+#define WRITE_ONCE(x, val) \
+do {\
+
[PATCH v3 19/34] xen/riscv: introduce guest_access.h
All necessary dummiy implementation of functions in this header will be introduced in stubs.c Signed-off-by: Oleksii Kurochko --- Changes in V3: - remove unnessary inclusion of types.h header. - drop copy_to_guest_phys. it isn't needed yet - add SPDX - add comment above guest_handle_okay() - update the commit message --- Changes in V2: - change xen/mm.h to xen/types.h --- xen/arch/riscv/include/asm/guest_access.h | 29 +++ 1 file changed, 29 insertions(+) create mode 100644 xen/arch/riscv/include/asm/guest_access.h diff --git a/xen/arch/riscv/include/asm/guest_access.h b/xen/arch/riscv/include/asm/guest_access.h new file mode 100644 index 00..c55951f538 --- /dev/null +++ b/xen/arch/riscv/include/asm/guest_access.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_GUEST_ACCESS_H__ +#define __ASM_RISCV_GUEST_ACCESS_H__ + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned len); +unsigned long raw_copy_from_guest(void *to, const void *from, unsigned len); +unsigned long raw_clear_guest(void *to, unsigned int len); + +#define __raw_copy_to_guest raw_copy_to_guest +#define __raw_copy_from_guest raw_copy_from_guest +#define __raw_clear_guest raw_clear_guest + +/* + * Pre-validate a guest handle. + * Allows use of faster __copy_* functions. + */ +/* All RISCV guests are paging mode external and hence safe */ +#define guest_handle_okay(hnd, nr) (1) +#define guest_handle_subrange_okay(hnd, first, last) (1) + +#endif /* __ASM_RISCV_GUEST_ACCESS_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.43.0
[PATCH v3 21/34] xen/riscv: introduce p2m.h
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- add SPDX
- drop unneeded for now p2m types.
- return false in all functions implemented with BUG() inside.
- update the commit message
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/ppc/include/asm/p2m.h | 3 +-
xen/arch/riscv/include/asm/p2m.h | 102 +++
2 files changed, 103 insertions(+), 2 deletions(-)
create mode 100644 xen/arch/riscv/include/asm/p2m.h
diff --git a/xen/arch/ppc/include/asm/p2m.h b/xen/arch/ppc/include/asm/p2m.h
index 25ba054668..3bc05b7c05 100644
--- a/xen/arch/ppc/include/asm/p2m.h
+++ b/xen/arch/ppc/include/asm/p2m.h
@@ -50,8 +50,7 @@ static inline void memory_type_changed(struct domain *d)
static inline int guest_physmap_mark_populate_on_demand(struct domain *d,
unsigned long gfn,
unsigned int order)
{
-BUG_ON("unimplemented");
-return 1;
+return -EOPNOTSUPP;
}
static inline int guest_physmap_add_entry(struct domain *d,
diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h
new file mode 100644
index 00..d270ef6635
--- /dev/null
+++ b/xen/arch/riscv/include/asm/p2m.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_RISCV_P2M_H__
+#define __ASM_RISCV_P2M_H__
+
+#include
+
+#define paddr_bits PADDR_BITS
+
+/*
+ * List of possible type for each page in the p2m entry.
+ * The number of available bit per page in the pte for this purpose is 4 bits.
+ * So it's possible to only have 16 fields. If we run out of value in the
+ * future, it's possible to use higher value for pseudo-type and don't store
+ * them in the p2m entry.
+ */
+typedef enum {
+p2m_invalid = 0,/* Nothing mapped here */
+p2m_ram_rw, /* Normal read/write guest RAM */
+} p2m_type_t;
+
+#include
+
+static inline int get_page_and_type(struct page_info *page,
+struct domain *domain,
+unsigned long type)
+{
+BUG();
+return -EINVAL;
+}
+
+/* Look up a GFN and take a reference count on the backing page. */
+typedef unsigned int p2m_query_t;
+#define P2M_ALLOC(1u<<0) /* Populate PoD and paged-out entries */
+#define P2M_UNSHARE (1u<<1) /* Break CoW sharing */
+
+static inline struct page_info *get_page_from_gfn(
+struct domain *d, unsigned long gfn, p2m_type_t *t, p2m_query_t q)
+{
+BUG();
+return NULL;
+}
+
+static inline void memory_type_changed(struct domain *d)
+{
+BUG();
+}
+
+
+static inline int guest_physmap_mark_populate_on_demand(struct domain *d,
unsigned long gfn,
+unsigned int order)
+{
+return -EOPNOTSUPP;
+}
+
+static inline int guest_physmap_add_entry(struct domain *d,
+gfn_t gfn,
+mfn_t mfn,
+unsigned long page_order,
+p2m_type_t t)
+{
+BUG();
+return -EINVAL;
+}
+
+/* Untyped version for RAM only, for compatibility */
+static inline int __must_check
+guest_physmap_add_page(struct domain *d, gfn_t gfn, mfn_t mfn,
+ unsigned int page_order)
+{
+return guest_physmap_add_entry(d, gfn, mfn, page_order, p2m_ram_rw);
+}
+
+static inline mfn_t gfn_to_mfn(struct domain *d, gfn_t gfn)
+{
+BUG();
+return _mfn(0);
+}
+
+static inline bool arch_acquire_resource_check(struct domain *d)
+{
+/*
+ * The reference counting of foreign entries in set_foreign_p2m_entry()
+ * is supported on RISCV.
+ */
+return true;
+}
+
+static inline void p2m_altp2m_check(struct vcpu *v, uint16_t idx)
+{
+/* Not supported on RISCV. */
+}
+
+#endif /* __ASM_RISCV_P2M_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 31/34] xen/riscv: add minimal stuff to mm.h to build full Xen
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- update the commit message
- introduce DIRECTMAP_VIRT_START.
- drop changes related pfn_to_paddr() and paddr_to_pfn as they were remvoe in
[PATCH v2 32/39] xen/riscv: add minimal stuff to asm/page.h to build full Xen
- code style fixes.
- drop get_page_nr and put_page_nr as they don't need for time being
- drop CONFIG_STATIC_MEMORY related things
- code style fixes
---
Changes in V2:
- define stub for arch_get_dma_bitsize(void)
---
xen/arch/riscv/include/asm/config.h | 2 +
xen/arch/riscv/include/asm/mm.h | 248
2 files changed, 250 insertions(+)
diff --git a/xen/arch/riscv/include/asm/config.h
b/xen/arch/riscv/include/asm/config.h
index fb9fc9daaa..400309f4ef 100644
--- a/xen/arch/riscv/include/asm/config.h
+++ b/xen/arch/riscv/include/asm/config.h
@@ -67,6 +67,8 @@
#define XEN_VIRT_START 0xC000 /* (_AC(-1, UL) + 1 - GB(1)) */
+#define DIRECTMAP_VIRT_STARTSLOTN(200)
+
#define FRAMETABLE_VIRT_START SLOTN(196)
#define FRAMETABLE_SIZE GB(3)
#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table))
diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h
index 57026e134d..14fce72fde 100644
--- a/xen/arch/riscv/include/asm/mm.h
+++ b/xen/arch/riscv/include/asm/mm.h
@@ -3,8 +3,251 @@
#ifndef _ASM_RISCV_MM_H
#define _ASM_RISCV_MM_H
+#include
+#include
+#include
+
+#include
#include
+#define paddr_to_pdx(pa)mfn_to_pdx(maddr_to_mfn(pa))
+#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn))
+#define gaddr_to_gfn(ga)_gfn(paddr_to_pfn(ga))
+#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn))
+#define maddr_to_mfn(ma)_mfn(paddr_to_pfn(ma))
+#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)va))
+#define vmap_to_page(va)mfn_to_page(vmap_to_mfn(va))
+#define paddr_to_pdx(pa)mfn_to_pdx(maddr_to_mfn(pa))
+#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn))
+#define gaddr_to_gfn(ga)_gfn(paddr_to_pfn(ga))
+#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn))
+#define maddr_to_mfn(ma)_mfn(paddr_to_pfn(ma))
+#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)va))
+#define vmap_to_page(va)mfn_to_page(vmap_to_mfn(va))
+
+#define virt_to_maddr(va) ((paddr_t)((vaddr_t)(va) & PADDR_MASK))
+#define maddr_to_virt(pa) ((void *)((paddr_t)(pa) | DIRECTMAP_VIRT_START))
+
+/* Convert between Xen-heap virtual addresses and machine frame numbers. */
+#define __virt_to_mfn(va) (virt_to_maddr(va) >> PAGE_SHIFT)
+#define __mfn_to_virt(mfn) maddr_to_virt((paddr_t)(mfn) << PAGE_SHIFT)
+
+/* Convert between Xen-heap virtual addresses and page-info structures. */
+static inline struct page_info *virt_to_page(const void *v)
+{
+BUG();
+return NULL;
+}
+
+/*
+ * We define non-underscored wrappers for above conversion functions.
+ * These are overriden in various source files while underscored version
+ * remain intact.
+ */
+#define virt_to_mfn(va) __virt_to_mfn(va)
+#define mfn_to_virt(mfn)__mfn_to_virt(mfn)
+
+struct page_info
+{
+/* Each frame can be threaded onto a doubly-linked list. */
+struct page_list_entry list;
+
+/* Reference count and various PGC_xxx flags and fields. */
+unsigned long count_info;
+
+/* Context-dependent fields follow... */
+union {
+/* Page is in use: ((count_info & PGC_count_mask) != 0). */
+struct {
+/* Type reference count and various PGT_xxx flags and fields. */
+unsigned long type_info;
+} inuse;
+/* Page is on a free list: ((count_info & PGC_count_mask) == 0). */
+union {
+struct {
+/*
+ * Index of the first *possibly* unscrubbed page in the buddy.
+ * One more bit than maximum possible order to accommodate
+ * INVALID_DIRTY_IDX.
+ */
+#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1)
+unsigned long first_dirty:MAX_ORDER + 1;
+
+/* Do TLBs need flushing for safety before next page use? */
+bool need_tlbflush:1;
+
+#define BUDDY_NOT_SCRUBBING0
+#define BUDDY_SCRUBBING1
+#define BUDDY_SCRUB_ABORT 2
+unsigned long scrub_state:2;
+};
+
+unsigned long val;
+} free;
+
+} u;
+
+union {
+/* Page is in use, but not as a shadow. */
+struct {
+/* Owner of this page (zero if page is anonymous). */
+struct domain *domain;
+} inuse;
+
+/* Page is on a free list. */
+struct {
+/* Order-size of the free chunk this page is the head of. */
+unsigned int order;
+} free;
+
+} v;
+
+union {
+/*
+ * Timestamp from 'TLB clock', used to avoid extra safety flushes.
+ * Only valid for: a) free pages, and b) pages with zero type count
+
[PATCH v3 22/34] xen/riscv: introduce regs.h
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- update the commit message
- add Acked-by: Jan Beulich
- remove "include " and use a forward declaration instead.
---
Changes in V2:
- change xen/lib.h to xen/bug.h
- remove unnecessary empty line
---
xen/arch/riscv/include/asm/regs.h | 29 +
1 file changed, 29 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/regs.h
diff --git a/xen/arch/riscv/include/asm/regs.h
b/xen/arch/riscv/include/asm/regs.h
new file mode 100644
index 00..86bebc5810
--- /dev/null
+++ b/xen/arch/riscv/include/asm/regs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ARM_RISCV_REGS_H__
+#define __ARM_RISCV_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+#include
+
+#define hyp_mode(r) (0)
+
+struct cpu_user_regs;
+
+static inline bool guest_mode(const struct cpu_user_regs *r)
+{
+BUG();
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARM_RISCV_REGS_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 34/34] xen/README: add compiler and binutils versions for RISC-V64
Signed-off-by: Oleksii Kurochko --- Changes in V3: - new patch --- README | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README b/README index c8a108449e..1015a285c0 100644 --- a/README +++ b/README @@ -48,6 +48,9 @@ provided by your OS distributor: - For ARM 64-bit: - GCC 5.1 or later - GNU Binutils 2.24 or later + - For RISC-V 64-bit: +- GCC 13.2.1 or later +- GNU Binutils 2.40 or later * POSIX compatible awk * Development install of zlib (e.g., zlib-dev) * Development install of Python 2.7 or later (e.g., python-dev) -- 2.43.0
[PATCH v3 30/34] xen/riscv: add minimal stuff to processor.h to build full Xen
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- Update the commit message
- rename get_processor_id to smp_processor_id
- code style fixes
- update the cpu_relax instruction: use pause instruction instead of div %0,
%0, zero
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/processor.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/xen/arch/riscv/include/asm/processor.h
b/xen/arch/riscv/include/asm/processor.h
index 6db681d805..a3bff6c9c3 100644
--- a/xen/arch/riscv/include/asm/processor.h
+++ b/xen/arch/riscv/include/asm/processor.h
@@ -12,6 +12,9 @@
#ifndef __ASSEMBLY__
+/* TODO: need to be implemeted */
+#define smp_processor_id() 0
+
/* On stack VCPU state */
struct cpu_user_regs
{
@@ -53,6 +56,18 @@ struct cpu_user_regs
unsigned long pregs;
};
+/* TODO: need to implement */
+#define cpu_to_core(cpu) (0)
+#define cpu_to_socket(cpu) (0)
+
+static inline void cpu_relax(void)
+{
+/* Encoding of the pause instruction */
+__asm__ __volatile__ ( ".insn 0x10F" );
+
+barrier();
+}
+
static inline void wfi(void)
{
__asm__ __volatile__ ("wfi");
--
2.43.0
[PATCH v3 27/34] xen/riscv: define an address of frame table
Also, the patch adds some helpful macros that assist in avoiding the redefinition of memory layout for each MMU mode. Signed-off-by: Oleksii Kurochko --- Changes in V3: - drop OFFSET_BITS, and use PAGE_SHIFT instead. - code style fixes. - add comment how macros are useful. - move all memory related layout definitions close to comment with memory layout description. - make memory layout description generic for any MMU mode. --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/config.h | 85 +++-- 1 file changed, 55 insertions(+), 30 deletions(-) diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index f0544c6a20..fb9fc9daaa 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -6,6 +6,14 @@ #include #include +#ifdef CONFIG_RISCV_64 +#define CONFIG_PAGING_LEVELS 3 +#define RV_STAGE1_MODE SATP_MODE_SV39 +#else +#define CONFIG_PAGING_LEVELS 2 +#define RV_STAGE1_MODE SATP_MODE_SV32 +#endif + /* * RISC-V64 Layout: * @@ -22,25 +30,56 @@ * * It means that: * top VA bits are simply ignored for the purpose of translating to PA. +#endif * - * - *Start addr| End addr| Size | Slot |area description - * - * C080 | |1016 MB | L2 511 | Unused - * C060 | C080 | 2 MB | L2 511 | Fixmap - * C020 | C060 | 4 MB | L2 511 | FDT - * C000 | C020 | 2 MB | L2 511 | Xen - * ... | 1 GB | L2 510 | Unused - * 0032 | 007F8000 | 309 GB | L2 200-509 | Direct map - * ... | 1 GB | L2 199 | Unused - * 0031 | 0031C000 | 3 GB | L2 196-198 | Frametable - * ... | 1 GB | L2 195 | Unused - * 00308000 | 0030C000 | 1 GB | L2 194 | VMAP - * ... | 194 GB | L2 0 - 193 | Unused - * + * SATP_MODE_SV32 | SATP_MODE_SV39 | SATP_MODE_SV48 | SATP_MODE_SV57 + * ==|==|==|= + * BA0 | FFE0 | C000 | FF80 | + * BA1 | 1900 | 0032 | 6400 | 00C8 + * BA2 | 1880 | 0031 | 6200 | 00C4 + * BA3 | 1840 | 00308000 | 6100 | 00C2 * -#endif + * === + * Start addr | End addr | Size | Root PT slot | Area description + * === + * BA0 + 0x80 | |1016 MB | 511 | Unused + * BA0 + 0x40 | BA0 + 0x80 | 2 MB | 511 | Fixmap + * BA0 + 0x20 | BA0 + 0x40 | 4 MB | 511 | FDT + * BA0| BA0 + 0x20 | 2 MB | 511 | Xen + * ... | 1 GB | 510 | Unused + * BA1 + 0x00 | BA1 + 0x4D8000 | 309 GB | 200-509| Direct map + * ... | 1 GB | 199 | Unused + * BA2 + 0x00 | BA2 + 0xC000 | 3 GB | 196-198| Frametable + * ... | 1 GB | 195 | Unused + * BA3 + 0x00 | BA3 + 0x4000 | 1 GB | 194 | VMAP + * ... | 194 GB | 0 - 193| Unused + * === */ +#define VPN_BITS(9) + +#define HYP_PT_ROOT_LEVEL (CONFIG_PAGING_LEVELS - 1) + +#ifdef CONFIG_RISCV_64 + +#define SLOTN_ENTRY_BITS(HYP_PT_ROOT_LEVEL * VPN_BITS + PAGE_SHIFT) +#define SLOTN(slot) (_AT(vaddr_t, slot) << SLOTN_ENTRY_BITS) +#define SLOTN_ENTRY_SIZESLOTN(1) + +#define XEN_VIRT_START 0xC000 /* (_AC(-1, UL) + 1 - GB(1)) */ + +#define FRAMETABLE_VIRT_START SLOTN(196) +#define FRAMETABLE_SIZE GB(3) +#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) +#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + FRAMETABLE_SIZE - 1) + +#define VMAP_VIRT_START SLOTN(194) +#define VMAP_VIRT_SIZE GB(1) + +#else +#error "RV32 isn't supported" +#endif + +#define HYPERVISOR_VIRT_START XEN_VIRT_START #if defined(CONFIG_RISCV_64) # define LONG_BYTEORDER 3 @@ -77,24 +116,10 @@ name: #endif -#ifdef CONFIG_RISCV_64 -#define XEN_VIRT_START 0xC000 /* (_AC(-1, UL) + 1 - GB(1)) */
[PATCH v3 33/34] xen/riscv: enable full Xen build
Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in V3: - Reviewed-by: Jan Beulich - unrealted change dropped in tiny64_defconfig --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/Makefile | 16 +++- xen/arch/riscv/arch.mk | 4 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 5523191bb7..c10d43c7e5 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -11,10 +11,24 @@ $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ $(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds - $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) -o $@ + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(objtree)/common/symbols-dummy.o -o $(dot-target).0 + $(NM) -pa --format=sysv $(dot-target).0 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).0.S + $(MAKE) $(build)=$(@D) $(dot-target).0.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(dot-target).0.o -o $(dot-target).1 + $(NM) -pa --format=sysv $(dot-target).1 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).1.S + $(MAKE) $(build)=$(@D) $(dot-target).1.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) \ + $(dot-target).1.o -o $@ $(NM) -pa --format=sysv $@ \ | $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \ > $@.map + rm -f $(@D)/.$(@F).[0-9]* $(obj)/xen.lds: $(src)/xen.lds.S FORCE $(call if_changed_dep,cpp_lds_S) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8403f96b6f..12b1673fae 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -13,7 +13,3 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c # -mcmodel=medlow would force Xen into the lower half. CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany - -# TODO: Drop override when more of the build is working -override ALL_OBJS-y = arch/$(SRCARCH)/built_in.o -override ALL_LIBS-y = -- 2.43.0
[PATCH v3 18/34] xen/riscv: introduce domain.h
Signed-off-by: Oleksii Kurochko
Acked-by: Jan Beulich
---
Changes in V3:
- add SPDX
- add Acked-by: Jan Beulich
- update the commit message
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/domain.h | 53 +
1 file changed, 53 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/domain.h
diff --git a/xen/arch/riscv/include/asm/domain.h
b/xen/arch/riscv/include/asm/domain.h
new file mode 100644
index 00..0f5dc2be40
--- /dev/null
+++ b/xen/arch/riscv/include/asm/domain.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_RISCV_DOMAIN_H__
+#define __ASM_RISCV_DOMAIN_H__
+
+#include
+#include
+
+struct hvm_domain
+{
+uint64_t params[HVM_NR_PARAMS];
+};
+
+#define is_domain_direct_mapped(d) ((void)(d), 0)
+
+struct arch_vcpu_io {
+};
+
+struct arch_vcpu {
+};
+
+struct arch_domain {
+struct hvm_domain hvm;
+};
+
+#include
+
+static inline struct vcpu_guest_context *alloc_vcpu_guest_context(void)
+{
+return xmalloc(struct vcpu_guest_context);
+}
+
+static inline void free_vcpu_guest_context(struct vcpu_guest_context *vgc)
+{
+xfree(vgc);
+}
+
+struct guest_memory_policy {};
+static inline void update_guest_memory_policy(struct vcpu *v,
+ struct guest_memory_policy *gmp)
+{}
+
+static inline void arch_vcpu_block(struct vcpu *v) {}
+
+#endif /* __ASM_RISCV_DOMAIN_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 25/34] xen/riscv: introduce monitor.h
Signed-off-by: Oleksii Kurochko
---
Taking into account conversion in [PATCH v6 0/9] Introduce generic headers
(https://lore.kernel.org/xen-devel/cover.1703072575.git.oleksii.kuroc...@gmail.com/)
this patch can be changed
---
Changes in V3:
- new patch.
---
xen/arch/riscv/include/asm/monitor.h | 26 ++
1 file changed, 26 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/monitor.h
diff --git a/xen/arch/riscv/include/asm/monitor.h
b/xen/arch/riscv/include/asm/monitor.h
new file mode 100644
index 00..f4fe2c0690
--- /dev/null
+++ b/xen/arch/riscv/include/asm/monitor.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_RISCV_MONITOR_H__
+#define __ASM_RISCV_MONITOR_H__
+
+#include
+
+#include
+
+struct domain;
+
+static inline uint32_t arch_monitor_get_capabilities(struct domain *d)
+{
+BUG_ON("unimplemented");
+return 0;
+}
+
+#endif /* __ASM_RISCV_MONITOR_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 23/34] xen/riscv: introduce time.h
Signed-off-by: Oleksii Kurochko
Acked-by: Jan Beulich
---
Changes in V3:
- Acked-by: Jan Beulich
- add SPDX
- Add new line
---
Changes in V2:
- change xen/lib.h to xen/bug.h
- remove inclusion of as it's not needed.
---
xen/arch/riscv/include/asm/time.h | 29 +
1 file changed, 29 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/time.h
diff --git a/xen/arch/riscv/include/asm/time.h
b/xen/arch/riscv/include/asm/time.h
new file mode 100644
index 00..1f22af3bce
--- /dev/null
+++ b/xen/arch/riscv/include/asm/time.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_RISCV_TIME_H__
+#define __ASM_RISCV_TIME_H__
+
+#include
+#include
+
+struct vcpu;
+
+/* TODO: implement */
+static inline void force_update_vcpu_system_time(struct vcpu *v) { BUG(); }
+
+typedef unsigned long cycles_t;
+
+static inline cycles_t get_cycles(void)
+{
+ return csr_read(CSR_TIME);
+}
+
+#endif /* __ASM_RISCV_TIME_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 26/34] xen/riscv: add definition of __read_mostly
The definition of __read_mostly should be removed in:
https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b3...@suse.com/
The patch introduces it in arch-specific header to not
block enabling of full Xen build for RISC-V.
Signed-off-by: Oleksii Kurochko
---
- [PATCH] move __read_mostly to xen/cache.h [2]
Right now, the patch series doesn't have a direct dependency on [2] and it
provides __read_mostly in the patch:
[PATCH v3 26/34] xen/riscv: add definition of __read_mostly
However, it will be dropped as soon as [2] is merged or at least when the
final version of the patch [2] is provided.
[2]
https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b3...@suse.com/
---
xen/arch/riscv/include/asm/cache.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/xen/arch/riscv/include/asm/cache.h
b/xen/arch/riscv/include/asm/cache.h
index 69573eb051..94bd94db53 100644
--- a/xen/arch/riscv/include/asm/cache.h
+++ b/xen/arch/riscv/include/asm/cache.h
@@ -3,4 +3,6 @@
#ifndef _ASM_RISCV_CACHE_H
#define _ASM_RISCV_CACHE_H
+#define __read_mostly __section(".data.read_mostly")
+
#endif /* _ASM_RISCV_CACHE_H */
--
2.43.0
[PATCH v3 09/34] xen/riscv: introduce system.h
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- Add SPDX
- fix code style issue
- change prototype of local_irq_is_enabled to return bool.
update the return code.
- update the code style
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/system.h | 90 +
1 file changed, 90 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/system.h
diff --git a/xen/arch/riscv/include/asm/system.h
b/xen/arch/riscv/include/asm/system.h
new file mode 100644
index 00..08c12158fc
--- /dev/null
+++ b/xen/arch/riscv/include/asm/system.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _ASM_RISCV_BARRIER_H
+#define _ASM_RISCV_BARRIER_H
+
+#include
+
+#include
+
+#ifndef __ASSEMBLY__
+
+#define RISCV_FENCE(p, s) \
+__asm__ __volatile__ ( "fence " #p "," #s : : : "memory" )
+
+/* These barriers need to enforce ordering on both devices or memory. */
+#define mb()RISCV_FENCE(iorw, iorw)
+#define rmb() RISCV_FENCE(ir, ir)
+#define wmb() RISCV_FENCE(ow, ow)
+
+/* These barriers do not need to enforce ordering on devices, just memory. */
+#define smp_mb()RISCV_FENCE(rw, rw)
+#define smp_rmb() RISCV_FENCE(r, r)
+#define smp_wmb() RISCV_FENCE(w, w)
+#define smp_mb__before_atomic() smp_mb()
+#define smp_mb__after_atomic() smp_mb()
+
+/*
+#define smp_store_release(p, v) \
+do {\
+compiletime_assert_atomic_type(*p); \
+RISCV_FENCE(rw, w); \
+WRITE_ONCE(*p, v); \
+} while (0)
+
+#define smp_load_acquire(p) \
+({ \
+typeof(*p) p1 = READ_ONCE(*p); \
+compiletime_assert_atomic_type(*p); \
+RISCV_FENCE(r,rw); \
+p1; \
+})
+*/
+
+static inline unsigned long local_save_flags(void)
+{
+return csr_read(sstatus);
+}
+
+static inline void local_irq_enable(void)
+{
+csr_set(sstatus, SSTATUS_SIE);
+}
+
+static inline void local_irq_disable(void)
+{
+csr_clear(sstatus, SSTATUS_SIE);
+}
+
+#define local_irq_save(x) \
+({ \
+x = csr_read_clear(CSR_SSTATUS, SSTATUS_SIE); \
+local_irq_disable();\
+})
+
+static inline void local_irq_restore(unsigned long flags)
+{
+ csr_set(CSR_SSTATUS, flags & SSTATUS_SIE);
+}
+
+static inline bool local_irq_is_enabled(void)
+{
+unsigned long flags = local_save_flags();
+
+return (flags & SSTATUS_SIE) != 0;
+}
+
+#define arch_fetch_and_add(x, v) __sync_fetch_and_add(x, v)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_BARRIER_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 24/34] xen/riscv: introduce event.h
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- add SPDX
- add BUG() inside stubs.
- update the commit message
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/event.h | 40 ++
1 file changed, 40 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/event.h
diff --git a/xen/arch/riscv/include/asm/event.h
b/xen/arch/riscv/include/asm/event.h
new file mode 100644
index 00..65cc5ae168
--- /dev/null
+++ b/xen/arch/riscv/include/asm/event.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_RISCV_EVENT_H__
+#define __ASM_RISCV_EVENT_H__
+
+#include
+
+void vcpu_mark_events_pending(struct vcpu *v);
+
+static inline int vcpu_event_delivery_is_enabled(struct vcpu *v)
+{
+BUG();
+return 0;
+}
+
+static inline int local_events_need_delivery(void)
+{
+BUG();
+return 0;
+}
+
+static inline void local_event_delivery_enable(void)
+{
+BUG();
+}
+
+/* No arch specific virq definition now. Default to global. */
+static inline bool arch_virq_is_global(unsigned int virq)
+{
+return true;
+}
+
+#endif
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 00/34] Enable build of full Xen for RISC-V
This patch series performs all of the additions necessary to drop the
build overrides for RISCV and enable the full Xen build. Except in cases
where compatibile implementations already exist (e.g. atomic.h and
bitops.h), the newly added definitions are simple.
The patch series is based on the following patch series:
- [PATCH v6 0/9] Introduce generic headers [1]
- [PATCH] move __read_mostly to xen/cache.h [2]
Right now, the patch series doesn't have a direct dependency on [2] and it
provides __read_mostly in the patch:
[PATCH v3 26/34] xen/riscv: add definition of __read_mostly
However, it will be dropped as soon as [2] is merged or at least when the
final version of the patch [2] is provided.
[1]
https://lore.kernel.org/xen-devel/cover.1703072575.git.oleksii.kuroc...@gmail.com/
[2]
https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b3...@suse.com/
---
Changes in V3:
- Update the cover letter message
- The following patches were dropped as they were merged to staging:
[PATCH v2 03/39] xen/riscv:introduce asm/byteorder.h
[PATCH v2 04/39] xen/riscv: add public arch-riscv.h
[PATCH v2 05/39] xen/riscv: introduce spinlock.h
[PATCH v2 20/39] xen/riscv: define bug frame tables in xen.lds.S
[PATCH v2 34/39] xen: add RISCV support for pmu.h
[PATCH v2 35/39] xen: add necessary headers to common to build full Xen for
RISC-V
- Instead of the following patches were introduced new:
[PATCH v2 10/39] xen/riscv: introduce asm/iommu.h
[PATCH v2 11/39] xen/riscv: introduce asm/nospec.h
- remove "asm/" for commit messages which start with "xen/riscv:"
- code style updates.
- add emulation of {cmp}xchg_* for 1 and 2 bytes types.
- code style fixes.
- add SPDX and footer for the newly added headers.
- introduce generic find-next-bit.c.
- some other mionor changes. ( details please find in a patch )
---
Changes in V2:
- Drop the following patches as they are the part of [2]:
[PATCH v1 06/57] xen/riscv: introduce paging.h
[PATCH v1 08/57] xen/riscv: introduce asm/device.h
[PATCH v1 10/57] xen/riscv: introduce asm/grant_table.h
[PATCH v1 12/57] xen/riscv: introduce asm/hypercall.h
[PATCH v1 13/57] xen/riscv: introduce asm/iocap.h
[PATCH v1 15/57] xen/riscv: introduce asm/mem_access.h
[PATCH v1 18/57] xen/riscv: introduce asm/random.h
[PATCH v1 21/57] xen/riscv: introduce asm/xenoprof.h
[PATCH v1 24/57] xen/riscv: introduce asm/percpu.h
[PATCH v1 29/57] xen/riscv: introduce asm/hardirq.h
[PATCH v1 33/57] xen/riscv: introduce asm/altp2m.h
[PATCH v1 38/57] xen/riscv: introduce asm/monitor.h
[PATCH v1 39/57] xen/riscv: introduce asm/numa.h
[PATCH v1 42/57] xen/riscv: introduce asm/softirq.h
- xen/lib.h in most of the cases were changed to xen/bug.h as
mostly functionilty of bug.h is used.
- align arch-riscv.h with Arm's version of it.
- change the Author of commit with introduction of asm/atomic.h.
- update some definition from spinlock.h.
- code style changes.
---
Bobby Eshleman (1):
xen/riscv: introduce atomic.h
Oleksii Kurochko (33):
xen/riscv: disable unnecessary configs
xen/riscv: use some asm-generic headers
xen: add support in public/hvm/save.h for PPC and RISC-V
xen/riscv: introduce cpufeature.h
xen/riscv: introduce guest_atomics.h
xen: avoid generation of empty asm/iommu.h
xen/asm-generic: introdure nospec.h
xen/riscv: introduce setup.h
xen/riscv: introduce system.h
xen/riscv: introduce bitops.h
xen/riscv: introduce flushtlb.h
xen/riscv: introduce smp.h
xen/riscv: introduce cmpxchg.h
xen/riscv: introduce io.h
xen/lib: introduce generic find next bit operations
xen/riscv: add compilation of generic find-next-bit.c
xen/riscv: introduce domain.h
xen/riscv: introduce guest_access.h
xen/riscv: introduce irq.h
xen/riscv: introduce p2m.h
xen/riscv: introduce regs.h
xen/riscv: introduce time.h
xen/riscv: introduce event.h
xen/riscv: introduce monitor.h
xen/riscv: add definition of __read_mostly
xen/riscv: define an address of frame table
xen/riscv: add required things to current.h
xen/riscv: add minimal stuff to page.h to build full Xen
xen/riscv: add minimal stuff to processor.h to build full Xen
xen/riscv: add minimal stuff to mm.h to build full Xen
xen/rirscv: add minimal amount of stubs to build full Xen
xen/riscv: enable full Xen build
xen/README: add compiler and binutils versions for RISC-V64
README| 3 +
.../gitlab-ci/riscv-fixed-randconfig.yaml | 27 +
xen/arch/arm/include/asm/Makefile | 1 +
xen/arch/ppc/include/asm/Makefile | 1 +
xen/arch/ppc/include/asm/nospec.h | 15 -
xen/arch/ppc/include/asm/p2m.h| 3 +-
xen/arch/riscv/Kconfig| 1 +
xen/arch/riscv/Makefile | 17 +-
xen/arch/riscv/arch.mk| 4 -
[PATCH v3 11/34] xen/riscv: introduce flushtlb.h
Signed-off-by: Oleksii Kurochko
Acked-by: Jan Beulich
---
Changes in V3:
- add SPDX & footer
- add Acked-by: Jan Beulich
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/flushtlb.h | 33 +++
1 file changed, 33 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/flushtlb.h
diff --git a/xen/arch/riscv/include/asm/flushtlb.h
b/xen/arch/riscv/include/asm/flushtlb.h
new file mode 100644
index 00..3bdcb08e3a
--- /dev/null
+++ b/xen/arch/riscv/include/asm/flushtlb.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_RISCV_FLUSHTLB_H__
+#define __ASM_RISCV_FLUSHTLB_H__
+
+#include
+
+/*
+ * Filter the given set of CPUs, removing those that definitely flushed their
+ * TLB since @page_timestamp.
+ */
+/* XXX lazy implementation just doesn't clear anything */
+static inline void tlbflush_filter(cpumask_t *mask, uint32_t page_timestamp) {}
+
+#define tlbflush_current_time() (0)
+
+static inline void page_set_tlbflush_timestamp(struct page_info *page)
+{
+BUG();
+}
+
+/* Flush specified CPUs' TLBs */
+void arch_flush_tlb_mask(const cpumask_t *mask);
+
+#endif /* __ASM_RISCV_FLUSHTLB_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 20/34] xen/riscv: introduce irq.h
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- add SPDX
- remove all that was wraped to HAS_DEVICETREE_... as for RISC-V it is going
to be
always selected.
- update the commit message
---
Changes in V2:
- add ifdef CONFIG_HAS_DEVICE_TREE for things that shouldn't be
in case !CONFIG_HAS_DEVICE_TREE
- use proper includes.
---
xen/arch/riscv/include/asm/irq.h | 37
1 file changed, 37 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/irq.h
diff --git a/xen/arch/riscv/include/asm/irq.h b/xen/arch/riscv/include/asm/irq.h
new file mode 100644
index 00..a4434fb8ae
--- /dev/null
+++ b/xen/arch/riscv/include/asm/irq.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_RISCV_IRQ_H__
+#define __ASM_RISCV_IRQ_H__
+
+#include
+
+/* TODO */
+#define nr_irqs 0U
+#define nr_static_irqs 0
+#define arch_hwdom_irqs(domid) 0U
+
+#define domain_pirq_to_irq(d, pirq) (pirq)
+
+#define arch_evtchn_bind_pirq(d, pirq) ((void)((d) + (pirq)))
+
+struct arch_pirq {
+};
+
+struct arch_irq_desc {
+unsigned int type;
+};
+
+static inline void arch_move_irqs(struct vcpu *v)
+{
+BUG();
+}
+
+#endif /* __ASM_RISCV_IRQ_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 05/34] xen/riscv: introduce guest_atomics.h
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- update the commit message
- drop TODO commit.
- add ASSERT_UNREACHABLE for stubs guest functions.
- Add SPDX & footer
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/guest_atomics.h | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/guest_atomics.h
diff --git a/xen/arch/riscv/include/asm/guest_atomics.h
b/xen/arch/riscv/include/asm/guest_atomics.h
new file mode 100644
index 00..98f7df7b6a
--- /dev/null
+++ b/xen/arch/riscv/include/asm/guest_atomics.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_RISCV_GUEST_ATOMICS_H
+#define __ASM_RISCV_GUEST_ATOMICS_H
+
+#define guest_testop(name) \
+static inline int guest_##name(struct domain *d, int nr, volatile void *p) \
+{ \
+(void) d; \
+(void) nr; \
+(void) p; \
+\
+ASSERT_UNREACHABLE(); \
+\
+return 0; \
+}
+
+#define guest_bitop(name) \
+static inline void guest_##name(struct domain *d, int nr, volatile void *p) \
+{ \
+(void) d; \
+(void) nr; \
+(void) p; \
+ASSERT_UNREACHABLE(); \
+}
+
+guest_bitop(set_bit)
+guest_bitop(clear_bit)
+guest_bitop(change_bit)
+
+#undef guest_bitop
+
+guest_testop(test_and_set_bit)
+guest_testop(test_and_clear_bit)
+guest_testop(test_and_change_bit)
+
+#undef guest_testop
+
+#define guest_test_bit(d, nr, p) ((void)(d), test_bit(nr, p))
+
+#endif /* __ASM_RISCV_GUEST_ATOMICS_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 03/34] xen: add support in public/hvm/save.h for PPC and RISC-V
Signed-off-by: Oleksii Kurochko --- Changes in V3: - update the commit message. - For PPC and RISC-V nothing to include in public/hvm/save.h, so just comment was added. --- Changes in V2: - remove copyright an the top of hvm/save.h as the header write now is a newly introduced empty header. --- xen/include/public/hvm/save.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/public/hvm/save.h b/xen/include/public/hvm/save.h index ff0048e5f8..31b5cd163b 100644 --- a/xen/include/public/hvm/save.h +++ b/xen/include/public/hvm/save.h @@ -89,8 +89,8 @@ DECLARE_HVM_SAVE_TYPE(END, 0, struct hvm_save_end); #include "../arch-x86/hvm/save.h" #elif defined(__arm__) || defined(__aarch64__) #include "../arch-arm/hvm/save.h" -#elif defined(__powerpc64__) -#include "../arch-ppc.h" +#elif defined(__powerpc64__) || defined(__riscv) +/* no specific header to include */ #else #error "unsupported architecture" #endif -- 2.43.0
[PATCH v3 06/34] xen: avoid generation of empty asm/iommu.h
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- new patch.
---
xen/include/xen/iommu.h | 4
1 file changed, 4 insertions(+)
diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h
index f53d045e2c..8adbf29d3b 100644
--- a/xen/include/xen/iommu.h
+++ b/xen/include/xen/iommu.h
@@ -337,7 +337,9 @@ extern int iommu_add_extra_reserved_device_memory(unsigned
long start,
extern int iommu_get_extra_reserved_device_memory(iommu_grdm_t *func,
void *ctxt);
+#ifdef CONFIG_HAS_PASSTHROUGH
#include
+#endif
#ifndef iommu_call
# define iommu_call(ops, fn, args...) ((ops)->fn(args))
@@ -345,7 +347,9 @@ extern int
iommu_get_extra_reserved_device_memory(iommu_grdm_t *func,
#endif
struct domain_iommu {
+#ifdef CONFIG_HAS_PASSTHROUGH
struct arch_iommu arch;
+#endif
/* iommu_ops */
const struct iommu_ops *platform_ops;
--
2.43.0
[PATCH v3 10/34] xen/riscv: introduce bitops.h
Taken from Linux-6.4.0-rc1
Xen's bitops.h consists of several Linux's headers:
* linux/arch/include/asm/bitops.h:
* The following function were removed as they aren't used in Xen:
* test_and_change_bit
* test_and_set_bit_lock
* clear_bit_unlock
* __clear_bit_unlock
* The following functions were renamed in the way how they are
used by common code:
* __test_and_set_bit
* __test_and_clear_bit
* The declaration and implementation of the following functios
were updated to make Xen build happy:
* clear_bit
* set_bit
* __test_and_clear_bit
* __test_and_set_bit
* linux/include/asm-generic/bitops/find.h ( only few function
declaration were taken, as implementation will be provided by
Xen ).
* linux/arch/include/linux/bits.h ( taken only definitions for BIT_MASK,
BIT_WORD, BITS_PER_BYTE )
Additionaly, the following bit ops are introduced:
* __ffs
* ffsl
* fls
* flsl
* ffs
* ffz
* find_first_bit_set
* hweight64
* test_bit
Some of the introduced bit operations are included in asm-generic,
as they exhibit similarity across multiple architectures.
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- update the commit message
- Introduce the following asm-generic bitops headers:
create mode 100644 xen/arch/riscv/include/asm/bitops.h
create mode 100644 xen/include/asm-generic/bitops/bitops-bits.h
create mode 100644 xen/include/asm-generic/bitops/ffs.h
create mode 100644 xen/include/asm-generic/bitops/ffz.h
create mode 100644 xen/include/asm-generic/bitops/find-first-bit-set.h
create mode 100644 xen/include/asm-generic/bitops/fls.h
create mode 100644 xen/include/asm-generic/bitops/flsl.h
create mode 100644 xen/include/asm-generic/bitops/hweight.h
create mode 100644 xen/include/asm-generic/bitops/test-bit.h
- switch some bitops functions to asm-generic's versions.
- re-sync some macros with Linux kernel version mentioned in the commit
message.
- Xen code style fixes.
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/bitops.h | 267 ++
xen/include/asm-generic/bitops/bitops-bits.h | 10 +
xen/include/asm-generic/bitops/ffs.h | 9 +
xen/include/asm-generic/bitops/ffz.h | 13 +
.../asm-generic/bitops/find-first-bit-set.h | 17 ++
xen/include/asm-generic/bitops/fls.h | 18 ++
xen/include/asm-generic/bitops/flsl.h | 10 +
xen/include/asm-generic/bitops/hweight.h | 13 +
xen/include/asm-generic/bitops/test-bit.h | 16 ++
9 files changed, 373 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/bitops.h
create mode 100644 xen/include/asm-generic/bitops/bitops-bits.h
create mode 100644 xen/include/asm-generic/bitops/ffs.h
create mode 100644 xen/include/asm-generic/bitops/ffz.h
create mode 100644 xen/include/asm-generic/bitops/find-first-bit-set.h
create mode 100644 xen/include/asm-generic/bitops/fls.h
create mode 100644 xen/include/asm-generic/bitops/flsl.h
create mode 100644 xen/include/asm-generic/bitops/hweight.h
create mode 100644 xen/include/asm-generic/bitops/test-bit.h
diff --git a/xen/arch/riscv/include/asm/bitops.h
b/xen/arch/riscv/include/asm/bitops.h
new file mode 100644
index 00..d210f529c8
--- /dev/null
+++ b/xen/arch/riscv/include/asm/bitops.h
@@ -0,0 +1,267 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2012 Regents of the University of California */
+
+#ifndef _ASM_RISCV_BITOPS_H
+#define _ASM_RISCV_BITOPS_H
+
+#include
+
+#include
+
+/* Based on linux/arch/include/linux/bits.h */
+
+#define BIT_MASK(nr)(1UL << ((nr) % BITS_PER_LONG))
+#define BIT_WORD(nr)((nr) / BITS_PER_LONG)
+
+#define __set_bit(n,p) set_bit(n,p)
+#define __clear_bit(n,p)clear_bit(n,p)
+
+/* Based on linux/arch/include/asm/bitops.h */
+
+#if ( BITS_PER_LONG == 64 )
+#define __AMO(op) "amo" #op ".d"
+#elif ( BITS_PER_LONG == 32 )
+#define __AMO(op) "amo" #op ".w"
+#else
+#error "Unexpected BITS_PER_LONG"
+#endif
+
+#define __test_and_op_bit_ord(op, mod, nr, addr, ord) \
+({ \
+unsigned long __res, __mask; \
+__mask = BIT_MASK(nr); \
+__asm__ __volatile__ ( \
+__AMO(op) #ord " %0, %2, %1" \
+: "=r" (__res), "+A" (addr[BIT_WORD(nr)]) \
+: "r" (mod(__mask))\
+: "memory"); \
+((__res & __mask) != 0); \
+})
+
+#define __op_bit_ord(op, mod, nr, addr, ord) \
+__asm__ __volatile__ ( \
+__AMO(op) #ord " zero, %1, %0" \
+: "+A" (addr[BIT_WORD(nr)])\
+
[PATCH v3 08/34] xen/riscv: introduce setup.h
Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V3: - add SPDX - add Acked-by: Jan Beulich --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/setup.h | 17 + 1 file changed, 17 insertions(+) create mode 100644 xen/arch/riscv/include/asm/setup.h diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/asm/setup.h new file mode 100644 index 00..7613a5dbd0 --- /dev/null +++ b/xen/arch/riscv/include/asm/setup.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_RISCV_SETUP_H__ +#define __ASM_RISCV_SETUP_H__ + +#define max_init_domid (0) + +#endif /* __ASM_RISCV_SETUP_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.43.0
[PATCH v3 12/34] xen/riscv: introduce smp.h
Signed-off-by: Oleksii Kurochko --- Changes in V3: - drop cpu_is_offline() as it was moved to xen/smp.h. - add SPDX. - drop unnessary #ifdef. - fix "No new line" - update the commit message --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/smp.h | 28 1 file changed, 28 insertions(+) create mode 100644 xen/arch/riscv/include/asm/smp.h diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/smp.h new file mode 100644 index 00..336db5906e --- /dev/null +++ b/xen/arch/riscv/include/asm/smp.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_SMP_H +#define __ASM_RISCV_SMP_H + +#include +#include + +DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); +DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); + +#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu)) + +/* + * Do we, for platform reasons, need to actually keep CPUs online when we + * would otherwise prefer them to be off? + */ +#define park_offline_cpus false + +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.43.0
[PATCH v3 01/34] xen/riscv: disable unnecessary configs
This patch disables unnecessary configs for two cases: 1. By utilizing EXTRA_FIXED_RANDCONFIG and risc-fixed-randconfig.yaml file for randconfig builds (GitLab CI jobs). 2. By using tiny64_defconfig for non-randconfig builds. Signed-off-by: Oleksii Kurochko --- Changes in V3: - Remove EXTRA_FIXED_RANDCONFIG for non-randconfig jobs. For non-randconfig jobs, it is sufficient to disable configs by using the defconfig. - Remove double blank lines in build.yaml file before archlinux-current-gcc-riscv64-debug --- Changes in V2: - update the commit message. - remove xen/arch/riscv/Kconfig changes. --- .../gitlab-ci/riscv-fixed-randconfig.yaml | 27 +++ xen/arch/riscv/configs/tiny64_defconfig | 17 2 files changed, 44 insertions(+) diff --git a/automation/gitlab-ci/riscv-fixed-randconfig.yaml b/automation/gitlab-ci/riscv-fixed-randconfig.yaml index f1282b40c9..344f39c2d8 100644 --- a/automation/gitlab-ci/riscv-fixed-randconfig.yaml +++ b/automation/gitlab-ci/riscv-fixed-randconfig.yaml @@ -5,3 +5,30 @@ CONFIG_EXPERT=y CONFIG_GRANT_TABLE=n CONFIG_MEM_ACCESS=n + CONFIG_COVERAGE=n + CONFIG_SCHED_CREDIT=n + CONFIG_SCHED_CREDIT2=n + CONFIG_SCHED_RTDS=n + CONFIG_SCHED_NULL=n + CONFIG_SCHED_ARINC653=n + CONFIG_TRACEBUFFER=n + CONFIG_HYPFS=n + CONFIG_SPECULATIVE_HARDEN_ARRAY=n + CONFIG_ARGO=n + CONFIG_HYPFS_CONFIG=n + CONFIG_CORE_PARKING=n + CONFIG_DEBUG_TRACE=n + CONFIG_IOREQ_SERVER=n + CONFIG_CRASH_DEBUG=n + CONFIG_KEXEC=n + CONFIG_LIVEPATCH=n + CONFIG_NUMA=n + CONFIG_PERF_COUNTERS=n + CONFIG_HAS_PMAP=n + CONFIG_TRACEBUFFER=n + CONFIG_XENOPROF=n + CONFIG_COMPAT=n + CONFIG_COVERAGE=n + CONFIG_UBSAN=n + CONFIG_NEEDS_LIBELF=n + CONFIG_XSM=n diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig index 09defe236b..35915255e6 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -7,6 +7,23 @@ # CONFIG_GRANT_TABLE is not set # CONFIG_SPECULATIVE_HARDEN_ARRAY is not set # CONFIG_MEM_ACCESS is not set +# CONFIG_ARGO is not set +# CONFIG_HYPFS_CONFIG is not set +# CONFIG_CORE_PARKING is not set +# CONFIG_DEBUG_TRACE is not set +# CONFIG_IOREQ_SERVER is not set +# CONFIG_CRASH_DEBUG is not setz +# CONFIG_KEXEC is not set +# CONFIG_LIVEPATCH is not set +# CONFIG_NUMA is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_HAS_PMAP is not set +# CONFIG_TRACEBUFFER is not set +# CONFIG_XENOPROF is not set +# CONFIG_COMPAT is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NEEDS_LIBELF is not set CONFIG_RISCV_64=y CONFIG_DEBUG=y -- 2.43.0
[PATCH v3 07/34] xen/asm-generic: introdure nospec.h
The header is similar between Arm, PPC, and RISC-V,
so it has been moved to asm-generic.
Signed-off-by: Oleksii Kurochko
---
Changes in V3:
- new patch.
---
xen/arch/arm/include/asm/Makefile | 1 +
xen/arch/ppc/include/asm/Makefile | 1 +
xen/arch/ppc/include/asm/nospec.h | 15 ---
xen/arch/riscv/include/asm/Makefile | 1 +
.../include/asm => include/asm-generic}/nospec.h | 10 +-
5 files changed, 8 insertions(+), 20 deletions(-)
delete mode 100644 xen/arch/ppc/include/asm/nospec.h
rename xen/{arch/arm/include/asm => include/asm-generic}/nospec.h (54%)
diff --git a/xen/arch/arm/include/asm/Makefile
b/xen/arch/arm/include/asm/Makefile
index c3f4291ee2..dfb4e9e45c 100644
--- a/xen/arch/arm/include/asm/Makefile
+++ b/xen/arch/arm/include/asm/Makefile
@@ -3,6 +3,7 @@ generic-y += altp2m.h
generic-y += device.h
generic-y += hardirq.h
generic-y += iocap.h
+generic-y += nospec.h
generic-y += numa.h
generic-y += paging.h
generic-y += percpu.h
diff --git a/xen/arch/ppc/include/asm/Makefile
b/xen/arch/ppc/include/asm/Makefile
index adb752b804..0e96ad54c3 100644
--- a/xen/arch/ppc/include/asm/Makefile
+++ b/xen/arch/ppc/include/asm/Makefile
@@ -5,6 +5,7 @@ generic-y += div64.h
generic-y += hardirq.h
generic-y += hypercall.h
generic-y += iocap.h
+generic-y += nospec.h
generic-y += numa.h
generic-y += paging.h
generic-y += percpu.h
diff --git a/xen/arch/ppc/include/asm/nospec.h
b/xen/arch/ppc/include/asm/nospec.h
deleted file mode 100644
index b97322e48d..00
--- a/xen/arch/ppc/include/asm/nospec.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* From arch/arm/include/asm/nospec.h. */
-#ifndef __ASM_PPC_NOSPEC_H__
-#define __ASM_PPC_NOSPEC_H__
-
-static inline bool evaluate_nospec(bool condition)
-{
-return condition;
-}
-
-static inline void block_speculation(void)
-{
-}
-
-#endif /* __ASM_PPC_NOSPEC_H__ */
diff --git a/xen/arch/riscv/include/asm/Makefile
b/xen/arch/riscv/include/asm/Makefile
index adb752b804..0e96ad54c3 100644
--- a/xen/arch/riscv/include/asm/Makefile
+++ b/xen/arch/riscv/include/asm/Makefile
@@ -5,6 +5,7 @@ generic-y += div64.h
generic-y += hardirq.h
generic-y += hypercall.h
generic-y += iocap.h
+generic-y += nospec.h
generic-y += numa.h
generic-y += paging.h
generic-y += percpu.h
diff --git a/xen/arch/arm/include/asm/nospec.h
b/xen/include/asm-generic/nospec.h
similarity index 54%
rename from xen/arch/arm/include/asm/nospec.h
rename to xen/include/asm-generic/nospec.h
index 51c7aea4f4..5ded9746f3 100644
--- a/xen/arch/arm/include/asm/nospec.h
+++ b/xen/include/asm-generic/nospec.h
@@ -1,8 +1,8 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. */
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _ASM_GENERIC_NOSPEC_H
+#define _ASM_GENERIC_NOSPEC_H
-#ifndef _ASM_ARM_NOSPEC_H
-#define _ASM_ARM_NOSPEC_H
+#include
static inline bool evaluate_nospec(bool condition)
{
@@ -13,7 +13,7 @@ static inline void block_speculation(void)
{
}
-#endif /* _ASM_ARM_NOSPEC_H */
+#endif /* _ASM_GENERIC_NOSPEC_H */
/*
* Local variables:
--
2.43.0
[PATCH v3 04/34] xen/riscv: introduce cpufeature.h
Signed-off-by: Oleksii Kurochko
Acked-by: Jan Beulich
---
Changes in V3:
- add SPDX and footer
- update declaration of cpu_nr_siblings() to return unsigned int instead of
int.
- add Acked-by: Jan Beulich
---
Changes in V2:
- Nothing changed. Only rebase.
---
xen/arch/riscv/include/asm/cpufeature.h | 23 +++
1 file changed, 23 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/cpufeature.h
diff --git a/xen/arch/riscv/include/asm/cpufeature.h
b/xen/arch/riscv/include/asm/cpufeature.h
new file mode 100644
index 00..c08b7d67ad
--- /dev/null
+++ b/xen/arch/riscv/include/asm/cpufeature.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_RISCV_CPUFEATURE_H
+#define __ASM_RISCV_CPUFEATURE_H
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned int cpu_nr_siblings(unsigned int cpu)
+{
+return 1;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_RISCV_CPUFEATURE_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.43.0
[PATCH v3 02/34] xen/riscv: use some asm-generic headers
Some headers are the same as asm-generic verions of them so use them instead of arch-specific headers. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- As [PATCH v6 0/9] Introduce generic headers (https://lore.kernel.org/xen-devel/cover.1703072575.git.oleksii.kuroc...@gmail.com/) is not stable, the list in asm/Makefile can be changed, but the changes will be easy. --- Changes in V3: - remove monitor.h from the RISC-V asm/Makefile list. - add Acked-by: Jan Beulich --- Changes in V2: - New commit introduced in V2. --- xen/arch/riscv/include/asm/Makefile | 13 + 1 file changed, 13 insertions(+) create mode 100644 xen/arch/riscv/include/asm/Makefile diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/asm/Makefile new file mode 100644 index 00..adb752b804 --- /dev/null +++ b/xen/arch/riscv/include/asm/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +generic-y += altp2m.h +generic-y += device.h +generic-y += div64.h +generic-y += hardirq.h +generic-y += hypercall.h +generic-y += iocap.h +generic-y += numa.h +generic-y += paging.h +generic-y += percpu.h +generic-y += random.h +generic-y += softirq.h +generic-y += vm_event.h -- 2.43.0
Re: [BUG]i2c_hid_acpi broken with 4.17.2 on Framework Laptop 13 AMD
Le ven. 22 déc. 2023 à 15:37, Sébastien Chaumat a écrit : > By request of the laptop vendor (Framework) I'm going to open the bug > @fedora for them to jump in. > > https://bugzilla.redhat.com/show_bug.cgi?id=2255625 Sébastien
Re: [BUG]i2c_hid_acpi broken with 4.17.2 on Framework Laptop 13 AMD
By request of the laptop vendor (Framework) I'm going to open the bug
@fedora for them to jump in.
> > I noticed that on baremetal :
> >
> > 53: 0 0 0 0 0 1268
> > 0 0 0 0 0 0 0
> >0 0 0 amd_gpio5 FRMW0005:00
> > 54: 0 0 0 0 0 1
> > 0 0 0 0 0 0 0
> >0 0 0 amd_gpio 84 FRMW0004:00
> > 55: 0 0 0 0 0 1403
> > 0 0 0 0 0 0 0
> >0 0 0 amd_gpio8 PIXA3854:00
> >
> > with xen with IRQ7 setup only once there's only (the touchpad is
> > PIXA3854:00)
> >
> > 176: 0 0 0 0 0 0
> > 1 0 0 0 0 0 0
> >0 0 0 amd_gpio8
> >
>
> Interestingly when IRQ7 is setup twice (normal xen)
> > 176: 0 0 0 0 0 0
> > 1 0 0 0 0 0 0
> >0 0 0 amd_gpio8 PIXA3854:00
>
> That's odd, as with IRQ7 (wrongly) setup as edge, it should also be marked
> as non-sharable. Otoh with the "i2c-PIXA3854:00:" error above it's no
> surprise no interrupt is set up there.
>
forget this one, I made a mistake when skipping IRQ7.
The "amd_gpio8 PIXA3854:00"for IRQ176 is identical with or without
IRQ7 double initialization.
>> Furthermore it might be interesting to know whether ELCR would give us
> >>> any hint in this case. Sadly depending on where you look,
> >>> applicability of this pair of registers (I/O ports 0x4d0 and 0x4d1)
> >>> to other than EISA systems is claimed true or false. Could you perhaps
> >>> make Xen simply log the values read from those two ports, by e.g.
> >>> inserting
> >>>
> >>> printk("ELCR: %02x, %02x\n", inb(0x4d0), inb(0x4d1));
> >>>
> >>> in, say, setup_dump_irqs()?
> >>>
> >>
> > did that but I don't know how to trigger the dump.
>
> There's no need to trigger the dump. The message will be logged during
> boot, and hence ought to be visible in "xl dmesg" output.
Got :
(XEN) ELCR: 00, 00
Le ven. 22 déc. 2023 à 09:46, Jan Beulich a écrit :
> On 21.12.2023 21:41, Sébastien Chaumat wrote:
> > Le jeu. 21 déc. 2023 à 14:29, Juergen Gross a écrit :
> >
> >> On 21.12.23 13:40, Jan Beulich wrote:
> >>> On 20.12.2023 17:34, Sébastien Chaumat wrote:
> Here are the patches I made to xen and linux kernel
> Plus dmesg (bare metal,xen) and "xl dmesg"
> >>>
> >>> So the problem looks to be that pci_xen_initial_domain() results in
> >>> permanent setup of IRQ7, when there only "static" ACPI tables (in
> >>> particular source overrides in MADT) are consulted. The necessary
> >>> settings, however, are known only after _CRS for the device was
> >>> evaluated (and possibly _PRS followed by invocation of _SRS). All of
> >>> this happens before xen_register_gsi() is called. But that function's
> >>> call to xen_register_pirq() is short-circuited by the very first if()
> >>> in xen_register_pirq() when there was an earlier invocation. Hence
> >>> the (wrong) "edge" binding remains in place, as was established by
> >>> the earlier call here.
> >>>
> >>> Jürgen, there's an interesting comment in xen_bind_pirq_gsi_to_irq(),
> >>> right before invoking irq_set_chip_and_handler_name(). Despite what
> >>> the comment says (according to my reading), the fasteoi one is _not_
> >>> used in all cases. Assuming there's a reason for this, it's not clear
> >>> to me whether updating the handler later on is a valid thing to do.
> >>> __irq_set_handler() being even an exported symbol suggests that might
> >>> be an option to use here. Then again merely updating the handler may
> >>> not be sufficient, seeing there are also e.g. IRQD_TRIGGER_MASK and
> >>> IRQD_LEVEL.
> >>
> >> I understand the last paragraph of that comment to reason, that in case
> >> pirq_needs_eoi() return true even in case of an edge triggered
> interrupt,
> >> the outcome is still okay.
> >>
> >> I don't think updating the handler later is valid.
> >>
> >>> Sébastien, to prove the (still pretty weak) theory that the change in
> >>> handler is all that's needed to make things work in your case, could
> >>> you fiddle with pci_xen_initial_domain() to have it skip IRQ7? (That
> >>> of course won't be a proper solution, but ought to be okay for your
> >>> system.) The main weakness of the theory is that IRQ7 really isn't
> >>> very special in this regard - other PCI IRQs routed to the low 16
> >>> IO-APIC pins ought to have similar issues (from the log, on your
> >>> system this would be at least IRQ6 and IRQ10, except that they happen
> >>> to be edge/low, so
Re: [PATCH v6 5/9] xen/asm-generic: introduce stub header numa.h
On 22/12/2023 13:58, Julien Grall wrote: Hi Jan, On 22/12/2023 13:20, Jan Beulich wrote: On 22.12.2023 14:07, Oleksii wrote: On Fri, 2023-12-22 at 09:22 +0100, Jan Beulich wrote: On 21.12.2023 20:09, Julien Grall wrote: On 20/12/2023 14:08, Oleksii Kurochko wrote: is common through some archs so it is moved to asm-generic. Signed-off-by: Oleksii Kurochko Reviewed-by: Michal Orzel Acked-by: Jan Beulich Acked-by: Shawn Anastasio I think this patch will need to be rebased on top of the lastest staging as this should clash with 51ffb3311895. No, and I'd like to withdraw my ack here. In this case a stub header isn't the right choice imo - the !NUMA case should be handled in common code. I would have submitted the patch I have, if only the first_valid_mfn patch hadn't been committed already (which I now need to re-base over). I haven't seen your patch yet (waiting for it), but I assume that will still be necessary and remain the same across Arm, PPC, and RISC-V. What am I missing? asm/numa.h will be necessary for an arch only if it actually has a way to have CONFIG_NUMA enabled. Below, for your reference, the patch in the not-yet-rebased form. As you can see, Arm's (and PPC's) header goes away. If and when they choose to support NUMA, they may need to regain one; whether at that point we can sort how an asm-generic/ form of the header might sensibly look like remains to be seen. Jan NUMA: no need for asm/numa.h when !NUMA There's no point in every architecture carrying the same stubs for the case when NUMA isn't enabled (or even supported). Move all of that to xen/numa.h; replace explicit uses of asm/numa.h in common code. Make inclusion of asm/numa.h dependent upon NUMA=y. Address the TODO regarding first_valid_mfn by making the variable static when NUMA=y, thus also addressing a Misrs C:2012 rule 8.4 concern. Drop the not really applicable "implement NUMA support" comment - in a !NUMA section this simply makes no sense. I have to admit, I am not really thrill with the approach you have taken. As I said before, I don't quite understand the problem of having first_valid_mfn exposed in all the circumstances. This is better than trying to do... --- unstable.orig/xen/common/page_alloc.c +++ unstable/xen/common/page_alloc.c @@ -140,7 +140,6 @@ #include #include -#include #include #include @@ -256,10 +255,14 @@ static PAGE_LIST_HEAD(page_broken_list); * BOOT-TIME ALLOCATOR */ +#ifndef CONFIG_NUMA /* * first_valid_mfn is exported because it is use in ARM specific NUMA * helpers. See comment in arch/arm/include/asm/numa.h. */ +#else +static +#endif ... this sort ugliness. Just to add more thoughts. My main concern here is that we likely have other variables that may only be exposed for a given arch. I would rather not like if we start sprinkling the code with #ifdef CONFIG_XXX static #else. If there is a desire for everyone to start reducing the scope of the variable. Then we should come up with a way to do what you did above on the same line rather than multiple one. Maybe: STATIC_IF(CONFIG_NUMA) unsigned long first_valid_mfn. Cheers, -- Julien Grall
Re: [PATCH v6 9/9] xen/asm-generic: introduce generic device.h
Hi Oleksii,
On 22/12/2023 13:16, Oleksii wrote:
On Thu, 2023-12-21 at 19:38 +, Julien Grall wrote:
Hi,
On 20/12/2023 14:08, Oleksii Kurochko wrote:
Arm, PPC and RISC-V use the same device.h thereby device.h
was moved to asm-generic. Arm's device.h was taken as a base with
the following changes:
- #ifdef PCI related things.
- #ifdef ACPI related things.
- Rename #ifdef guards.
- Add SPDX tag.
- #ifdef CONFIG_HAS_DEVICE_TREE related things.
- #ifdef-ing iommu related things with CONFIG_HAS_PASSTHROUGH.
Also Arm and PPC are switched to asm-generic version of device.h
Signed-off-by: Oleksii Kurochko
---
Jan wrote the following:
Overall I think there are too many changes done all in one
go here.
But it's mostly Arm which is affected, so I'll leave
judging about that
to the Arm maintainers.
Arm maintainers, will it be fine for you to not split the
patch?
So in general I agree with Jan, patches should be kept small so they
are
easy to review.
Given the discussion has been on-going for a while (we are at v6), I
will give an attempt to review the patch as-is. But in the future,
please try to split. The smaller it is, the easier to review. For
code
movement and refactoring, I tend to first have a few refactoring
patches
and then move the code in a separate patch. So it is easier to spot
the
differences.
Thanks, I'll separate the patch.
---
Changes in V6:
- Rebase only.
---
Changes in V5:
- Removed generated file: xen/include/headers++.chk.new
- Removed pointless #ifdef CONFIG_HAS_DEVICE_TREE ... #endif for
PPC as
CONFIG_HAS_DEVICE_TREE will be always used for PPC.
---
Changes in V4:
- Updated the commit message
- Switched Arm and PPC to asm-generic version of device.h
- Replaced HAS_PCI with CONFIG_HAS_PCI
- ifdef-ing iommu filed of dev_archdata struct with
CONFIG_HAS_PASSTHROUGH
- ifdef-ing iommu_fwspec of device struct with
CONFIG_HAS_PASSTHROUGH
- ifdef-ing DT related things with CONFIG_HAS_DEVICE_TREE
- Updated the commit message ( remove a note with question about
if device.h should be in asm-generic or not )
- Replaced DEVICE_IC with DEVICE_INTERRUPT_CONTROLLER
- Rationalized usage of CONFIG_HAS_* in device.h
- Fixed indents for ACPI_DEVICE_START and ACPI_DEVICE_END
---
Changes in V3:
- ifdef device tree related things.
- update the commit message
---
Changes in V2:
- take ( as common ) device.h from Arm as PPC and RISC-V
use it as a base.
- #ifdef PCI related things.
- #ifdef ACPI related things.
- rename DEVICE_GIC to DEVIC_IC.
- rename #ifdef guards.
- switch Arm and PPC to generic device.h
- add SPDX tag
- update the commit message
---
xen/arch/arm/device.c | 15 ++-
xen/arch/arm/domain_build.c | 2 +-
xen/arch/arm/gic-v2.c | 4 +-
xen/arch/arm/gic-v3.c | 6 +-
xen/arch/arm/gic.c | 4 +-
xen/arch/arm/include/asm/Makefile | 1 +
xen/arch/ppc/include/asm/Makefile | 1 +
xen/arch/ppc/include/asm/device.h | 53
.../asm => include/asm-generic}/device.h | 125 +++--
-
9 files changed, 102 insertions(+), 109 deletions(-)
delete mode 100644 xen/arch/ppc/include/asm/device.h
rename xen/{arch/arm/include/asm => include/asm-generic}/device.h
(79%)
diff --git a/xen/arch/arm/device.c b/xen/arch/arm/device.c
index 1f631d3274..affbe79f9a 100644
--- a/xen/arch/arm/device.c
+++ b/xen/arch/arm/device.c
@@ -16,7 +16,10 @@
#include
extern const struct device_desc _sdevice[], _edevice[];
+
+#ifdef CONFIG_ACPI
extern const struct acpi_device_desc _asdevice[], _aedevice[];
+#endif
int __init device_init(struct dt_device_node *dev, enum
device_class class,
const void *data)
@@ -45,6 +48,7 @@ int __init device_init(struct dt_device_node
*dev, enum device_class class,
return -EBADF;
}
+#ifdef CONFIG_ACPI
int __init acpi_device_init(enum device_class class, const void
*data, int class_type)
{
const struct acpi_device_desc *desc;
@@ -61,6 +65,7 @@ int __init acpi_device_init(enum device_class
class, const void *data, int class
return -EBADF;
}
+#endif
enum device_class device_get_class(const struct dt_device_node
*dev)
{
@@ -329,9 +334,13 @@ int handle_device(struct domain *d, struct
dt_device_node *dev, p2m_type_t p2mt,
struct map_range_data mr_data = {
.d = d,
.p2mt = p2mt,
- .skip_mapping = !own_device ||
- (is_pci_passthrough_enabled() &&
- (device_get_class(dev) ==
DEVICE_PCI_HOSTBRIDGE)),
+ .skip_mapping =
+ !own_device
+#ifdef CONFIG_HAS_PCI
+ ||
Re: [PATCH v6 5/9] xen/asm-generic: introduce stub header numa.h
Hi Jan, On 22/12/2023 13:20, Jan Beulich wrote: On 22.12.2023 14:07, Oleksii wrote: On Fri, 2023-12-22 at 09:22 +0100, Jan Beulich wrote: On 21.12.2023 20:09, Julien Grall wrote: On 20/12/2023 14:08, Oleksii Kurochko wrote: is common through some archs so it is moved to asm-generic. Signed-off-by: Oleksii Kurochko Reviewed-by: Michal Orzel Acked-by: Jan Beulich Acked-by: Shawn Anastasio I think this patch will need to be rebased on top of the lastest staging as this should clash with 51ffb3311895. No, and I'd like to withdraw my ack here. In this case a stub header isn't the right choice imo - the !NUMA case should be handled in common code. I would have submitted the patch I have, if only the first_valid_mfn patch hadn't been committed already (which I now need to re-base over). I haven't seen your patch yet (waiting for it), but I assume that will still be necessary and remain the same across Arm, PPC, and RISC-V. What am I missing? asm/numa.h will be necessary for an arch only if it actually has a way to have CONFIG_NUMA enabled. Below, for your reference, the patch in the not-yet-rebased form. As you can see, Arm's (and PPC's) header goes away. If and when they choose to support NUMA, they may need to regain one; whether at that point we can sort how an asm-generic/ form of the header might sensibly look like remains to be seen. Jan NUMA: no need for asm/numa.h when !NUMA There's no point in every architecture carrying the same stubs for the case when NUMA isn't enabled (or even supported). Move all of that to xen/numa.h; replace explicit uses of asm/numa.h in common code. Make inclusion of asm/numa.h dependent upon NUMA=y. Address the TODO regarding first_valid_mfn by making the variable static when NUMA=y, thus also addressing a Misrs C:2012 rule 8.4 concern. Drop the not really applicable "implement NUMA support" comment - in a !NUMA section this simply makes no sense. I have to admit, I am not really thrill with the approach you have taken. As I said before, I don't quite understand the problem of having first_valid_mfn exposed in all the circumstances. This is better than trying to do... --- unstable.orig/xen/common/page_alloc.c +++ unstable/xen/common/page_alloc.c @@ -140,7 +140,6 @@ #include #include -#include #include #include @@ -256,10 +255,14 @@ static PAGE_LIST_HEAD(page_broken_list); * BOOT-TIME ALLOCATOR */ +#ifndef CONFIG_NUMA /* * first_valid_mfn is exported because it is use in ARM specific NUMA * helpers. See comment in arch/arm/include/asm/numa.h. */ +#else +static +#endif ... this sort ugliness. I am not going to Nack the patch. But I am definitely not going to ack it. with this change. Cheers, -- Julien Grall
Re: [PATCH v6 5/9] xen/asm-generic: introduce stub header numa.h
On 22.12.2023 14:07, Oleksii wrote:
> On Fri, 2023-12-22 at 09:22 +0100, Jan Beulich wrote:
>> On 21.12.2023 20:09, Julien Grall wrote:
>>> On 20/12/2023 14:08, Oleksii Kurochko wrote:
is common through some archs so it is moved
to asm-generic.
Signed-off-by: Oleksii Kurochko
Reviewed-by: Michal Orzel
Acked-by: Jan Beulich
Acked-by: Shawn Anastasio
>>>
>>> I think this patch will need to be rebased on top of the lastest
>>> staging
>>> as this should clash with 51ffb3311895.
>>
>> No, and I'd like to withdraw my ack here. In this case a stub header
>> isn't
>> the right choice imo - the !NUMA case should be handled in common
>> code. I
>> would have submitted the patch I have, if only the first_valid_mfn
>> patch
>> hadn't been committed already (which I now need to re-base over).
> I haven't seen your patch yet (waiting for it), but I assume that
> will still be necessary and remain the same across Arm,
> PPC, and RISC-V.
>
> What am I missing?
asm/numa.h will be necessary for an arch only if it actually has a way
to have CONFIG_NUMA enabled. Below, for your reference, the patch in
the not-yet-rebased form. As you can see, Arm's (and PPC's) header goes
away. If and when they choose to support NUMA, they may need to regain
one; whether at that point we can sort how an asm-generic/ form of the
header might sensibly look like remains to be seen.
Jan
NUMA: no need for asm/numa.h when !NUMA
There's no point in every architecture carrying the same stubs for the
case when NUMA isn't enabled (or even supported). Move all of that to
xen/numa.h; replace explicit uses of asm/numa.h in common code. Make
inclusion of asm/numa.h dependent upon NUMA=y.
Address the TODO regarding first_valid_mfn by making the variable static
when NUMA=y, thus also addressing a Misrs C:2012 rule 8.4 concern. Drop
the not really applicable "implement NUMA support" comment - in a !NUMA
section this simply makes no sense.
Signed-off-by: Jan Beulich
---
This is an alternative proposal to
https://lists.xen.org/archives/html/xen-devel/2023-12/msg01586.html
and its earlier forms.
--- unstable.orig/xen/arch/arm/include/asm/numa.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __ARCH_ARM_NUMA_H
-#define __ARCH_ARM_NUMA_H
-
-#include
-
-typedef u8 nodeid_t;
-
-#ifndef CONFIG_NUMA
-
-/* Fake one node for now. See also node_online_map. */
-#define cpu_to_node(cpu) 0
-#define node_to_cpumask(node) (cpu_online_map)
-
-/*
- * TODO: make first_valid_mfn static when NUMA is supported on Arm, this
- * is required because the dummy helpers are using it.
- */
-extern mfn_t first_valid_mfn;
-
-/* XXX: implement NUMA support */
-#define node_spanned_pages(nid) (max_page - mfn_x(first_valid_mfn))
-#define node_start_pfn(nid) (mfn_x(first_valid_mfn))
-#define __node_distance(a, b) (20)
-
-#endif
-
-#define arch_want_default_dmazone() (false)
-
-#endif /* __ARCH_ARM_NUMA_H */
-/*
- * Local variables:
- * mode: C
- * c-file-style: "BSD"
- * c-basic-offset: 4
- * indent-tabs-mode: nil
- * End:
- */
--- unstable.orig/xen/arch/arm/smpboot.c
+++ unstable/xen/arch/arm/smpboot.c
@@ -42,7 +42,7 @@ integer_param("maxcpus", max_cpus);
/* CPU logical map: map xen cpuid to an MPIDR */
register_t __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
-/* Fake one node for now. See also asm/numa.h */
+/* Fake one node for now. See also xen/numa.h */
nodemask_t __read_mostly node_online_map = { { [0] = 1UL } };
/* Xen stack for bringing up the first CPU. */
--- unstable.orig/xen/arch/ppc/include/asm/numa.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __ASM_PPC_NUMA_H__
-#define __ASM_PPC_NUMA_H__
-
-#include
-#include
-
-typedef uint8_t nodeid_t;
-
-/* Fake one node for now. See also node_online_map. */
-#define cpu_to_node(cpu) 0
-#define node_to_cpumask(node) (cpu_online_map)
-
-/*
- * TODO: make first_valid_mfn static when NUMA is supported on PPC, this
- * is required because the dummy helpers are using it.
- */
-extern mfn_t first_valid_mfn;
-
-/* XXX: implement NUMA support */
-#define node_spanned_pages(nid) (max_page - mfn_x(first_valid_mfn))
-#define node_start_pfn(nid) (mfn_x(first_valid_mfn))
-#define __node_distance(a, b) (20)
-
-#define arch_want_default_dmazone() (false)
-
-#endif /* __ASM_PPC_NUMA_H__ */
--- unstable.orig/xen/common/page_alloc.c
+++ unstable/xen/common/page_alloc.c
@@ -140,7 +140,6 @@
#include
#include
-#include
#include
#include
@@ -256,10 +255,14 @@ static PAGE_LIST_HEAD(page_broken_list);
* BOOT-TIME ALLOCATOR
*/
+#ifndef CONFIG_NUMA
/*
* first_valid_mfn is exported because it is use in ARM specific NUMA
* helpers. See comment in arch/arm/include/asm/numa.h.
*/
+#else
+static
+#endif
mfn_t first_valid_mfn = INVALID_MFN_INITIALIZER;
struct bootmem_region {
--- unstable.orig/xen/common/sysctl.c
+++ unstable/xen/common/sysctl.c
@@ -22,8 +22,8 @@
#include
#include
#include
-#include
#include
+#include
#include
#include
#include
---
Re: [PATCH v6 9/9] xen/asm-generic: introduce generic device.h
Hi Julien,
On Thu, 2023-12-21 at 19:38 +, Julien Grall wrote:
> Hi,
>
> On 20/12/2023 14:08, Oleksii Kurochko wrote:
> > Arm, PPC and RISC-V use the same device.h thereby device.h
> > was moved to asm-generic. Arm's device.h was taken as a base with
> > the following changes:
> > - #ifdef PCI related things.
> > - #ifdef ACPI related things.
> > - Rename #ifdef guards.
> > - Add SPDX tag.
> > - #ifdef CONFIG_HAS_DEVICE_TREE related things.
> > - #ifdef-ing iommu related things with CONFIG_HAS_PASSTHROUGH.
> >
> > Also Arm and PPC are switched to asm-generic version of device.h
> >
> > Signed-off-by: Oleksii Kurochko
> > ---
> >
> > Jan wrote the following:
> > Overall I think there are too many changes done all in one
> > go here.
> > But it's mostly Arm which is affected, so I'll leave
> > judging about that
> > to the Arm maintainers.
> >
> > Arm maintainers, will it be fine for you to not split the
> > patch?
>
> So in general I agree with Jan, patches should be kept small so they
> are
> easy to review.
>
> Given the discussion has been on-going for a while (we are at v6), I
> will give an attempt to review the patch as-is. But in the future,
> please try to split. The smaller it is, the easier to review. For
> code
> movement and refactoring, I tend to first have a few refactoring
> patches
> and then move the code in a separate patch. So it is easier to spot
> the
> differences.
Thanks, I'll separate the patch.
>
> > ---
> > Changes in V6:
> > - Rebase only.
> > ---
> > Changes in V5:
> > - Removed generated file: xen/include/headers++.chk.new
> > - Removed pointless #ifdef CONFIG_HAS_DEVICE_TREE ... #endif for
> > PPC as
> > CONFIG_HAS_DEVICE_TREE will be always used for PPC.
> > ---
> > Changes in V4:
> > - Updated the commit message
> > - Switched Arm and PPC to asm-generic version of device.h
> > - Replaced HAS_PCI with CONFIG_HAS_PCI
> > - ifdef-ing iommu filed of dev_archdata struct with
> > CONFIG_HAS_PASSTHROUGH
> > - ifdef-ing iommu_fwspec of device struct with
> > CONFIG_HAS_PASSTHROUGH
> > - ifdef-ing DT related things with CONFIG_HAS_DEVICE_TREE
> > - Updated the commit message ( remove a note with question about
> > if device.h should be in asm-generic or not )
> > - Replaced DEVICE_IC with DEVICE_INTERRUPT_CONTROLLER
> > - Rationalized usage of CONFIG_HAS_* in device.h
> > - Fixed indents for ACPI_DEVICE_START and ACPI_DEVICE_END
> > ---
> > Changes in V3:
> > - ifdef device tree related things.
> > - update the commit message
> > ---
> > Changes in V2:
> > - take ( as common ) device.h from Arm as PPC and RISC-V
> > use it as a base.
> > - #ifdef PCI related things.
> > - #ifdef ACPI related things.
> > - rename DEVICE_GIC to DEVIC_IC.
> > - rename #ifdef guards.
> > - switch Arm and PPC to generic device.h
> > - add SPDX tag
> > - update the commit message
> >
> > ---
> > xen/arch/arm/device.c | 15 ++-
> > xen/arch/arm/domain_build.c | 2 +-
> > xen/arch/arm/gic-v2.c | 4 +-
> > xen/arch/arm/gic-v3.c | 6 +-
> > xen/arch/arm/gic.c | 4 +-
> > xen/arch/arm/include/asm/Makefile | 1 +
> > xen/arch/ppc/include/asm/Makefile | 1 +
> > xen/arch/ppc/include/asm/device.h | 53
> > .../asm => include/asm-generic}/device.h | 125 +++--
> > -
> > 9 files changed, 102 insertions(+), 109 deletions(-)
> > delete mode 100644 xen/arch/ppc/include/asm/device.h
> > rename xen/{arch/arm/include/asm => include/asm-generic}/device.h
> > (79%)
> >
> > diff --git a/xen/arch/arm/device.c b/xen/arch/arm/device.c
> > index 1f631d3274..affbe79f9a 100644
> > --- a/xen/arch/arm/device.c
> > +++ b/xen/arch/arm/device.c
> > @@ -16,7 +16,10 @@
> > #include
> >
> > extern const struct device_desc _sdevice[], _edevice[];
> > +
> > +#ifdef CONFIG_ACPI
> > extern const struct acpi_device_desc _asdevice[], _aedevice[];
> > +#endif
> >
> > int __init device_init(struct dt_device_node *dev, enum
> > device_class class,
> > const void *data)
> > @@ -45,6 +48,7 @@ int __init device_init(struct dt_device_node
> > *dev, enum device_class class,
> > return -EBADF;
> > }
> >
> > +#ifdef CONFIG_ACPI
> > int __init acpi_device_init(enum device_class class, const void
> > *data, int class_type)
> > {
> > const struct acpi_device_desc *desc;
> > @@ -61,6 +65,7 @@ int __init acpi_device_init(enum device_class
> > class, const void *data, int class
> >
> > return -EBADF;
> > }
> > +#endif
> >
> > enum device_class device_get_class(const struct dt_device_node
> > *dev)
> > {
> > @@ -329,9 +334,13 @@ int handle_device(struct domain *d, struct
> > dt_device_node *dev, p2m_type_t p2mt,
> > struct
Re: [PATCH v6 4/9] xen/asm-generic: introduce stub header monitor.h
On 22.12.2023 14:02, Oleksii wrote:
> On Wed, 2023-12-20 at 16:33 +, Andrew Cooper wrote:
>> On 20/12/2023 2:08 pm, Oleksii Kurochko wrote:
>>> diff --git a/xen/include/asm-generic/monitor.h b/xen/include/asm-
>>> generic/monitor.h
>>> new file mode 100644
>>> index 00..74e4870cd7
>>> --- /dev/null
>>> +++ b/xen/include/asm-generic/monitor.h
>>> @@ -0,0 +1,57 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +/*
>>> + * include/asm-generic/monitor.h
>>> + *
>>> + * Arch-specific monitor_op domctl handler.
>>> + *
>>> + * Copyright (c) 2015 Tamas K Lengyel (ta...@tklengyel.com)
>>> + * Copyright (c) 2016, Bitdefender S.R.L.
>>> + *
>>> + */
>>> +
>>> +#ifndef __ASM_GENERIC_MONITOR_H__
>>> +#define __ASM_GENERIC_MONITOR_H__
>>> +
>>> +#include
>>> +
>>> +struct domain;
>>> +struct xen_domctl_monitor_op;
>>> +
>>> +static inline
>>> +void arch_monitor_allow_userspace(struct domain *d, bool
>>> allow_userspace)
>>> +{
>>> +}
>>> +
>>> +static inline
>>> +int arch_monitor_domctl_op(struct domain *d, struct
>>> xen_domctl_monitor_op *mop)
>>> +{
>>> + /* No arch-specific monitor ops on GENERIC. */
>>> + return -EOPNOTSUPP;
>>> +}
>>> +
>>> +int arch_monitor_domctl_event(struct domain *d,
>>> + struct xen_domctl_monitor_op *mop);
>>
>> Turn this into a static inline like the others, and you can delete:
>>
>> arch/ppc/stubs.c:100
>>
>> int arch_monitor_domctl_event(struct domain *d,
>> struct xen_domctl_monitor_op *mop)
>> {
>> BUG_ON("unimplemented");
>> }
>>
>> because new architectures shouldn't have to stub one random piece of
>> a
>> subsystem when using the generic "nothing special" header.
>>
>> Given the filtering for arch_monitor_domctl_op(), this one probably
>> wants to be ASSERT_UNREACHABLE(); return 0.
> What you wrote makes sense. However, doing it that way may limit the
> reuse of other parts of the asm-generic header. It would require
> introducing an architecture-specific monitor.h header, which would be
> nearly identical.
>
> For instance, at present, the only difference between Arm, PPC, and
> RISC-V is arch_monitor_domctl_event(). If this function is implemented
> with BUG_ON("unimplemented"), reusing the asm-generic monitor.h header
> for Arm (as it is partly done now) becomes challenging.
>
> To address this, I propose wrapping arch_monitor_domctl_event() in
> #ifdef:
>
> #ifndef HAS_ARCH_MONITOR_DOMCTL_EVENT
> int arch_monitor_domctl_event(struct domain *d,
> struct xen_domctl_monitor_op *mop)
> {
> BUG_ON("unimplemented");
> }
> #endif
>
> In the architecture-specific monitor.h, you would define
> HAS_ARCH_MONITOR_DOMCTL_EVENT and provide the architecture-specific
> implementation of the function. For example, in the case of Arm:
>
> #ifndef __ASM_ARM_MONITOR_H__
> #define __ASM_ARM_MONITOR_H__
>
> #include
> #include
>
> #define HAS_ARCH_MONITOR_DOMCTL_EVENT
>
> #include
>
> static inline uint32_t arch_monitor_get_capabilities(struct domain *d)
> {
> uint32_t capabilities = 0;
>
> capabilities = (1U << XEN_DOMCTL_MONITOR_EVENT_GUEST_REQUEST |
> 1U << XEN_DOMCTL_MONITOR_EVENT_PRIVILEGED_CALL);
>
> return capabilities;
> }
>
> int monitor_smc(void);
>
> #endif /* __ASM_ARM_MONITOR_H__ */
>
> This approach maintains a clean and modular structure, allowing for
> architecture-specific variations while reusing the majority of the code
> from the generic header.
>
> Does it make sense?
With the state things are in right now in the tree, perhaps yes. But
as with NUMA and other subsystems: Generally the case of the subsystem
not used should be handled in common code. What's in asm-generic/ is
supposed to be a default implementation when the subsystem _is_ used.
Unlike NUMA, there's no Kconfig control for MONITOR (or VM_EVENT).
Hence why getting this sorted is somewhat more involved here; (ab)using
the asm-generic/ header for the time being is an option, but would then
need properly justifying (imo).
Jan
Re: [PATCH v6 7/9] xen: ifdef inclusion of in
Hi Julien, On Thu, 2023-12-21 at 19:20 +, Julien Grall wrote: > > > On 21/12/2023 19:19, Julien Grall wrote: > > Hi Oleksii, > > > > On 20/12/2023 14:08, Oleksii Kurochko wrote: > > > Ifdef-ing inclusion of allows to avoid > > > generation of empty for cases when > > > CONFIG_GRANT_TABLE is not enabled. > > > > It would have been nice to explain the reason of this change. Is > > this a > > compilation error or just a nice thing to have? > > > > The reason I am asking is... > > > > > > > > The following changes were done for Arm: > > > should be included directly because it > > > contains > > > gnttab_dom0_frames() macros which is unique for Arm and is used > > > in > > > arch/arm/domain_build.c. > > > is #ifdef-ed with CONFIG_GRANT_TABLE in > > > so in case of !CONFIG_GRANT_TABLE > > > gnttab_dom0_frames > > > won't be available for use in arch/arm/domain_build.c. > > > > ... I find rather ugly that we require domain_build.c to include > > both > > asm/grant_table.h and xen/grant_table.h. > > > > Right now, I don't have a better approach, so I would be ok so long > > the > > rationale of the change is explained in the commit message. > > Urgh, I just realized that this is explained in the commit message. > Please ignore my comment about expanding the commit message. Sorry > for > the noise. It's OK. Thanks for review! ~ Oleksii
Re: [PATCH v6 5/9] xen/asm-generic: introduce stub header numa.h
On Fri, 2023-12-22 at 09:22 +0100, Jan Beulich wrote: > On 21.12.2023 20:09, Julien Grall wrote: > > On 20/12/2023 14:08, Oleksii Kurochko wrote: > > > is common through some archs so it is moved > > > to asm-generic. > > > > > > Signed-off-by: Oleksii Kurochko > > > Reviewed-by: Michal Orzel > > > Acked-by: Jan Beulich > > > Acked-by: Shawn Anastasio > > > > I think this patch will need to be rebased on top of the lastest > > staging > > as this should clash with 51ffb3311895. > > No, and I'd like to withdraw my ack here. In this case a stub header > isn't > the right choice imo - the !NUMA case should be handled in common > code. I > would have submitted the patch I have, if only the first_valid_mfn > patch > hadn't been committed already (which I now need to re-base over). I haven't seen your patch yet (waiting for it), but I assume that will still be necessary and remain the same across Arm, PPC, and RISC-V. What am I missing? ~ Oleksii
Re: [PATCH v6 4/9] xen/asm-generic: introduce stub header monitor.h
On Wed, 2023-12-20 at 16:33 +, Andrew Cooper wrote:
> On 20/12/2023 2:08 pm, Oleksii Kurochko wrote:
> > diff --git a/xen/include/asm-generic/monitor.h b/xen/include/asm-
> > generic/monitor.h
> > new file mode 100644
> > index 00..74e4870cd7
> > --- /dev/null
> > +++ b/xen/include/asm-generic/monitor.h
> > @@ -0,0 +1,57 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * include/asm-generic/monitor.h
> > + *
> > + * Arch-specific monitor_op domctl handler.
> > + *
> > + * Copyright (c) 2015 Tamas K Lengyel (ta...@tklengyel.com)
> > + * Copyright (c) 2016, Bitdefender S.R.L.
> > + *
> > + */
> > +
> > +#ifndef __ASM_GENERIC_MONITOR_H__
> > +#define __ASM_GENERIC_MONITOR_H__
> > +
> > +#include
> > +
> > +struct domain;
> > +struct xen_domctl_monitor_op;
> > +
> > +static inline
> > +void arch_monitor_allow_userspace(struct domain *d, bool
> > allow_userspace)
> > +{
> > +}
> > +
> > +static inline
> > +int arch_monitor_domctl_op(struct domain *d, struct
> > xen_domctl_monitor_op *mop)
> > +{
> > + /* No arch-specific monitor ops on GENERIC. */
> > + return -EOPNOTSUPP;
> > +}
> > +
> > +int arch_monitor_domctl_event(struct domain *d,
> > + struct xen_domctl_monitor_op *mop);
>
> Turn this into a static inline like the others, and you can delete:
>
> arch/ppc/stubs.c:100
>
> int arch_monitor_domctl_event(struct domain *d,
> struct xen_domctl_monitor_op *mop)
> {
> BUG_ON("unimplemented");
> }
>
> because new architectures shouldn't have to stub one random piece of
> a
> subsystem when using the generic "nothing special" header.
>
> Given the filtering for arch_monitor_domctl_op(), this one probably
> wants to be ASSERT_UNREACHABLE(); return 0.
What you wrote makes sense. However, doing it that way may limit the
reuse of other parts of the asm-generic header. It would require
introducing an architecture-specific monitor.h header, which would be
nearly identical.
For instance, at present, the only difference between Arm, PPC, and
RISC-V is arch_monitor_domctl_event(). If this function is implemented
with BUG_ON("unimplemented"), reusing the asm-generic monitor.h header
for Arm (as it is partly done now) becomes challenging.
To address this, I propose wrapping arch_monitor_domctl_event() in
#ifdef:
#ifndef HAS_ARCH_MONITOR_DOMCTL_EVENT
int arch_monitor_domctl_event(struct domain *d,
struct xen_domctl_monitor_op *mop)
{
BUG_ON("unimplemented");
}
#endif
In the architecture-specific monitor.h, you would define
HAS_ARCH_MONITOR_DOMCTL_EVENT and provide the architecture-specific
implementation of the function. For example, in the case of Arm:
#ifndef __ASM_ARM_MONITOR_H__
#define __ASM_ARM_MONITOR_H__
#include
#include
#define HAS_ARCH_MONITOR_DOMCTL_EVENT
#include
static inline uint32_t arch_monitor_get_capabilities(struct domain *d)
{
uint32_t capabilities = 0;
capabilities = (1U << XEN_DOMCTL_MONITOR_EVENT_GUEST_REQUEST |
1U << XEN_DOMCTL_MONITOR_EVENT_PRIVILEGED_CALL);
return capabilities;
}
int monitor_smc(void);
#endif /* __ASM_ARM_MONITOR_H__ */
This approach maintains a clean and modular structure, allowing for
architecture-specific variations while reusing the majority of the code
from the generic header.
Does it make sense?
~ Oleksii
[libvirt test] 184208: tolerable all pass - PUSHED
flight 184208 libvirt real [real] http://logs.test-lab.xenproject.org/osstest/logs/184208/ Failures :-/ but no regressions. Tests which did not succeed, but are not blocking: test-armhf-armhf-libvirt 16 saverestore-support-checkfail like 184199 test-armhf-armhf-libvirt-raw 15 saverestore-support-checkfail like 184199 test-armhf-armhf-libvirt-qcow2 15 saverestore-support-check fail like 184199 test-amd64-i386-libvirt-xsm 15 migrate-support-checkfail never pass test-amd64-amd64-libvirt 15 migrate-support-checkfail never pass test-amd64-i386-libvirt 15 migrate-support-checkfail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass test-arm64-arm64-libvirt-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-libvirt-xsm 16 saverestore-support-checkfail never pass test-arm64-arm64-libvirt 15 migrate-support-checkfail never pass test-arm64-arm64-libvirt 16 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass test-amd64-amd64-libvirt-xsm 15 migrate-support-checkfail never pass test-armhf-armhf-libvirt 15 migrate-support-checkfail never pass test-amd64-i386-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-qcow2 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-qcow2 15 saverestore-support-checkfail never pass test-arm64-arm64-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-raw 15 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-vhd 14 migrate-support-checkfail never pass test-armhf-armhf-libvirt-raw 14 migrate-support-checkfail never pass test-armhf-armhf-libvirt-qcow2 14 migrate-support-checkfail never pass version targeted for testing: libvirt b72d7c46e54109c5df98977d30d7c78dac79514d baseline version: libvirt 9fc140c72d4a9d2ad44bd69474023e130b3da13b Last test of basis 184199 2023-12-21 04:20:29 Z1 days Testing same since 184208 2023-12-22 04:20:26 Z0 days1 attempts People who touched revisions under test: Han Han jobs: build-amd64-xsm pass build-arm64-xsm pass build-i386-xsm pass build-amd64 pass build-arm64 pass build-armhf pass build-i386 pass build-amd64-libvirt pass build-arm64-libvirt pass build-armhf-libvirt pass build-i386-libvirt pass build-amd64-pvopspass build-arm64-pvopspass build-armhf-pvopspass build-i386-pvops pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsmpass test-amd64-amd64-libvirt-xsm pass test-arm64-arm64-libvirt-xsm pass test-amd64-i386-libvirt-xsm pass test-amd64-amd64-libvirt pass test-arm64-arm64-libvirt pass test-armhf-armhf-libvirt pass test-amd64-i386-libvirt pass test-amd64-amd64-libvirt-pairpass test-amd64-i386-libvirt-pair pass test-arm64-arm64-libvirt-qcow2 pass test-armhf-armhf-libvirt-qcow2 pass test-arm64-arm64-libvirt-raw pass test-armhf-armhf-libvirt-raw pass test-amd64-i386-libvirt-raw pass test-amd64-amd64-libvirt-vhd pass sg-report-flight on osstest.test-lab.xenproject.org logs: /home/logs/logs images: /home/logs/images Logs, config files, etc. are available at http://logs.test-lab.xenproject.org/osstest/logs Explanation of these reports, and of osstest in general, is at
Re: hvmloader - allow_memory_relocate overlaps
On 21.12.2023 19:08, Neowutran wrote:
> On 2023-12-19 17:12, Jan Beulich wrote:
>> On 16.12.2023 08:01, Neowutran wrote:
>>> I am wondering if the variable "allow_memory_relocate" is still
>>> relevant today and if its default value is still relevant.
>>> Should it be defined to 0 by default instead of 1 (it seems to be a
>>> workaround for qemu-traditional, so maybe an outdated default value ? ) ?
>>
>> So are you saying you use qemu-trad?
> No, I am using "qemu_xen" ( from
> xenstore-read -> 'device-model =
> "qemu_xen"'
>
>> Otherwise isn't libxl suppressing this behavior anyway?
> If by "isn't libxl suppressing this behavior" you means if libxl is setting
> the value of "allow_memory_relocate", then the answer is no.
>
> Following this lead, I checked in what code path
> "allow_memory_relocate" could be defined.
>
> It is only defined in one code path,
>
> In the file "tools/libs/light/libxl_dm.c",
> in the function "void libxl__spawn_local_dm(libxl__egc *egc,
> libxl__dm_spawn_state *dmss)":
>
> '''
> // ...
> if (b_info->type == LIBXL_DOMAIN_TYPE_HVM) {
> // ...
>
> libxl__xs_printf(gc, XBT_NULL,
> GCSPRINTF("%s/hvmloader/allow-memory-relocate",
> path),
> "%d",
>
> b_info->device_model_version==LIBXL_DEVICE_MODEL_VERSION_QEMU_XEN_TRADITIONAL
> &&
> !libxl__vnuma_configured(b_info));
> // ...
> '''
>
> However, on QubesOS (my system), "local_dm" is never used, "stub_dm"
> is always used.
>
> In the function "void lib
> xl__spawn_stub_dm(libxl__egc *egc, libxl__stub_dm_spawn_state *sdss)",
> the value of "allow_memory_relocate" is never defined.
>
> I tried to patch the code to define "allow_memory_relocate" in
> "libxl__spawn_stub_dm":
>
> '''
> --- a/tools/libs/light/libxl_dm.c
> +++ b/tools/libs/light/libxl_dm.c
> @@ -2431,6 +2431,10 @@ void libxl__spawn_stub_dm(libxl__egc *egc,
> libxl__stub_dm_spawn_state *sdss)
> libxl__xs_get_dompath(gc,
> guest_domid)),
> "%s",
>
> libxl_bios_type_to_string(guest_config->b_info.u.hvm.bios));
> +libxl__xs_printf(gc, XBT_NULL,
> + libxl__sprintf(gc,
> "%s/hvmloader/allow-memory-relocate", libxl__xs_get_dompath(gc, guest_domid)),
> + "%d",
> + 0);
> }
> ret = xc_domain_set_target(ctx->xch, dm_domid, guest_domid);
> if (ret<0) {
> '''
>
> And it is indeed another way to solve my issue.
> However I do not understand the xen hypervisor enough to known i
> f
> "allow-memory-relocate" should have been defined in
> "libxl__spawn_stub_dm" or if the real issue is somewhere else.
I think it should be done the same no matter where qemu runs. Back at the
time iirc only qemu-trad could run in a stubdom, which may explain the
omission. Cc-ing the two guys who are likely in the best position to tell
for sure.
>>> Code extract:
>>>
>>> tools/firmware/hvmloader/pci.c
>>> "
>>>/*
>>> * Do we allow hvmloader to relocate guest memory in order to
>>> * increase the size of the lowmem MMIO hole? Defaulting to 1
>>> * here will
>>> mean that non-libxl toolstacks (including xend and
>>> * home-grown ones) means that those using qemu-xen will still
>>> * experience the memory relocation bug described below; but it
>>> * also means that those using q
>>> emu-traditional will *not*
>>> * experience any change; and it also means that there is a
>>> * work-around for those using qemu-xen, namely switching to
>>> * qemu-traditional.
>>> *
>>> * If we defaulted to 0, and failing to resize the hole caused any
>>> * problems with qemu-traditional, then there is no work-around.
>>> *
>>> * Since xend can
> only use qemu-traditional, I think this is the
>>> * option that will have the least impact.
>>> */
>>> bool allow_memory_relocate = 1;
>>> "
>>>
>>> "
>>> /*
>>> * At the moment qemu-xen can't deal with relocated memory regions.
>>> * It's too close to the release to make a proper fix; for now,
>>> * only allow t
>>> he MMIO hole to grow large enough to move guest memory
>>> * if we're running qemu-traditional. Items that don't fit will be
>>> * relocated into the 64-bit address space.
>>> *
>>> * This loop now does the following:
>>> * - If allow_memory_relocate, increase the MMIO hole until it's
>>> * big enough, or
>>> until it's 2GiB
>>> * - If !allow_memory_relocate, increase the MMIO hole until it's
>>> * big enough, or until it's 2GiB, or until it overlaps guest
>>> * memory
>>> */
>>> while ( (mmio_total > (pci_mem_end - pci_mem_start))
>>>
> && ((pci_mem_start << 1) != 0)
>>> &&
[ovmf test] 184210: all pass - PUSHED
flight 184210 ovmf real [real] http://logs.test-lab.xenproject.org/osstest/logs/184210/ Perfect :-) All tests in this flight passed as required version targeted for testing: ovmf d01defe06b35eb3fe9c94e7b2e08a8762873f924 baseline version: ovmf 5d533bbc27732a421e3bf35c5af77782b8a85e6f Last test of basis 184202 2023-12-21 10:12:56 Z1 days Testing same since 184210 2023-12-22 09:12:48 Z0 days1 attempts People who touched revisions under test: Abdul Lateef Attar jobs: build-amd64-xsm pass build-i386-xsm pass build-amd64 pass build-i386 pass build-amd64-libvirt pass build-i386-libvirt pass build-amd64-pvopspass build-i386-pvops pass test-amd64-amd64-xl-qemuu-ovmf-amd64 pass test-amd64-i386-xl-qemuu-ovmf-amd64 pass sg-report-flight on osstest.test-lab.xenproject.org logs: /home/logs/logs images: /home/logs/images Logs, config files, etc. are available at http://logs.test-lab.xenproject.org/osstest/logs Explanation of these reports, and of osstest in general, is at http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master Test harness code can be found at http://xenbits.xen.org/gitweb?p=osstest.git;a=summary Pushing revision : To xenbits.xen.org:/home/xen/git/osstest/ovmf.git 5d533bbc27..d01defe06b d01defe06b35eb3fe9c94e7b2e08a8762873f924 -> xen-tested-master
Re: [PATCH] move __read_mostly to xen/cache.h
On 22.12.2023 10:39, Oleksii wrote: > On Tue, 2023-08-08 at 12:32 +0200, Jan Beulich wrote: >> On 08.08.2023 12:18, Andrew Cooper wrote: >>> On 08/08/2023 10:46 am, Jan Beulich wrote: There's no need for every arch to define its own identical copy. If down the road an arch needs to customize it, we can add #ifndef around the common #define. To be on the safe side build-breakage-wise, change a couple of #include to the xen/ equivalent. Signed-off-by: Jan Beulich >>> >>> Could we find a better place to put this? >>> >>> __read_mostly is just a section. It's relationship to the cache is >>> only >>> microarchitectural, and is not the same kind of information as the >>> rest >>> of cache.h >>> >>> __ro_after_init is only here because __read_mostly is here, but has >>> absolutely nothing to do with caches whatsoever. >>> >>> If we're cleaning them up, they ought to live elsewhere. >> >> I would be considering init.h (for having most other __section() >> uses, >> and for also needing __read_mostly), but that's not a great place to >> put these either. In fact I see less connection there than for >> cache.h. >> So the primary need is a good suggestion (I'm hesitant to suggest to >> introduce section.h just for this). > Andrew sent some suggestions here: > https://lore.kernel.org/xen-devel/3df1dad8-3476-458f-9022-160e0af57...@citrix.com/ > > Will that work for you? I still need to properly look at the suggested options. Jan
[linux-linus test] 184206: tolerable FAIL - PUSHED
flight 184206 linux-linus real [real] flight 184211 linux-linus real-retest [real] http://logs.test-lab.xenproject.org/osstest/logs/184206/ http://logs.test-lab.xenproject.org/osstest/logs/184211/ Failures :-/ but no regressions. Tests which are failing intermittently (not blocking): test-armhf-armhf-libvirt-qcow2 10 host-ping-check-xen fail pass in 184211-retest Tests which did not succeed, but are not blocking: test-armhf-armhf-libvirt-qcow2 15 saverestore-support-check fail in 184211 like 184201 test-armhf-armhf-libvirt-qcow2 14 migrate-support-check fail in 184211 never pass test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stopfail like 184201 test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stopfail like 184201 test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stopfail like 184201 test-armhf-armhf-libvirt 16 saverestore-support-checkfail like 184201 test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stopfail like 184201 test-armhf-armhf-libvirt-raw 15 saverestore-support-checkfail like 184201 test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 184201 test-amd64-amd64-libvirt 15 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-libvirt-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-xl-thunderx 15 migrate-support-checkfail never pass test-arm64-arm64-libvirt-xsm 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-thunderx 16 saverestore-support-checkfail never pass test-arm64-arm64-xl 15 migrate-support-checkfail never pass test-arm64-arm64-xl 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-credit2 15 migrate-support-checkfail never pass test-arm64-arm64-xl-credit2 16 saverestore-support-checkfail never pass test-armhf-armhf-xl 15 migrate-support-checkfail never pass test-armhf-armhf-xl 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-rtds 15 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-arndale 15 migrate-support-checkfail never pass test-armhf-armhf-xl-arndale 16 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit1 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit1 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-credit1 15 migrate-support-checkfail never pass test-arm64-arm64-xl-credit1 16 saverestore-support-checkfail never pass test-arm64-arm64-xl-xsm 15 migrate-support-checkfail never pass test-arm64-arm64-xl-xsm 16 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-qcow2 14 migrate-support-checkfail never pass test-amd64-amd64-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-raw 14 migrate-support-checkfail never pass test-arm64-arm64-libvirt-raw 15 saverestore-support-checkfail never pass test-arm64-arm64-xl-vhd 14 migrate-support-checkfail never pass test-arm64-arm64-xl-vhd 15 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass test-armhf-armhf-xl-vhd 14 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 15 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 15 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 16 saverestore-support-checkfail never pass test-armhf-armhf-libvirt 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 15 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 16 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-raw 14 migrate-support-checkfail never pass version targeted for testing: linux9a6b294ab496650e9f270123730df37030911b55 baseline version: linuxa4aebe936554dac6a91e5d091179c934f8325708 Last test of basis 184201 2023-12-21 08:46:02 Z1 days Testing same since 184206 2023-12-21 22:43:55 Z0 days1 attempts People who touched revisions under test: Alex Lu Alexander Graf Andrii Nakryiko Andy Gospodarek Arnd Bergmann Avraham Stern Carolina Jubran Chandan Kumar Rout (A Contingent Worker at Intel) Chen-Yu Tsai Chris Mi Dan Carpenter Daniel Golle Dave Ertman David Ahern David Howells David S. Miller Dinghao Liu duanqiangwen Edward Adam Davis Eric Dumazet Felix Fietkau Frédéric Danis Geliang Tang Hangbin Liu Hou Tao Hyunwoo
Re: [PATCH] move __read_mostly to xen/cache.h
On Tue, 2023-08-08 at 12:32 +0200, Jan Beulich wrote: > On 08.08.2023 12:18, Andrew Cooper wrote: > > On 08/08/2023 10:46 am, Jan Beulich wrote: > > > There's no need for every arch to define its own identical copy. > > > If down > > > the road an arch needs to customize it, we can add #ifndef around > > > the > > > common #define. > > > > > > To be on the safe side build-breakage-wise, change a couple of > > > #include > > > to the xen/ equivalent. > > > > > > Signed-off-by: Jan Beulich > > > > Could we find a better place to put this? > > > > __read_mostly is just a section. It's relationship to the cache is > > only > > microarchitectural, and is not the same kind of information as the > > rest > > of cache.h > > > > __ro_after_init is only here because __read_mostly is here, but has > > absolutely nothing to do with caches whatsoever. > > > > If we're cleaning them up, they ought to live elsewhere. > > I would be considering init.h (for having most other __section() > uses, > and for also needing __read_mostly), but that's not a great place to > put these either. In fact I see less connection there than for > cache.h. > So the primary need is a good suggestion (I'm hesitant to suggest to > introduce section.h just for this). Andrew sent some suggestions here: https://lore.kernel.org/xen-devel/3df1dad8-3476-458f-9022-160e0af57...@citrix.com/ Will that work for you? > In the absence of this, can we > perhaps deal with this in a 2nd step, thus not blocking this patch > and > therefore not needing to then also clean up PPC-specific code? ~ Oleksii
Re: [PATCH v2 30/39] xen/riscv: define an address of frame table
On Fri, 2023-12-22 at 09:08 +0100, Jan Beulich wrote:
> On 21.12.2023 20:59, Oleksii wrote:
> > On Mon, 2023-12-18 at 12:22 +0100, Jan Beulich wrote:
> > > On 18.12.2023 11:36, Oleksii wrote:
> > > > On Thu, 2023-12-14 at 16:48 +0100, Jan Beulich wrote:
> > > > > On 24.11.2023 11:30, Oleksii Kurochko wrote:
> > > > > > +#define SLOTN_ENTRY_SIZE SLOTN(1)
> > > > > > +
> > > > > > #define XEN_VIRT_START 0xC000 /* (_AC(-1, UL)
> > > > > > + 1
> > > > > > -
> > > > > > GB(1)) */
> > > > > > +
> > > > > > +#define FRAMETABLE_VIRT_START SLOTN(196)
> > > > > > +#define FRAMETABLE_SIZE GB(3)
> > > > > > +#define FRAMETABLE_NR (FRAMETABLE_SIZE /
> > > > > > sizeof(*frame_table))
> > > > > > +#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START +
> > > > > > FRAMETABLE_SIZE - 1)
> > > > > > +
> > > > > > +#define VMAP_VIRT_START SLOTN(194)
> > > > > > +#define VMAP_VIRT_SIZE GB(1)
> > > > >
> > > > > May I suggest that you keep these blocks sorted by slot
> > > > > number?
> > > > > Or
> > > > > wait,
> > > > > the layout comment further up is also in decreasing order, so
> > > > > that's
> > > > > fine here, but then can all of this please be moved next to
> > > > > the
> > > > > comment
> > > > > actually providing the necessary context (thus eliminating
> > > > > the
> > > > > need
> > > > > for
> > > > > new comments)?
> > > > Sure, I'll put this part close to layout comment.
> > > >
> > > > > You'll then also notice that the generalization here
> > > > > (keeping basically the same layout for e.g. SATP_MODE_SV48,
> > > > > just
> > > > > shifted
> > > > > by 9 bits) isn't in line with the comment there.
> > > > Does it make sense to add another one table with updated
> > > > addresses
> > > > for
> > > > SATP_MODE_SV48?
> > >
> > > Well, especially if you mean to support that mode, its layout
> > > surely
> > > wants writing down. I was hoping though that maybe you/we could
> > > get
> > > away
> > > without multiple tables, but e.g. use one having multiple
> > > columns.
> > I came up with the following but I am not sure that it is really
> > convient:
> > /*
> > * RISC-V64 Layout:
> > *
> > #if RV_STAGE1_MODE == SATP_MODE_SV39
> > *
> > * From the riscv-privileged doc:
> > * When mapping between narrower and wider addresses,
> > * RISC-V zero-extends a narrower physical address to a wider
> > size.
> > * The mapping between 64-bit virtual addresses and the 39-bit
> > usable
> > * address space of Sv39 is not based on zero-extension but
> > instead
> > * follows an entrenched convention that allows an OS to use one
> > or
> > * a few of the most-significant bits of a full-size (64-bit)
> > virtual
> > * address to quickly distinguish user and supervisor address
> > regions.
> > *
> > * It means that:
> > * top VA bits are simply ignored for the purpose of translating
> > to
> > PA.
> > #endif
> > *
> > * SATP_MODE_SV32 SATP_MODE_SV39 SATP_MODE_SV48
> > SATP_MODE_SV57
> > *
> >
> > ---
> > * BA0 | FFE0 | C000 | FF80 |
> >
> > * BA1 | 1900 | 0032 | 6400 |
> > 00C8
> > * BA2 | 1880 | 0031 | 6200 |
> > 00C4
> > * BA3 | 1840 | 00308000 | 6100 |
> > 00C2
> > *
> > *
> > ===
> >
> > =
> > * Start addr | End addr | Size | Slot |area
> > description
> > *
> > ===
> >
> > =
> > * BA0 + 0x80 | |1016 MB |
> > L${HYP_PT_ROOT_LEVEL} 511 | Unused
> > * BA0 + 0x40 | BA0 + 0x80 | 2 MB |
> > L${HYP_PT_ROOT_LEVEL} 511 | Fixmap
> > * BA0 + 0x20 | BA0 + 0x40 | 4 MB |
> > L${HYP_PT_ROOT_LEVEL} 511 | FDT
> > * BA0 | BA0 + 0x20 | 2 MB |
> > L${HYP_PT_ROOT_LEVEL} 511 | Xen
> > * ... | 1 GB |
> > L${HYP_PT_ROOT_LEVEL} 510 | Unused
> > * BA1 + 0x00 | BA1 + 0x4D8000 | 309 GB |
> > L${HYP_PT_ROOT_LEVEL} 200-509 | Direct map
> > * ... | 1 GB |
> > L${HYP_PT_ROOT_LEVEL} 199 | Unused
> > * BA2 + 0x00 | BA2 + 0xC000 | 3 GB |
> > L${HYP_PT_ROOT_LEVEL} 196-198 | Frametable
> > * ... | 1 GB |
> > L${HYP_PT_ROOT_LEVEL} 195 | Unused
> > * BA3 + 0x00 | BA3 + 0x4000 | 1 GB |
> > L${HYP_PT_ROOT_LEVEL} 194 | VMAP
> > * ... | 194 GB |
> > L${HYP_PT_ROOT_LEVEL} 0 - 193 | Unused
> > *
> > ===
> >
> > =
> > */
> >
> > Do you have better ideas?
>
Re: [PATCH v11 05/17] vpci: add hooks for PCI device assign/de-assign
On 02.12.2023 02:27, Volodymyr Babchuk wrote: > @@ -886,6 +890,10 @@ static int deassign_device(struct domain *d, uint16_t > seg, uint8_t bus, > > pdev->fault.count = 0; > > +write_lock(>pci_lock); > +ret = vpci_assign_device(pdev); > +write_unlock(>pci_lock); > + > out: > if ( ret ) > printk(XENLOG_G_ERR "%pd: deassign (%pp) failed (%d)\n", Considering the function we're in, I think this "assign" deserves a comment. It's necessary for hwdom only aiui, i.e. particularly not for the more typical case of putting the device in quarantine? Jan
Re: [BUG]i2c_hid_acpi broken with 4.17.2 on Framework Laptop 13 AMD
On 21.12.2023 21:41, Sébastien Chaumat wrote: > Le jeu. 21 déc. 2023 à 14:29, Juergen Gross a écrit : > >> On 21.12.23 13:40, Jan Beulich wrote: >>> On 20.12.2023 17:34, Sébastien Chaumat wrote: Here are the patches I made to xen and linux kernel Plus dmesg (bare metal,xen) and "xl dmesg" >>> >>> So the problem looks to be that pci_xen_initial_domain() results in >>> permanent setup of IRQ7, when there only "static" ACPI tables (in >>> particular source overrides in MADT) are consulted. The necessary >>> settings, however, are known only after _CRS for the device was >>> evaluated (and possibly _PRS followed by invocation of _SRS). All of >>> this happens before xen_register_gsi() is called. But that function's >>> call to xen_register_pirq() is short-circuited by the very first if() >>> in xen_register_pirq() when there was an earlier invocation. Hence >>> the (wrong) "edge" binding remains in place, as was established by >>> the earlier call here. >>> >>> Jürgen, there's an interesting comment in xen_bind_pirq_gsi_to_irq(), >>> right before invoking irq_set_chip_and_handler_name(). Despite what >>> the comment says (according to my reading), the fasteoi one is _not_ >>> used in all cases. Assuming there's a reason for this, it's not clear >>> to me whether updating the handler later on is a valid thing to do. >>> __irq_set_handler() being even an exported symbol suggests that might >>> be an option to use here. Then again merely updating the handler may >>> not be sufficient, seeing there are also e.g. IRQD_TRIGGER_MASK and >>> IRQD_LEVEL. >> >> I understand the last paragraph of that comment to reason, that in case >> pirq_needs_eoi() return true even in case of an edge triggered interrupt, >> the outcome is still okay. >> >> I don't think updating the handler later is valid. >> >>> Sébastien, to prove the (still pretty weak) theory that the change in >>> handler is all that's needed to make things work in your case, could >>> you fiddle with pci_xen_initial_domain() to have it skip IRQ7? (That >>> of course won't be a proper solution, but ought to be okay for your >>> system.) The main weakness of the theory is that IRQ7 really isn't >>> very special in this regard - other PCI IRQs routed to the low 16 >>> IO-APIC pins ought to have similar issues (from the log, on your >>> system this would be at least IRQ6 and IRQ10, except that they happen >>> to be edge/low, so fitting the ISA defaults); only IRQ16 and up would >>> work okay. >>> >> > > Doing just that : IQR7 is now of type level > xen-pirq -ioapic-level pinctrl_amd > > > (but is ioapic-level there totally equivalent to the fasteoi of baremetal) > Still the touchpad does not work. > > And we have now : > Dec 21 20:13:57 fedora kernel: i2c_hid_acpi i2c-PIXA3854:00: failed to > reset device: -61 > Dec 21 20:14:17 fedora kernel: i2c_hid_acpi: probe of i2c-PIXA3854:00 > failed with error -61 > > in addition to > Dec 21 20:13:57 fedora kernel: i2c_hid_acpi i2c-FRMW0004:00: failed to > reset device: -61 > Dec 21 20:13:57 fedora kernel: i2c_hid_acpi i2c-FRMW0005:00: failed to > reset device: -61 > Dec 21 20:14:17 fedora kernel: i2c_hid_acpi: probe of i2c-FRMW0004:00 > failed with error -61 > Dec 21 20:14:17 fedora kernel: i2c_hid_acpi: probe of i2c-FRMW0005:00 > failed with error -61 So there's more to this, which I'm afraid will (first) need looking into by a person familiar with the involved drivers. > I noticed that on baremetal : > > 53: 0 0 0 0 0 1268 > 0 0 0 0 0 0 0 >0 0 0 amd_gpio5 FRMW0005:00 > 54: 0 0 0 0 0 1 > 0 0 0 0 0 0 0 >0 0 0 amd_gpio 84 FRMW0004:00 > 55: 0 0 0 0 0 1403 > 0 0 0 0 0 0 0 >0 0 0 amd_gpio8 PIXA3854:00 > > with xen with IRQ7 setup only once there's only (the touchpad is > PIXA3854:00) > > 176: 0 0 0 0 0 0 > 1 0 0 0 0 0 0 >0 0 0 amd_gpio8 > > Interestingly when IRQ7 is setup twice (normal xen) > 176: 0 0 0 0 0 0 > 1 0 0 0 0 0 0 >0 0 0 amd_gpio8 PIXA3854:00 That's odd, as with IRQ7 (wrongly) setup as edge, it should also be marked as non-sharable. Otoh with the "i2c-PIXA3854:00:" error above it's no surprise no interrupt is set up there. >> Furthermore it might be interesting to know whether ELCR would give us >>> any hint in this case. Sadly depending on where you look, >>>
Re: [PATCH v6 5/9] xen/asm-generic: introduce stub header numa.h
On 21.12.2023 20:09, Julien Grall wrote: > On 20/12/2023 14:08, Oleksii Kurochko wrote: >> is common through some archs so it is moved >> to asm-generic. >> >> Signed-off-by: Oleksii Kurochko >> Reviewed-by: Michal Orzel >> Acked-by: Jan Beulich >> Acked-by: Shawn Anastasio > > I think this patch will need to be rebased on top of the lastest staging > as this should clash with 51ffb3311895. No, and I'd like to withdraw my ack here. In this case a stub header isn't the right choice imo - the !NUMA case should be handled in common code. I would have submitted the patch I have, if only the first_valid_mfn patch hadn't been committed already (which I now need to re-base over). Jan
Re: [PATCH v2 30/39] xen/riscv: define an address of frame table
On 21.12.2023 20:59, Oleksii wrote:
> On Mon, 2023-12-18 at 12:22 +0100, Jan Beulich wrote:
>> On 18.12.2023 11:36, Oleksii wrote:
>>> On Thu, 2023-12-14 at 16:48 +0100, Jan Beulich wrote:
On 24.11.2023 11:30, Oleksii Kurochko wrote:
> +#define SLOTN_ENTRY_SIZE SLOTN(1)
> +
> #define XEN_VIRT_START 0xC000 /* (_AC(-1, UL) + 1
> -
> GB(1)) */
> +
> +#define FRAMETABLE_VIRT_START SLOTN(196)
> +#define FRAMETABLE_SIZE GB(3)
> +#define FRAMETABLE_NR (FRAMETABLE_SIZE /
> sizeof(*frame_table))
> +#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START +
> FRAMETABLE_SIZE - 1)
> +
> +#define VMAP_VIRT_START SLOTN(194)
> +#define VMAP_VIRT_SIZE GB(1)
May I suggest that you keep these blocks sorted by slot number?
Or
wait,
the layout comment further up is also in decreasing order, so
that's
fine here, but then can all of this please be moved next to the
comment
actually providing the necessary context (thus eliminating the
need
for
new comments)?
>>> Sure, I'll put this part close to layout comment.
>>>
You'll then also notice that the generalization here
(keeping basically the same layout for e.g. SATP_MODE_SV48, just
shifted
by 9 bits) isn't in line with the comment there.
>>> Does it make sense to add another one table with updated addresses
>>> for
>>> SATP_MODE_SV48?
>>
>> Well, especially if you mean to support that mode, its layout surely
>> wants writing down. I was hoping though that maybe you/we could get
>> away
>> without multiple tables, but e.g. use one having multiple columns.
> I came up with the following but I am not sure that it is really
> convient:
> /*
> * RISC-V64 Layout:
> *
> #if RV_STAGE1_MODE == SATP_MODE_SV39
> *
> * From the riscv-privileged doc:
> * When mapping between narrower and wider addresses,
> * RISC-V zero-extends a narrower physical address to a wider size.
> * The mapping between 64-bit virtual addresses and the 39-bit usable
> * address space of Sv39 is not based on zero-extension but instead
> * follows an entrenched convention that allows an OS to use one or
> * a few of the most-significant bits of a full-size (64-bit) virtual
> * address to quickly distinguish user and supervisor address
> regions.
> *
> * It means that:
> * top VA bits are simply ignored for the purpose of translating to
> PA.
> #endif
> *
> * SATP_MODE_SV32 SATP_MODE_SV39 SATP_MODE_SV48
> SATP_MODE_SV57
> *
> ---
> * BA0 | FFE0 | C000 | FF80 |
>
> * BA1 | 1900 | 0032 | 6400 |
> 00C8
> * BA2 | 1880 | 0031 | 6200 |
> 00C4
> * BA3 | 1840 | 00308000 | 6100 |
> 00C2
> *
> *
> ===
> =
> * Start addr| End addr | Size | Slot |area
> description
> *
> ===
> =
> * BA0 + 0x80 | |1016 MB |
> L${HYP_PT_ROOT_LEVEL} 511 | Unused
> * BA0 + 0x40 | BA0 + 0x80 | 2 MB |
> L${HYP_PT_ROOT_LEVEL} 511 | Fixmap
> * BA0 + 0x20 | BA0 + 0x40 | 4 MB |
> L${HYP_PT_ROOT_LEVEL} 511 | FDT
> * BA0| BA0 + 0x20 | 2 MB |
> L${HYP_PT_ROOT_LEVEL} 511 | Xen
> * ... | 1 GB |
> L${HYP_PT_ROOT_LEVEL} 510 | Unused
> * BA1 + 0x00 | BA1 + 0x4D8000 | 309 GB |
> L${HYP_PT_ROOT_LEVEL} 200-509 | Direct map
> * ... | 1 GB |
> L${HYP_PT_ROOT_LEVEL} 199 | Unused
> * BA2 + 0x00 | BA2 + 0xC000 | 3 GB |
> L${HYP_PT_ROOT_LEVEL} 196-198 | Frametable
> * ... | 1 GB |
> L${HYP_PT_ROOT_LEVEL} 195 | Unused
> * BA3 + 0x00 | BA3 + 0x4000 | 1 GB |
> L${HYP_PT_ROOT_LEVEL} 194 | VMAP
> * ... | 194 GB |
> L${HYP_PT_ROOT_LEVEL} 0 - 193 | Unused
> *
> ===
> =
> */
>
> Do you have better ideas?
It doesn't look too bad imo, at the first glance, albeit the line
wrapping damage of course makes it a little hard to look at. In the
last table with all lines saying L${HYP_PT_ROOT_LEVEL}, perhaps that
could be put in the table heading (instead of "Slot" say e.g. "Root
PT slot")?
Jan
