On 9/6/2023 9:09 PM, Mukul Joshi wrote:
This patch fixes the following unaligned 64-bit doorbell
warning seen when submitting packets on HIQ on GFX v9.4.3
by making the HIQ doorbell 64-bit aligned.
The warning is seen when GPU is loaded in any mode other
than SPX mode.
[ +0.000301]
Acked-by: Alex Deucher
On Thu, Sep 7, 2023 at 12:20 AM Yifan Zhang wrote:
>
> gc info usage misses type conversion.
>
> Signed-off-by: Yifan Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git
On 9/6/2023 8:53 PM, Alex Deucher wrote:
On Wed, Sep 6, 2023 at 12:05 AM Lijo Lazar wrote:
SMU v13.0.6 SOCs have 100MHz reference clock.
Do we want to use the vbios value on boards that have a vbios? If
it's the same on all variants, then this is probably fine as is.
Yes, it's the
[AMD Official Use Only - General]
> -Original Message-
> From: Imre Deak
> Sent: Friday, August 25, 2023 9:56 PM
> To: Lin, Wayne
> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
> ly...@redhat.com; jani.nik...@intel.com; ville.syrj...@linux.intel.com;
> Wentland,
Hi Dave, Daniel,
Fixes for 6.6. Bigger than usual since this is ~3 weeks of fixes.
The following changes since commit 3698a75f5a98d0a6599e2878ab25d30a82dd836a:
Merge tag 'drm-intel-next-fixes-2023-08-24' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next (2023-08-25 12:55:55
>From gfx10 and onwards, there are two bitmaps in driver,
CU bitmap and WGP bitmap, current log for harvesting WGP is
misleading, the disabling unit is WGP not CU for gfx10 and later.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
gc info usage misses type conversion.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index
Signed-off-by: Lin.Cao
---
drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h
b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h
index 8b6b2bd5c148..ed937f70895c 100644
---
Hi,
On 2023/9/6 17:40, Christian König wrote:
Am 06.09.23 um 11:08 schrieb suijingfeng:
Well, welcome to correct me if I'm wrong.
You seem to have some very basic misunderstandings here.
The term framebuffer describes some VRAM memory used for scanout.
This framebuffer is exposed to
On 2023/9/7 00:00, Alex Deucher wrote:
On Tue, Sep 5, 2023 at 1:25 PM suijingfeng wrote:
Hi,
On 2023/9/5 13:50, Christian König wrote:
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over
which one
is primary at
[AMD Official Use Only - General]
Yeah, nice catch. But personally I would prefer to change the check as "if
(retry <= 0)".
Either way, the patch is reviewed-by: Evan Quan
Evan
> -Original Message-
> From: Dan Carpenter
> Sent: Wednesday, September 6, 2023 6:55 PM
> To: Quan, Evan ;
Acked-by: Anitha Chrisanthus
> -Original Message-
> From: Jim Cromie
> Sent: Wednesday, September 6, 2023 12:02 PM
> To: linux-ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; amd-
> g...@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org; intel-
>
Hi Jim
On 9/6/2023 12:02 PM, Jim Cromie wrote:
By at least strong convention, a print-buffer's trailing newline says
"message complete, send it". The exception (no TNL, followed by a call
to pr_cont) proves the general rule.
Most DRM.debug calls already comport with this: 207 DRM_DEV_DEBUG,
On 2023-09-06 11:39, Mukul Joshi wrote:
This patch fixes the following unaligned 64-bit doorbell
warning seen when submitting packets on HIQ on GFX v9.4.3
by making the HIQ doorbell 64-bit aligned.
The warning is seen when GPU is loaded in any mode other
than SPX mode.
[ +0.000301]
On 2023-08-25 10:18, Melissa Wen wrote:
> On 08/22, Pekka Paalanen wrote:
>> On Thu, 10 Aug 2023 15:02:47 -0100
>> Melissa Wen wrote:
>>
>>> Instead of relying on color block names to get the transfer function
>>> intention regarding encoding pixel's luminance, define supported
>>>
On 9/1/2023 09:32, Jeff Johnson wrote:
On 8/30/2023 11:20 PM, Evan Quan wrote:
To support the WBRF mechanism, Wifi adapters utilized in the system must
Since this is the first mention of WBRF in the core wireless code IMO
you should indicate what this is an acronym for and briefly describe
Commit 254986e324ad ("drm/radeon: Use the drm suballocation manager
implementation.")
made the fence wait in amdgpu_sa_bo_new() interruptible but there is no
code to handle an interrupt. This caused the kernel to randomly explode
in high-VRAM-pressure situations so make it uninterruptible again.
On 2023-08-10 12:02, Melissa Wen wrote:
> Hi all,
>
> Here is the next version of our work to enable AMD driver-specific color
> management properties [1][2]. This series is a collection of
> contributions from Joshua, Harry, and me to enhance the AMD KMS color
> pipeline for Steam Deck/SteamOS
On 2023-08-10 12:02, Melissa Wen wrote:
> On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
> delinearizing and/or normalizing the color space before applying a 3D
> LUT. Add pre-defined transfer function to enable delinearizing content
> with or without shaper LUT, where AMD
On 2023-08-10 12:02, Melissa Wen wrote:
> Add 3D LUT property for plane gamma correction using a 3D lookup table.
> Since a 3D LUT has a limited number of entries in each dimension we want
> to use them in an optimal fashion. This means using the 3D LUT in a
> colorspace that is optimized for
On Wed, 6 Sep 2023 11:51:59 +0800
Sui Jingfeng wrote:
> Hi,
>
>
> On 2023/9/5 22:52, Alex Williamson wrote:
> > On Tue, 5 Sep 2023 03:57:15 +0800
> > Sui Jingfeng wrote:
> >
> >> From: Sui Jingfeng
> >>
> >> On a machine with multiple GPUs, a Linux user has no control over which
> >> one
[AMD Official Use Only - General]
Reviewed-by: David Yat Sin
> -Original Message-
> From: Kuehling, Felix
> Sent: Friday, July 28, 2023 4:00 PM
> To: Francis, David ; amd-gfx@lists.freedesktop.org;
> Yat Sin, David
> Subject: Re: [PATCH v3] drm/amdgpu: Add EXT_COHERENT memory
On 2023-08-10 12:02, Melissa Wen wrote:
> From: Harry Wentland
>
> The region and segment calculation was incapable of dealing
> with regions of more than 16 segments. We first fix this.
>
> Now that we can support regions up to 256 elements we can
> define a better segment distribution for
Incorrect CFLAGS- usage failed to add -DDYNAMIC_DEBUG_MODULE when needed,
which broke builds with:
CONFIG_DRM_USE_DYNAMIC_DEBUG=Y
CONFIG_DYNAMIC_DEBUG_CORE=Y
CONFIG_DYNAMIC_DEBUG=N
Also add subdir-ccflags so that all drivers pick up the addition.
Fixes: 84ec67288c10 ("drm_print: wrap drm_*_dbg
By at least strong convention, a print-buffer's trailing newline says
"message complete, send it". The exception (no TNL, followed by a call
to pr_cont) proves the general rule.
Most DRM.debug calls already comport with this: 207 DRM_DEV_DEBUG,
1288 drm_dbg. Clean up the remainders, in
By at least strong convention, a print-buffer's trailing newline says
"message complete, send it". The exception (no TNL, followed by a call
to pr_cont) proves the general rule.
Most DRM.debug calls already comport with this: 207 DRM_DEV_DEBUG,
1288 drm_dbg. Clean up the remainders, in
By at least strong convention, a print-buffer's trailing newline says
"message complete, send it". The exception (no TNL, followed by a call
to pr_cont) proves the general rule.
Most DRM.debug calls already comport with this: 207 DRM_DEV_DEBUG,
1288 drm_dbg. Clean up the remainders, in
By at least strong convention, a print-buffer's trailing newline says
"message complete, send it". The exception (no TNL, followed by a call
to pr_cont) proves the general rule.
Most DRM.debug calls already comport with this: 207 DRM_DEV_DEBUG,
1288 drm_dbg. Clean up the remainders, in
By at least strong convention, a print-buffer's trailing newline says
"message complete, send it". The exception (no TNL, followed by a call
to pr_cont) proves the general rule.
Most DRM.debug calls already comport with this rule/convention:
207 DRM_DEV_DEBUG, 1288 drm_dbg. Clean up the
On 2023-08-10 12:03, Melissa Wen wrote:
> From: Joshua Ashton
>
> Signed-off-by: Joshua Ashton
> Signed-off-by: Melissa Wen
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 32 +--
> .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +-
> include/uapi/drm/drm_mode.h
On 2023-08-10 12:03, Melissa Wen wrote:
> Map the plane CTM driver-specific property to DC plane, instead of DC
> stream. The remaining steps to program DPP block are already implemented
> on DC shared-code.
>
> Signed-off-by: Melissa Wen
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
On 2023-08-10 12:03, Melissa Wen wrote:
> Plane CTM for pre-blending color space conversion. Only enable
> driver-specific plane CTM property on drivers that support both pre- and
> post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it
> conflits with DRM CRTC CTM property.
>
>
On 2023-08-28 04:20, Pekka Paalanen wrote:
> On Fri, 25 Aug 2023 13:37:08 -0100
> Melissa Wen wrote:
>
>> On 08/22, Pekka Paalanen wrote:
>>> On Thu, 10 Aug 2023 15:03:11 -0100
>>> Melissa Wen wrote:
>>>
dc->caps.color.mpc.gamut_remap says there is a post-blending color block
On Wed, Sep 6, 2023 at 10:42 AM Rodrigo Vivi wrote:
>
> On Mon, Sep 04, 2023 at 08:32:40AM +0200, Andi Shyti wrote:
> > Hi Jim,
> >
> > On Sun, Sep 03, 2023 at 12:46:00PM -0600, Jim Cromie wrote:
> > > By at least strong convention, a print-buffer's trailing newline says
> > > "message complete,
On 2023-08-10 12:03, Melissa Wen wrote:
> From: Joshua Ashton
>
> Need to funnel the color caps through to these functions so it can check
> that the hardware is capable.
>
> v2:
> - remove redundant color caps assignment on plane degamma map (Harry)
> - pass color caps to degamma params
>
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: Yu, Lang
Sent: Wednesday, September 6, 2023 7:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Gopalakrishnan,
Veerabadhran (Veera) ; Yu, Lang
; Dan Carpenter
Subject: [PATCH]
On Mon, Sep 04, 2023 at 08:32:40AM +0200, Andi Shyti wrote:
> Hi Jim,
>
> On Sun, Sep 03, 2023 at 12:46:00PM -0600, Jim Cromie wrote:
> > By at least strong convention, a print-buffer's trailing newline says
> > "message complete, send it". The exception (no TNL, followed by a call
> > to
+ Shashank
On Wed, Sep 6, 2023 at 11:45 AM Mukul Joshi wrote:
>
> This patch fixes the following unaligned 64-bit doorbell
> warning seen when submitting packets on HIQ on GFX v9.4.3
> by making the HIQ doorbell 64-bit aligned.
> The warning is seen when GPU is loaded in any mode other
> than
On Tue, Sep 5, 2023 at 1:25 PM suijingfeng wrote:
>
> Hi,
>
>
> On 2023/9/5 13:50, Christian König wrote:
> > Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
> >> From: Sui Jingfeng
> >>
> >> On a machine with multiple GPUs, a Linux user has no control over
> >> which one
> >> is primary at boot
Rename KGD_MAX_QUEUES to AMDGPU_MAX_QUEUES to conform with
the naming convention followed in amdgpu_gfx.h. No functional
change.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 ++--
Currently, we store CU info only for a single XCC assuming
that it is the same for all XCCs. However, that may not be
true. As a result, store CU info for all XCCs. This info is
later used for CU masking.
Signed-off-by: Mukul Joshi
---
v1->v2:
- Incorporate Felix's review comments.
The CU mask passed from user-space will change based on
different spatial partitioning mode. As a result, update
CU masking code for GFX9.4.3 to work for all partitioning
modes.
Signed-off-by: Mukul Joshi
---
v1->v2:
- Incorporate Felix's review comments.
Update cache info reporting in sysfs to report the correct
number of CUs and associated cache information based on
different spatial partitioning modes.
Signed-off-by: Mukul Joshi
---
v1->v2:
- Revert the change in kfd_crat.c
- Add a comment to not change value of CRAT_SIBLINGMAP_SIZE.
This patch fixes the following unaligned 64-bit doorbell
warning seen when submitting packets on HIQ on GFX v9.4.3
by making the HIQ doorbell 64-bit aligned.
The warning is seen when GPU is loaded in any mode other
than SPX mode.
[ +0.000301] [ cut here ]
[ +0.03]
This matches the behavior for soc15 and nv.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index ef297b41623b..2ecc8c9a078b 100644
---
On Wed, Sep 6, 2023 at 12:05 AM Lijo Lazar wrote:
>
> SMU v13.0.6 SOCs have 100MHz reference clock.
>
Do we want to use the vbios value on boards that have a vbios? If
it's the same on all variants, then this is probably fine as is.
Alex
> Signed-off-by: Lijo Lazar
> ---
>
On 2023-08-29 04:51, Pekka Paalanen wrote:
> On Mon, 28 Aug 2023 12:56:04 -0100
> Melissa Wen wrote:
>
>> On 08/28, Pekka Paalanen wrote:
>>> On Mon, 28 Aug 2023 09:45:44 +0100
>>> Joshua Ashton wrote:
>>>
Degamma has always been on the plane on AMD. CRTC DEGAMMA_LUT has actually
On 2023-08-28 04:17, Pekka Paalanen wrote:
> On Fri, 25 Aug 2023 13:29:44 -0100
> Melissa Wen wrote:
>
>> On 08/22, Pekka Paalanen wrote:
>>> On Thu, 10 Aug 2023 15:02:59 -0100
>>> Melissa Wen wrote:
>>>
The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
On 06/09/2023 16:25, Shashank Sharma wrote:
On 05/09/2023 08:04, Christian König wrote:
Testing for reset is pointless since the reset can start right after the
test. Grab the reset semaphore instead.
The same PASID can be used by more than once VMID, build a mask of VMIDs
to reset instead
On 05/09/2023 08:04, Christian König wrote:
Testing for reset is pointless since the reset can start right after the
test. Grab the reset semaphore instead.
The same PASID can be used by more than once VMID, build a mask of VMIDs
to reset instead of just restting the first one.
On 05/09/2023 08:04, Christian König wrote:
Testing for reset is pointless since the reset can start right after the
test. Grab the reset semaphore instead.
The same PASID can be used by more than once VMID, build a mask of VMIDs
to reset instead of just restting the first one.
On Tue, Sep 5, 2023 at 10:05 PM Lin.Cao wrote:
>
Please fix up the title and the patch description. Something like:
drm/amdgpu: update pm4_mes_runlist
struct pm4_mes_runlist in amdgpu is in conflict with the spec. struct
pm4_mes_runlist is
different with mes pm4 packet nv10 spec. Add last
On Wed, Sep 6, 2023 at 8:25 AM Lang Yu wrote:
>
> On 09/06/ , Dan Carpenter wrote:
>
> Thanks for reporting this bug. Can you give a link to this bug report? Commit
> message requests it.
> ("Reported-by: should be immediately followed by Link: with a URL to the
> report")
For something
Hello Qingqing Zhuo,
This is a semi-automatic email about new static checker warnings.
The patch 8774029f76b9: "drm/amd/display: Add DCN35 CLK_MGR" from Aug
2, 2023, leads to the following Smatch complaint:
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c:980
Hi,
On 2023/9/6 14:45, Christian König wrote:
Firmware framebuffer device already get killed by the
drm_aperture_remove_conflicting_pci_framebuffers()
function (or its siblings). So, this series is definitely not to
interact with the firmware framebuffer
(or more intelligent framebuffer
Here is the list of new warning which were introduced while I was out
of office. The line numbers are from linux-next next-20230905.
regards,
dan carpenter
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c:292
dcn35_update_clocks() warn: inconsistent indenting
This loop will exit with "retry" set to -1 if it fails but the code
checks for if "retry" is zero. Fix this by changing post-op to a
pre-op. --retry vs retry--.
Fixes: e01eeffc3f86 ("drm/amd/pm: avoid driver getting empty metrics table for
the first time")
Signed-off-by: Dan Carpenter
---
On Wed, Sep 06, 2023 at 07:07:32PM +0800, Lang Yu wrote:
> On 09/06/ , Dan Carpenter wrote:
>
> Thanks for reporting this bug. Can you give a link to this bug report? Commit
> message requests it.
> ("Reported-by: should be immediately followed by Link: with a URL to the
> report")
>
My email
Hello Lang Yu,
The patch 5d5eac7e8303: "drm/amdgpu: add selftest framework for
UMSCH" from Jun 21, 2023 (linux-next), leads to the following Smatch
static checker warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c:338 setup_umsch_mm_test()
warn: unsigned error codes
Hi,
On 2023/9/5 22:52, Alex Williamson wrote:
On Tue, 5 Sep 2023 03:57:15 +0800
Sui Jingfeng wrote:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
problem by introduced the
Hi,
On 2023/9/5 23:05, Thomas Zimmermann wrote:
You might have found a bug in the ast driver. Ast has means to detect
if the device has been POSTed and maybe do that. If this doesn't work
correctly, it needs a fix.
That sounds fine.
The bug is not a big deal, I'm just take it as an example
From: Wenjing Liu
[why]
ODM power optimization excludes subvp power optimization but subvp
optimization can override ODM power optimization even if subvp optimization
configuration is not found. This happens with 4k144hz + 1 5k desktop plane.
We could have applied ODM power optimization however
From: Ian Chen
Add flag skip_implict_edp_power_control check in function
dcn32_disable_link_output to fix DCN35 issue.
Reviewed-by: Robin Chen
Acked-by: Stylon Wang
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 --
1 file changed, 4 insertions(+), 2
From: Wenjing Liu
[why]
We have a few cases where we need to perform update topology update
in dc update interface. However some of the updates are not seamless
This could cause user noticible glitches. To enforce seamless transition
we are adding a checking condition and error logging so the
From: Wenjing Liu
[how]
- Add minimial transition log with reason and base state.
- Do not log set dpms interfaces for virtual signal in stream.
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 7 +++
From: Aric Cyr
Acked-by: Stylon Wang
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 05ab24c81041..bece61d2508b 100644
---
From: Wenjing Liu
[why]
During 8k video plane resizing we could transition from MPC combine mode
back to ODM combine 2:1 + 8k video plane. In this transition minimal
transition state is based on new state with ODM combine enabled.
We are skipping this and it causes corruption because we have to
From: Muhammad Ahmed
[What]
MST now recognizes both connected displays
Reviewed-by: Charlene Liu
Acked-by: Stylon Wang
Signed-off-by: Muhammad Ahmed
---
.../display/dc/dce110/dce110_hw_sequencer.c | 30 +++
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 8 ++---
From: Charlene Liu
[why]
fix some non-initialized register mask and update golden setting
Reviewed-by: Duncan Ma
Acked-by: Stylon Wang
Signed-off-by: Charlene Liu
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 56 ++-
.../display/dc/dcn10/dcn10_stream_encoder.h | 5
From: Austin Zheng
Why:
vrr_active_fixed should also be checked when
determining if DRR is in use
How:
Add check for vrr_active_fixed when allow_freesync
and vrr_active_variable are also checked
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Austin Zheng
---
From: Sridevi Arvindekar
[WHY]
Code cleanup found in internal tests
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Sridevi Arvindekar
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Qingqing Zhuo
[Why & How]
Some registers are never used in the driver
but defined. Remove them.
Reviewed-by: Roman Li
Acked-by: Stylon Wang
Signed-off-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h | 2 --
1 file changed, 2 deletions(-)
diff --git
From: Dillon Varone
[WHY]
Add support for programming dp dto via dccg.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 10 ++
2 files
From: Wenjing Liu
[why]
In some cases such as 8k desktop surface with 144Hz timing, we decide to
enable ODM power optimization but this surface doesn't have a minimum
transition state. Therefore we cannot switch off ODM power optimization
seamlessly
This creates path depedency on ODM power
From: Wenjing Liu
[why]
Current dc update design has limitation to support transition from
ODM combine to minimum transition to MPC combine state seamlessly
at the capability boundary when MPO plane is resizing. This will
require dc update high level refactor in order to remove the design
From: Wenjing Liu
[why]
The result of predict_pipe_split calculation is no longer used but the
function is not removed. This will cause unnecessary calculation
of pipe split prediction in every frame update.
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
From: Aurabindo Pillai
[Why]
For enabling automated testing, add a hook to DCHUBBUB interface so that
mall status can be queried by userspace through debugfs. This removes
dependence on requiring a userspace tool like UMR for querying status
for MALL static screen IGT test.
Reviewed-by: Alvin
From: Ethan Bitnun
[Description]
- Add new logs to be used by the AutoDPMTest
- Enclose AutoDPMTest logs in settings
- Add logging definition
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Ethan Bitnun
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 36
From: Paul Hsieh
[Why]
Some panels request main link off before specific vertical line.
If source turn off main link after specific vertical line then
panel defect will be exposed.
[How]
Add interface to support turn off main link before specific
vertical line
Reviewed-by: Robin Chen
From: Wayne Lin
[Why]
In drm_dp_mst_topology_mgr_resume() today, it will resume the
mst branch to be ready handling mst mode and also consecutively do
the mst topology probing. Which will cause the dirver have chance
to fire hotplug event before restoring the old state. Then Userspace
will react
From: Mustapha Ghaddar
[HOW & Why]
There seems to be an issue with 2nd DPIA acquiring link encoder for tiled
displays.
Solution is to remove check for eng_id before we get first dynamic encoder for
it
Reviewed-by: Cruise Hung
Reviewed-by: Meenakshikumar Somasundaram
Cc: Mario Limonciello
From: Wenjing Liu
[why]
build scaling param is overriding validation policy regarding small viewport
support. Even if ODM + windowed MPO is not supported. The decision has
to be made at the time of validation. When building scaling params, we might
be building an initial dc state as an input to
From: Nicholas Susanto
[Why]
DML calculations differ with DCN3.1 spreadsheet values due to
translations errors from the visual basic code
[How]
Add missing calculations that set the value for DSCDelay
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by:
From: Anthony Koo
- Add new params to dmub_feature_caps for checking replay
support in FW
Acked-by: Stylon Wang
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Swapnil Patel
[Why]
Currently the driver looks DCN registers to access if BL is on or not.
This check is not valid if we are using AUX based brightness control.
This causes driver to not send out "backlight off" command during power off
sequence as it already thinks it is off.
[How]
Only
From: Bhawanpreet Lakha
Dirty rect can be used with replay, so enable them to allow for more
powersaving.
Reviewed-by: Sun peng Li
Acked-by: Stylon Wang
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
1 file changed, 2 insertions(+), 1
From: Aurabindo Pillai
[Why]
Set a default return value of -ENOTSUPP to indicate that the hardware
does not support querying ODM Combine mode.
Reviewed-by: Rodrigo Siqueira
Acked-by: Stylon Wang
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |
From: Alvin Lee
[Description]
- When disabling a phantom pipe, we first enable the phantom
OTG so the double buffer update can successfully take place
- However, want to avoid locking the phantom otherwise setting
DPG_EN=1 for the phantom pipe is blocked (without this we could
hit
From: Alvin Lee
[Description]
Before enabling the phantom OTG for an update we
must enable DPG to avoid underflow.
Reviewed-by: Samson Tam
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 50 +--
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix MST bugs
- Fix ODM combine debugfs
- Fix DML calculations
- Fix 2nd DPIA encoder issue
- Fix AUX-based backlight control
- Fix on MPO+ODM use case
- Fix DCCG clock programming
- Improvements on replay
- Improvements
Fixes: 77b13b916728 ("drm/amdgpu: add selftest framework for UMSCH")
Signed-off-by: Lang Yu
Reported-by: Dan Carpenter
Link: https://lore.kernel.org/all/ZPhddADtKmOuVyDq@lang-desktop
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
When reset method is not passed in reset context, look for the handler
for default reset method. On Aldebaran, default reset method for SOCs
connected to CPU over XGMI is MODE2.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/aldebaran.c | 16 +++-
1 file changed, 7
On 9/6/2023 3:23 PM, Christian König wrote:
> Am 06.09.23 um 08:55 schrieb Ma Jun:
>> [1] Remove the irq flags setting code since pci_alloc_irq_vectors()
>> handles these flags.
>> [2] Free the msi vectors in case of error.
>>
>> v2:
>> - Remove local variable initializing code (Christian)
>> -
On 09/06/ , Dan Carpenter wrote:
Thanks for reporting this bug. Can you give a link to this bug report? Commit
message requests it.
("Reported-by: should be immediately followed by Link: with a URL to the
report")
Regards,
Lang
> Hello Lang Yu,
>
> The patch 5d5eac7e8303: "drm/amdgpu: add
Hi
Am 06.09.23 um 11:48 schrieb suijingfeng:
[...]
There's 'nomodeset', which disables all native drivers. It's useful
for debugging or as a quick-fix if the graphics driver breaks. If you
want to disable a specific driver, please use one of the options for
blacklisting.
Yeah, the
Am 06.09.23 um 12:31 schrieb Sui Jingfeng:
Hi,
On 2023/9/6 14:45, Christian König wrote:
Firmware framebuffer device already get killed by the
drm_aperture_remove_conflicting_pci_framebuffers()
function (or its siblings). So, this series is definitely not to
interact with the firmware
[AMD Official Use Only - General]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Zhou1, Tao
Sent: Wednesday, September 6, 2023 18:10
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ;
Yang, Stanley ; Li, Candice ; Chai,
Thomas
Cc: Zhou1, Tao
[AMD Official Use Only - General]
Reviewed-by: Tao Zhou
> -Original Message-
> From: amd-gfx On Behalf Of Hawking
> Zhang
> Sent: Wednesday, September 6, 2023 6:12 PM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ; Yang,
> Stanley ; Li, Candice ; Chai,
> Thomas
> Cc: Zhang, Hawking
gfx_v9_4_3_ue|ce_reg_list is an array per gfx core instance
correct the settings of se_num and reg_inst for some of
gfx ras counters so all the available register instances
can be polled for ras status.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 40
Print out row, column and bank value of UMC error address for UMC v12.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
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