[PATCH] drm/amd/display: fix missing cleanup for remove s3_debug in dm_early_fini()
Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8837259215d9..2c12385e0e4f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1436,6 +1436,12 @@ static int amdgpu_dm_early_fini(void *handle) amdgpu_dm_audio_fini(adev); +#if defined(CONFIG_DEBUG_KERNEL_DC) + device_create_file( + adev_to_drm(adev)->dev, + _attr_s3_debug); +#endif + return 0; } -- 2.25.1
[PATCH v2 2/2] drm/amd/pm: change return value in aldebaran_get_power_limit()
v1:
1. change return value to avoid smu driver probe fails when FEATURE_PPT is
not enabled.
2. if FEATURE_PPT is not enabled, set power limit value to 0.
v2:
instead dev_err with dev_warn
Signed-off-by: Kevin Wang
---
.../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 97cc6fb9b22b..a9f1a2dfbb51 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1194,8 +1194,19 @@ static int aldebaran_get_power_limit(struct smu_context
*smu,
uint32_t power_limit = 0;
int ret;
- if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
- return -EINVAL;
+ if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
+ if (current_power_limit)
+ *current_power_limit = 0;
+ if (default_power_limit)
+ *default_power_limit = 0;
+ if (max_power_limit)
+ *max_power_limit = 0;
+
+ dev_warn(smu->adev->dev,
+ "the PPT feature is not enabled, set power limit to 0");
+
+ return 0;
+ }
/* Valid power data is available only from primary die.
* For secondary die show the value as 0.
--
2.25.1
[PATCH v2 1/2] drm/amd/pm: skip to load smu microcode on sriov for aldebaran
v1:
1. skip to load smu firmware in sriov mode for aldebaran chip
2. using vbios pptable if in sriov mode.
v2:
clean up smu driver code in sriov code path
Signed-off-by: Kevin Wang
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 102 --
1 file changed, 70 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index a421ba85bd6d..3765624d8fd6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -85,6 +85,10 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
const struct common_firmware_header *header;
struct amdgpu_firmware_info *ucode = NULL;
+ /* doesn't need to load smu firmware in IOV mode */
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
switch (adev->asic_type) {
case CHIP_ALDEBARAN:
chip_name = "aldebaran";
@@ -268,52 +272,86 @@ static int smu_v13_0_set_pptable_v2_1(struct smu_context
*smu, void **table,
return 0;
}
-int smu_v13_0_setup_pptable(struct smu_context *smu)
+static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void
**table, uint32_t *size)
{
struct amdgpu_device *adev = smu->adev;
- const struct smc_firmware_header_v1_0 *hdr;
- int ret, index;
- uint32_t size = 0;
uint16_t atom_table_size;
uint8_t frev, crev;
- void *table;
- uint16_t version_major, version_minor;
+ int ret, index;
+ dev_info(adev->dev, "use vbios provided pptable\n");
+ index =
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ powerplayinfo);
- if (amdgpu_smu_pptable_id >= 0) {
- smu->smu_table.boot_values.pp_table_id = amdgpu_smu_pptable_id;
- dev_info(adev->dev, "override pptable id %d\n",
amdgpu_smu_pptable_id);
- }
+ ret = amdgpu_atombios_get_data_table(adev, index, _table_size,
, ,
+(uint8_t **));
+ if (ret)
+ return ret;
+
+ if (size)
+ *size = atom_table_size;
+
+ return 0;
+}
+
+static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void
**table, uint32_t *size,
+ uint32_t pptable_id)
+{
+ const struct smc_firmware_header_v1_0 *hdr;
+ struct amdgpu_device *adev = smu->adev;
+ uint16_t version_major, version_minor;
+ int ret;
hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
+ if (!hdr)
+ return -EINVAL;
+
+ dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
+
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
- if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
- dev_info(adev->dev, "use driver provided pptable %d\n",
smu->smu_table.boot_values.pp_table_id);
- switch (version_minor) {
- case 1:
- ret = smu_v13_0_set_pptable_v2_1(smu, , ,
-
smu->smu_table.boot_values.pp_table_id);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- if (ret)
- return ret;
+ if (version_major != 2) {
+ dev_err(adev->dev, "Unsupported smu firwmare version %d.%d\n",
+ version_major, version_minor);
+ return -EINVAL;
+ }
- } else {
- dev_info(adev->dev, "use vbios provided pptable\n");
- index =
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
- powerplayinfo);
+ switch (version_minor) {
+ case 1:
+ ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
- ret = amdgpu_atombios_get_data_table(adev, index,
_table_size, , ,
-(uint8_t **));
- if (ret)
- return ret;
- size = atom_table_size;
+ return 0;
+}
+
+int smu_v13_0_setup_pptable(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t size = 0, pptable_id = 0;
+ void *table;
+ int ret = 0;
+
+ /* override pptable_id from driver parameter */
+ if (amdgpu_smu_pptable_id >= 0) {
+
[PATCH v2 1/2] drm/amd/pm: skip to load smu microcode on sriov for aldebaran
v1:
1. skip to load smu firmware in sriov mode for aldebaran chip
2. using vbios pptable if in sriov mode.
v2:
clean up smu driver code in sriov code path
Signed-off-by: Kevin Wang
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 41 +++
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index a421ba85bd6d..ebc081dc01cd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -85,6 +85,10 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
const struct common_firmware_header *header;
struct amdgpu_firmware_info *ucode = NULL;
+ /* doesn't need to load smu firmware in IOV mode */
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
switch (adev->asic_type) {
case CHIP_ALDEBARAN:
chip_name = "aldebaran";
@@ -273,34 +277,38 @@ int smu_v13_0_setup_pptable(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev;
const struct smc_firmware_header_v1_0 *hdr;
int ret, index;
- uint32_t size = 0;
+ uint32_t size = 0, pp_table_id;
uint16_t atom_table_size;
uint8_t frev, crev;
void *table;
uint16_t version_major, version_minor;
+ if (!amdgpu_sriov_vf(adev)) {
+ if (amdgpu_smu_pptable_id >= 0) {
+ pp_table_id = amdgpu_smu_pptable_id;
+ dev_info(adev->dev, "override pptable id %d\n",
pp_table_id);
+ } else {
+ pp_table_id = smu->smu_table.boot_values.pp_table_id;
+ dev_info(adev->dev, "use driver provided pptable %d\n",
pp_table_id);
+ }
- if (amdgpu_smu_pptable_id >= 0) {
- smu->smu_table.boot_values.pp_table_id = amdgpu_smu_pptable_id;
- dev_info(adev->dev, "override pptable id %d\n",
amdgpu_smu_pptable_id);
- }
+ hdr = (const struct smc_firmware_header_v1_0 *)
adev->pm.fw->data;
+ version_major = le16_to_cpu(hdr->header.header_version_major);
+ version_minor = le16_to_cpu(hdr->header.header_version_minor);
+ if (version_major != 2) {
+ dev_err(adev->dev, "Unsupported smu firwmare version
%d.%d\n",
+version_major, version_minor);
+ return -EINVAL;
+ }
- hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
- version_major = le16_to_cpu(hdr->header.header_version_major);
- version_minor = le16_to_cpu(hdr->header.header_version_minor);
- if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
- dev_info(adev->dev, "use driver provided pptable %d\n",
smu->smu_table.boot_values.pp_table_id);
switch (version_minor) {
case 1:
- ret = smu_v13_0_set_pptable_v2_1(smu, , ,
-
smu->smu_table.boot_values.pp_table_id);
+ ret = smu_v13_0_set_pptable_v2_1(smu, , ,
pp_table_id);
break;
default:
ret = -EINVAL;
break;
}
- if (ret)
- return ret;
} else {
dev_info(adev->dev, "use vbios provided pptable\n");
@@ -309,11 +317,12 @@ int smu_v13_0_setup_pptable(struct smu_context *smu)
ret = amdgpu_atombios_get_data_table(adev, index,
_table_size, , ,
(uint8_t **));
- if (ret)
- return ret;
size = atom_table_size;
}
+ if (ret)
+ return ret;
+
if (!smu->smu_table.power_play_table)
smu->smu_table.power_play_table = table;
if (!smu->smu_table.power_play_table_size)
--
2.25.1
[PATCH v2 2/2] drm/amd/pm: change return value in aldebaran_get_power_limit()
v1:
1. change return value to avoid smu driver probe fails when FEATURE_PPT is
not enabled.
2. if FEATURE_PPT is not enabled, set power limit value to 0.
v2:
instead dev_err with dev_warn
Signed-off-by: Kevin Wang
---
.../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 97cc6fb9b22b..a9f1a2dfbb51 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1194,8 +1194,19 @@ static int aldebaran_get_power_limit(struct smu_context
*smu,
uint32_t power_limit = 0;
int ret;
- if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
- return -EINVAL;
+ if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
+ if (current_power_limit)
+ *current_power_limit = 0;
+ if (default_power_limit)
+ *default_power_limit = 0;
+ if (max_power_limit)
+ *max_power_limit = 0;
+
+ dev_warn(smu->adev->dev,
+ "the PPT feature is not enabled, set power limit to 0");
+
+ return 0;
+ }
/* Valid power data is available only from primary die.
* For secondary die show the value as 0.
--
2.25.1
[PATCH 4/5] drm/amd/pm: change return value in aldebaran_get_power_limit()
1. change return value to avoid smu driver probe fails when FEATURE_PPT is
not enabled.
2. if FEATURE_PPT is not enabled, set power limit value to 0.
Signed-off-by: Kevin Wang
---
.../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index fd04391364ac..e00ac43515bb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1194,8 +1194,19 @@ static int aldebaran_get_power_limit(struct smu_context
*smu,
uint32_t power_limit = 0;
int ret;
- if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
- return -EINVAL;
+ if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
+ if (current_power_limit)
+ *current_power_limit = 0;
+ if (default_power_limit)
+ *default_power_limit = 0;
+ if (max_power_limit)
+ *max_power_limit = 0;
+
+ dev_err(smu->adev->dev,
+ "the PPT feature is not enabled, set power limit to 0");
+
+ return 0;
+ }
/* Valid power data is available only from primary die.
* For secondary die show the value as 0.
--
2.25.1
[PATCH 5/5] drm/amd/pm: change pp_dpm_sclk/mclk/fclk attribute is RO for aldebaran
the following clock is only support voltage DPM, change attribute to RO:
1. pp_dpm_sclk
2. pp_dpm_mclk
3. pp_dpm_fclk
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 769f58d5ae1a..f894b34418df 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2094,14 +2094,19 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
*states = ATTR_STATE_UNSUPPORTED;
}
- if (asic_type == CHIP_ARCTURUS) {
- /* Arcturus does not support standalone mclk/socclk/fclk level
setting */
+ switch (asic_type) {
+ case CHIP_ARCTURUS:
+ case CHIP_ALDEBARAN:
+ /* the Mi series card does not support standalone
mclk/socclk/fclk level setting */
if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
DEVICE_ATTR_IS(pp_dpm_socclk) ||
DEVICE_ATTR_IS(pp_dpm_fclk)) {
dev_attr->attr.mode &= ~S_IWUGO;
dev_attr->store = NULL;
}
+ break;
+ default:
+ break;
}
if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
--
2.25.1
[PATCH 3/5] drm/amd/pm: change smu msg's attribute to allow working under sriov
the following message is allowed in sriov mode: 1. GetEnabledSmuFeaturesLow 2. GetEnabledSmuFeaturesHigh Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 97cc6fb9b22b..fd04391364ac 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -90,8 +90,8 @@ static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures,0), MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), - MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow,0), - MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0), + MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow,1), + MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,1), MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh,0), -- 2.25.1
[PATCH 2/5] drm/amd/pm: skip to load smu microcode on sriov for aldebaran
1. skip to load smu firmware in sriov mode for aldebaran chip
2. using vbios pptable if in sriov mode.
Signed-off-by: Kevin Wang
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 66 ++-
1 file changed, 36 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index a421ba85bd6d..a0ca7e7a0903 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -85,6 +85,10 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
const struct common_firmware_header *header;
struct amdgpu_firmware_info *ucode = NULL;
+ /* doesn't need to load smu firmware in IOV mode */
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
switch (adev->asic_type) {
case CHIP_ALDEBARAN:
chip_name = "aldebaran";
@@ -279,41 +283,43 @@ int smu_v13_0_setup_pptable(struct smu_context *smu)
void *table;
uint16_t version_major, version_minor;
+ if (!amdgpu_sriov_vf(adev)) {
+ if (amdgpu_smu_pptable_id >= 0) {
+ smu->smu_table.boot_values.pp_table_id =
amdgpu_smu_pptable_id;
+ dev_info(adev->dev, "override pptable id %d\n",
amdgpu_smu_pptable_id);
+ }
- if (amdgpu_smu_pptable_id >= 0) {
- smu->smu_table.boot_values.pp_table_id = amdgpu_smu_pptable_id;
- dev_info(adev->dev, "override pptable id %d\n",
amdgpu_smu_pptable_id);
- }
-
- hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
- version_major = le16_to_cpu(hdr->header.header_version_major);
- version_minor = le16_to_cpu(hdr->header.header_version_minor);
- if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
- dev_info(adev->dev, "use driver provided pptable %d\n",
smu->smu_table.boot_values.pp_table_id);
- switch (version_minor) {
- case 1:
- ret = smu_v13_0_set_pptable_v2_1(smu, , ,
-
smu->smu_table.boot_values.pp_table_id);
- break;
- default:
- ret = -EINVAL;
- break;
+ hdr = (const struct smc_firmware_header_v1_0 *)
adev->pm.fw->data;
+ version_major = le16_to_cpu(hdr->header.header_version_major);
+ version_minor = le16_to_cpu(hdr->header.header_version_minor);
+ if (version_major == 2 &&
smu->smu_table.boot_values.pp_table_id > 0) {
+ dev_info(adev->dev, "use driver provided pptable %d\n",
smu->smu_table.boot_values.pp_table_id);
+ switch (version_minor) {
+ case 1:
+ ret = smu_v13_0_set_pptable_v2_1(smu, ,
,
+
smu->smu_table.boot_values.pp_table_id);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ if (ret)
+ return ret;
+ goto out;
}
- if (ret)
- return ret;
+ }
- } else {
- dev_info(adev->dev, "use vbios provided pptable\n");
- index =
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
- powerplayinfo);
+ dev_info(adev->dev, "use vbios provided pptable\n");
+ index =
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ powerplayinfo);
- ret = amdgpu_atombios_get_data_table(adev, index,
_table_size, , ,
-(uint8_t **));
- if (ret)
- return ret;
- size = atom_table_size;
- }
+ ret = amdgpu_atombios_get_data_table(adev, index, _table_size,
, ,
+(uint8_t **));
+ if (ret)
+ return ret;
+ size = atom_table_size;
+out:
if (!smu->smu_table.power_play_table)
smu->smu_table.power_play_table = table;
if (!smu->smu_table.power_play_table_size)
--
2.25.1
[PATCH 1/5] drm/amd/pm: correct DPM_XGMI/VCN_DPM feature name
the following feature is wrong, it will cause sysnode of pp_features show error:
1. DPM_XGMI
2. VCN_DPM
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 -
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c| 16
.../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 4 ++--
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 1d3765b873df..3fdee6cf01ed 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -297,7 +297,6 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(DS_FCLK), \
__SMU_DUMMY_MAP(DS_MP1CLK), \
__SMU_DUMMY_MAP(DS_MP0CLK), \
- __SMU_DUMMY_MAP(XGMI), \
__SMU_DUMMY_MAP(XGMI_PER_LINK_PWR_DWN), \
__SMU_DUMMY_MAP(DPM_GFX_PACE), \
__SMU_DUMMY_MAP(MEM_VDDCI_SCALING), \
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 6ec8492f71f5..b4d98465bb36 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -163,14 +163,14 @@ static const struct cmn2asic_mapping
arcturus_feature_mask_map[SMU_FEATURE_COUNT
FEA_MAP(DPM_SOCCLK),
FEA_MAP(DPM_FCLK),
FEA_MAP(DPM_MP0CLK),
- ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
+ FEA_MAP(DPM_XGMI),
FEA_MAP(DS_GFXCLK),
FEA_MAP(DS_SOCCLK),
FEA_MAP(DS_LCLK),
FEA_MAP(DS_FCLK),
FEA_MAP(DS_UCLK),
FEA_MAP(GFX_ULV),
- ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
+ ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
FEA_MAP(RSMU_SMN_CG),
FEA_MAP(WAFL_CG),
FEA_MAP(PPT),
@@ -721,13 +721,13 @@ static int arcturus_get_current_clk_freq_by_table(struct
smu_context *smu,
member_type = METRICS_AVERAGE_SOCCLK;
break;
case PPCLK_VCLK:
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
member_type = METRICS_CURR_VCLK;
else
member_type = METRICS_AVERAGE_VCLK;
break;
case PPCLK_DCLK:
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
member_type = METRICS_CURR_DCLK;
else
member_type = METRICS_AVERAGE_DCLK;
@@ -1916,16 +1916,16 @@ static int arcturus_dpm_set_vcn_enable(struct
smu_context *smu, bool enable)
int ret = 0;
if (enable) {
- if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
- ret = smu_cmn_feature_set_enabled(smu,
SMU_FEATURE_VCN_PG_BIT, 1);
+ if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu,
SMU_FEATURE_VCN_DPM_BIT, 1);
if (ret) {
dev_err(smu->adev->dev, "[EnableVCNDPM]
failed!\n");
return ret;
}
}
} else {
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
- ret = smu_cmn_feature_set_enabled(smu,
SMU_FEATURE_VCN_PG_BIT, 0);
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu,
SMU_FEATURE_VCN_DPM_BIT, 0);
if (ret) {
dev_err(smu->adev->dev, "[DisableVCNDPM]
failed!\n");
return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 856eeaf293b8..97cc6fb9b22b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -156,14 +156,14 @@ static const struct cmn2asic_mapping
aldebaran_feature_mask_map[SMU_FEATURE_COUN
ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT,
FEATURE_DPM_SOCCLK_BIT),
ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT,
FEATURE_DPM_FCLK_BIT),
ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT,
FEATURE_DPM_LCLK_BIT),
- ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_BIT,
FEATURE_DPM_XGMI_BIT),
+ ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT,
[PATCH] drm/amd/pm: correct aldebaran smu feature mapping FEATURE_DATA_CALCULATIONS
correct smu feature mapping: FEATURE_DATA_CALCULATIONS
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 3 +--
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 1d3765b873df..6239c30fcd5f 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -282,6 +282,7 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(TDC), \
__SMU_DUMMY_MAP(THERMAL), \
__SMU_DUMMY_MAP(GFX_PER_CU_CG), \
+ __SMU_DUMMY_MAP(DATA_CALCULATIONS), \
__SMU_DUMMY_MAP(RM),\
__SMU_DUMMY_MAP(DS_DCEFCLK),\
__SMU_DUMMY_MAP(ACDC), \
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 856eeaf293b8..4af602d6ee02 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -64,7 +64,6 @@
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_UCLK_BIT)| \
FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
@@ -150,7 +149,7 @@ static const struct cmn2asic_mapping
aldebaran_clk_map[SMU_CLK_COUNT] = {
};
static const struct cmn2asic_mapping
aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
- ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_PREFETCHER_BIT,
FEATURE_DATA_CALCULATIONS),
+ ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT,
FEATURE_DATA_CALCULATIONS),
ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT,
FEATURE_DPM_GFXCLK_BIT),
ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT,
FEATURE_DPM_UCLK_BIT),
ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT,
FEATURE_DPM_SOCCLK_BIT),
--
2.25.1
[PATCH v3 2/3] drm/amdgpu/ttm: replace duplicate code with exiting function
using exiting function to replace duplicate code blocks in
amdgpu_ttm_vram_write().
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2aa2eb5de37a..f4ff3c9350b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2207,7 +2207,6 @@ static ssize_t amdgpu_ttm_vram_write(struct file *f,
const char __user *buf,
return -ENXIO;
while (size) {
- unsigned long flags;
uint32_t value;
if (*pos >= adev->gmc.mc_vram_size)
@@ -2217,11 +2216,7 @@ static ssize_t amdgpu_ttm_vram_write(struct file *f,
const char __user *buf,
if (r)
return r;
- spin_lock_irqsave(>mmio_idx_lock, flags);
- WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x8000);
- WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
- WREG32_NO_KIQ(mmMM_DATA, value);
- spin_unlock_irqrestore(>mmio_idx_lock, flags);
+ amdgpu_device_mm_access(adev, *pos, , 4, true);
result += 4;
buf += 4;
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 1/3] drm/amdgpu: split amdgpu_device_access_vram() into two small parts
split amdgpu_device_access_vram()
1. amdgpu_device_mm_access(): using MM_INDEX/MM_DATA to access vram
2. amdgpu_device_aper_access(): using vram aperature to access vram (option)
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 98 --
2 files changed, 79 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 61a0897e984a..54cf647bd018 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1109,8 +1109,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
void amdgpu_device_fini(struct amdgpu_device *adev);
int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
+void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write);
+size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write);
+
void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
- uint32_t *buf, size_t size, bool write);
+ void *buf, size_t size, bool write);
uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
uint32_t reg, uint32_t acc_flags);
void amdgpu_device_wreg(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index eb1f3f42e00b..37fa199be8b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -285,7 +285,7 @@ bool amdgpu_device_supports_smart_shift(struct drm_device
*dev)
*/
/**
- * amdgpu_device_vram_access - read/write a buffer in vram
+ * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
*
* @adev: amdgpu_device pointer
* @pos: offset of the buffer in vram
@@ -293,19 +293,60 @@ bool amdgpu_device_supports_smart_shift(struct drm_device
*dev)
* @size: read/write size, sizeof(@buf) must > @size
* @write: true - write to vram, otherwise - read from vram
*/
-void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
- uint32_t *buf, size_t size, bool write)
+void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write)
{
unsigned long flags;
- uint32_t hi = ~0;
+ uint32_t hi = ~0, tmp = 0;
+ uint32_t *data = buf;
uint64_t last;
+ BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
+
+ spin_lock_irqsave(>mmio_idx_lock, flags);
+ for (last = pos + size; pos < last; pos += 4) {
+ tmp = pos >> 31;
+ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x8000);
+ if (tmp != hi) {
+ WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
+ hi = tmp;
+ }
+ if (write)
+ WREG32_NO_KIQ(mmMM_DATA, *data++);
+ else
+ *data++ = RREG32_NO_KIQ(mmMM_DATA);
+ }
+
+ spin_unlock_irqrestore(>mmio_idx_lock, flags);
+}
+
+/**
+ * amdgpu_device_vram_access - access vram by vram aperature
+ *
+ * @adev: amdgpu_device pointer
+ * @pos: offset of the buffer in vram
+ * @buf: virtual address of the buffer in system memory
+ * @size: read/write size, sizeof(@buf) must > @size
+ * @write: true - write to vram, otherwise - read from vram
+ *
+ * The return value means how many bytes have been transferred.
+ */
+size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write)
+{
#ifdef CONFIG_64BIT
+ void __iomem *addr;
+ size_t count = 0;
+ uint64_t last;
+
+ if (!adev->mman.aper_base_kaddr)
+ return 0;
+
last = min(pos + size, adev->gmc.visible_vram_size);
if (last > pos) {
- void __iomem *addr = adev->mman.aper_base_kaddr + pos;
- size_t count = last - pos;
+ addr = adev->mman.aper_base_kaddr + pos;
+ count = last - pos;
if (write) {
memcpy_toio(addr, buf, count);
@@ -317,30 +358,37 @@ void amdgpu_device_vram_access(struct amdgpu_device
*adev, loff_t pos,
memcpy_fromio(buf, addr, count);
}
- if (count == size)
- return;
-
- pos += count;
- buf += count / 4;
- size -= count;
}
+
+ return count;
+#else
+ return 0;
#endif
+}
- spin_lock_irqsave(>mmio_idx_lock, flags);
- for (last = pos + size; pos < last; pos += 4) {
- uint32_t tmp = pos >> 31;
+/**
+ * amdgpu_
[PATCH v3 3/3] drm/amdgpu/ttm: optimize vram access in amdgpu_ttm_access_memory()
1. using vram aper to access vram if possible
2. avoid MM_INDEX/MM_DATA is not working when mmio protect feature is
enabled.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 84 ++---
1 file changed, 49 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f4ff3c9350b3..0aacdafd1ef6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1407,6 +1407,41 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct
ttm_buffer_object *bo,
return ttm_bo_eviction_valuable(bo, place);
}
+static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
+ void *buf, size_t size, bool write)
+{
+ while (size) {
+ uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
+ uint64_t bytes = 4 - (pos & 0x3);
+ uint32_t shift = (pos & 0x3) * 8;
+ uint32_t mask = 0x << shift;
+ uint32_t value = 0;
+
+ if (size < bytes) {
+ mask &= 0x >> (bytes - size) * 8;
+ bytes = size;
+ }
+
+ if (mask != 0x) {
+ amdgpu_device_mm_access(adev, aligned_pos, , 4,
false);
+ if (write) {
+ value &= ~mask;
+ value |= (*(uint32_t *)buf << shift) & mask;
+ amdgpu_device_mm_access(adev, aligned_pos,
, 4, true);
+ } else {
+ value = (value & mask) >> shift;
+ memcpy(buf, , bytes);
+ }
+ } else {
+ amdgpu_device_mm_access(adev, aligned_pos, buf, 4,
write);
+ }
+
+ pos += bytes;
+ buf += bytes;
+ size -= bytes;
+ }
+}
+
/**
* amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
*
@@ -1426,50 +1461,29 @@ static int amdgpu_ttm_access_memory(struct
ttm_buffer_object *bo,
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
struct amdgpu_res_cursor cursor;
- unsigned long flags;
- uint32_t value = 0;
int ret = 0;
if (bo->mem.mem_type != TTM_PL_VRAM)
return -EIO;
amdgpu_res_first(>mem, offset, len, );
- while (cursor.remaining) {
- uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
- uint64_t bytes = 4 - (cursor.start & 3);
- uint32_t shift = (cursor.start & 3) * 8;
- uint32_t mask = 0x << shift;
- if (cursor.size < bytes) {
- mask &= 0x >> (bytes - cursor.size) * 8;
- bytes = cursor.size;
- }
-
- if (mask != 0x) {
- spin_lock_irqsave(>mmio_idx_lock, flags);
- WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) |
0x8000);
- WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
- value = RREG32_NO_KIQ(mmMM_DATA);
- if (write) {
- value &= ~mask;
- value |= (*(uint32_t *)buf << shift) & mask;
- WREG32_NO_KIQ(mmMM_DATA, value);
- }
- spin_unlock_irqrestore(>mmio_idx_lock, flags);
- if (!write) {
- value = (value & mask) >> shift;
- memcpy(buf, , bytes);
- }
- } else {
- bytes = cursor.size & ~0x3ULL;
- amdgpu_device_vram_access(adev, cursor.start,
- (uint32_t *)buf, bytes,
- write);
+ while (cursor.remaining) {
+ size_t count, size = cursor.size;
+ loff_t pos = cursor.start;
+
+ count = amdgpu_device_aper_access(adev, pos, buf, size, write);
+ size -= count;
+ if (size) {
+ /* using MM to access rest vram and handle un-aligned
address */
+ pos += count;
+ buf += count;
+ amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
}
- ret += bytes;
- buf = (uint8_t *)buf + bytes;
- amdgpu_res_next(, bytes);
+ ret += cursor.s
[RFC PATCH v2 2/3] drm/amdgpu/ttm: replace duplicate code with exiting function
using exiting function to replace duplicate code blocks in
amdgpu_ttm_vram_write().
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2aa2eb5de37a..f4ff3c9350b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2207,7 +2207,6 @@ static ssize_t amdgpu_ttm_vram_write(struct file *f,
const char __user *buf,
return -ENXIO;
while (size) {
- unsigned long flags;
uint32_t value;
if (*pos >= adev->gmc.mc_vram_size)
@@ -2217,11 +2216,7 @@ static ssize_t amdgpu_ttm_vram_write(struct file *f,
const char __user *buf,
if (r)
return r;
- spin_lock_irqsave(>mmio_idx_lock, flags);
- WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x8000);
- WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
- WREG32_NO_KIQ(mmMM_DATA, value);
- spin_unlock_irqrestore(>mmio_idx_lock, flags);
+ amdgpu_device_mm_access(adev, *pos, , 4, true);
result += 4;
buf += 4;
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[RFC PATCH v2 1/3] drm/amdgpu: split amdgpu_device_access_vram() into two small parts
split amdgpu_device_access_vram()
1. amdgpu_device_mm_access(): using MM_INDEX/MM_DATA to access vram
2. amdgpu_device_aper_access(): using vram aperature to access vram (option)
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 98 --
2 files changed, 79 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 61a0897e984a..54cf647bd018 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1109,8 +1109,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
void amdgpu_device_fini(struct amdgpu_device *adev);
int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
+void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write);
+size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write);
+
void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
- uint32_t *buf, size_t size, bool write);
+ void *buf, size_t size, bool write);
uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
uint32_t reg, uint32_t acc_flags);
void amdgpu_device_wreg(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index eb1f3f42e00b..37fa199be8b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -285,7 +285,7 @@ bool amdgpu_device_supports_smart_shift(struct drm_device
*dev)
*/
/**
- * amdgpu_device_vram_access - read/write a buffer in vram
+ * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
*
* @adev: amdgpu_device pointer
* @pos: offset of the buffer in vram
@@ -293,19 +293,60 @@ bool amdgpu_device_supports_smart_shift(struct drm_device
*dev)
* @size: read/write size, sizeof(@buf) must > @size
* @write: true - write to vram, otherwise - read from vram
*/
-void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
- uint32_t *buf, size_t size, bool write)
+void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write)
{
unsigned long flags;
- uint32_t hi = ~0;
+ uint32_t hi = ~0, tmp = 0;
+ uint32_t *data = buf;
uint64_t last;
+ BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
+
+ spin_lock_irqsave(>mmio_idx_lock, flags);
+ for (last = pos + size; pos < last; pos += 4) {
+ tmp = pos >> 31;
+ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x8000);
+ if (tmp != hi) {
+ WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
+ hi = tmp;
+ }
+ if (write)
+ WREG32_NO_KIQ(mmMM_DATA, *data++);
+ else
+ *data++ = RREG32_NO_KIQ(mmMM_DATA);
+ }
+
+ spin_unlock_irqrestore(>mmio_idx_lock, flags);
+}
+
+/**
+ * amdgpu_device_vram_access - access vram by vram aperature
+ *
+ * @adev: amdgpu_device pointer
+ * @pos: offset of the buffer in vram
+ * @buf: virtual address of the buffer in system memory
+ * @size: read/write size, sizeof(@buf) must > @size
+ * @write: true - write to vram, otherwise - read from vram
+ *
+ * The return value means how many bytes have been transferred.
+ */
+size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write)
+{
#ifdef CONFIG_64BIT
+ void __iomem *addr;
+ size_t count = 0;
+ uint64_t last;
+
+ if (!adev->mman.aper_base_kaddr)
+ return 0;
+
last = min(pos + size, adev->gmc.visible_vram_size);
if (last > pos) {
- void __iomem *addr = adev->mman.aper_base_kaddr + pos;
- size_t count = last - pos;
+ addr = adev->mman.aper_base_kaddr + pos;
+ count = last - pos;
if (write) {
memcpy_toio(addr, buf, count);
@@ -317,30 +358,37 @@ void amdgpu_device_vram_access(struct amdgpu_device
*adev, loff_t pos,
memcpy_fromio(buf, addr, count);
}
- if (count == size)
- return;
-
- pos += count;
- buf += count / 4;
- size -= count;
}
+
+ return count;
+#else
+ return 0;
#endif
+}
- spin_lock_irqsave(>mmio_idx_lock, flags);
- for (last = pos + size; pos < last; pos += 4) {
- uint32_t tmp = pos >> 31;
+/**
+ * amdgpu_
[RFC PATCH v2 3/3] drm/amdgpu/ttm: optimize vram access in amdgpu_ttm_access_memory()
1. using vram aper to access vram if possible
2. avoid MM_INDEX/MM_DATA is not working when mmio protect feature is
enabled.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 91 +++--
1 file changed, 54 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f4ff3c9350b3..62ea5089b4f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1407,6 +1407,56 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct
ttm_buffer_object *bo,
return ttm_bo_eviction_valuable(bo, place);
}
+static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
+ void *buf, size_t size, bool write)
+{
+ while (size) {
+ uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
+ uint64_t bytes = 4 - (pos & 0x3);
+ uint32_t shift = (pos & 0x3) * 8;
+ uint32_t mask = 0x << shift;
+ uint32_t value = 0;
+
+ if (size < bytes) {
+ mask &= 0x >> (bytes - size) * 8;
+ bytes = size;
+ }
+
+ if (mask != 0x) {
+ amdgpu_device_mm_access(adev, aligned_pos, , 4,
false);
+ if (write) {
+ value &= ~mask;
+ value |= (*(uint32_t *)buf << shift) & mask;
+ amdgpu_device_mm_access(adev, aligned_pos,
, 4, true);
+ } else {
+ value = (value & mask) >> shift;
+ memcpy(buf, , bytes);
+ }
+ } else {
+ amdgpu_device_mm_access(adev, aligned_pos, buf, 4,
write);
+ }
+
+ pos += bytes;
+ buf += bytes;
+ size -= bytes;
+ }
+}
+
+static void amdgpu_ttm_vram_access(struct amdgpu_device *adev, loff_t pos,
+ void *buf, size_t size, bool write)
+{
+ size_t count;
+
+ count = amdgpu_device_aper_access(adev, pos, buf, size, write);
+ size -= count;
+ if (size) {
+ /* using MM to access rest vram and handle un-aligned address */
+ pos += count;
+ buf += count;
+ amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
+ }
+}
+
/**
* amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
*
@@ -1426,8 +1476,6 @@ static int amdgpu_ttm_access_memory(struct
ttm_buffer_object *bo,
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
struct amdgpu_res_cursor cursor;
- unsigned long flags;
- uint32_t value = 0;
int ret = 0;
if (bo->mem.mem_type != TTM_PL_VRAM)
@@ -1435,41 +1483,10 @@ static int amdgpu_ttm_access_memory(struct
ttm_buffer_object *bo,
amdgpu_res_first(>mem, offset, len, );
while (cursor.remaining) {
- uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
- uint64_t bytes = 4 - (cursor.start & 3);
- uint32_t shift = (cursor.start & 3) * 8;
- uint32_t mask = 0x << shift;
-
- if (cursor.size < bytes) {
- mask &= 0x >> (bytes - cursor.size) * 8;
- bytes = cursor.size;
- }
-
- if (mask != 0x) {
- spin_lock_irqsave(>mmio_idx_lock, flags);
- WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) |
0x8000);
- WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
- value = RREG32_NO_KIQ(mmMM_DATA);
- if (write) {
- value &= ~mask;
- value |= (*(uint32_t *)buf << shift) & mask;
- WREG32_NO_KIQ(mmMM_DATA, value);
- }
- spin_unlock_irqrestore(>mmio_idx_lock, flags);
- if (!write) {
- value = (value & mask) >> shift;
- memcpy(buf, , bytes);
- }
- } else {
- bytes = cursor.size & ~0x3ULL;
- amdgpu_device_vram_access(adev, cursor.start,
- (uint32_t *)buf, bytes,
- write);
- }
-
- ret += bytes;
- buf = (uint8_t *)buf + bytes;
- amdgpu_res_next
[RFC PATCH 3/3] drm/amdgpu/ttm: optimize vram access in amdgpu_ttm_access_memory()
1. using vram aper to access vram if possible
2. avoid MM_INDEX/MM_DATA is not working when mmio protect feature is
enabled.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 95 +++--
1 file changed, 58 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2c98e4345ad3..bf2d50a918e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1407,6 +1407,60 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct
ttm_buffer_object *bo,
return ttm_bo_eviction_valuable(bo, place);
}
+static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
+ void *buf, size_t size, bool write)
+{
+ while (size) {
+ uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
+ uint64_t bytes = 4 - (pos & 0x3);
+ uint32_t shift = (pos & 0x3) * 8;
+ uint32_t mask = 0x << shift;
+ uint32_t value = 0;
+
+ if (size < bytes) {
+ mask &= 0x >> (bytes - size) * 8;
+ bytes = size;
+ }
+
+ if (mask != 0x) {
+ amdgpu_device_mm_access(adev, aligned_pos, , 4,
false);
+ if (write) {
+ value &= ~mask;
+ value |= (*(uint32_t *)buf << shift) & mask;
+ amdgpu_device_mm_access(adev, aligned_pos,
, 4, true);
+ } else {
+ value = (value & mask) >> shift;
+ memcpy(buf, , bytes);
+ }
+ } else {
+ amdgpu_device_mm_access(adev, aligned_pos, buf, 4,
write);
+ }
+
+ pos += bytes;
+ buf += bytes;
+ size -= bytes;
+ }
+}
+
+static void amdgpu_ttm_vram_access(struct amdgpu_device *adev, loff_t pos,
+ void *buf, size_t size, bool write)
+{
+ size_t count;
+
+ count = amdgpu_device_aper_access(adev, pos, buf, size, write);
+ if (count == size)
+ return;
+
+ if (count && count < size) {
+ pos += count;
+ buf += count;
+ size -= count;
+ }
+
+ if (size)
+ amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
+}
+
/**
* amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
*
@@ -1426,8 +1480,6 @@ static int amdgpu_ttm_access_memory(struct
ttm_buffer_object *bo,
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
struct amdgpu_res_cursor cursor;
- unsigned long flags;
- uint32_t value = 0;
int ret = 0;
if (bo->mem.mem_type != TTM_PL_VRAM)
@@ -1435,41 +1487,10 @@ static int amdgpu_ttm_access_memory(struct
ttm_buffer_object *bo,
amdgpu_res_first(>mem, offset, len, );
while (cursor.remaining) {
- uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
- uint64_t bytes = 4 - (cursor.start & 3);
- uint32_t shift = (cursor.start & 3) * 8;
- uint32_t mask = 0x << shift;
-
- if (cursor.size < bytes) {
- mask &= 0x >> (bytes - cursor.size) * 8;
- bytes = cursor.size;
- }
-
- if (mask != 0x) {
- spin_lock_irqsave(>mmio_idx_lock, flags);
- WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) |
0x8000);
- WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
- value = RREG32_NO_KIQ(mmMM_DATA);
- if (write) {
- value &= ~mask;
- value |= (*(uint32_t *)buf << shift) & mask;
- WREG32_NO_KIQ(mmMM_DATA, value);
- }
- spin_unlock_irqrestore(>mmio_idx_lock, flags);
- if (!write) {
- value = (value & mask) >> shift;
- memcpy(buf, , bytes);
- }
- } else {
- bytes = cursor.size & ~0x3ULL;
- amdgpu_device_vram_access(adev, cursor.start,
- (uint32_t *)buf, bytes,
- write);
- }
-
- ret += bytes;
- buf = (uint8_t *)buf + bytes;
-
[RFC PATCH 1/3] drm/amdgpu: split amdgpu_device_access_vram() into two small parts
split amdgpu_device_access_vram()
1. amdgpu_device_mm_access(): using MM_INDEX/MM_DATA to access vram
2. amdgpu_device_aper_access(): using vram aperature to access vram (option)
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 101 -
2 files changed, 82 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d14b4968a026..dd2fc89f5c16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1102,8 +1102,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
void amdgpu_device_fini(struct amdgpu_device *adev);
int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
+void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write);
+size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write);
+
void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
- uint32_t *buf, size_t size, bool write);
+ void *buf, size_t size, bool write);
uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
uint32_t reg, uint32_t acc_flags);
void amdgpu_device_wreg(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index eb1f3f42e00b..4a9a7e4d3908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -285,7 +285,7 @@ bool amdgpu_device_supports_smart_shift(struct drm_device
*dev)
*/
/**
- * amdgpu_device_vram_access - read/write a buffer in vram
+ * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
*
* @adev: amdgpu_device pointer
* @pos: offset of the buffer in vram
@@ -293,19 +293,58 @@ bool amdgpu_device_supports_smart_shift(struct drm_device
*dev)
* @size: read/write size, sizeof(@buf) must > @size
* @write: true - write to vram, otherwise - read from vram
*/
-void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
- uint32_t *buf, size_t size, bool write)
+void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write)
{
unsigned long flags;
- uint32_t hi = ~0;
+ uint32_t hi = ~0, tmp = 0;
+ uint32_t *data = buf;
uint64_t last;
+ BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
+
+ spin_lock_irqsave(>mmio_idx_lock, flags);
+ for (last = pos + size; pos < last; pos += 4) {
+ tmp = pos >> 31;
+
+ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x8000);
+ if (tmp != hi) {
+ WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
+ hi = tmp;
+ }
+ if (write)
+ WREG32_NO_KIQ(mmMM_DATA, *data++);
+ else
+ *data++ = RREG32_NO_KIQ(mmMM_DATA);
+ }
+ spin_unlock_irqrestore(>mmio_idx_lock, flags);
+}
+
+/**
+ * amdgpu_device_vram_access - access vram by vram aperature
+ *
+ * @adev: amdgpu_device pointer
+ * @pos: offset of the buffer in vram
+ * @buf: virtual address of the buffer in system memory
+ * @size: read/write size, sizeof(@buf) must > @size
+ * @write: true - write to vram, otherwise - read from vram
+ */
+size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
+void *buf, size_t size, bool write)
+{
#ifdef CONFIG_64BIT
+ void __iomem *addr;
+ size_t count = 0;
+ uint64_t last;
+
+ if (!adev->mman.aper_base_kaddr)
+ return 0;
+
last = min(pos + size, adev->gmc.visible_vram_size);
if (last > pos) {
- void __iomem *addr = adev->mman.aper_base_kaddr + pos;
- size_t count = last - pos;
+ addr = adev->mman.aper_base_kaddr + pos;
+ count = last - pos;
if (write) {
memcpy_toio(addr, buf, count);
@@ -317,30 +356,42 @@ void amdgpu_device_vram_access(struct amdgpu_device
*adev, loff_t pos,
memcpy_fromio(buf, addr, count);
}
- if (count == size)
- return;
-
- pos += count;
- buf += count / 4;
- size -= count;
}
+
+ return count;
+#else
+ return 0;
#endif
+}
- spin_lock_irqsave(>mmio_idx_lock, flags);
- for (last = pos + size; pos < last; pos += 4) {
- uint32_t tmp = pos >> 31;
+/**
+ * amdgpu_device_vram_access - read/write a buffer in vram
+ *
+ * @adev: amdgpu_devic
[RFC PATCH 2/3] drm/amdgpu/ttm: replace duplicate code with exiting function
using exiting function to replace duplicate code blocks in
amdgpu_ttm_vram_write().
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2aa2eb5de37a..2c98e4345ad3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2207,7 +2207,6 @@ static ssize_t amdgpu_ttm_vram_write(struct file *f,
const char __user *buf,
return -ENXIO;
while (size) {
- unsigned long flags;
uint32_t value;
if (*pos >= adev->gmc.mc_vram_size)
@@ -2217,11 +2216,7 @@ static ssize_t amdgpu_ttm_vram_write(struct file *f,
const char __user *buf,
if (r)
return r;
- spin_lock_irqsave(>mmio_idx_lock, flags);
- WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x8000);
- WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
- WREG32_NO_KIQ(mmMM_DATA, value);
- spin_unlock_irqrestore(>mmio_idx_lock, flags);
+ amdgpu_device_vram_access(adev, *pos, , 4, true);
result += 4;
buf += 4;
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[RFC PATCH v2] drm/amdgpu/ttm: optimize vram access in amdgpu_ttm_access_memory()
1. using vram aper to access vram if possible
2. avoid MM_INDEX/MM_DATA is not working when mmio protect feature is
enabled.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 126 +---
1 file changed, 89 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2aa2eb5de37a..8f6f605bc459 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1407,6 +1407,91 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct
ttm_buffer_object *bo,
return ttm_bo_eviction_valuable(bo, place);
}
+static void amdgpu_ttm_vram_mm_align_access(struct amdgpu_device *adev, loff_t
pos,
+ uint32_t *value, bool write)
+{
+ unsigned long flags;
+
+ BUG_ON(!IS_ALIGNED(pos, 4));
+
+ spin_lock_irqsave(>mmio_idx_lock, flags);
+ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x8000);
+ WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
+ if (write)
+ WREG32_NO_KIQ(mmMM_DATA, *value);
+ else
+ *value = RREG32_NO_KIQ(mmMM_DATA);
+ spin_unlock_irqrestore(>mmio_idx_lock, flags);
+}
+
+static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
+ void *buf, size_t size, bool write)
+{
+ while (size) {
+ uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
+ uint64_t bytes = 4 - (pos & 0x3);
+ uint32_t shift = (pos & 0x3) * 8;
+ uint32_t mask = 0x << shift;
+ uint32_t value = 0;
+
+ if (size < bytes) {
+ mask &= 0x >> (bytes - size) * 8;
+ bytes = size;
+ }
+
+ if (mask != 0x) {
+ amdgpu_ttm_vram_mm_align_access(adev, aligned_pos,
, false);
+ if (write) {
+ value &= ~mask;
+ value |= (*(uint32_t *)buf << shift) & mask;
+ amdgpu_ttm_vram_mm_align_access(adev,
aligned_pos, , true);
+ } else {
+ value = (value & mask) >> shift;
+ memcpy(buf, , bytes);
+ }
+ } else {
+ amdgpu_ttm_vram_mm_align_access(adev, aligned_pos, buf,
write);
+ }
+
+ pos += bytes;
+ buf += bytes;
+ size -= bytes;
+ }
+}
+
+static void amdgpu_ttm_vram_access(struct amdgpu_device *adev, loff_t pos,
+ void *buf, size_t size, bool write)
+{
+ uint64_t last;
+
+#ifdef CONFIG_64BIT
+ last = min(pos + size, adev->gmc.visible_vram_size);
+ if (last > pos) {
+ void __iomem *addr = adev->mman.aper_base_kaddr + pos;
+ size_t count = last - pos;
+
+ if (write) {
+ memcpy_toio(addr, buf, count);
+ mb();
+ amdgpu_device_flush_hdp(adev, NULL);
+ } else {
+ amdgpu_device_invalidate_hdp(adev, NULL);
+ mb();
+ memcpy_fromio(buf, addr, count);
+ }
+
+ if (count == size)
+ return;
+
+ pos += count;
+ buf += count;
+ size -= count;
+ }
+#endif
+
+ amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
+}
+
/**
* amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
*
@@ -1426,8 +1511,6 @@ static int amdgpu_ttm_access_memory(struct
ttm_buffer_object *bo,
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
struct amdgpu_res_cursor cursor;
- unsigned long flags;
- uint32_t value = 0;
int ret = 0;
if (bo->mem.mem_type != TTM_PL_VRAM)
@@ -1435,41 +1518,10 @@ static int amdgpu_ttm_access_memory(struct
ttm_buffer_object *bo,
amdgpu_res_first(>mem, offset, len, );
while (cursor.remaining) {
- uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
- uint64_t bytes = 4 - (cursor.start & 3);
- uint32_t shift = (cursor.start & 3) * 8;
- uint32_t mask = 0x << shift;
-
- if (cursor.size < bytes) {
- mask &= 0x >> (bytes - cursor.size) * 8;
- bytes = cursor.size;
- }
-
- if (mask != 0x) {
- spin_lock_irqsave(>mmio_idx_lock, flags);
- WREG32_NO_KIQ(mmMM_IN
[PATCH] drm/amdgpu: add non-aligned address supported in amdgpu_device_vram_access()
1. add non-aligned address support in amdgpu_device_vram_access()
2. reduce duplicate code in amdgpu_ttm_access_memory()
because the MM_INDEX{HI}/DATA are protected register, it is not working
in sriov environment when mmio protect feature is enabled (in some asics),
and the old function amdgpu_ttm_access_memory() will force using MM_INDEX/DATA
to handle non-aligned address by default, it will cause the register(MM_DATA)
is always return 0.
with the patch, the memory will be accessed in the aper way first.
(in visible memory or enable pcie large-bar feature), then using
MM_INDEX{HI}/MM_DATA to access rest vram memroy.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 69 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 42 ++---
3 files changed, 58 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d14b4968a026..8095d9a9c857 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1103,7 +1103,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev);
int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
- uint32_t *buf, size_t size, bool write);
+ void *buf, size_t size, bool write);
uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
uint32_t reg, uint32_t acc_flags);
void amdgpu_device_wreg(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e6702d136a6d..2047e3c2b365 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -280,6 +280,54 @@ bool amdgpu_device_supports_smart_shift(struct drm_device
*dev)
amdgpu_acpi_is_power_shift_control_supported());
}
+static inline void amdgpu_device_vram_mmio_align_access_locked(struct
amdgpu_device *adev, loff_t pos,
+ uint32_t *value,
bool write)
+{
+ BUG_ON(!IS_ALIGNED(pos, 4));
+
+ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x8000);
+ WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
+ if (write)
+ WREG32_NO_KIQ(mmMM_DATA, *value);
+ else
+ *value = RREG32_NO_KIQ(mmMM_DATA);
+}
+
+static void amdgpu_device_vram_mmio_access_locked(struct amdgpu_device *adev,
loff_t pos,
+ void *buf, size_t size, bool
write)
+{
+ while (size) {
+ uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
+ uint64_t bytes = 4 - (pos & 0x3);
+ uint32_t shift = (pos & 0x3) * 8;
+ uint32_t mask = 0x << shift;
+ uint32_t value = 0;
+
+ if (size < bytes) {
+ mask &= 0x >> (bytes - size) * 8;
+ bytes = size;
+ }
+
+ if (mask != 0x) {
+ amdgpu_device_vram_mmio_align_access_locked(adev,
aligned_pos, , false);
+ if (write) {
+ value &= ~mask;
+ value |= (*(uint32_t *)buf << shift) & mask;
+
amdgpu_device_vram_mmio_align_access_locked(adev, aligned_pos, , true);
+ } else {
+ value = (value & mask) >> shift;
+ memcpy(buf, , bytes);
+ }
+ } else {
+ amdgpu_device_vram_mmio_align_access_locked(adev,
aligned_pos, buf, write);
+ }
+
+ pos += bytes;
+ buf += bytes;
+ size -= bytes;
+ }
+}
+
/*
* VRAM access helper functions
*/
@@ -294,13 +342,11 @@ bool amdgpu_device_supports_smart_shift(struct drm_device
*dev)
* @write: true - write to vram, otherwise - read from vram
*/
void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
- uint32_t *buf, size_t size, bool write)
+ void *buf, size_t size, bool write)
{
unsigned long flags;
- uint32_t hi = ~0;
uint64_t last;
-
#ifdef CONFIG_64BIT
last = min(pos + size, adev->gmc.visible_vram_size);
if (last > pos) {
@@ -321,25 +367,12 @@ void amdgpu_device_vram_access(struct amdgpu_device
*adev, loff_t pos,
return;
pos += count;
- buf += count / 4;
+ buf += count;
size -= count;
}
#endif
-
spin_lock_irqsave(>mmio_idx_lock, flags);
- for (last = pos + size
[PATCH] drm/amdgpu: fix sdma firmware version error in sriov
Re-adjust the function return order to avoid empty sdma version in the
sriov environment. (read amdgpu_firmware_info)
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index deb907f96090..98059bce692f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -147,9 +147,6 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device
*adev)
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
- if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
- return 0;
-
DRM_DEBUG("\n");
switch (adev->asic_type) {
@@ -187,6 +184,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device
*adev)
(void *)>sdma.instance[0],
sizeof(struct amdgpu_sdma_instance));
+ if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
+ return 0;
+
DRM_DEBUG("psp_load == '%s'\n",
adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" :
"false");
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: optimize code about format string in gfx_v10_0_init_microcode()
the memset() and snprintf() is not necessary.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 80729ea8416a..11a64ca8a5ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3935,7 +3935,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device
*adev)
{
const char *chip_name;
char fw_name[40];
- char wks[10];
+ char *wks = "";
int err;
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
@@ -3948,7 +3948,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device
*adev)
DRM_DEBUG("\n");
- memset(wks, 0, sizeof(wks));
switch (adev->asic_type) {
case CHIP_NAVI10:
chip_name = "navi10";
@@ -3957,7 +3956,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device
*adev)
chip_name = "navi14";
if (!(adev->pdev->device == 0x7340 &&
adev->pdev->revision != 0x00))
- snprintf(wks, sizeof(wks), "_wks");
+ wks = "_wks";
break;
case CHIP_NAVI12:
chip_name = "navi12";
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error
1.correct KFD SDMA RLC queue register offset error.
(all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL)
2.HQD_N_REGS (19+6+7+12)
12: the 2 more resgisters than navi1x (SDMAx_RLCy_MIDCMD_DATA{9,10})
the patch also can be fixed NULL pointer issue when read
/sys/kernel/debug/kfd/hqds on sienna_cichlid chip.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
index fad3b91f74f5..d39cff4a1fe3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
@@ -156,16 +156,16 @@ static uint32_t get_sdma_rlc_reg_offset(struct
amdgpu_device *adev,
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
break;
case 1:
- sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
break;
case 2:
- sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
- mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
+ mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
break;
case 3:
- sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
- mmSDMA3_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
+ mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
break;
}
@@ -450,7 +450,7 @@ static int hqd_sdma_dump_v10_3(struct kgd_dev *kgd,
engine_id, queue_id);
uint32_t i = 0, reg;
#undef HQD_N_REGS
-#define HQD_N_REGS (19+6+7+10)
+#define HQD_N_REGS (19+6+7+12)
*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
if (*dump == NULL)
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amdkfd: disable kfd debugfs node of hang_hws on vf mode
v1:
the kfd debugfs node is rely on kgd2kfd probe success,
if not, the kfd_debugfs should not be created,
and the node of "hang_hws" should be disabled on vf mode.
v2:
also move kfd_debugfs_fini() into kgd2kfd_device_exit() function.
1. move kfd_debugfs_init() function into kgd2kfd_probe() function.
2. disable "hang_hws" debugfs node on vf mode.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c | 7 ---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +++
drivers/gpu/drm/amd/amdkfd/kfd_module.c | 3 ---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 4 ++--
4 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
index 673d5e34f213..f9a81f34d09e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
@@ -88,7 +88,7 @@ static const struct file_operations kfd_debugfs_hang_hws_fops
= {
.release = single_release,
};
-void kfd_debugfs_init(void)
+void kfd_debugfs_init(bool is_vf)
{
debugfs_root = debugfs_create_dir("kfd", NULL);
@@ -98,8 +98,9 @@ void kfd_debugfs_init(void)
kfd_debugfs_hqds_by_device, _debugfs_fops);
debugfs_create_file("rls", S_IFREG | 0444, debugfs_root,
kfd_debugfs_rls_by_device, _debugfs_fops);
- debugfs_create_file("hang_hws", S_IFREG | 0200, debugfs_root,
- kfd_debugfs_hang_hws_read,
_debugfs_hang_hws_fops);
+ if (!is_vf)
+ debugfs_create_file("hang_hws", S_IFREG | 0200, debugfs_root,
+ kfd_debugfs_hang_hws_read,
_debugfs_hang_hws_fops);
}
void kfd_debugfs_fini(void)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index dedb8e33b953..aa9154a8410f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -649,6 +649,8 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
ida_init(>doorbell_ida);
+ kfd_debugfs_init(vf);
+
return kfd;
}
@@ -884,6 +886,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd)
amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
}
+ kfd_debugfs_fini();
kfree(kfd);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index 5e90fe642192..6b9f735c55ea 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -61,8 +61,6 @@ static int kfd_init(void)
*/
kfd_procfs_init();
- kfd_debugfs_init();
-
return 0;
err_create_wq:
@@ -76,7 +74,6 @@ static int kfd_init(void)
static void kfd_exit(void)
{
- kfd_debugfs_fini();
kfd_process_destroy_wq();
kfd_procfs_shutdown();
kfd_topology_shutdown();
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index daa9d47514c6..f3ddd8c5b11e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -1174,7 +1174,7 @@ static inline int kfd_devcgroup_check_permission(struct
kfd_dev *kfd)
/* Debugfs */
#if defined(CONFIG_DEBUG_FS)
-void kfd_debugfs_init(void);
+void kfd_debugfs_init(bool is_vf);
void kfd_debugfs_fini(void);
int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data);
int pqm_debugfs_mqds(struct seq_file *m, void *data);
@@ -1189,7 +1189,7 @@ int dqm_debugfs_execute_queues(struct
device_queue_manager *dqm);
#else
-static inline void kfd_debugfs_init(void) {}
+static inline void kfd_debugfs_init(bool is_vf) {}
static inline void kfd_debugfs_fini(void) {}
#endif
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdkfd: disable kfd debugfs node of hang_hws on vf mode
the kfd debugfs node is rely on kgd2kfd probe success,
if not, the kfd_debugfs should not be created,
and the node of "hang_hws" should be disabled on vf mode.
1. move kfd_debugfs_init() function into kgd2kfd_probe() function.
2. disable "hang_hws" debugfs node on vf mode.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c | 7 ---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_module.c | 2 --
drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 4 ++--
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
index 673d5e34f213..f9a81f34d09e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
@@ -88,7 +88,7 @@ static const struct file_operations kfd_debugfs_hang_hws_fops
= {
.release = single_release,
};
-void kfd_debugfs_init(void)
+void kfd_debugfs_init(bool is_vf)
{
debugfs_root = debugfs_create_dir("kfd", NULL);
@@ -98,8 +98,9 @@ void kfd_debugfs_init(void)
kfd_debugfs_hqds_by_device, _debugfs_fops);
debugfs_create_file("rls", S_IFREG | 0444, debugfs_root,
kfd_debugfs_rls_by_device, _debugfs_fops);
- debugfs_create_file("hang_hws", S_IFREG | 0200, debugfs_root,
- kfd_debugfs_hang_hws_read,
_debugfs_hang_hws_fops);
+ if (!is_vf)
+ debugfs_create_file("hang_hws", S_IFREG | 0200, debugfs_root,
+ kfd_debugfs_hang_hws_read,
_debugfs_hang_hws_fops);
}
void kfd_debugfs_fini(void)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index dedb8e33b953..3b493ffaf2aa 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -649,6 +649,8 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
ida_init(>doorbell_ida);
+ kfd_debugfs_init(vf);
+
return kfd;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index 5e90fe642192..930447bd080d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -61,8 +61,6 @@ static int kfd_init(void)
*/
kfd_procfs_init();
- kfd_debugfs_init();
-
return 0;
err_create_wq:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index daa9d47514c6..f3ddd8c5b11e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -1174,7 +1174,7 @@ static inline int kfd_devcgroup_check_permission(struct
kfd_dev *kfd)
/* Debugfs */
#if defined(CONFIG_DEBUG_FS)
-void kfd_debugfs_init(void);
+void kfd_debugfs_init(bool is_vf);
void kfd_debugfs_fini(void);
int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data);
int pqm_debugfs_mqds(struct seq_file *m, void *data);
@@ -1189,7 +1189,7 @@ int dqm_debugfs_execute_queues(struct
device_queue_manager *dqm);
#else
-static inline void kfd_debugfs_init(void) {}
+static inline void kfd_debugfs_init(bool is_vf) {}
static inline void kfd_debugfs_fini(void) {}
#endif
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: correction of ucode fw_size calculation errors
correct big and little endian problems on different platforms.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 85a6a10e048f..0a00a7cc8eaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4354,7 +4354,7 @@ static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
- r = amdgpu_bo_create_reserved(adev,
mec_hdr->header.ucode_size_bytes,
+ r = amdgpu_bo_create_reserved(adev, fw_size,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
>gfx.mec.mec_fw_obj,
>gfx.mec.mec_fw_gpu_addr,
@@ -5769,7 +5769,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct
amdgpu_device *adev)
le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
- r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
+ r = amdgpu_bo_create_reserved(adev, fw_size,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
>gfx.pfp.pfp_fw_obj,
>gfx.pfp.pfp_fw_gpu_addr,
@@ -5847,7 +5847,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct
amdgpu_device *adev)
le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
- r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
+ r = amdgpu_bo_create_reserved(adev, fw_size,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
>gfx.ce.ce_fw_obj,
>gfx.ce.ce_fw_gpu_addr,
@@ -5924,7 +5924,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct
amdgpu_device *adev)
le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
- r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
+ r = amdgpu_bo_create_reserved(adev, fw_size,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
>gfx.me.me_fw_obj,
>gfx.me.me_fw_gpu_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 06811a1f4625..831398e15b84 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2013,7 +2013,7 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
- r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
+ r = amdgpu_bo_create_reserved(adev, fw_size,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
>gfx.mec.mec_fw_obj,
>gfx.mec.mec_fw_gpu_addr,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 6274cae4a065..00610def69ea 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -174,7 +174,7 @@ int smu_v11_0_load_microcode(struct smu_context *smu)
hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
src = (const uint32_t *)(adev->pm.fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
- smc_fw_size = hdr->header.ucode_size_bytes;
+ smc_fw_size = le32_to_cpu(hdr->header.ucode_size_bytes;)
for (i = 1; i < smc_fw_size/4 - 1; i++) {
WREG32_PCIE(addr_start, src[i]);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0864083e7435..d7ea8215d7dc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -149,7 +149,7 @@ int smu_v13_0_load_microcode(struct smu_context *smu)
hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
src = (const uint32_t *)(adev->pm.fw->data +
le32_to_cpu(
[PATCH] Revert "drm/amdgpu: add psp RAP L0 check support"
This reverts commit a77e3752c319e479c538a84c3b0f6d87f6fa4bc7.
Disable PSP RAP L0 self test until to RAP feature ready.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d9856cae9a39..80a4dc51951e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2365,7 +2365,6 @@ static int psp_hw_init(void *handle)
{
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
mutex_lock(>firmware.mutex);
/*
@@ -2383,14 +2382,7 @@ static int psp_hw_init(void *handle)
}
mutex_unlock(>firmware.mutex);
-
- ret = psp_rap_invoke(>psp, TA_CMD_RAP__VALIDATE_L0, );
- if (ret || status != TA_RAP_STATUS__SUCCESS) {
- dev_err(adev->dev, "RAP: (%d) Failed to Invoke Validate L0,
status %d\n",
- ret, status);
- }
-
- return ret;
+ return 0;
failed:
adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm: remove duplicate XGMI feature mask
replace SMU feature XGMI with XGMI_DPM.
it will cause show to be incorrect in pp_features node.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/inc/smu_types.h| 1 -
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index aa4822202587..f9f45b6764fa 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -282,7 +282,6 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(DS_FCLK), \
__SMU_DUMMY_MAP(DS_MP1CLK), \
__SMU_DUMMY_MAP(DS_MP0CLK), \
- __SMU_DUMMY_MAP(XGMI), \
__SMU_DUMMY_MAP(DPM_GFX_PACE), \
__SMU_DUMMY_MAP(MEM_VDDCI_SCALING), \
__SMU_DUMMY_MAP(MEM_MVDD_SCALING), \
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index f76d1b8aeecc..8189457a3ae6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -162,7 +162,7 @@ static const struct cmn2asic_mapping
arcturus_feature_mask_map[SMU_FEATURE_COUNT
FEA_MAP(DPM_SOCCLK),
FEA_MAP(DPM_FCLK),
FEA_MAP(DPM_MP0CLK),
- ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
+ FEA_MAP(DPM_XGMI),
FEA_MAP(DS_GFXCLK),
FEA_MAP(DS_SOCCLK),
FEA_MAP(DS_LCLK),
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix parameter error of RREG32_PCIE() in amdgpu_regs_pcie
the register offset isn't needed division by 4 to pass RREG32_PCIE()
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index a09469f84251..f3434a6f120f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -317,7 +317,7 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file
*f, char __user *buf,
while (size) {
uint32_t value;
- value = RREG32_PCIE(*pos >> 2);
+ value = RREG32_PCIE(*pos);
r = put_user(value, (uint32_t *)buf);
if (r) {
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: add pci BDF info in trace amdgpu_device_r[w]reg()
add pci BDF info in amdgpu_device_r[w]reg trace event to support
muti-device in one host.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 53 +-
2 files changed, 33 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 71805dfd9e25..8819672d3ecb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -355,7 +355,7 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
ret = adev->pcie_rreg(adev, reg * 4);
}
- trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
+ trace_amdgpu_device_rreg(adev->pdev, reg, ret);
return ret;
}
@@ -440,7 +440,7 @@ void amdgpu_device_wreg(struct amdgpu_device *adev,
adev->pcie_wreg(adev, reg * 4, v);
}
- trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
+ trace_amdgpu_device_wreg(adev->pdev, reg, v);
}
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index ce8dc995c10c..1fa774fb805e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -35,42 +35,51 @@
#define AMDGPU_JOB_GET_TIMELINE_NAME(job) \
job->base.s_fence->finished.ops->get_timeline_name(>base.s_fence->finished)
+
TRACE_EVENT(amdgpu_device_rreg,
- TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
- TP_ARGS(did, reg, value),
+ TP_PROTO(struct pci_dev *pdev, uint32_t reg, uint32_t value),
+ TP_ARGS(pdev, reg, value),
TP_STRUCT__entry(
- __field(unsigned, did)
- __field(uint32_t, reg)
- __field(uint32_t, value)
+__field(uint16_t, device)
+__field(uint8_t, bus)
+__field(uint8_t, devfn)
+__field(uint32_t, reg)
+__field(uint32_t, value)
),
TP_fast_assign(
- __entry->did = did;
+ __entry->device = pdev->device;
+ __entry->bus = pdev->bus->number;
+ __entry->devfn = pdev->devfn;
__entry->reg = reg;
__entry->value = value;
- ),
- TP_printk("0x%04lx, 0x%08lx, 0x%08lx",
- (unsigned long)__entry->did,
- (unsigned long)__entry->reg,
- (unsigned long)__entry->value)
+ ),
+ TP_printk("%04x %02x:%02x.%1x: 0x%08x, 0x%08x",
+ __entry->device,
+ __entry->bus, __entry->devfn >> 3, __entry->devfn & 0x7,
+ __entry->reg, __entry->value)
);
TRACE_EVENT(amdgpu_device_wreg,
- TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
- TP_ARGS(did, reg, value),
+ TP_PROTO(struct pci_dev *pdev, uint32_t reg, uint32_t value),
+ TP_ARGS(pdev, reg, value),
TP_STRUCT__entry(
- __field(unsigned, did)
- __field(uint32_t, reg)
- __field(uint32_t, value)
+__field(uint16_t, device)
+__field(uint8_t, bus)
+__field(uint8_t, devfn)
+__field(uint32_t, reg)
+__field(uint32_t, value)
),
TP_fast_assign(
- __entry->did = did;
+ __entry->device = pdev->device;
+ __entry->bus = pdev->bus->number;
+ __entry->devfn = pdev->devfn;
__entry->reg = reg;
__entry->value = value;
- ),
- TP_printk("0x%04lx, 0x%08lx, 0x%08lx",
- (unsigned long)__entry->did,
- (unsigned long)__entry->reg,
- (unsigned long)__entry->value)
+ ),
+ TP_printk("%04x %02x:%02x.%1x: 0x%08x, 0x%08x",
+ __entry->device,
+ __entry->bus, __entry->devfn >> 3, __entry->devfn & 0x7,
+ __entry->reg, __entry->value)
);
TRACE_EVENT(amdgpu_iv,
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdgpu: refine PSP TA firmware info print in debugfs
refine PSP TA firmware info print in amdgpu_firmware_info().
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 50 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
2 files changed, 21 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 6c8ea9d26320..1a27673271b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -289,23 +289,23 @@ static int amdgpu_firmware_info(struct
drm_amdgpu_info_firmware *fw_info,
break;
case AMDGPU_INFO_FW_TA:
switch (query_fw->index) {
- case 0:
+ case TA_FW_TYPE_PSP_XGMI:
fw_info->ver = adev->psp.ta_fw_version;
fw_info->feature = adev->psp.ta_xgmi_ucode_version;
break;
- case 1:
+ case TA_FW_TYPE_PSP_RAS:
fw_info->ver = adev->psp.ta_fw_version;
fw_info->feature = adev->psp.ta_ras_ucode_version;
break;
- case 2:
+ case TA_FW_TYPE_PSP_HDCP:
fw_info->ver = adev->psp.ta_fw_version;
fw_info->feature = adev->psp.ta_hdcp_ucode_version;
break;
- case 3:
+ case TA_FW_TYPE_PSP_DTM:
fw_info->ver = adev->psp.ta_fw_version;
fw_info->feature = adev->psp.ta_dtm_ucode_version;
break;
- case 4:
+ case TA_FW_TYPE_PSP_RAP:
fw_info->ver = adev->psp.ta_fw_version;
fw_info->feature = adev->psp.ta_rap_ucode_version;
break;
@@ -1355,6 +1355,17 @@ static int amdgpu_debugfs_firmware_info_show(struct
seq_file *m, void *unused)
struct atom_context *ctx = adev->mode_info.atom_context;
int ret, i;
+ static const char *ta_fw_name[TA_FW_TYPE_PSP_COUNT] = {
+#define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
+ TA_FW_NAME(ASD),
+ TA_FW_NAME(XGMI),
+ TA_FW_NAME(RAS),
+ TA_FW_NAME(HDCP),
+ TA_FW_NAME(DTM),
+ TA_FW_NAME(RAP),
+#undef TA_FW_NAME
+ };
+
/* VCE */
query_fw.fw_type = AMDGPU_INFO_FW_VCE;
ret = amdgpu_firmware_info(_info, _fw, adev);
@@ -1472,35 +1483,14 @@ static int amdgpu_debugfs_firmware_info_show(struct
seq_file *m, void *unused)
fw_info.feature, fw_info.ver);
query_fw.fw_type = AMDGPU_INFO_FW_TA;
- for (i = 0; i < 5; i++) {
+ for (i = TA_FW_TYPE_PSP_ASD; i < TA_FW_TYPE_PSP_COUNT; i++) {
query_fw.index = i;
ret = amdgpu_firmware_info(_info, _fw, adev);
if (ret)
continue;
- switch (query_fw.index) {
- case 0:
- seq_printf(m, "TA %s feature version: 0x%08x, firmware
version: 0x%08x\n",
- "RAS", fw_info.feature, fw_info.ver);
- break;
- case 1:
- seq_printf(m, "TA %s feature version: 0x%08x, firmware
version: 0x%08x\n",
- "XGMI", fw_info.feature, fw_info.ver);
- break;
- case 2:
- seq_printf(m, "TA %s feature version: 0x%08x, firmware
version: 0x%08x\n",
- "HDCP", fw_info.feature, fw_info.ver);
- break;
- case 3:
- seq_printf(m, "TA %s feature version: 0x%08x, firmware
version: 0x%08x\n",
- "DTM", fw_info.feature, fw_info.ver);
- break;
- case 4:
- seq_printf(m, "TA %s feature version: 0x%08x, firmware
version: 0x%08x\n",
- "RAP", fw_info.feature, fw_info.ver);
- break;
- default:
- return -EINVAL;
- }
+
+ seq_printf(m, "TA %s feature version: 0x%08x, firmware version:
0x%08x\n",
+ ta_fw_name[i], fw_info.feature, fw_info.ver);
}
/* SMC */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 46449e70348b..c03f32ec3ebc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -136,6 +136,7 @@ enum ta_fw_type {
TA_FW_TYPE_PSP_DTM,
TA_FW_TYPE_PSP_RAP,
[PATCH 2/2] drm/amdgpu: add SECURE DISPLAY TA firmware info in debugfs
add SECUREDISPLAY TA firmware info in amdgpu_fimrware_info() Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 1a27673271b0..ed51dd0468e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -309,6 +309,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_rap_ucode_version; break; + case TA_FW_TYPE_PSP_SECUREDISPLAY: + fw_info->ver = adev->psp.ta_fw_version; + fw_info->feature = adev->psp.ta_securedisplay_ucode_version; + break; default: return -EINVAL; } @@ -1363,6 +1367,7 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) TA_FW_NAME(HDCP), TA_FW_NAME(DTM), TA_FW_NAME(RAP), + TA_FW_NAME(SECUREDISPLAY), #undef TA_FW_NAME }; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: correct TA RAP firmware information print error
miss RAP TA in loop ( when i == 4)
Fix:
drm/amdgpu: add RAP TA version print in amdgpu_firmware_info
Signed-off-by: Kevin Wang
Reported-by: Candice Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index a5ed9530f542..6c8ea9d26320 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1472,7 +1472,7 @@ static int amdgpu_debugfs_firmware_info_show(struct
seq_file *m, void *unused)
fw_info.feature, fw_info.ver);
query_fw.fw_type = AMDGPU_INFO_FW_TA;
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < 5; i++) {
query_fw.index = i;
ret = amdgpu_firmware_info(_info, _fw, adev);
if (ret)
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: remove unused variable in amdgpu_dma_buf_unmap()
clean up unsued variable in amdgpu_dma_buf_unmap().
Fixes:
drm/amdgpu: Remove amdgpu_device arg from free_sgt api
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index e83d73ec0e9d..5ec6556ebf7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -356,10 +356,6 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment
*attach,
struct sg_table *sgt,
enum dma_data_direction dir)
{
- struct dma_buf *dma_buf = attach->dmabuf;
- struct drm_gem_object *obj = dma_buf->priv;
- struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
-
if (sgt->sgl->page_link) {
dma_unmap_sgtable(attach->dev, sgt, dir, 0);
sg_free_table(sgt);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: add RAP TA version print in amdgpu_firmware_info
add RAP TA version print in amdgpu_firmware_info. Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index ce031a77cda5..a5ed9530f542 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -305,6 +305,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_dtm_ucode_version; break; + case 4: + fw_info->ver = adev->psp.ta_fw_version; + fw_info->feature = adev->psp.ta_rap_ucode_version; + break; default: return -EINVAL; } @@ -1490,6 +1494,10 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", "DTM", fw_info.feature, fw_info.ver); break; + case 4: + seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", + "RAP", fw_info.feature, fw_info.ver); + break; default: return -EINVAL; } -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: optimize list operation in amdgpu_xgmi
simplify the list opertion.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 541ef6be390f..659b385b27b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -324,7 +324,7 @@ static void amdgpu_xgmi_sysfs_rem_dev_info(struct
amdgpu_device *adev,
struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
{
- struct amdgpu_hive_info *hive = NULL, *tmp = NULL;
+ struct amdgpu_hive_info *hive = NULL;
int ret;
if (!adev->gmc.xgmi.hive_id)
@@ -337,11 +337,9 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct
amdgpu_device *adev)
mutex_lock(_mutex);
- if (!list_empty(_hive_list)) {
- list_for_each_entry_safe(hive, tmp, _hive_list, node) {
- if (hive->hive_id == adev->gmc.xgmi.hive_id)
- goto pro_end;
- }
+ list_for_each_entry(hive, _hive_list, node) {
+ if (hive->hive_id == adev->gmc.xgmi.hive_id)
+ goto pro_end;
}
hive = kzalloc(sizeof(*hive), GFP_KERNEL);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm/swsmu: unify the init soft gpu metrics function
the soft gpu metrics is not asic related data structure. unify them to reduce duplicate code. Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/pm/inc/smu_v11_0.h| 4 --- drivers/gpu/drm/amd/pm/inc/smu_v12_0.h| 2 -- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 ++- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 ++- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 ++- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 24 -- .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 ++- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 ++- .../gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c| 12 - drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 25 +++ drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h| 2 ++ 11 files changed, 42 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h index c7d57e9555cc..e49c2d08a983 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h @@ -272,10 +272,6 @@ int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu); int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu); -void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics); - -void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics); - int smu_v11_0_gfx_ulv_control(struct smu_context *smu, bool enablement); diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v12_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v12_0.h index fa2e8cb07967..02de3b6199e5 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v12_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v12_0.h @@ -60,7 +60,5 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ int smu_v12_0_set_driver_table_location(struct smu_context *smu); -void smu_v12_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics); - #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index f0cc4de9ced5..45564a776e9b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -2239,7 +2239,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2276,6 +2276,8 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, gpu_metrics->pcie_link_speed = arcturus_get_current_pcie_link_speed(smu); + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + *table = (void *)gpu_metrics; return sizeof(struct gpu_metrics_v1_0); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index f7f78daffd27..6e641f1513d8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -2314,7 +2314,7 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, mutex_unlock(>metrics_lock); - smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2354,6 +2354,8 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, gpu_metrics->pcie_link_speed = smu_v11_0_get_current_pcie_link_speed(smu); + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + *table = (void *)gpu_metrics; return sizeof(struct gpu_metrics_v1_0); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index e3ba40d9f83f..34add528d83c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -2950,7 +2950,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); gpu_metrics->temperature_edge = metrics->TemperatureEdge; gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot; @@ -2993,6 +2993,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, gpu_metrics->pcie_link_speed = smu_v11_0_get_current_pcie_link_speed(smu); + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + *table =
[RFC PATCH 3/3] drm/ttm: add ttm mem trace event support
add ttm memory related trace event support
trace events:
ttm:ttm_shrink
ttm:ttm_mem_global_reserve
ttm:ttm_mem_global_free
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/ttm/ttm_memory.c | 7
drivers/gpu/drm/ttm/ttm_trace.h | 70
2 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
index acd63b70d814..27470b1f1f13 100644
--- a/drivers/gpu/drm/ttm/ttm_memory.c
+++ b/drivers/gpu/drm/ttm/ttm_memory.c
@@ -39,6 +39,8 @@
#include
#include
+#include "ttm_trace.h"
+
#define TTM_MEMORY_ALLOC_RETRIES 4
struct ttm_mem_global ttm_mem_glob;
@@ -272,6 +274,7 @@ static void ttm_shrink(struct ttm_mem_global *glob, bool
from_wq,
int ret;
spin_lock(>lock);
+ trace_ttm_shrink(from_wq, extra, ctx);
while (ttm_zones_above_swap_target(glob, from_wq, extra)) {
spin_unlock(>lock);
@@ -518,6 +521,8 @@ static void ttm_mem_global_free_zone(struct ttm_mem_global
*glob,
zone->used_mem -= amount;
}
spin_unlock(>lock);
+ trace_ttm_mem_global_free(single_zone->name, amount,
+ single_zone->used_mem, single_zone->max_mem);
}
void ttm_mem_global_free(struct ttm_mem_global *glob,
@@ -590,6 +595,8 @@ static int ttm_mem_global_reserve(struct ttm_mem_global
*glob,
ret = 0;
out_unlock:
spin_unlock(>lock);
+ trace_ttm_mem_global_reserve(single_zone->name, amount,
+ single_zone->used_mem, single_zone->max_mem);
ttm_check_swapping(glob);
return ret;
diff --git a/drivers/gpu/drm/ttm/ttm_trace.h b/drivers/gpu/drm/ttm/ttm_trace.h
index 9f7cc34b243b..e25b8a2c423c 100644
--- a/drivers/gpu/drm/ttm/ttm_trace.h
+++ b/drivers/gpu/drm/ttm/ttm_trace.h
@@ -388,6 +388,76 @@ TRACE_EVENT(ttm_bo_vm_access,
__entry->offset, __entry->len, __entry->mem_type)
);
+TRACE_EVENT(ttm_shrink,
+ TP_PROTO(bool from_wq, uint64_t extra, struct ttm_operation_ctx
*ctx),
+ TP_ARGS(from_wq, extra, ctx),
+ TP_STRUCT__entry(
+__field(bool, from_wq)
+__field(bool, interruptible)
+__field(bool, wait_gpu)
+__field(uint64_t, extra)
+),
+
+ TP_fast_assign(
+ __entry->from_wq = from_wq;
+ __entry->extra = extra;
+ __entry->interruptible= ctx->interruptible;
+ __entry->wait_gpu = !ctx->no_wait_gpu;
+ ),
+
+ TP_printk("ttm_shrink: from_wq=%s, interruptible=%s, wait_gpu=%s,
extra=0x%llx(%lld)",
+ __entry->from_wq ? "true" : "false",
+ __entry->interruptible ? "true" : "false",
+ __entry->wait_gpu? "true" : "false",
+ __entry->extra, __entry->extra)
+);
+
+TRACE_EVENT(ttm_mem_global_reserve,
+ TP_PROTO(const char *zone_name, uint64_t amount,
+uint64_t used_mem, uint64_t max_mem),
+ TP_ARGS(zone_name, amount, used_mem, max_mem),
+ TP_STRUCT__entry(
+__string(zone, zone_name)
+__field(uint64_t, amount)
+__field(uint64_t, used_mem)
+__field(uint64_t, max_mem)
+),
+
+ TP_fast_assign(
+ __assign_str(zone, zone_name);
+ __entry->amount = amount;
+ __entry->used_mem = used_mem;
+ __entry->max_mem = max_mem;
+ ),
+
+ TP_printk("zone:%s, amount=%lld, used=%lld/%lld",
+ __get_str(zone), __entry->amount,
+ __entry->used_mem, __entry->max_mem)
+);
+
+TRACE_EVENT(ttm_mem_global_free,
+ TP_PROTO(const char *zone_name, uint64_t amount,
+uint64_t used_mem, uint64_t max_mem),
+ TP_ARGS(zone_name, amount, used_mem, max_mem),
+ TP_STRUCT__entry(
+__string(zone, zone_name)
+__field(uint64_t, amount)
+__field(uint64_t, used_mem)
+__field(uint64_t, max_mem)
+),
+
+ TP_fast_assign(
+ __assign_str(zone, zone_name);
+ __entry->amount = amount;
+ __entry->used_mem = used_mem;
+ __entry->max_mem = max_mem;
+ ),
+
+
[RFC PATCH 2/3] drm/ttm: add ttm vm bo trace event support
add ttm bo VM related trace event support
trace events:
ttm:ttm_bo_mmap
ttm:ttm_bo_vm_fault
ttm:ttm_bo_vm_access
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/ttm/ttm_bo_vm.c | 12 -
drivers/gpu/drm/ttm/ttm_trace.h | 78 +
2 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 01693e8f24b7..aece2024c1fd 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -42,6 +42,8 @@
#include
#include
+#include "ttm_trace.h"
+
static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo,
struct vm_fault *vmf)
{
@@ -429,15 +431,17 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
ret = ttm_bo_vm_reserve(bo, vmf);
if (ret)
- return ret;
+ goto out;
prot = vma->vm_page_prot;
ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT, 1);
if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
- return ret;
+ goto out;
dma_resv_unlock(bo->base.resv);
+out:
+ trace_ttm_bo_vm_fault(bo, vmf, ret);
return ret;
}
EXPORT_SYMBOL(ttm_bo_vm_fault);
@@ -516,6 +520,8 @@ int ttm_bo_vm_access(struct vm_area_struct *vma, unsigned
long addr,
if (ret)
return ret;
+ trace_ttm_bo_vm_access(bo, !!write, offset, len);
+
switch (bo->mem.mem_type) {
case TTM_PL_SYSTEM:
if (unlikely(bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
@@ -618,6 +624,7 @@ int ttm_bo_mmap(struct file *filp, struct vm_area_struct
*vma,
goto out_unref;
ttm_bo_mmap_vma_setup(bo, vma);
+ trace_ttm_bo_mmap(bo, vma);
return 0;
out_unref:
ttm_bo_put(bo);
@@ -629,6 +636,7 @@ int ttm_bo_mmap_obj(struct vm_area_struct *vma, struct
ttm_buffer_object *bo)
{
ttm_bo_get(bo);
ttm_bo_mmap_vma_setup(bo, vma);
+ trace_ttm_bo_mmap(bo, vma);
return 0;
}
EXPORT_SYMBOL(ttm_bo_mmap_obj);
diff --git a/drivers/gpu/drm/ttm/ttm_trace.h b/drivers/gpu/drm/ttm/ttm_trace.h
index 7c5e55725e8e..9f7cc34b243b 100644
--- a/drivers/gpu/drm/ttm/ttm_trace.h
+++ b/drivers/gpu/drm/ttm/ttm_trace.h
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#define TTM_PLACEMENT_FLAGS_TRACE \
{ TTM_PL_FLAG_SYSTEM, "SYSTEM"},\
@@ -310,6 +311,83 @@ TRACE_EVENT(ttm_bo_release,
TP_printk("bo:%p", __entry->bo)
);
+TRACE_EVENT(ttm_bo_mmap,
+ TP_PROTO(struct ttm_buffer_object *bo, struct vm_area_struct *vma),
+ TP_ARGS(bo, vma),
+ TP_STRUCT__entry(
+__field(struct ttm_buffer_object *, bo)
+__field(unsigned long, vm_start)
+__field(unsigned long, vm_end)
+__field(unsigned long, vm_pgoff)
+__field(unsigned long, vm_flags)
+),
+
+ TP_fast_assign(
+ __entry->bo = bo;
+ __entry->vm_start = vma->vm_start;
+ __entry->vm_end = vma->vm_end;
+ __entry->vm_pgoff = vma->vm_pgoff;
+ __entry->vm_flags = vma->vm_flags;
+ ),
+
+ TP_printk("bo:%p, vm_start=%lx, vm_end=%lx, vm_pgoff=%lx,
vm_flags=%s",
+ __entry->bo,
+ __entry->vm_start, __entry->vm_end, __entry->vm_pgoff,
+ show_vma_flags(__entry->vm_flags))
+);
+
+TRACE_EVENT(ttm_bo_vm_fault,
+ TP_PROTO(struct ttm_buffer_object *bo, struct vm_fault *vmf, int
result),
+ TP_ARGS(bo, vmf, result),
+ TP_STRUCT__entry(
+__field(struct ttm_buffer_object *, bo)
+__field(struct vm_area_struct *, vma)
+__field(unsigned long, fault_address)
+__field(unsigned long, fault_pgoff)
+__field(int, result)
+__field(unsigned int, flags)
+),
+
+ TP_fast_assign(
+ __entry->bo = bo;
+ __entry->vma = vmf->vma;
+ __entry->fault_address = vmf->address;
+ __entry->fault_pgoff = vmf->pgoff;
+ __entry->flags = vmf->flags;
+ __entry->result = result;
+ ),
+
+ TP_printk("bo:%p, vma=%p, fault_address=%lx, fault_pgoff=%lx,
fault_flags=%s %s",
+ __e
[RFC PATCH 1/3] drm/ttm: add ttm bo trace event support
add ttm bo related trace event support
trace events:
ttm:ttm_bo_add_mem_to_lru
ttm:ttm_bo_del_from_lru
ttm:ttm_bo_move_mem
ttm:ttm_bo_wait
ttm:ttm_bo_evict
ttm:ttm_bo_swapout
ttm:ttm_bo_device_init
ttm:ttm_bo_device_release
ttm:ttm_bo_init_reserved
ttm:ttm_bo_validate
ttm:ttm_bo_release
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/ttm/ttm_bo.c | 23 +++
drivers/gpu/drm/ttm/ttm_module.c | 3 +
drivers/gpu/drm/ttm/ttm_trace.h | 321 +++
3 files changed, 347 insertions(+)
create mode 100644 drivers/gpu/drm/ttm/ttm_trace.h
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index e3931e515906..074afd05aaa8 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -43,6 +43,8 @@
#include
#include
+#include "ttm_trace.h"
+
static void ttm_bo_global_kobj_release(struct kobject *kobj);
/**
@@ -143,6 +145,8 @@ static void ttm_bo_add_mem_to_lru(struct ttm_buffer_object
*bo,
if (mem->placement & TTM_PL_FLAG_NO_EVICT)
return;
+ trace_ttm_bo_add_mem_to_lru(bo, mem);
+
man = ttm_manager_type(bdev, mem->mem_type);
list_add_tail(>lru, >lru[bo->priority]);
@@ -167,6 +171,8 @@ static void ttm_bo_del_from_lru(struct ttm_buffer_object
*bo)
notify = true;
}
+ trace_ttm_bo_del_from_lru(bo, notify);
+
if (notify && bdev->driver->del_from_lru_notify)
bdev->driver->del_from_lru_notify(bo);
}
@@ -299,6 +305,8 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object
*bo,
}
}
+ trace_ttm_bo_move_mem(bo, mem, evict);
+
if (bdev->driver->move_notify)
bdev->driver->move_notify(bo, evict, mem);
@@ -542,6 +550,8 @@ static void ttm_bo_release(struct kref *kref)
size_t acc_size = bo->acc_size;
int ret;
+ trace_ttm_bo_release(bo);
+
if (!bo->deleted) {
ret = ttm_bo_individualize_resv(bo);
if (ret) {
@@ -668,6 +678,8 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
ttm_resource_free(bo, _mem);
goto out;
}
+
+ trace_ttm_bo_evict(bo, _mem);
bo->evicted = true;
out:
return ret;
@@ -1151,6 +1163,8 @@ int ttm_bo_validate(struct ttm_buffer_object *bo,
dma_resv_assert_held(bo->base.resv);
+ trace_ttm_bo_validate(bo);
+
/*
* Remove the backing store if no placement is given.
*/
@@ -1263,6 +1277,8 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev,
}
atomic_inc(_bo_glob.bo_count);
+ trace_ttm_bo_init_reserved(bo, size);
+
/*
* For ttm_bo_type_device buffers, allocate
* address space from the device.
@@ -1487,6 +1503,8 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev)
if (!ret)
ttm_bo_global_release();
+ trace_ttm_bo_device_release(bdev);
+
return ret;
}
EXPORT_SYMBOL(ttm_bo_device_release);
@@ -1537,6 +1555,8 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev,
list_add_tail(>device_list, >device_list);
mutex_unlock(_global_mutex);
+ trace_ttm_bo_device_init(bdev);
+
return 0;
}
EXPORT_SYMBOL(ttm_bo_device_init);
@@ -1580,6 +1600,8 @@ int ttm_bo_wait(struct ttm_buffer_object *bo,
timeout = dma_resv_wait_timeout_rcu(bo->base.resv, true,
interruptible, timeout);
+
+ trace_ttm_bo_wait(bo, interruptible, timeout);
if (timeout < 0)
return timeout;
@@ -1670,6 +1692,7 @@ int ttm_bo_swapout(struct ttm_bo_global *glob, struct
ttm_operation_ctx *ctx)
* anyone tries to access a ttm page.
*/
+ trace_ttm_bo_swapout(bo, i);
if (bo->bdev->driver->swap_notify)
bo->bdev->driver->swap_notify(bo);
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
index 6ff40c041d79..8b70e8aebecb 100644
--- a/drivers/gpu/drm/ttm/ttm_module.c
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -35,6 +35,9 @@
#include
#include
+#define CREATE_TRACE_POINTS
+#include "ttm_trace.h"
+
static DECLARE_WAIT_QUEUE_HEAD(exit_q);
static atomic_t device_released;
diff --git a/drivers/gpu/drm/ttm/ttm_trace.h b/drivers/gpu/drm/ttm/ttm_trace.h
new file mode 100644
index ..7c5e55725e8e
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_trace.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublic
[RFC PATCH 0/3] add ttm trace event support
the kernel ftrace can better help analyze the kernel running status. add some trace events to support TTM. add trace events list: ttm:ttm_bo_add_mem_to_lru ttm:ttm_bo_del_from_lru ttm:ttm_bo_move_mem ttm:ttm_bo_wait ttm:ttm_bo_evict ttm:ttm_bo_swapout ttm:ttm_bo_device_init ttm:ttm_bo_device_release ttm:ttm_bo_init_reserved ttm:ttm_bo_validate ttm:ttm_bo_release ttm:ttm_bo_mmap ttm:ttm_bo_vm_fault ttm:ttm_bo_vm_access ttm:ttm_shrink ttm:ttm_mem_global_reserve ttm:ttm_mem_global_free Kevin Wang (3): drm/ttm: add ttm bo trace event support drm/ttm: add ttm vm bo trace event support drm/ttm: add ttm mem trace event support drivers/gpu/drm/ttm/ttm_bo.c | 23 ++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 12 +- drivers/gpu/drm/ttm/ttm_memory.c | 7 + drivers/gpu/drm/ttm/ttm_module.c | 3 + drivers/gpu/drm/ttm/ttm_trace.h | 469 +++ 5 files changed, 512 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/ttm/ttm_trace.h -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm: remove unused message SMU_MSG_SpareX
the SpareX is reserved by SMU firmwared,
the driver never use it.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 2 --
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 2 --
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 2 --
3 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index b76270e8767c..68c87d4b1ce3 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -133,8 +133,6 @@
__SMU_DUMMY_MAP(PowerUpSdma), \
__SMU_DUMMY_MAP(SetHardMinIspclkByFreq), \
__SMU_DUMMY_MAP(SetHardMinVcn), \
- __SMU_DUMMY_MAP(Spare1), \
- __SMU_DUMMY_MAP(Spare2), \
__SMU_DUMMY_MAP(SetAllowFclkSwitch), \
__SMU_DUMMY_MAP(SetMinVideoGfxclkFreq), \
__SMU_DUMMY_MAP(ActiveProcessNotify), \
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 2f0cb0ea243b..3d639c530e2f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -81,7 +81,6 @@ static struct cmn2asic_msg_mapping
vangogh_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TransferTableDram2Smu,
PPSMC_MSG_TransferTableDram2Smu,0),
MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset,
0),
MSG_MAP(GetEnabledSmuFeatures,
PPSMC_MSG_GetEnabledSmuFeatures,0),
- MSG_MAP(Spare1, PPSMC_MSG_spare1,
0),
MSG_MAP(SetHardMinSocclkByFreq,
PPSMC_MSG_SetHardMinSocclkByFreq, 0),
MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk,
0),
MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn,
0),
@@ -93,7 +92,6 @@ static struct cmn2asic_msg_mapping
vangogh_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(SetSoftMaxSocclkByFreq,
PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq,
0),
MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn,
0),
- MSG_MAP(Spare2, PPSMC_MSG_spare2,
0),
MSG_MAP(SetPowerLimitPercentage,
PPSMC_MSG_SetPowerLimitPercentage, 0),
MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg,
0),
MSG_MAP(PowerUpJpeg,PPSMC_MSG_PowerUpJpeg,
0),
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 6c8a8ccd2f84..dfe4eeeb4596 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -56,8 +56,6 @@ static struct cmn2asic_msg_mapping
renoir_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(PowerUpSdma,PPSMC_MSG_PowerUpSdma,
1),
MSG_MAP(SetHardMinIspclkByFreq,
PPSMC_MSG_SetHardMinIspclkByFreq, 1),
MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
1),
- MSG_MAP(Spare1, PPSMC_MSG_spare1,
1),
- MSG_MAP(Spare2, PPSMC_MSG_spare2,
1),
MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch,
1),
MSG_MAP(SetMinVideoGfxclkFreq,
PPSMC_MSG_SetMinVideoGfxclkFreq,1),
MSG_MAP(ActiveProcessNotify,PPSMC_MSG_ActiveProcessNotify,
1),
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: fix sysfs amdgpu_current_backlight_pwm NULL pointer issue
fix NULL pointer issue when read sysfs amdgpu_current_backlight_pwm sysfs node.
calltrace:
[ 248.273833] BUG: kernel NULL pointer dereference, address: 0130
[ 248.273930] #PF: supervisor read access in kernel mode
[ 248.273993] #PF: error_code(0x) - not-present page
[ 248.274054] PGD 0 P4D 0
[ 248.274092] Oops: [#1] SMP PTI
[ 248.274138] CPU: 2 PID: 1377 Comm: cat Tainted: G OE
5.9.0-rc5-drm-next-5.9+ #1
[ 248.274233] Hardware name: System manufacturer System Product Name/Z170-A,
BIOS 3802 03/15/2018
[ 248.274641] RIP: 0010:dc_link_get_backlight_level+0x5/0x70 [amdgpu]
[ 248.274718] Code: 67 ff ff ff 41 b9 03 00 00 00 e9 45 ff ff ff d1 ea e9 55
ff ff ff 0f 1f 44 00 00 66 2e
0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 <48> 8b 87 30 01 00 00 48 8b 00 48 8b 88
88 03 00 00 48 8d 81 e8 01
[ 248.274919] RSP: 0018:b5ad809b3df0 EFLAGS: 00010203
[ 248.274982] RAX: a0f77d1c0010 RBX: a0f793ae9168 RCX: 0001
[ 248.275064] RDX: a0f79753db00 RSI: 0001 RDI:
[ 248.275145] RBP: b5ad809b3e00 R08: b5ad809b3da0 R09:
[ 248.275225] R10: b5ad809b3e68 R11: R12: a0f793ae9190
[ 248.275306] R13: b5ad809b3ef0 R14: 0001 R15: a0f793ae9168
[ 248.275388] FS: 7f5f1ec4d540() GS:a0f79ec8()
knlGS:
[ 248.275480] CS: 0010 DS: ES: CR0: 80050033
[ 248.275547] CR2: 0130 CR3: 00042a03c005 CR4: 003706e0
[ 248.275628] DR0: DR1: DR2:
[ 248.275708] DR3: DR6: fffe0ff0 DR7: 0400
[ 248.275789] Call Trace:
[ 248.276124] ? current_backlight_read+0x24/0x40 [amdgpu]
[ 248.276194] seq_read+0xc3/0x3f0
[ 248.276240] full_proxy_read+0x5c/0x90
[ 248.276290] vfs_read+0xa7/0x190
[ 248.276334] ksys_read+0xa7/0xe0
[ 248.276379] __x64_sys_read+0x1a/0x20
[ 248.276429] do_syscall_64+0x37/0x80
[ 248.276477] entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 248.276538] RIP: 0033:0x7f5f1e75c191
[ 248.276585] Code: fe ff ff 48 8d 3d b7 9d 0a 00 48 83 ec 08 e8 46 4d 02 00
66 0f 1f 44 00 00 48 8d 05 71 07
2e 00 8b 00 85 c0 75 13 31 c0 0f 05 <48> 3d 00 f0 ff ff 77 57 f3 c3 0f 1f 44 00
00 41 54 55 49 89 d4 53Hw
[ 248.276784] RSP: 002b:7ffcb1fc3f38 EFLAGS: 0246 ORIG_RAX:
[ 248.276872] RAX: ffda RBX: 0002 RCX: 7f5f1e75c191
[ 248.276953] RDX: 0002 RSI: 7f5f1ec2b000 RDI: 0003
[ 248.277034] RBP: 0002 R08: R09:
[ 248.277115] R10: 0022 R11: 0246 R12: 7f5f1ec2b000
[ 248.277195] R13: 0003 R14: 7f5f1ec2b00f R15: 0002
[ 248.277279] Modules linked in: amdgpu(OE) iommu_v2 gpu_sched ttm(OE)
drm_kms_helper cec drm
i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt rpcsec_gss_krb5
auth_rpcgss nfsv4 nfs
lockd grace fscache nls_iso8859_1 snd_hda_codec_realtek snd_hda_codec_hdmi
snd_hda_codec_generic
ledtrig_audio intel_rapl_msr intel_rapl_common snd_hda_intel snd_intel_dspcfg
x86_pkg_temp_thermal
intel_powerclamp snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_seq_midi
snd_seq_midi_event mei_hdcp
coretemp snd_rawmidi snd_seq kvm_intel kvm snd_seq_device snd_timer irqbypass
joydev snd input_leds soundcore
crct10dif_pclmul crc32_pclmul ghash_clmulni_intel aesni_intel crypto_simd
cryptd glue_helper rapl intel_cstate
mac_hid mei_me serio_raw mei eeepc_wmi wmi_bmof asus_wmi mxm_wmi
intel_wmi_thunderbolt acpi_pad sparse_keymap
efi_pstore sch_fq_codel parport_pc ppdev lp parport sunrpc ip_tables x_tables
autofs4 hid_logitech_hidpp
hid_logitech_dj hid_generic usbhid hid e1000e psmouse ahci libahci wmi video
[ 248.278211] CR2: 0130
[ 248.278221] ---[ end trace 1fbe72fe6f91091d ]---
[ 248.357226] RIP: 0010:dc_link_get_backlight_level+0x5/0x70 [amdgpu]
[ 248.357272] Code: 67 ff ff ff 41 b9 03 00 00 00 e9 45 ff ff ff d1 ea e9 55
ff ff ff 0f 1f 44 00 00 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 <48> 8b 87
30 01 00 00 48 8b 00 48 8b 88 88 03 00 00 48 8d 81 e8 01
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 9e1071b2181f..f4a2088ab179 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2487,9 +2487,14 @@ enum dc_status dc_link_validate_mode_timing(
static struct abm *get_abm_from_stream_res(const struct dc_link *link)
{
int i;
- struct dc *dc = link->ctx->dc;
+ struct dc *dc = NULL;
struct abm *abm = NULL;
+ if (!link || !link->ctx)
+ return NULL;
+
+ dc = link->ct
[PATCH] drm/amdgpu: change trace event parameter name from 'driect' to 'immediate'
s/direct/immediate/g
amdgpu vm has renamed parameter name from 'direct' to 'immedate'.
however, the trace event is not updated yet.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 24 +++
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index ee9480d14cbc..324d5e3f3579 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -366,15 +366,15 @@ TRACE_EVENT(amdgpu_vm_update_ptes,
TRACE_EVENT(amdgpu_vm_set_ptes,
TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
-uint32_t incr, uint64_t flags, bool direct),
- TP_ARGS(pe, addr, count, incr, flags, direct),
+uint32_t incr, uint64_t flags, bool immediate),
+ TP_ARGS(pe, addr, count, incr, flags, immediate),
TP_STRUCT__entry(
__field(u64, pe)
__field(u64, addr)
__field(u32, count)
__field(u32, incr)
__field(u64, flags)
-__field(bool, direct)
+__field(bool, immediate)
),
TP_fast_assign(
@@ -383,32 +383,32 @@ TRACE_EVENT(amdgpu_vm_set_ptes,
__entry->count = count;
__entry->incr = incr;
__entry->flags = flags;
- __entry->direct = direct;
+ __entry->immediate = immediate;
),
TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%llx, count=%u, "
- "direct=%d", __entry->pe, __entry->addr, __entry->incr,
- __entry->flags, __entry->count, __entry->direct)
+ "immediate=%d", __entry->pe, __entry->addr, __entry->incr,
+ __entry->flags, __entry->count, __entry->immediate)
);
TRACE_EVENT(amdgpu_vm_copy_ptes,
- TP_PROTO(uint64_t pe, uint64_t src, unsigned count, bool direct),
- TP_ARGS(pe, src, count, direct),
+ TP_PROTO(uint64_t pe, uint64_t src, unsigned count, bool immediate),
+ TP_ARGS(pe, src, count, immediate),
TP_STRUCT__entry(
__field(u64, pe)
__field(u64, src)
__field(u32, count)
-__field(bool, direct)
+__field(bool, immediate)
),
TP_fast_assign(
__entry->pe = pe;
__entry->src = src;
__entry->count = count;
- __entry->direct = direct;
+ __entry->immediate = immediate;
),
- TP_printk("pe=%010Lx, src=%010Lx, count=%u, direct=%d",
+ TP_printk("pe=%010Lx, src=%010Lx, count=%u, immediate=%d",
__entry->pe, __entry->src, __entry->count,
- __entry->direct)
+ __entry->immediate)
);
TRACE_EVENT(amdgpu_vm_flush,
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/pm: add smc v2_1 printer in amdgpu_ucode_print_smc_hdr()
the smc v2_0 printer is not compatible with the smc v2_1 .
1. add smc v2_1 printer.
2. cleanup code
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 29 +++
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 2b7c90b7a712..1beb08af347f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -68,23 +68,32 @@ void amdgpu_ucode_print_smc_hdr(const struct
common_firmware_header *hdr)
{
uint16_t version_major = le16_to_cpu(hdr->header_version_major);
uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
+ const struct smc_firmware_header_v1_0 *v1_0_hdr;
+ const struct smc_firmware_header_v2_0 *v2_0_hdr;
+ const struct smc_firmware_header_v2_1 *v2_1_hdr;
DRM_DEBUG("SMC\n");
amdgpu_ucode_print_common_hdr(hdr);
if (version_major == 1) {
- const struct smc_firmware_header_v1_0 *smc_hdr =
- container_of(hdr, struct smc_firmware_header_v1_0,
header);
-
- DRM_DEBUG("ucode_start_addr: %u\n",
le32_to_cpu(smc_hdr->ucode_start_addr));
+ v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0,
header);
+ DRM_DEBUG("ucode_start_addr: %u\n",
le32_to_cpu(v1_0_hdr->ucode_start_addr));
} else if (version_major == 2) {
- const struct smc_firmware_header_v1_0 *v1_hdr =
- container_of(hdr, struct smc_firmware_header_v1_0,
header);
- const struct smc_firmware_header_v2_0 *v2_hdr =
- container_of(v1_hdr, struct smc_firmware_header_v2_0,
v1_0);
+ switch (version_minor) {
+ case 0:
+ v2_0_hdr = container_of(hdr, struct
smc_firmware_header_v2_0, v1_0.header);
+ DRM_DEBUG("ppt_offset_bytes: %u\n",
le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
+ DRM_DEBUG("ppt_size_bytes: %u\n",
le32_to_cpu(v2_0_hdr->ppt_size_bytes));
+ break;
+ case 1:
+ v2_1_hdr = container_of(hdr, struct
smc_firmware_header_v2_1, v1_0.header);
+ DRM_DEBUG("pptable_count: %u\n",
le32_to_cpu(v2_1_hdr->pptable_count));
+ DRM_DEBUG("pptable_entry_offset: %u\n",
le32_to_cpu(v2_1_hdr->pptable_entry_offset));
+ break;
+ default:
+ break;
+ }
- DRM_DEBUG("ppt_offset_bytes: %u\n",
le32_to_cpu(v2_hdr->ppt_offset_bytes));
- DRM_DEBUG("ppt_size_bytes: %u\n",
le32_to_cpu(v2_hdr->ppt_size_bytes));
} else {
DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major,
version_minor);
}
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: add missing clock gating info in amdgpu_pm_info
add missing clock gating informations in amdgpu_pm_info
1. AMD_CG_SUPPORT_VCN_MGCG
2. AMD_CG_SUPPORT_HDP_DS
3. AMD_CG_SUPPORT_HDP_SD
4. AMD_CG_SUPPORT_IH_CG
5. AMD_CG_SUPPORT_JPEG_MGCG
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index a33b1cc50008..7b6ef05a1d35 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -64,6 +64,11 @@ static const struct cg_flag_name clocks[] = {
{AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
{AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
+ {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
+ {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
+ {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
+ {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
+ {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock
Gating"},
{AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: cleanup debug information in amdgpu_set_pp_features()
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e57153d1fa24..a33b1cc50008 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -941,8 +941,6 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
if (ret)
return -EINVAL;
- pr_debug("featuremask = 0x%llx\n", featuremask);
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0) {
pm_runtime_put_autosuspend(ddev->dev);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: cleanup debug log in amdgpu_set_pp_features()
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e57153d1fa24..a33b1cc50008 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -941,8 +941,6 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
if (ret)
return -EINVAL;
- pr_debug("featuremask = 0x%llx\n", featuremask);
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0) {
pm_runtime_put_autosuspend(ddev->dev);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/swsmu: correct wrong feature bit mapping
1.
when smc feature bit isn't mapped,
the feature state isn't showed on sysfs node of pp_features.
2.
add pp_features table title
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 27 --
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index c30d3338825f..92b2ea4c197b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -431,10 +431,9 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
char *buf)
{
uint32_t feature_mask[2] = { 0 };
- int32_t feature_index = 0;
+ int feature_index = 0;
uint32_t count = 0;
- uint32_t sort_feature[SMU_FEATURE_COUNT];
- uint64_t hw_feature_count = 0;
+ int8_t sort_feature[SMU_FEATURE_COUNT];
size_t size = 0;
int ret = 0, i;
@@ -447,23 +446,31 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context
*smu,
size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
feature_mask[1], feature_mask[0]);
+ memset(sort_feature, -1, sizeof(sort_feature));
+
for (i = 0; i < SMU_FEATURE_COUNT; i++) {
feature_index = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_FEATURE,
i);
if (feature_index < 0)
continue;
+
sort_feature[feature_index] = i;
- hw_feature_count++;
}
- for (i = 0; i < hw_feature_count; i++) {
+ size += sprintf(buf + size, "%-2s. %-20s %-3s : %-s\n",
+ "No", "Feature", "Bit", "State");
+
+ for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+ if (sort_feature[i] < 0)
+ continue;
+
size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
- count++,
- smu_get_feature_name(smu, sort_feature[i]),
- i,
- !!smu_cmn_feature_is_enabled(smu,
sort_feature[i]) ?
- "enabled" : "disabled");
+ count++,
+ smu_get_feature_name(smu, sort_feature[i]),
+ i,
+ !!smu_cmn_feature_is_enabled(smu,
sort_feature[i]) ?
+ "enabled" : "disabled");
}
return size;
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: update module paramter doc of amdgpu_dpm
the vega20 isn't supported swsmu. Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 03f4aab1fe99..9d28054b8aae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -279,7 +279,7 @@ module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_ /** * DOC: dpm (int) * Override for dynamic power management setting - * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) + * (0 = disable, 1 = enable) * The default is -1 (auto). */ MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/swsmu: correct wrong feature bit mapping
1.
when smc feature bit isn't mapped,
the feature state isn't showed on sysfs node of pp_features.
2.
add pp_features table title
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 27 --
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index c30d3338825f..92b2ea4c197b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -431,10 +431,9 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
char *buf)
{
uint32_t feature_mask[2] = { 0 };
- int32_t feature_index = 0;
+ int feature_index = 0;
uint32_t count = 0;
- uint32_t sort_feature[SMU_FEATURE_COUNT];
- uint64_t hw_feature_count = 0;
+ int8_t sort_feature[SMU_FEATURE_COUNT];
size_t size = 0;
int ret = 0, i;
@@ -447,23 +446,31 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context
*smu,
size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
feature_mask[1], feature_mask[0]);
+ memset(sort_feature, -1, sizeof(sort_feature));
+
for (i = 0; i < SMU_FEATURE_COUNT; i++) {
feature_index = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_FEATURE,
i);
if (feature_index < 0)
continue;
+
sort_feature[feature_index] = i;
- hw_feature_count++;
}
- for (i = 0; i < hw_feature_count; i++) {
+ size += sprintf(buf + size, "%-2s. %-20s %-3s : %-s\n",
+ "No", "Feature", "Bit", "State");
+
+ for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+ if (sort_feature[i] < 0)
+ continue;
+
size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
- count++,
- smu_get_feature_name(smu, sort_feature[i]),
- i,
- !!smu_cmn_feature_is_enabled(smu,
sort_feature[i]) ?
- "enabled" : "disabled");
+ count++,
+ smu_get_feature_name(smu, sort_feature[i]),
+ i,
+ !!smu_cmn_feature_is_enabled(smu,
sort_feature[i]) ?
+ "enabled" : "disabled");
}
return size;
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/swsmu: Add missing feature map for sienna_cichlid
it will cause smu sysfs node of "pp_features" show error.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index b1a18fbb7682..85ae724c66d7 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -227,6 +227,7 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(DPM_MP0CLK),\
__SMU_DUMMY_MAP(DPM_LINK), \
__SMU_DUMMY_MAP(DPM_DCEFCLK), \
+ __SMU_DUMMY_MAP(DPM_XGMI), \
__SMU_DUMMY_MAP(DS_GFXCLK), \
__SMU_DUMMY_MAP(DS_SOCCLK), \
__SMU_DUMMY_MAP(DS_LCLK), \
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index c27806fd07e0..ca2abb2e5340 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -151,14 +151,17 @@ static struct cmn2asic_mapping
sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT
FEA_MAP(DPM_GFXCLK),
FEA_MAP(DPM_GFX_GPO),
FEA_MAP(DPM_UCLK),
+ FEA_MAP(DPM_FCLK),
FEA_MAP(DPM_SOCCLK),
FEA_MAP(DPM_MP0CLK),
FEA_MAP(DPM_LINK),
FEA_MAP(DPM_DCEFCLK),
+ FEA_MAP(DPM_XGMI),
FEA_MAP(MEM_VDDCI_SCALING),
FEA_MAP(MEM_MVDD_SCALING),
FEA_MAP(DS_GFXCLK),
FEA_MAP(DS_SOCCLK),
+ FEA_MAP(DS_FCLK),
FEA_MAP(DS_LCLK),
FEA_MAP(DS_DCEFCLK),
FEA_MAP(DS_UCLK),
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: remove gfxhub_v1_1_funcs set
remove duplicate gfxhub v1.1 function set.
put function of gfxhub_v1_1_get_xgmi_info to gfxhub v1_0 function set.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c | 13 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 10 +-
4 files changed, 5 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index fad887a66886..d83577b77a66 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -22,6 +22,7 @@
*/
#include "amdgpu.h"
#include "gfxhub_v1_0.h"
+#include "gfxhub_v1_1.h"
#include "gc/gc_9_0_offset.h"
#include "gc/gc_9_0_sh_mask.h"
@@ -412,4 +413,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {
.gart_disable = gfxhub_v1_0_gart_disable,
.set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,
.init = gfxhub_v1_0_init,
+ .get_xgmi_info = gfxhub_v1_1_get_xgmi_info,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
index 1e24b6d51e41..c0ab71df0d90 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
@@ -21,7 +21,6 @@
*
*/
#include "amdgpu.h"
-#include "gfxhub_v1_0.h"
#include "gfxhub_v1_1.h"
#include "gc/gc_9_2_1_offset.h"
@@ -29,7 +28,7 @@
#include "soc15_common.h"
-static int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
+int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
{
u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
u32 max_region =
@@ -67,13 +66,3 @@ static int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device
*adev)
return 0;
}
-
-const struct amdgpu_gfxhub_funcs gfxhub_v1_1_funcs = {
- .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,
- .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,
- .gart_enable = gfxhub_v1_0_gart_enable,
- .gart_disable = gfxhub_v1_0_gart_disable,
- .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,
- .init = gfxhub_v1_0_init,
- .get_xgmi_info = gfxhub_v1_1_get_xgmi_info,
-};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h
index ae5759ffbee3..d753cf28a0a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h
@@ -24,6 +24,6 @@
#ifndef __GFXHUB_V1_1_H__
#define __GFXHUB_V1_1_H__
-extern const struct amdgpu_gfxhub_funcs gfxhub_v1_1_funcs;
+int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 6e9de02d5455..33c34cae9f42 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1166,15 +1166,7 @@ static void gmc_v9_0_set_mmhub_funcs(struct
amdgpu_device *adev)
static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_ARCTURUS:
- case CHIP_VEGA20:
- adev->gfxhub.funcs = _v1_1_funcs;
- break;
- default:
- adev->gfxhub.funcs = _v1_0_funcs;
- break;
- }
+ adev->gfxhub.funcs = _v1_0_funcs;
}
static int gmc_v9_0_early_init(void *handle)
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amdgpu: add condition check for trace_amdgpu_cs()
v1:
add trace event enabled check to avoid nop loop when submit multi ibs
in amdgpu_cs_ioctl() function.
v2:
add a new wrapper function to trace all amdgpu cs ibs.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ffbcaf4bfb8b..1921e61a37b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1275,13 +1275,24 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
return r;
}
+static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)
+{
+ int i;
+
+ if (!trace_amdgpu_cs_enabled())
+ return;
+
+ for (i = 0; i < parser->job->num_ibs; i++)
+ trace_amdgpu_cs(parser, i);
+}
+
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
struct amdgpu_device *adev = dev->dev_private;
union drm_amdgpu_cs *cs = data;
struct amdgpu_cs_parser parser = {};
bool reserved_buffers = false;
- int i, r;
+ int r;
if (amdgpu_ras_intr_triggered())
return -EHWPOISON;
@@ -1319,8 +1330,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
reserved_buffers = true;
- for (i = 0; i < parser.job->num_ibs; i++)
- trace_amdgpu_cs(, i);
+ trace_amdgpu_cs_ibs();
r = amdgpu_cs_vm_handling();
if (r)
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: add condition check for trace_amdgpu_cs()
add trace event enabled check to avoid nop loop when submit multi ibs in amdgpu_cs_ioctl() function. Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index ffbcaf4bfb8b..409694f074ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1319,8 +1319,9 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) reserved_buffers = true; - for (i = 0; i < parser.job->num_ibs; i++) - trace_amdgpu_cs(, i); + if (trace_amdgpu_cs_enabled()) + for (i = 0; i < parser.job->num_ibs; i++) + trace_amdgpu_cs(, i); r = amdgpu_cs_vm_handling(); if (r) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix amdgpu_bo_release_notify() comment error
fix amdgpu_bo_release_notify() comment error. Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 3d95b3edb635..4cb750ed6851 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1301,7 +1301,7 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, } /** - * amdgpu_bo_move_notify - notification about a BO being released + * amdgpu_bo_release_notify - notification about a BO being released * @bo: pointer to a buffer object * * Wipes VRAM buffers whose contents should not be leaked before the -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: drop log message in amdgpu_dpm_baco_reset()
Reviewed-by: Kevin Wang
Best Regards,
Kevin
On 8/13/20 12:25 PM, Alex Deucher wrote:
The caller does this now for all reset types. This is now
a duplicate call.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 2082c0acd216..1c661c7ab49f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -1110,8 +1110,6 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev)
struct smu_context *smu = >smu;
int ret = 0;
- dev_info(adev->dev, "GPU BACO reset\n");
-
if (is_support_sw_smu(adev)) {
ret = smu_baco_enter(smu);
if (ret)
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: don't create entity when use cpu to update page table
the entity isn't needed when vm use cpu to update page table.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 ++
1 file changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 71e005cf2952..e15c29d613d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2802,20 +2802,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
spin_lock_init(>invalidated_lock);
INIT_LIST_HEAD(>freed);
-
- /* create scheduler entities for page table updates */
- r = drm_sched_entity_init(>immediate, DRM_SCHED_PRIORITY_NORMAL,
- adev->vm_manager.vm_pte_scheds,
- adev->vm_manager.vm_pte_num_scheds, NULL);
- if (r)
- return r;
-
- r = drm_sched_entity_init(>delayed, DRM_SCHED_PRIORITY_NORMAL,
- adev->vm_manager.vm_pte_scheds,
- adev->vm_manager.vm_pte_num_scheds, NULL);
- if (r)
- goto error_free_immediate;
-
vm->pte_support_ats = false;
vm->is_compute_context = false;
@@ -2835,10 +2821,25 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
!amdgpu_gmc_vram_full_visible(>gmc)),
"CPU update of VM recommended only for large BAR system\n");
- if (vm->use_cpu_for_update)
+ if (vm->use_cpu_for_update) {
vm->update_funcs = _vm_cpu_funcs;
- else
+ } else {
+ /* create scheduler entities for page table updates */
+ r = drm_sched_entity_init(>immediate,
DRM_SCHED_PRIORITY_NORMAL,
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds,
NULL);
+ if (r)
+ return r;
+
+ r = drm_sched_entity_init(>delayed,
DRM_SCHED_PRIORITY_NORMAL,
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds,
NULL);
+ if (r)
+ goto error_free_immediate;
+
vm->update_funcs = _vm_sdma_funcs;
+ }
+
vm->last_update = NULL;
vm->last_unlocked = dma_fence_get_stub();
@@ -2895,10 +2896,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
error_free_delayed:
dma_fence_put(vm->last_unlocked);
- drm_sched_entity_destroy(>delayed);
+ if (!vm->use_cpu_for_update)
+ drm_sched_entity_destroy(>delayed);
error_free_immediate:
- drm_sched_entity_destroy(>immediate);
+ if (!vm->use_cpu_for_update)
+ drm_sched_entity_destroy(>immediate);
return r;
}
@@ -3120,8 +3123,10 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct
amdgpu_vm *vm)
amdgpu_bo_unref();
WARN_ON(vm->root.base.bo);
- drm_sched_entity_destroy(>immediate);
- drm_sched_entity_destroy(>delayed);
+ if (!vm->use_cpu_for_update) {
+ drm_sched_entity_destroy(>immediate);
+ drm_sched_entity_destroy(>delayed);
+ }
if (!RB_EMPTY_ROOT(>va.rb_root)) {
dev_err(adev->dev, "still active bo inside vm\n");
--
2.27.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix uninit-value in arcturus_log_thermal_throttling_event()
when function arcturus_get_smu_metrics_data() call failed,
it will cause the variable "throttler_status" isn't initialized before use.
warning:
powerplay/arcturus_ppt.c:2268:24: warning: ‘throttler_status’ may be used
uninitialized in this function [-Wmaybe-uninitialized]
2268 | if (throttler_status & logging_label[throttler_idx].feature_mask) {
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index e58af84433c7..946dbc0db1b1 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2253,14 +2253,17 @@ static const struct throttling_logging_label {
};
static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
{
+ int ret;
int throttler_idx, throtting_events = 0, buf_idx = 0;
struct amdgpu_device *adev = smu->adev;
uint32_t throttler_status;
char log_buf[256];
- arcturus_get_smu_metrics_data(smu,
- METRICS_THROTTLER_STATUS,
- _status);
+ ret = arcturus_get_smu_metrics_data(smu,
+ METRICS_THROTTLER_STATUS,
+ _status);
+ if (ret)
+ return;
memset(log_buf, 0, sizeof(log_buf));
for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
--
2.27.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amd/swsmu: allow asic to handle sensor type by itself
1. allow asic to handle sensor type by itself.
2. if not, use smu common sensor to handle it.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 3b427fa099fe..55463e7a11e2 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1948,6 +1948,10 @@ int smu_read_sensor(struct smu_context *smu,
mutex_lock(>mutex);
+ if (smu->ppt_funcs->read_sensor)
+ if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
+ goto unlock;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
*((uint32_t *)data) = pstate_table->gfxclk_pstate.standard *
100;
@@ -1978,11 +1982,12 @@ int smu_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
- if (smu->ppt_funcs->read_sensor)
- ret = smu->ppt_funcs->read_sensor(smu, sensor, data,
size);
+ *size = 0;
+ ret = -EOPNOTSUPP;
break;
}
+unlock:
mutex_unlock(>mutex);
return ret;
--
2.27.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/swsmu: correct smu lock type on smu_read_sensor()
instead "mutex" with "sensor_lock" on smu_read_sensor().
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++--
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 2 --
5 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 55463e7a11e2..69d7f7de9adf 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1946,7 +1946,7 @@ int smu_read_sensor(struct smu_context *smu,
if (!data || !size)
return -EINVAL;
- mutex_lock(>mutex);
+ mutex_lock(>sensor_lock);
if (smu->ppt_funcs->read_sensor)
if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
@@ -1988,7 +1988,7 @@ int smu_read_sensor(struct smu_context *smu,
}
unlock:
- mutex_unlock(>mutex);
+ mutex_unlock(>sensor_lock);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index f13979687b9e..5e56509a8f54 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1066,7 +1066,6 @@ static int arcturus_read_sensor(struct smu_context *smu,
if (!data || !size)
return -EINVAL;
- mutex_lock(>sensor_lock);
switch (sensor) {
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
*(uint32_t *)data = pptable->FanMaximumRpm;
@@ -1109,7 +1108,6 @@ static int arcturus_read_sensor(struct smu_context *smu,
ret = -EOPNOTSUPP;
break;
}
- mutex_unlock(>sensor_lock);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 6aaf483858a0..ece0f2a37704 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1710,7 +1710,6 @@ static int navi10_read_sensor(struct smu_context *smu,
if(!data || !size)
return -EINVAL;
- mutex_lock(>sensor_lock);
switch (sensor) {
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
*(uint32_t *)data = pptable->FanMaximumRpm;
@@ -1749,7 +1748,6 @@ static int navi10_read_sensor(struct smu_context *smu,
ret = -EOPNOTSUPP;
break;
}
- mutex_unlock(>sensor_lock);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 575ae4be98a2..3f4de2c30bfc 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -950,7 +950,6 @@ static int renoir_read_sensor(struct smu_context *smu,
if (!data || !size)
return -EINVAL;
- mutex_lock(>sensor_lock);
switch (sensor) {
case AMDGPU_PP_SENSOR_GPU_LOAD:
ret = renoir_get_current_activity_percent(smu, sensor,
(uint32_t *)data);
@@ -974,7 +973,6 @@ static int renoir_read_sensor(struct smu_context *smu,
ret = -EOPNOTSUPP;
break;
}
- mutex_unlock(>sensor_lock);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dcc5d25a7894..d4e52866e04f 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1521,7 +1521,6 @@ static int sienna_cichlid_read_sensor(struct smu_context
*smu,
if(!data || !size)
return -EINVAL;
- mutex_lock(>sensor_lock);
switch (sensor) {
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
*(uint32_t *)data = pptable->FanMaximumRpm;
@@ -1560,7 +1559,6 @@ static int sienna_cichlid_read_sensor(struct smu_context
*smu,
ret = -EOPNOTSUPP;
break;
}
- mutex_unlock(>sensor_lock);
return ret;
}
--
2.27.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amd/smu: unify smu ppt callback marcos
v1: add the new macro "smu_ppt_xxx()" to unify smu callback interfaces
v2: rename the macro smu_ppt_xxx to smu_ppt_funcs.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/smu_internal.h | 267 ++-
1 file changed, 82 insertions(+), 185 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 880ef54884f8..afd786b6c0b4 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -25,191 +25,88 @@
#include "amdgpu_smu.h"
-#define smu_init_microcode(smu) \
- ((smu)->ppt_funcs->init_microcode ?
(smu)->ppt_funcs->init_microcode((smu)) : 0)
-#define smu_fini_microcode(smu) \
- ((smu)->ppt_funcs->fini_microcode ?
(smu)->ppt_funcs->fini_microcode((smu)) : 0)
-#define smu_init_smc_tables(smu) \
- ((smu)->ppt_funcs->init_smc_tables ?
(smu)->ppt_funcs->init_smc_tables((smu)) : 0)
-#define smu_fini_smc_tables(smu) \
- ((smu)->ppt_funcs->fini_smc_tables ?
(smu)->ppt_funcs->fini_smc_tables((smu)) : 0)
-#define smu_init_power(smu) \
- ((smu)->ppt_funcs->init_power ? (smu)->ppt_funcs->init_power((smu)) : 0)
-#define smu_fini_power(smu) \
- ((smu)->ppt_funcs->fini_power ? (smu)->ppt_funcs->fini_power((smu)) : 0)
-
-#define smu_setup_pptable(smu) \
- ((smu)->ppt_funcs->setup_pptable ?
(smu)->ppt_funcs->setup_pptable((smu)) : 0)
-#define smu_powergate_sdma(smu, gate) \
- ((smu)->ppt_funcs->powergate_sdma ?
(smu)->ppt_funcs->powergate_sdma((smu), (gate)) : 0)
-
-#define smu_get_vbios_bootup_values(smu) \
- ((smu)->ppt_funcs->get_vbios_bootup_values ?
(smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
-#define smu_check_fw_version(smu) \
- ((smu)->ppt_funcs->check_fw_version ?
(smu)->ppt_funcs->check_fw_version((smu)) : 0)
-#define smu_write_pptable(smu) \
- ((smu)->ppt_funcs->write_pptable ?
(smu)->ppt_funcs->write_pptable((smu)) : 0)
-#define smu_set_min_dcef_deep_sleep(smu, clk) \
- ((smu)->ppt_funcs->set_min_dcef_deep_sleep ?
(smu)->ppt_funcs->set_min_dcef_deep_sleep((smu), (clk)) : 0)
-#define smu_set_driver_table_location(smu) \
- ((smu)->ppt_funcs->set_driver_table_location ?
(smu)->ppt_funcs->set_driver_table_location((smu)) : 0)
-#define smu_set_tool_table_location(smu) \
- ((smu)->ppt_funcs->set_tool_table_location ?
(smu)->ppt_funcs->set_tool_table_location((smu)) : 0)
-#define smu_notify_memory_pool_location(smu) \
- ((smu)->ppt_funcs->notify_memory_pool_location ?
(smu)->ppt_funcs->notify_memory_pool_location((smu)) : 0)
-#define smu_gfx_off_control(smu, enable) \
- ((smu)->ppt_funcs->gfx_off_control ?
(smu)->ppt_funcs->gfx_off_control((smu), (enable)) : 0)
-
-#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
- ((smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk ?
(smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
-#define smu_system_features_control(smu, en) \
- ((smu)->ppt_funcs->system_features_control ?
(smu)->ppt_funcs->system_features_control((smu), (en)) : 0)
-#define smu_init_max_sustainable_clocks(smu) \
- ((smu)->ppt_funcs->init_max_sustainable_clocks ?
(smu)->ppt_funcs->init_max_sustainable_clocks((smu)) : 0)
-#define smu_set_default_od_settings(smu) \
- ((smu)->ppt_funcs->set_default_od_settings ?
(smu)->ppt_funcs->set_default_od_settings((smu)) : 0)
-
-#define smu_send_smc_msg_with_param(smu, msg, param, read_arg) \
- ((smu)->ppt_funcs->send_smc_msg_with_param?
(smu)->ppt_funcs->send_smc_msg_with_param((smu), (msg), (param), (read_arg)) :
0)
-
-static inline int smu_send_smc_msg(struct smu_context *smu, enum
smu_message_type msg, uint32_t *read_arg) {
- return smu_send_smc_msg_with_param(smu, msg, 0, read_arg);
-}
-
-#define smu_alloc_dpm_context(smu) \
- ((smu)->ppt_funcs->alloc_dpm_context ?
(smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
-#define smu_init_display_count(smu, count) \
- ((smu)->ppt_funcs->init_display_count ?
(smu)->ppt_funcs->init_display_count((smu), (count)) : 0)
-#define smu_feature_set_allowed_mask(smu) \
- ((smu)->ppt_funcs->set_allowed_mask?
(smu)->ppt_funcs->set_allowed_mask((smu)) : 0)
-#define smu_feature_get_enabled_mask(smu, mask, num) \
- ((smu)->ppt_funcs->get_enabled_mask?
(smu)->ppt_funcs->get_enabled_mask((smu), (mask), (num)) : 0)
-#define smu_is_dpm_running(smu) \
- ((smu)->ppt_funcs->is_dpm_running ?
(smu)->ppt_funcs->is_dpm_running((smu)) : 0)
-#define smu_notify_display_change(smu) \
- ((smu)->ppt_funcs->notify_display_change?
(smu)->ppt_fun
[PATCH] drm/amd/smu: unify pptable_func{} callback interface
the pptable_func callback sets should be has unify interface,
so use "smu" as the pptable_func interface first parameter.
fix interfaces:
1. i2c_eeprom_init
2. i2c_eeprom_fini
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 ++--
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++--
drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 16a107cd8b2d..b27d0b18eafa 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2338,7 +2338,7 @@ static bool arcturus_i2c_adapter_is_added(struct
i2c_adapter *control)
return control->dev.parent == >pdev->dev;
}
-static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
+static int arcturus_i2c_eeprom_control_init(struct smu_context *smu, struct
i2c_adapter *control)
{
struct amdgpu_device *adev = to_amdgpu_device(control);
int res;
@@ -2360,7 +2360,7 @@ static int arcturus_i2c_eeprom_control_init(struct
i2c_adapter *control)
return res;
}
-static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
+static void arcturus_i2c_eeprom_control_fini(struct smu_context *smu, struct
i2c_adapter *control)
{
if (!arcturus_i2c_adapter_is_added(control))
return;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 01afc8f07879..7b349e038972 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -491,8 +491,8 @@ struct pptable_funcs {
int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
int (*update_pcie_parameters)(struct smu_context *smu, uint32_t
pcie_gen_cap, uint32_t pcie_width_cap);
- int (*i2c_eeprom_init)(struct i2c_adapter *control);
- void (*i2c_eeprom_fini)(struct i2c_adapter *control);
+ int (*i2c_eeprom_init)(struct smu_context *smu, struct i2c_adapter
*control);
+ void (*i2c_eeprom_fini)(struct smu_context *smu, struct i2c_adapter
*control);
void (*get_unique_id)(struct smu_context *smu);
int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks
*clock_table);
int (*init_microcode)(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 149f5e50e619..880ef54884f8 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -200,9 +200,9 @@ static inline int smu_send_smc_msg(struct smu_context *smu,
enum smu_message_typ
((smu)->ppt_funcs->set_power_source ?
(smu)->ppt_funcs->set_power_source((smu), (power_src)) : 0)
#define smu_i2c_eeprom_init(smu, control) \
- ((smu)->ppt_funcs->i2c_eeprom_init ?
(smu)->ppt_funcs->i2c_eeprom_init((control)) : 0)
+ ((smu)->ppt_funcs->i2c_eeprom_init ?
(smu)->ppt_funcs->i2c_eeprom_init((smu), (control)) : 0)
#define smu_i2c_eeprom_fini(smu, control) \
- ((smu)->ppt_funcs->i2c_eeprom_fini ?
(smu)->ppt_funcs->i2c_eeprom_fini((control)) : 0)
+ ((smu)->ppt_funcs->i2c_eeprom_fini ?
(smu)->ppt_funcs->i2c_eeprom_fini((smu), (control)) : 0)
#define smu_get_unique_id(smu) \
((smu)->ppt_funcs->get_unique_id ?
(smu)->ppt_funcs->get_unique_id((smu)) : 0)
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amd/smu: unify pptable_func{} callback interface
the pptable_func callback sets should be has unify interface,
so use "smu" as the pptable_func interface first parameter.
fix interfaces:
1. i2c_eeprom_init
2. i2c_eeprom_fini
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 ++--
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++--
drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 16a107cd8b2d..b27d0b18eafa 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2338,7 +2338,7 @@ static bool arcturus_i2c_adapter_is_added(struct
i2c_adapter *control)
return control->dev.parent == >pdev->dev;
}
-static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
+static int arcturus_i2c_eeprom_control_init(struct smu_context *smu, struct
i2c_adapter *control)
{
struct amdgpu_device *adev = to_amdgpu_device(control);
int res;
@@ -2360,7 +2360,7 @@ static int arcturus_i2c_eeprom_control_init(struct
i2c_adapter *control)
return res;
}
-static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
+static void arcturus_i2c_eeprom_control_fini(struct smu_context *smu, struct
i2c_adapter *control)
{
if (!arcturus_i2c_adapter_is_added(control))
return;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 01afc8f07879..7b349e038972 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -491,8 +491,8 @@ struct pptable_funcs {
int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
int (*update_pcie_parameters)(struct smu_context *smu, uint32_t
pcie_gen_cap, uint32_t pcie_width_cap);
- int (*i2c_eeprom_init)(struct i2c_adapter *control);
- void (*i2c_eeprom_fini)(struct i2c_adapter *control);
+ int (*i2c_eeprom_init)(struct smu_context *smu, struct i2c_adapter
*control);
+ void (*i2c_eeprom_fini)(struct smu_context *smu, struct i2c_adapter
*control);
void (*get_unique_id)(struct smu_context *smu);
int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks
*clock_table);
int (*init_microcode)(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 149f5e50e619..880ef54884f8 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -200,9 +200,9 @@ static inline int smu_send_smc_msg(struct smu_context *smu,
enum smu_message_typ
((smu)->ppt_funcs->set_power_source ?
(smu)->ppt_funcs->set_power_source((smu), (power_src)) : 0)
#define smu_i2c_eeprom_init(smu, control) \
- ((smu)->ppt_funcs->i2c_eeprom_init ?
(smu)->ppt_funcs->i2c_eeprom_init((control)) : 0)
+ ((smu)->ppt_funcs->i2c_eeprom_init ?
(smu)->ppt_funcs->i2c_eeprom_init((smu), (control)) : 0)
#define smu_i2c_eeprom_fini(smu, control) \
- ((smu)->ppt_funcs->i2c_eeprom_fini ?
(smu)->ppt_funcs->i2c_eeprom_fini((control)) : 0)
+ ((smu)->ppt_funcs->i2c_eeprom_fini ?
(smu)->ppt_funcs->i2c_eeprom_fini((smu), (control)) : 0)
#define smu_get_unique_id(smu) \
((smu)->ppt_funcs->get_unique_id ?
(smu)->ppt_funcs->get_unique_id((smu)) : 0)
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/smu: unify smu ppt callback marcos
add the new macro "smu_ppt_xxx()" to unify smu callback interfaces
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/smu_internal.h | 266 ++-
1 file changed, 82 insertions(+), 184 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 880ef54884f8..0f9841bcdcb8 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -25,191 +25,89 @@
#include "amdgpu_smu.h"
-#define smu_init_microcode(smu) \
- ((smu)->ppt_funcs->init_microcode ?
(smu)->ppt_funcs->init_microcode((smu)) : 0)
-#define smu_fini_microcode(smu) \
- ((smu)->ppt_funcs->fini_microcode ?
(smu)->ppt_funcs->fini_microcode((smu)) : 0)
-#define smu_init_smc_tables(smu) \
- ((smu)->ppt_funcs->init_smc_tables ?
(smu)->ppt_funcs->init_smc_tables((smu)) : 0)
-#define smu_fini_smc_tables(smu) \
- ((smu)->ppt_funcs->fini_smc_tables ?
(smu)->ppt_funcs->fini_smc_tables((smu)) : 0)
-#define smu_init_power(smu) \
- ((smu)->ppt_funcs->init_power ? (smu)->ppt_funcs->init_power((smu)) : 0)
-#define smu_fini_power(smu) \
- ((smu)->ppt_funcs->fini_power ? (smu)->ppt_funcs->fini_power((smu)) : 0)
-
-#define smu_setup_pptable(smu) \
- ((smu)->ppt_funcs->setup_pptable ?
(smu)->ppt_funcs->setup_pptable((smu)) : 0)
-#define smu_powergate_sdma(smu, gate) \
- ((smu)->ppt_funcs->powergate_sdma ?
(smu)->ppt_funcs->powergate_sdma((smu), (gate)) : 0)
-
-#define smu_get_vbios_bootup_values(smu) \
- ((smu)->ppt_funcs->get_vbios_bootup_values ?
(smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
-#define smu_check_fw_version(smu) \
- ((smu)->ppt_funcs->check_fw_version ?
(smu)->ppt_funcs->check_fw_version((smu)) : 0)
-#define smu_write_pptable(smu) \
- ((smu)->ppt_funcs->write_pptable ?
(smu)->ppt_funcs->write_pptable((smu)) : 0)
-#define smu_set_min_dcef_deep_sleep(smu, clk) \
- ((smu)->ppt_funcs->set_min_dcef_deep_sleep ?
(smu)->ppt_funcs->set_min_dcef_deep_sleep((smu), (clk)) : 0)
-#define smu_set_driver_table_location(smu) \
- ((smu)->ppt_funcs->set_driver_table_location ?
(smu)->ppt_funcs->set_driver_table_location((smu)) : 0)
-#define smu_set_tool_table_location(smu) \
- ((smu)->ppt_funcs->set_tool_table_location ?
(smu)->ppt_funcs->set_tool_table_location((smu)) : 0)
-#define smu_notify_memory_pool_location(smu) \
- ((smu)->ppt_funcs->notify_memory_pool_location ?
(smu)->ppt_funcs->notify_memory_pool_location((smu)) : 0)
-#define smu_gfx_off_control(smu, enable) \
- ((smu)->ppt_funcs->gfx_off_control ?
(smu)->ppt_funcs->gfx_off_control((smu), (enable)) : 0)
-
-#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
- ((smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk ?
(smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
-#define smu_system_features_control(smu, en) \
- ((smu)->ppt_funcs->system_features_control ?
(smu)->ppt_funcs->system_features_control((smu), (en)) : 0)
-#define smu_init_max_sustainable_clocks(smu) \
- ((smu)->ppt_funcs->init_max_sustainable_clocks ?
(smu)->ppt_funcs->init_max_sustainable_clocks((smu)) : 0)
-#define smu_set_default_od_settings(smu) \
- ((smu)->ppt_funcs->set_default_od_settings ?
(smu)->ppt_funcs->set_default_od_settings((smu)) : 0)
-
-#define smu_send_smc_msg_with_param(smu, msg, param, read_arg) \
- ((smu)->ppt_funcs->send_smc_msg_with_param?
(smu)->ppt_funcs->send_smc_msg_with_param((smu), (msg), (param), (read_arg)) :
0)
-
-static inline int smu_send_smc_msg(struct smu_context *smu, enum
smu_message_type msg, uint32_t *read_arg) {
- return smu_send_smc_msg_with_param(smu, msg, 0, read_arg);
-}
-
-#define smu_alloc_dpm_context(smu) \
- ((smu)->ppt_funcs->alloc_dpm_context ?
(smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
-#define smu_init_display_count(smu, count) \
- ((smu)->ppt_funcs->init_display_count ?
(smu)->ppt_funcs->init_display_count((smu), (count)) : 0)
-#define smu_feature_set_allowed_mask(smu) \
- ((smu)->ppt_funcs->set_allowed_mask?
(smu)->ppt_funcs->set_allowed_mask((smu)) : 0)
-#define smu_feature_get_enabled_mask(smu, mask, num) \
- ((smu)->ppt_funcs->get_enabled_mask?
(smu)->ppt_funcs->get_enabled_mask((smu), (mask), (num)) : 0)
-#define smu_is_dpm_running(smu) \
- ((smu)->ppt_funcs->is_dpm_running ?
(smu)->ppt_funcs->is_dpm_running((smu)) : 0)
-#define smu_notify_display_change(smu) \
- ((smu)->ppt_funcs->notify_display_change?
(smu)->ppt_funcs->notify_display_change((smu)) : 0)
-#define smu_set_defa
[PATCH v2] drm/amdgpu: fix device attribute node create failed with multi gpu
the origin design will use varible of "attr->states" to save node
supported states on current gpu device, but for multi gpu device, when
probe second gpu device, the driver will check attribute node states
from previous gpu device wthether to create attribute node.
it will cause other gpu device create attribute node faild.
1. add member attr_list into amdgpu_device to link supported device attribute
node.
2. add new structure "struct amdgpu_device_attr_entry{}" to track device
attribute state.
3. drop member "states" from amdgpu_device_attr.
v2:
1. move "attr_list" into amdgpu_pm and rename to "pm_attr_list".
2. refine create & remove device node functions parameter.
fix:
drm/amdgpu: optimize amdgpu device attribute code
Signed-off-by: Kevin Wang
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 85 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 13 ++--
3 files changed, 58 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 956f6c710670..6a8aae70a0e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -450,6 +450,7 @@ struct amdgpu_pm {
/* Used for I2C access to various EEPROMs on relevant ASICs */
struct i2c_adapter smu_i2c;
+ struct list_headpm_attr_list;
};
#define R600_SSTU_DFLT 0
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 55815b899942..dd5be3bb4bb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1725,7 +1725,7 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
};
static int default_attr_update(struct amdgpu_device *adev, struct
amdgpu_device_attr *attr,
- uint32_t mask)
+ uint32_t mask, enum amdgpu_device_attr_states
*states)
{
struct device_attribute *dev_attr = >dev_attr;
const char *attr_name = dev_attr->attr.name;
@@ -1733,7 +1733,7 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
enum amd_asic_type asic_type = adev->asic_type;
if (!(attr->flags & mask)) {
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
return 0;
}
@@ -1741,34 +1741,34 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
if (asic_type <= CHIP_VEGA10)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
if (asic_type <= CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
if (asic_type < CHIP_VEGA20)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
if (asic_type == CHIP_ARCTURUS)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
(!is_support_sw_smu(adev) && hwmgr->od_enabled))
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pcie_bw)) {
/* PCIe Perf counters won't work on APU nodes */
if (adev->flags & AMD_IS_APU)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(unique_id)) {
if (!adev->unique_id)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_features)) {
if (adev->flags & AMD_IS_APU || asic_type <= CHIP_VEGA10)
- attr->states = ATTR_S
[PATCH] drm/amdgpu: fix device attribute node create failed with multi gpu
the origin design will use varible of "attr->states" to save node
supported states on current gpu device, but for multi gpu device, when
probe second gpu device, the driver will check attribute node states
from previous gpu device wthether to create attribute node.
it will cause other gpu device create attribute node faild.
1. add member attr_list into amdgpu_device to link supported device attribute
node.
2. add new structure "struct amdgpu_device_attr_entry{}" to track device
attribute state.
fix:
drm/amdgpu: optimize amdgpu device attribute code
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 75 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 13 +++--
3 files changed, 52 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bfce0931f9c1..b84146339ea3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -995,6 +995,7 @@ struct amdgpu_device {
charserial[16];
struct amdgpu_autodump autodump;
+ struct list_headattr_list;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 55815b899942..ac99aa0a16a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1725,7 +1725,7 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
};
static int default_attr_update(struct amdgpu_device *adev, struct
amdgpu_device_attr *attr,
- uint32_t mask)
+ uint32_t mask, enum amdgpu_device_attr_states
*states)
{
struct device_attribute *dev_attr = >dev_attr;
const char *attr_name = dev_attr->attr.name;
@@ -1733,7 +1733,7 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
enum amd_asic_type asic_type = adev->asic_type;
if (!(attr->flags & mask)) {
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
return 0;
}
@@ -1741,34 +1741,34 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
if (asic_type <= CHIP_VEGA10)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
if (asic_type <= CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
if (asic_type < CHIP_VEGA20)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
if (asic_type == CHIP_ARCTURUS)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
(!is_support_sw_smu(adev) && hwmgr->od_enabled))
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pcie_bw)) {
/* PCIe Perf counters won't work on APU nodes */
if (adev->flags & AMD_IS_APU)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(unique_id)) {
if (!adev->unique_id)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_features)) {
if (adev->flags & AMD_IS_APU || asic_type <= CHIP_VEGA10)
- attr->states = ATTR_STATE_UNSUPPORTED;
+ *states = ATTR_STATE_UNSUPPORTED;
}
if (asic_type == CHIP_ARCTURUS) {
@@ -1794,22 +1794,24 @@ static int amdgpu_device_attr_create(struct
amdgpu_device *adev,
[PATCH 2/2] drm/amd/powerplay: remove the support of vega20 from swsmu
by default, vega20 will use legacy powerplay driver.
in order to maintain the code conveniently in the future,
remove the support of vega20 from swsmu.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c|9 +-
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |1 -
drivers/gpu/drm/amd/powerplay/smu_v11_0.c |9 -
drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 3288 -
drivers/gpu/drm/amd/powerplay/vega20_ppt.h| 179 -
5 files changed, 1 insertion(+), 3485 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/powerplay/vega20_ppt.c
delete mode 100644 drivers/gpu/drm/amd/powerplay/vega20_ppt.h
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 9ad6f0f3aada..7894dd09c9f5 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -29,7 +29,6 @@
#include "smu_v11_0.h"
#include "smu_v12_0.h"
#include "atom.h"
-#include "vega20_ppt.h"
#include "arcturus_ppt.h"
#include "navi10_ppt.h"
#include "renoir_ppt.h"
@@ -567,9 +566,7 @@ int smu_update_table(struct smu_context *smu, enum
smu_table_id table_index, int
bool is_support_sw_smu(struct amdgpu_device *adev)
{
- if (adev->asic_type == CHIP_VEGA20)
- return (amdgpu_dpm == 2) ? true : false;
- else if (adev->asic_type >= CHIP_ARCTURUS)
+ if (adev->asic_type >= CHIP_ARCTURUS)
return true;
return false;
@@ -759,10 +756,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
smu->od_enabled = true;
switch (adev->asic_type) {
- case CHIP_VEGA20:
- adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
- vega20_set_ppt_funcs(smu);
- break;
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 6b3b451a8018..5c6bfe76d596 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -26,7 +26,6 @@
#include "amdgpu_smu.h"
#define SMU11_DRIVER_IF_VERSION_INV 0x
-#define SMU11_DRIVER_IF_VERSION_VG20 0x13
#define SMU11_DRIVER_IF_VERSION_ARCT 0x14
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index b6a7467260a6..960360918e7a 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -46,7 +46,6 @@
#include "asic_reg/smuio/smuio_11_0_0_offset.h"
#include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
-MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
@@ -148,9 +147,6 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
struct amdgpu_firmware_info *ucode = NULL;
switch (adev->asic_type) {
- case CHIP_VEGA20:
- chip_name = "vega20";
- break;
case CHIP_ARCTURUS:
chip_name = "arcturus";
break;
@@ -270,9 +266,6 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
smu_debug = (smu_version >> 0) & 0xff;
switch (smu->adev->asic_type) {
- case CHIP_VEGA20:
- smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VG20;
- break;
case CHIP_ARCTURUS:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
break;
@@ -1364,8 +1357,6 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu,
bool enable)
struct amdgpu_device *adev = smu->adev;
switch (adev->asic_type) {
- case CHIP_VEGA20:
- break;
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
deleted file mode 100644
index 61923530b2e4..
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ /dev/null
@@ -1,3288 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright not
[PATCH 1/2] drm/amd/powerplay: remove the support of xgmi pstate on vega20 from swsmu
the vega20 asic uses legacy powerplay driver by default.
1. cleanup is_support_sw_smu_xgmi() function.
(ony use for vega20 xgmi pstate check)
2. by default, the vega20 set xgmi pstate by legacy powerplay routine.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 4 ++--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 ---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 -
3 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index f36b58a7f485..65472b3dd815 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -1162,7 +1162,7 @@ int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
{
int ret = 0;
- if (is_support_sw_smu_xgmi(adev))
+ if (is_support_sw_smu(adev))
ret = smu_set_xgmi_pstate(>smu, pstate);
else if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->set_xgmi_pstate)
@@ -1197,4 +1197,4 @@ int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device
*adev, bool en)
return smu_allow_xgmi_power_down(smu, en);
return 0;
-}
\ No newline at end of file
+}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 1abc4be6b72e..9ad6f0f3aada 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -575,17 +575,6 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
return false;
}
-bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
-{
- if (!is_support_sw_smu(adev))
- return false;
-
- if (adev->asic_type == CHIP_VEGA20)
- return true;
-
- return false;
-}
-
int smu_sys_get_pp_table(struct smu_context *smu, void **table)
{
struct smu_table_context *smu_table = >smu_table;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 4d1c2a44a8b6..bac7e13dc801 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -675,7 +675,6 @@ int smu_update_table(struct smu_context *smu, enum
smu_table_id table_index, int
void *table_data, bool drv2smu);
bool is_support_sw_smu(struct amdgpu_device *adev);
-bool is_support_sw_smu_xgmi(struct amdgpu_device *adev);
int smu_reset(struct smu_context *smu);
int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
void *data, uint32_t *size);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/4] drm/amdgpu: cleanup unnecessary virt sriov check in amdgpu attribute
the amdgpu device attribute node will be created accordding to sriov vf
mode at runtime.
cleanup unnecessary sriov check in attribute operation function.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 105 -
1 file changed, 105 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index b75362bf0742..bc7de2f62d12 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -163,9 +163,6 @@ static ssize_t amdgpu_get_power_dpm_state(struct device
*dev,
enum amd_pm_state_type pm;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -199,9 +196,6 @@ static ssize_t amdgpu_set_power_dpm_state(struct device
*dev,
enum amd_pm_state_type state;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
-
if (strncmp("battery", buf, strlen("battery")) == 0)
state = POWER_STATE_TYPE_BATTERY;
else if (strncmp("balanced", buf, strlen("balanced")) == 0)
@@ -303,9 +297,6 @@ static ssize_t
amdgpu_get_power_dpm_force_performance_level(struct device *dev,
enum amd_dpm_forced_level level = 0xff;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -343,9 +334,6 @@ static ssize_t
amdgpu_set_power_dpm_force_performance_level(struct device *dev,
enum amd_dpm_forced_level current_level = 0xff;
int ret = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
-
if (strncmp("low", buf, strlen("low")) == 0) {
level = AMD_DPM_FORCED_LEVEL_LOW;
} else if (strncmp("high", buf, strlen("high")) == 0) {
@@ -475,9 +463,6 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
enum amd_pm_state_type pm = 0;
int i = 0, ret = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -514,9 +499,6 @@ static ssize_t amdgpu_get_pp_force_state(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
-
if (adev->pp_force_state_enabled)
return amdgpu_get_pp_cur_state(dev, attr, buf);
else
@@ -534,9 +516,6 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
unsigned long idx;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
-
if (strlen(buf) == 1)
adev->pp_force_state_enabled = false;
else if (is_support_sw_smu(adev))
@@ -592,9 +571,6 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
char *table = NULL;
int size, ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -634,9 +610,6 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
int ret = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -739,9 +712,6 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device
*dev,
const char delimiter[3] = {' ', '\n', '\0'};
uint32_t type;
- if (amdgpu_sriov_vf(adev))
- return -EINVAL;
-
if (count > 127)
return -EINVAL;
@@ -831,9 +801,6 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device
*dev,
ssize_t size;
int ret;
- if (amdgpu_sriov_vf(adev))
- return 0;
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -883,9 +850,6 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
uint64_t featuremask;
int ret;
- if (amdgpu_sriov_vf(adev))
- return -EINVAL;
-
ret = kstrtou64(buf, 0, );
if (ret)
return -EINVAL;
@@ -926,9 +890,6 @@ static ssize_t amdgpu_ge
[PATCH 2/4] drm/amdgpu: optimize amdgpu device attribute code
unified amdgpu device attribute node functions:
1. add some helper functions to create amdgpu device attribute node.
2. create device node according to device attr flags on different VF mode.
3. rename some functions name to adapt a new interface.
v2:
1. remove ATTR_STATE_DEAD, ATTR_STATE_ALIVE enum.
2. rename callback function perform to attr_update.
3. modify some variable names
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 494 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 46 +++
2 files changed, 262 insertions(+), 278 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c762deb5abc7..b75362bf0742 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -154,9 +154,9 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum
amd_pp_sensors senso
*
*/
-static ssize_t amdgpu_get_dpm_state(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -189,10 +189,10 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" :
"performance");
}
-static ssize_t amdgpu_set_dpm_state(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t count)
+static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -294,9 +294,9 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev,
*
*/
-static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
+ struct
device_attribute *attr,
+ char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -332,10 +332,10 @@ static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device *dev,
"unknown");
}
-static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- struct device_attribute
*attr,
- const char *buf,
- size_t count)
+static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
+ struct
device_attribute *attr,
+ const char *buf,
+ size_t count)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -873,10 +873,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device
*dev,
* the corresponding bit from original ppfeature masks and input the
* new ppfeature masks.
*/
-static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t count)
+static ssize_t amdgpu_set_pp_features(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -917,9 +917,9 @@ static ssize_t amdgpu_set_pp_feature_status(struct device
*dev,
return count;
}
-static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t amdgpu_get_pp_features(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu
[PATCH 4/4] drm/amdgpu: cleanup sriov mode check in internal swsmu driver
cleanup unnecessary check in internal swsmu driver:
1. cleanup amdgpu_sriov_is_pp_one_vf() check logic.
2. cleanup amdgpu_sriov_vf() check logic.
3. add sw smu ip block according to different vf mode.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/nv.c | 29 +++-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 170 ---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 7 +-
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 +-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c| 24 ---
5 files changed, 102 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 9c42316c47c0..cef516b89a34 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -452,6 +452,7 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
int nv_set_ip_blocks(struct amdgpu_device *adev)
{
int r;
+ enum amdgpu_sriov_vf_mode vf_mode;
adev->nbio.funcs = _v2_3_funcs;
adev->nbio.hdp_flush_reg = _v2_3_hdp_flush_reg;
@@ -494,12 +495,22 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _v10_1_ip_block);
break;
case CHIP_NAVI12:
+ vf_mode = amdgpu_virt_get_sriov_vf_mode(adev);
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
- amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ switch (vf_mode) {
+ case SRIOV_VF_MODE_BARE_METAL:
+ case SRIOV_VF_MODE_ONE_VF:
+ amdgpu_device_ip_block_add(adev,
_v11_0_ip_block);
+ break;
+ case SRIOV_VF_MODE_MULTI_VF:
+ default:
+ break;
+ }
+ }
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -508,9 +519,17 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
#endif
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
amdgpu_device_ip_block_add(adev, _v5_0_ip_block);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
- !amdgpu_sriov_vf(adev))
- amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ switch (vf_mode) {
+ case SRIOV_VF_MODE_BARE_METAL:
+ case SRIOV_VF_MODE_ONE_VF:
+ amdgpu_device_ip_block_add(adev,
_v11_0_ip_block);
+ break;
+ case SRIOV_VF_MODE_MULTI_VF:
+ default:
+ break;
+ }
+ }
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 607ff0270aee..8b305498a084 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -569,10 +569,9 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
{
if (adev->asic_type == CHIP_VEGA20)
return (amdgpu_dpm == 2) ? true : false;
- else if (adev->asic_type >= CHIP_ARCTURUS) {
- if (amdgpu_sriov_is_pp_one_vf(adev) || !amdgpu_sriov_vf(adev))
- return true;
- }
+ else if (adev->asic_type >= CHIP_ARCTURUS)
+ return true;
+
return false;
}
@@ -1131,59 +1130,58 @@ static int smu_smc_table_hw_init(struct smu_context
*smu,
return ret;
/* smu_dump_pptable(smu); */
- if (!amdgpu_sriov_vf(adev)) {
- /*
-* Copy pptable bo in the vram to smc with SMU MSGs such as
-* SetDriverDramAddr and TransferTableDram2Smu.
-*/
- ret = smu_write_pptable(smu);
- if (ret)
- return ret;
-
- /* issue Run*Btc msg */
- ret = smu_run_btc(smu);
- if (ret)
- return ret;
- ret = smu_feature_set_allowed_mask(smu);
- if (ret)
- re
[PATCH 1/4] drm/amdgpu: add amdgpu_virt_get_vf_mode helper function
the swsmu or powerplay(hwmgr) need to handle task according to different VF
mode,
this function to help query vf mode.
vf mode:
1. SRIOV_VF_MODE_BARE_METAL: the driver work on host OS (PF)
2. SRIOV_VF_MODE_ONE_VF: the driver work on guest OS with one VF
3. SRIOV_VF_MODE_MULTI_VF : the driver work on guest OS with multi VF
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 8
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index cbbb8d02535a..f3b38c9e04ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -370,3 +370,19 @@ void amdgpu_virt_disable_access_debugfs(struct
amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
}
+
+enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device
*adev)
+{
+ enum amdgpu_sriov_vf_mode mode;
+
+ if (amdgpu_sriov_vf(adev)) {
+ if (amdgpu_sriov_is_pp_one_vf(adev))
+ mode = SRIOV_VF_MODE_ONE_VF;
+ else
+ mode = SRIOV_VF_MODE_MULTI_VF;
+ } else {
+ mode = SRIOV_VF_MODE_BARE_METAL;
+ }
+
+ return mode;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index de27308802c9..b90e822cebd7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -35,6 +35,12 @@
/* tonga/fiji use this offset */
#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
+enum amdgpu_sriov_vf_mode {
+ SRIOV_VF_MODE_BARE_METAL = 0,
+ SRIOV_VF_MODE_ONE_VF,
+ SRIOV_VF_MODE_MULTI_VF,
+};
+
struct amdgpu_mm_table {
struct amdgpu_bo*bo;
uint32_t*cpu_addr;
@@ -323,4 +329,6 @@ void amdgpu_detect_virtualization(struct amdgpu_device
*adev);
bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
+
+enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device
*adev);
#endif
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/3] drm/amdgpu: cleanup sriov mode check in internal swsmu driver
cleanup unnecessary check in internal swsmu driver:
1. cleanup amdgpu_sriov_is_pp_one_vf() check logic.
2. cleanup amdgpu_sriov_vf() check logic.
3. add sw smu ip block according to different vf mode.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/nv.c | 29 +++-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 170 ---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 7 +-
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 +-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c| 24 ---
5 files changed, 102 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 9c42316c47c0..cef516b89a34 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -452,6 +452,7 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
int nv_set_ip_blocks(struct amdgpu_device *adev)
{
int r;
+ enum amdgpu_sriov_vf_mode vf_mode;
adev->nbio.funcs = _v2_3_funcs;
adev->nbio.hdp_flush_reg = _v2_3_hdp_flush_reg;
@@ -494,12 +495,22 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _v10_1_ip_block);
break;
case CHIP_NAVI12:
+ vf_mode = amdgpu_virt_get_sriov_vf_mode(adev);
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
- amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ switch (vf_mode) {
+ case SRIOV_VF_MODE_BARE_METAL:
+ case SRIOV_VF_MODE_ONE_VF:
+ amdgpu_device_ip_block_add(adev,
_v11_0_ip_block);
+ break;
+ case SRIOV_VF_MODE_MULTI_VF:
+ default:
+ break;
+ }
+ }
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -508,9 +519,17 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
#endif
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
amdgpu_device_ip_block_add(adev, _v5_0_ip_block);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
- !amdgpu_sriov_vf(adev))
- amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ switch (vf_mode) {
+ case SRIOV_VF_MODE_BARE_METAL:
+ case SRIOV_VF_MODE_ONE_VF:
+ amdgpu_device_ip_block_add(adev,
_v11_0_ip_block);
+ break;
+ case SRIOV_VF_MODE_MULTI_VF:
+ default:
+ break;
+ }
+ }
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 607ff0270aee..8b305498a084 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -569,10 +569,9 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
{
if (adev->asic_type == CHIP_VEGA20)
return (amdgpu_dpm == 2) ? true : false;
- else if (adev->asic_type >= CHIP_ARCTURUS) {
- if (amdgpu_sriov_is_pp_one_vf(adev) || !amdgpu_sriov_vf(adev))
- return true;
- }
+ else if (adev->asic_type >= CHIP_ARCTURUS)
+ return true;
+
return false;
}
@@ -1131,59 +1130,58 @@ static int smu_smc_table_hw_init(struct smu_context
*smu,
return ret;
/* smu_dump_pptable(smu); */
- if (!amdgpu_sriov_vf(adev)) {
- /*
-* Copy pptable bo in the vram to smc with SMU MSGs such as
-* SetDriverDramAddr and TransferTableDram2Smu.
-*/
- ret = smu_write_pptable(smu);
- if (ret)
- return ret;
-
- /* issue Run*Btc msg */
- ret = smu_run_btc(smu);
- if (ret)
- return ret;
- ret = smu_feature_set_allowed_mask(smu);
- if (ret)
- re
[PATCH 2/3] drm/amdgpu: optimize amdgpu device attribute code
unified amdgpu device attribute node functions:
1. add some helper functions to create amdgpu device attribute node.
2. create device node according to device attr flags on different VF mode.
3. rename some functions name to adapt a new interface.
4. remove unneccessary virt mode check in inernal functions (xxx_show,
xxx_store).
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 577 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 48 ++
2 files changed, 271 insertions(+), 354 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c762deb5abc7..367ac79418b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -154,18 +154,15 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev,
enum amd_pp_sensors senso
*
*/
-static ssize_t amdgpu_get_dpm_state(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
enum amd_pm_state_type pm;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -189,19 +186,16 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" :
"performance");
}
-static ssize_t amdgpu_set_dpm_state(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t count)
+static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
enum amd_pm_state_type state;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
-
if (strncmp("battery", buf, strlen("battery")) == 0)
state = POWER_STATE_TYPE_BATTERY;
else if (strncmp("balanced", buf, strlen("balanced")) == 0)
@@ -294,18 +288,15 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev,
*
*/
-static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
+ struct
device_attribute *attr,
+ char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
enum amd_dpm_forced_level level = 0xff;
int ret;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return 0;
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -332,10 +323,10 @@ static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device *dev,
"unknown");
}
-static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- struct device_attribute
*attr,
- const char *buf,
- size_t count)
+static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
+ struct
device_attribute *attr,
+ const char *buf,
+ size_t count)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -343,9 +334,6 @@ static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device *dev,
enum amd_dpm_forced_level current_level = 0xff;
int ret = 0;
- if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
- return -EINVAL;
-
if (strncmp("low", buf, strlen("low&
[PATCH 1/3] drm/amdgpu: add amdgpu_virt_get_vf_mode helper function
the swsmu or powerplay(hwmgr) need to handle task according to different VF
mode,
this function to help query vf mode.
vf mode:
1. SRIOV_VF_MODE_BARE_METAL: the driver work on host OS (PF)
2. SRIOV_VF_MODE_ONE_VF: the driver work on guest OS with one VF
3. SRIOV_VF_MODE_MULTI_VF : the driver work on guest OS with multi VF
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 8
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index cbbb8d02535a..f3b38c9e04ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -370,3 +370,19 @@ void amdgpu_virt_disable_access_debugfs(struct
amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
}
+
+enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device
*adev)
+{
+ enum amdgpu_sriov_vf_mode mode;
+
+ if (amdgpu_sriov_vf(adev)) {
+ if (amdgpu_sriov_is_pp_one_vf(adev))
+ mode = SRIOV_VF_MODE_ONE_VF;
+ else
+ mode = SRIOV_VF_MODE_MULTI_VF;
+ } else {
+ mode = SRIOV_VF_MODE_BARE_METAL;
+ }
+
+ return mode;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index de27308802c9..b90e822cebd7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -35,6 +35,12 @@
/* tonga/fiji use this offset */
#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
+enum amdgpu_sriov_vf_mode {
+ SRIOV_VF_MODE_BARE_METAL = 0,
+ SRIOV_VF_MODE_ONE_VF,
+ SRIOV_VF_MODE_MULTI_VF,
+};
+
struct amdgpu_mm_table {
struct amdgpu_bo*bo;
uint32_t*cpu_addr;
@@ -323,4 +329,6 @@ void amdgpu_detect_virtualization(struct amdgpu_device
*adev);
bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
+
+enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device
*adev);
#endif
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: cleanup not_vf & pp_not_vf in powerplay
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 14 +++---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 6 +++---
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index fc31499c2e5c..5d22a80c4dea 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -47,7 +47,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
return -ENOMEM;
hwmgr->adev = adev;
- hwmgr->not_vf = !amdgpu_sriov_vf(adev);
+ hwmgr->vf_mode = amdgpu_virt_get_sriov_vf_mode(adev);
hwmgr->device = amdgpu_cgs_create_device(adev);
mutex_init(>smu_lock);
mutex_init(>msg_lock);
@@ -1438,12 +1438,12 @@ static int pp_get_asic_baco_capability(void *handle,
bool *cap)
if (!hwmgr)
return -EINVAL;
- if (!(hwmgr->not_vf && amdgpu_dpm) ||
- !hwmgr->hwmgr_func->get_asic_baco_capability)
+ if (!hwmgr->pm_en)
return 0;
mutex_lock(>smu_lock);
- hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
+ if (hwmgr->hwmgr_func->get_asic_baco_capability)
+ hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
mutex_unlock(>smu_lock);
return 0;
@@ -1473,12 +1473,12 @@ static int pp_set_asic_baco_state(void *handle, int
state)
if (!hwmgr)
return -EINVAL;
- if (!(hwmgr->not_vf && amdgpu_dpm) ||
- !hwmgr->hwmgr_func->set_asic_baco_state)
+ if (!hwmgr->pm_en)
return 0;
mutex_lock(>smu_lock);
- hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
+ if (hwmgr->hwmgr_func->set_asic_baco_state)
+ hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum
BACO_STATE)state);
mutex_unlock(>smu_lock);
return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index f48fdc7f0382..e2379efcd621 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -221,9 +221,9 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
{
int ret = 0;
- hwmgr->pp_one_vf = amdgpu_sriov_is_pp_one_vf((struct amdgpu_device
*)hwmgr->adev);
- hwmgr->pm_en = (amdgpu_dpm && (hwmgr->not_vf || hwmgr->pp_one_vf))
- ? true : false;
+ hwmgr->pm_en = (amdgpu_dpm && vf_mode == SRIOV_VF_MODE_NORMAL)
+ ? true : false;
+
if (!hwmgr->pm_en)
return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 15ed6cbdf366..9edb70933c46 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -742,6 +742,7 @@ struct pp_hwmgr {
bool not_vf;
bool pm_en;
bool pp_one_vf;
+ enum amdgpu_sriov_vf_mode vf_mode;
struct mutex smu_lock;
struct mutex msg_lock;
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: clean up unused variable about ring lru
clean up unused variable:
1. ring_lru_list
2. ring_lru_list_lock
related-commit:
drm/amdgpu: remove ring lru handling
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ---
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 94dff899248d..e8ab3dde6a66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -953,9 +953,6 @@ struct amdgpu_device {
/* link all shadow bo */
struct list_headshadow_list;
struct mutexshadow_list_lock;
- /* keep an lru list of rings by HW IP */
- struct list_headring_lru_list;
- spinlock_t ring_lru_list_lock;
/* record hw reset is performed */
bool has_hw_reset;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 71ea56e220ae..38eb736091d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2990,9 +2990,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
INIT_LIST_HEAD(>shadow_list);
mutex_init(>shadow_list_lock);
- INIT_LIST_HEAD(>ring_lru_list);
- spin_lock_init(>ring_lru_list_lock);
-
INIT_DELAYED_WORK(>delayed_init_work,
amdgpu_device_delayed_init_work_handler);
INIT_DELAYED_WORK(>gfx.gfx_off_delay_work,
--
2.26.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix hpd bo size calculation error
the HPD bo size calculation error. the "mem.size" can't present actual BO size all time. Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 7f9ac1a14e6f..91c82383b016 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1113,7 +1113,7 @@ static int gfx_v10_0_mec_init(struct amdgpu_device *adev) return r; } - memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); + memset(hpd, 0, mec_hpd_size); amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index fb567cf5671b..01b22dad52fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1946,7 +1946,7 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev) return r; } - memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); + memset(hpd, 0, mec_hpd_size); amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/swsmu: clean up unused header in swsmu
clean up unused header in swsmu driver stack: 1. pp_debug.h 2. amd_pcie.h 3. soc15_common.h Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 - drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 -- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 1 - drivers/gpu/drm/amd/powerplay/smu_v11_0.c| 1 - drivers/gpu/drm/amd/powerplay/smu_v12_0.c| 1 - drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1 - 7 files changed, 10 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index f18e3fadbc26..8de8436f0839 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -23,15 +23,12 @@ #include #include -#include "pp_debug.h" #include "amdgpu.h" #include "amdgpu_smu.h" #include "smu_internal.h" -#include "soc15_common.h" #include "smu_v11_0.h" #include "smu_v12_0.h" #include "atom.h" -#include "amd_pcie.h" #include "vega20_ppt.h" #include "arcturus_ppt.h" #include "navi10_ppt.h" diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c index cc4427ebf169..61596e8d522c 100644 --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c @@ -21,7 +21,6 @@ * */ -#include "pp_debug.h" #include #include "amdgpu.h" #include "amdgpu_smu.h" diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 6e41f3c9ff1b..d66dfa7410b6 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -21,7 +21,6 @@ * */ -#include "pp_debug.h" #include #include #include "amdgpu.h" @@ -31,7 +30,6 @@ #include "amdgpu_atomfirmware.h" #include "smu_v11_0.h" #include "smu11_driver_if_navi10.h" -#include "soc15_common.h" #include "atom.h" #include "navi10_ppt.h" #include "smu_v11_0_pptable.h" diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index 653faadaafb3..7bf52ecba01d 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c @@ -24,7 +24,6 @@ #include "amdgpu.h" #include "amdgpu_smu.h" #include "smu_internal.h" -#include "soc15_common.h" #include "smu_v12_0_ppsmc.h" #include "smu12_driver_if.h" #include "smu_v12_0.h" diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 3a5d00573d2c..4fd77c7cfc80 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -26,7 +26,6 @@ #define SMU_11_0_PARTIAL_PPTABLE -#include "pp_debug.h" #include "amdgpu.h" #include "amdgpu_smu.h" #include "smu_internal.h" diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c index d52e624f16d3..169ebdad87b8 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c @@ -20,7 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "pp_debug.h" #include #include "amdgpu.h" #include "amdgpu_smu.h" diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index d7fa8c02c166..49ff3756bd9f 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -21,7 +21,6 @@ * */ -#include "pp_debug.h" #include #include "amdgpu.h" #include "amdgpu_smu.h" -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/swSMU/navi: add feature toggles for more things
Reviewed-by: Kevin Wang
Best Regards,
Kevin
On 10/9/19 9:17 PM, Alex Deucher wrote:
> Add toggles for more power features. Helpful in debugging.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 24 --
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index a583cf87b514..8e1f3be8ba6f 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -328,11 +328,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> memset(feature_mask, 0, sizeof(uint32_t) * num);
>
> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
> - | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
> - | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
> | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
> - | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
> - | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
> | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
> | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
> | FEATURE_MASK(FEATURE_PPT_BIT)
> @@ -342,8 +338,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
> | FEATURE_MASK(FEATURE_THERMAL_BIT)
> | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
> - | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
> - | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
> | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
> | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
> | FEATURE_MASK(FEATURE_BACO_BIT)
> @@ -352,11 +346,29 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
> | FEATURE_MASK(FEATURE_FW_CTF_BIT);
>
> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> +
> + if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
> +
> + if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
> +
> + if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
> +
> if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
>
> + if (adev->pm.pp_feature & PP_ULV_MASK)
> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
> +
> + if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
> +
> if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
> /* TODO: remove it once fw fix the bug */
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix null pointer deref in firmware header printing
On 9/5/19 5:41 PM, Yuan, Xiaojie wrote: > When CE's ucode_id(8) is used to get sdma_hdr, we will be accessing an > unallocated amdgpu_firmware_info instance. > > This issue appears on rhel7.7 with gcc 4.8.5. Newer compilers might have > optimized out such 'defined but not referenced' variable. > > [ 1120.798564] BUG: unable to handle kernel NULL pointer dereference at > 000a > [ 1120.806703] IP: [] psp_np_fw_load+0x1e3/0x390 [amdgpu] > [ 1120.813693] PGD 8002603ff067 PUD 271b8d067 PMD 0 > [ 1120.818931] Oops: [#1] SMP > [ 1120.822245] Modules linked in: amdgpu(OE+) amdkcl(OE) amd_iommu_v2 > amdttm(OE) amd_sched(OE) xt_CHECKSUM ipt_MASQUERADE nf_nat_masquerade_ipv4 > tun bridge stp llc devlink ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 > ipt_REJECT nf_reject_ipv4 xt_conntrack ebtable_nat ip6table_nat > nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle > ip6table_security ip6table_raw iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 > nf_nat_ipv4 nf_nat iptable_mangle iptable_security iptable_raw nf_conntrack > libcrc32c ip_set nfnetlink ebtable_filter ebtables ip6table_filter ip6_tables > iptable_filter sunrpc dm_mirror dm_region_hash dm_log dm_mod intel_pmc_core > intel_powerclamp coretemp intel_rapl joydev kvm_intel eeepc_wmi asus_wmi kvm > sparse_keymap iTCO_wdt irqbypass rfkill crc32_pclmul snd_hda_codec_realtek > mxm_wmi ghash_clmulni_intel intel_wmi_thunderbolt iTCO_vendor_support > snd_hda_codec_generic snd_hda_codec_hdmi aesni_intel lrw gf128mul glue_helper > ablk_helper sg cryptd pcspkr snd_hda_intel snd_hda_codec snd_hda_core > snd_hwdep snd_seq snd_seq_device snd_pcm snd_timer snd pinctrl_sunrisepoint > pinctrl_intel soundcore acpi_pad mei_me wmi mei i2c_i801 pcc_cpufreq > ip_tables ext4 mbcache jbd2 sd_mod crc_t10dif crct10dif_generic i915 > i2c_algo_bit iosf_mbi drm_kms_helper e1000e syscopyarea sysfillrect sysimgblt > fb_sys_fops ahci libahci drm ptp libata crct10dif_pclmul crct10dif_common > crc32c_intel serio_raw pps_core drm_panel_orientation_quirks video i2c_hid > [ 1120.954136] CPU: 4 PID: 2426 Comm: modprobe Tainted: G OE > 3.10.0-1062.el7.x86_64 #1 > [ 1120.964390] Hardware name: System manufacturer System Product Name/Z170-A, > BIOS 1302 11/09/2015 > [ 1120.973321] task: 991ef1e3c1c0 ti: 991ee625c000 task.ti: > 991ee625c000 > [ 1120.981020] RIP: 0010:[] [] > psp_np_fw_load+0x1e3/0x390 [amdgpu] > [ 1120.990483] RSP: 0018:991ee625f950 EFLAGS: 00010202 > [ 1120.995935] RAX: 0002 RBX: 991edf6b2d38 RCX: > 991edf6a > [ 1121.003391] RDX: RSI: 991f01d13898 RDI: > c110afb3 > [ 1121.010706] RBP: 991ee625f9b0 R08: R09: > > [ 1121.018029] R10: 04c4 R11: 991ee625f64e R12: > 991edf6b3220 > [ 1121.025353] R13: 991edf6a R14: 0008 R15: > 991edf6b2d30 > [ 1121.032666] FS: 7f97b0c0b740() GS:991f01d0() > knlGS: > [ 1121.041000] CS: 0010 DS: ES: CR0: 80050033 > [ 1121.046880] CR2: 000a CR3: 00025e604000 CR4: > 003607e0 > [ 1121.054239] DR0: DR1: DR2: > > [ 1121.061631] DR3: DR6: fffe0ff0 DR7: > 0400 > [ 1121.068938] Call Trace: > [ 1121.071494] [] psp_hw_init+0x218/0x270 [amdgpu] > [ 1121.077886] [] amdgpu_device_fw_loading+0xe8/0x160 > [amdgpu] > [ 1121.085296] [] ? vega10_ih_irq_init+0x4bc/0x730 [amdgpu] > [ 1121.092534] [] amdgpu_device_init+0x1495/0x1c90 [amdgpu] > [ 1121.099675] [] amdgpu_driver_load_kms+0x8b/0x2f0 > [amdgpu] > [ 1121.106888] [] drm_dev_register+0x12f/0x1d0 [drm] > [ 1121.113419] [] ? pci_enable_device_flags+0xe8/0x140 > [ 1121.120183] [] amdgpu_pci_probe+0xca/0x170 [amdgpu] > [ 1121.126919] [] local_pci_probe+0x4a/0xb0 > [ 1121.132622] [] pci_device_probe+0x109/0x160 > [ 1121.138607] [] driver_probe_device+0xc5/0x3e0 > [ 1121.144766] [] __driver_attach+0x93/0xa0 > [ 1121.150507] [] ? __device_attach+0x50/0x50 > [ 1121.156422] [] bus_for_each_dev+0x75/0xc0 > [ 1121.162213] [] driver_attach+0x1e/0x20 > [ 1121.167771] [] bus_add_driver+0x200/0x2d0 > [ 1121.173590] [] driver_register+0x64/0xf0 > [ 1121.179345] [] __pci_register_driver+0xa5/0xc0 > [ 1121.185593] [] ? 0xc099efff > [ 1121.190914] [] amdgpu_init+0xa4/0xb0 [amdgpu] > [ 1121.197101] [] do_one_initcall+0xba/0x240 > [ 1121.202901] [] load_module+0x271a/0x2bb0 > [ 1121.208598] [] ? ddebug_proc_write+0x100/0x100 > [ 1121.214894] [] SyS_init_module+0xef/0x140 > [ 1121.220698] [] system_call_fastpath+0x25/0x2a > [ 1121.226870] Code: b4 01 60 a2 00 00 31 c0 e8 83 60 33 e4 41 8b 47 08 48 8b > 4d d0 48 c7 c7 b3 af 10 c1 48 69 c0 68 07 00 00 48 8b 84 01 60 a2 00 00 <48> > 8b 70 08 31 c0 48 89 75 c8 e8 56 60 33 e4 48 8b 4d d0 48 c7 > [ 1121.247422] RIP [] psp_np_fw_load+0x1e3/0x390 [amdgpu] > [
Re: [PATCH] drm/amd/powerplay: fix 'unusedd variable' compile warning
Reviewed-by: Kevin Wang
On 9/5/19 5:30 PM, Quan, Evan wrote:
> Reviewed-by: Evan Quan
>
>> -Original Message-
>> From: Yuan, Xiaojie
>> Sent: 2019年9月5日 17:26
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Feng, Kenneth ; Quan, Evan
>> ; Wang, Kevin(Yang) ;
>> Yuan, Xiaojie
>> Subject: [PATCH] drm/amd/powerplay: fix 'unusedd variable' compile
>> warning
>>
>> Signed-off-by: Xiaojie Yuan
>> ---
>> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 --
>> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 --
>> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 --
>> drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 2 --
>> 4 files changed, 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
>> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
>> index 6e8eb0f94c8b..1c6732847185 100644
>> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
>> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
>> @@ -1931,7 +1931,5 @@ static const struct pptable_funcs
>> arcturus_ppt_funcs = {
>>
>> void arcturus_set_ppt_funcs(struct smu_context *smu) {
>> -struct smu_table_context *smu_table = >smu_table;
>> -
>> smu->ppt_funcs = _ppt_funcs;
>> }
>> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
>> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
>> index e3add8b59291..16634e657589 100644
>> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
>> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
>> @@ -1630,7 +1630,5 @@ static const struct pptable_funcs navi10_ppt_funcs
>> = {
>>
>> void navi10_set_ppt_funcs(struct smu_context *smu) {
>> -struct smu_table_context *smu_table = >smu_table;
>> -
>> smu->ppt_funcs = _ppt_funcs;
>> }
>> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
>> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
>> index b7fa8b158ff2..a5cf846b50d4 100644
>> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
>> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
>> @@ -257,8 +257,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
>>
>> void renoir_set_ppt_funcs(struct smu_context *smu) {
>> -struct smu_table_context *smu_table = >smu_table;
>> -
>> smu->ppt_funcs = _ppt_funcs;
>> smu->smc_if_version = SMU12_DRIVER_IF_VERSION; } diff --git
>> a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
>> b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
>> index 18d1b432f719..929f61891dfa 100644
>> --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
>> +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
>> @@ -3180,7 +3180,5 @@ static const struct pptable_funcs vega20_ppt_funcs
>> = {
>>
>> void vega20_set_ppt_funcs(struct smu_context *smu) {
>> -struct smu_table_context *smu_table = >smu_table;
>> -
>> smu->ppt_funcs = _ppt_funcs;
>> }
>> --
>> 2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/powerplay: update cached feature enablement status
Hi Evan,
this is know issue for me.
i think we should add update feature mask cached operation into
smu_feature_update_enable_state function.
Best Regards,
Kevin
On 8/21/19 5:24 PM, Evan Quan wrote:
> Need to update in cache feature enablement status after pp_feature
> settings. Another fix for the commit below:
> drm/amd/powerplay: implment sysfs feature status function in smu
>
> Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index c663d25db5ab..04867cafb322 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -96,11 +96,13 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context
> *smu, char *buf)
>
> int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
> {
> + struct smu_feature *feature = >smu_feature;
> int ret = 0;
> uint32_t feature_mask[2] = { 0 };
> uint64_t feature_2_enabled = 0;
> uint64_t feature_2_disabled = 0;
> uint64_t feature_enables = 0;
> + uint64_t feature_id;
>
> ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> if (ret)
> @@ -115,11 +117,25 @@ int smu_sys_set_pp_feature_mask(struct smu_context
> *smu, uint64_t new_mask)
> ret = smu_feature_update_enable_state(smu, feature_2_enabled,
> true);
> if (ret)
> return ret;
> +
> + mutex_lock(>mutex);
> + for (feature_id = 0; feature_id < 64; feature_id++) {
> + if (feature_2_enabled & (1ULL << feature_id))
> + test_and_set_bit(feature_id, feature->enabled);
> + }
> + mutex_unlock(>mutex);
> }
> if (feature_2_disabled) {
> ret = smu_feature_update_enable_state(smu, feature_2_disabled,
> false);
> if (ret)
> return ret;
> +
> + mutex_lock(>mutex);
> + for (feature_id = 0; feature_id < 64; feature_id++) {
> + if (feature_2_disabled & (1ULL << feature_id))
> + test_and_clear_bit(feature_id,
> feature->enabled);
> + }
> + mutex_unlock(>mutex);
> }
>
> return ret;
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs
sure, i know, I feel this is not a good way to do code when other asics have
similar problems.
we'd better add a helper function to check which sysfs interface is supported
for each asic.
or move these sysfs interface to asic file to create.
anyway, we can optimize this logic later.
Reviewed-by: Kevin Wang <mailto:kevin1.w...@amd.com>
Best Regards,
Kevin
On 8/16/19 3:52 PM, Quan, Evan wrote:
Bascially, we should not expose the sysfs interface for those features not
supported by the ASIC.
As, there are some tools/tests which judges whether the feature is supported by
the existence of the file.
This can fix some test failure in rocm test suit.
Regards,
Evan
From: Wang, Kevin(Yang) <mailto:kevin1.w...@amd.com>
Sent: Friday, August 16, 2019 3:16 PM
To: Quan, Evan <mailto:evan.q...@amd.com>;
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only
through sysfs
I don't recommend it. What's the problem if we keep it the way it is?
maybe other asic also has same problems, if do it, the other asic should add a
condition in there too.
eg: navi10 don't support sensor of "pp_dpm_pcie".
Best Regards,
Kevin
From: amd-gfx
mailto:amd-gfx-boun...@lists.freedesktop.org>>
on behalf of Evan Quan mailto:evan.q...@amd.com>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Quan, Evan mailto:evan.q...@amd.com>>
Subject: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only
through sysfs
Do not expose those unsupported clock domains through sysfs on
Arcturus.
Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c5642be9b44b..7accf2c7f8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
DRM_ERROR("failed to create device file
pp_dpm_socclk\n");
return ret;
}
- ret = device_create_file(adev->dev, _attr_pp_dpm_dcefclk);
- if (ret) {
- DRM_ERROR("failed to create device file
pp_dpm_dcefclk\n");
- return ret;
+ if (adev->asic_type != CHIP_ARCTURUS) {
+ ret = device_create_file(adev->dev,
_attr_pp_dpm_dcefclk);
+ if (ret) {
+ DRM_ERROR("failed to create device file
pp_dpm_dcefclk\n");
+ return ret;
+ }
}
}
if (adev->asic_type >= CHIP_VEGA20) {
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
return ret;
}
}
- ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
- if (ret) {
- DRM_ERROR("failed to create device file pp_dpm_pcie\n");
- return ret;
+ if (adev->asic_type != CHIP_ARCTURUS) {
+ ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_dpm_pcie\n");
+ return ret;
+ }
}
ret = device_create_file(adev->dev, _attr_pp_sclk_od);
if (ret) {
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
device_remove_file(adev->dev, _attr_pp_dpm_mclk);
if (adev->asic_type >= CHIP_VEGA10) {
device_remove_file(adev->dev, _attr_pp_dpm_socclk);
- device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
+ if (adev->asic_type != CHIP_ARCTURUS)
+ device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
}
- device_remove_file(adev->dev, _attr_pp_dpm_pcie);
+ if (adev->asic_type != CHIP_ARCTURUS)
+ device_remove_file(adev->dev, _attr_pp_dpm_pcie);
if (adev->asic_type >= CHIP_VEGA20)
device_remove_file(adev->dev, _attr_pp_dpm_fclk);
device_remove_file(adev->dev, _attr_pp_sclk_od);
--
2.22.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amd/powerplay: remove redundancy debug log about smu unsupported features
Reviewed-by: Kevin Wang
On 8/12/19 4:22 PM, Chengming Gui wrote:
> remove redundancy debug log about smu unsupported features
>
> Signed-off-by: Chengming Gui
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index e6fcbdf..03ce871 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -215,7 +215,6 @@ static int arcturus_get_smu_feature_index(struct
> smu_context *smc, uint32_t inde
>
> mapping = arcturus_feature_mask_map[index];
> if (!(mapping.valid_mapping)) {
> - pr_warn("Unsupported SMU feature: %d\n", index);
> return -EINVAL;
> }
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amd/powerplay: add arcturus_is_dpm_running function for arcturus
Reviewed-by: Kevin Wang
On 8/12/19 4:22 PM, Chengming Gui wrote:
> add arcturus_is_dpm_running function
>
> Signed-off-by: Chengming Gui
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index 03ce871..9107beb 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -51,6 +51,15 @@
> #define SMU_FEATURES_HIGH_MASK 0x
> #define SMU_FEATURES_HIGH_SHIFT 32
>
> +#define SMC_DPM_FEATURE ( \
> + FEATURE_DPM_PREFETCHER_MASK | \
> + FEATURE_DPM_GFXCLK_MASK | \
> + FEATURE_DPM_UCLK_MASK | \
> + FEATURE_DPM_SOCCLK_MASK | \
> + FEATURE_DPM_MP0CLK_MASK | \
> + FEATURE_DPM_FCLK_MASK | \
> + FEATURE_DPM_XGMI_MASK)
> +
> /* possible frequency drift (1Mhz) */
> #define EPSILON 1
>
> @@ -1873,6 +1882,17 @@ static void arcturus_dump_pptable(struct smu_context
> *smu)
>
> }
>
> +static bool arcturus_is_dpm_running(struct smu_context *smu)
> +{
> + int ret = 0;
> + uint32_t feature_mask[2];
> + unsigned long feature_enabled;
> + ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> + feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
> +((uint64_t)feature_mask[1] << 32));
> + return !!(feature_enabled & SMC_DPM_FEATURE);
> +}
> +
> static const struct pptable_funcs arcturus_ppt_funcs = {
> /* translate smu index into arcturus specific index */
> .get_smu_msg_index = arcturus_get_smu_msg_index,
> @@ -1910,6 +1930,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> /* debug (internal used) */
> .dump_pptable = arcturus_dump_pptable,
> .get_power_limit = arcturus_get_power_limit,
> + .is_dpm_running = arcturus_is_dpm_running,
> };
>
> void arcturus_set_ppt_funcs(struct smu_context *smu)
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 24/26] drm/amdgpu: add RAS callback for gfx
On 8/1/19 1:58 AM, Alex Deucher wrote:
> From: Dennis Li
>
> Add functions for RAS error inject and query error counter
>
> Signed-off-by: Dennis Li
> Reviewed-by: Tao Zhou
> Reviewed-by: Hawking Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 530 +++-
> 2 files changed, 531 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 1199b5828b90..554a59b3c4a6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -196,6 +196,8 @@ struct amdgpu_gfx_funcs {
> uint32_t *dst);
> void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
>u32 queue, u32 vmid);
> + int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
> + int (*query_ras_error_count) (struct amdgpu_device *adev, void
> *ras_error_status);
> };
>
> struct amdgpu_ngg_buf {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index fba552b93cc8..d7902e782be4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -318,6 +318,135 @@ enum ta_ras_gfx_subblock {
> TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
> TA_RAS_BLOCK__GFX_MAX
> };
> +
> +struct ras_gfx_subblock {
> + unsigned char *name;
> + int ta_subblock;
> + int supported_error_type;
> +};
> +
> +#define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d)
> \
> + [AMDGPU_RAS_BLOCK__##subblock] = { \
> + #subblock, \
> + TA_RAS_BLOCK__##subblock, \
> + ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \
> + }
> +
> +static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
> + AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1),
> + AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1),
> +
Re: [PATCH] drm/amd/powerplay: sort feature status index by asic feature id for smu
ping...
please help me review it , thanks.
BR
Kevin
On 7/31/19 3:51 PM, Wang, Kevin(Yang) wrote:
> before this change, the pp_feature sysfs show feature enable state by
> logic feature id, it is not easy to read.
> this change will sort pp_features show index by asic feature id.
>
> before:
> features high: 0x0623 low: 0xb3cdaffb
> 00. DPM_PREFETCHER ( 0) : enabeld
> 01. DPM_GFXCLK ( 1) : enabeld
> 02. DPM_UCLK ( 3) : enabeld
> 03. DPM_SOCCLK ( 4) : enabeld
> 04. DPM_MP0CLK ( 5) : enabeld
> 05. DPM_LINK ( 6) : enabeld
> 06. DPM_DCEFCLK ( 7) : enabeld
> 07. DS_GFXCLK(10) : enabeld
> 08. DS_SOCCLK(11) : enabeld
> 09. DS_LCLK (12) : disabled
> 10. PPT (23) : enabeld
> 11. TDC (24) : enabeld
> 12. THERMAL (33) : enabeld
> 13. RM (35) : disabled
> ..
>
> after:
> features high: 0x0623 low: 0xb3cdaffb
> 00. DPM_PREFETCHER ( 0) : enabeld
> 01. DPM_GFXCLK ( 1) : enabeld
> 02. DPM_GFX_PACE ( 2) : disabled
> 03. DPM_UCLK ( 3) : enabeld
> 04. DPM_SOCCLK ( 4) : enabeld
> 05. DPM_MP0CLK ( 5) : enabeld
> 06. DPM_LINK ( 6) : enabeld
> 07. DPM_DCEFCLK ( 7) : enabeld
> 08. MEM_VDDCI_SCALING( 8) : enabeld
> 09. MEM_MVDD_SCALING ( 9) : enabeld
> 10. DS_GFXCLK(10) : enabeld
> 11. DS_SOCCLK(11) : enabeld
> 12. DS_LCLK (12) : disabled
> 13. DS_DCEFCLK (13) : enabeld
> ..
>
> Signed-off-by: Kevin Wang
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index eabe8a6d0eb7..9e256aa3b357 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -62,6 +62,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu,
> char *buf)
> uint32_t feature_mask[2] = { 0 };
> int32_t feature_index = 0;
> uint32_t count = 0;
> + uint32_t sort_feature[SMU_FEATURE_COUNT];
> + uint64_t hw_feature_count = 0;
>
> ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> if (ret)
> @@ -74,11 +76,17 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context
> *smu, char *buf)
> feature_index = smu_feature_get_index(smu, i);
> if (feature_index < 0)
> continue;
> + sort_feature[feature_index] = i;
> + hw_feature_count++;
> + }
> +
> + for (i = 0; i < hw_feature_count; i++) {
> size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
> count++,
> -smu_get_feature_name(smu, i),
> -feature_index,
> -!!smu_feature_is_enabled(smu, i) ? "enabeld" :
> "disabled");
> +smu_get_feature_name(smu, sort_feature[i]),
> +i,
> +!!smu_feature_is_enabled(smu, sort_feature[i]) ?
> +"enabeld" : "disabled");
> }
>
> failed:
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amd/powerplay: support power profile retrieval and setting on arcturus
On 7/31/19 11:39 AM, Evan Quan wrote:
> Enable arcturus power profile retrieval and setting.
>
> Change-Id: I85447ba9ca7de8e197840f76ce3745363c4133a6
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 69
> 1 file changed, 69 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index c3f9487276c0..47d015035906 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -1503,6 +1503,73 @@ static int arcturus_get_power_limit(struct smu_context
> *smu,
> return 0;
> }
>
> +static int arcturus_get_power_profile_mode(struct smu_context *smu,
> +char *buf)
> +{
> + static const char *profile_name[] = {
> + "BOOTUP_DEFAULT",
> + "3D_FULL_SCREEN",
> + "POWER_SAVING",
> + "VIDEO",
> + "VR",
> + "COMPUTE",
> + "CUSTOM"};
> + uint32_t i, size = 0;
> + int16_t workload_type = 0;
> +
> + if (!smu->pm_enabled || !buf)
> + return -EINVAL;
> +
> + for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
> + /*
> + * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
> + * Not all profile modes are supported on arcturus.
> + */
> + workload_type = smu_workload_get_type(smu, i);
> + if (workload_type < 0)
> + continue;
> +
> + size += sprintf(buf + size, "%2d %14s%s\n",
> + i, profile_name[i], (i == smu->power_profile_mode) ?
> "*" : " ");
> + }
> +
> + return size;
> +}
> +
> +static int arcturus_set_power_profile_mode(struct smu_context *smu,
> +long *input,
> +uint32_t size)
> +{
> + int workload_type = 0;
> + uint32_t profile_mode = input[size];
> +
> + if (!smu->pm_enabled)
> + return -EINVAL;
> +
> + if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
> + pr_err("Invalid power profile mode %d\n", profile_mode);
> + return -EINVAL;
> + }
> +
> + /*
> + * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
> + * Not all profile modes are supported on arcturus.
> + */
> + workload_type = smu_workload_get_type(smu, profile_mode);
> + if (workload_type < 0) {
> + pr_err("Unsupported power profile mode %d on arcturus\n",
> profile_mode);
> + return -EINVAL;
> + }
> +
> + smu_send_smc_msg_with_param(smu,
> + SMU_MSG_SetWorkloadMask,
> + 1 << workload_type);
[kevin]:
please d check return value, after send message succeed, then modify
power_profile_mode value.
if send message failed, you can't update power_profile_mode value.
after fixed:
Reviewed-by: Kevin Wang
> +
> + smu->power_profile_mode = profile_mode;
> +
> + return 0;
> +}
> +
> static void arcturus_dump_pptable(struct smu_context *smu)
> {
> struct smu_table_context *table_context = >smu_table;
> @@ -1968,6 +2035,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .force_dpm_limit_value = arcturus_force_dpm_limit_value,
> .unforce_dpm_levels = arcturus_unforce_dpm_levels,
> .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
> + .get_power_profile_mode = arcturus_get_power_profile_mode,
> + .set_power_profile_mode = arcturus_set_power_profile_mode,
> /* debug (internal used) */
> .dump_pptable = arcturus_dump_pptable,
> .get_power_limit = arcturus_get_power_limit,
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amd/powerplay: enable SW SMU power profile switch support in KFD
Reviewed-by: Kevin Wang
BR
Kevin
On 7/31/19 11:39 AM, Evan Quan wrote:
> Hook up the SW SMU power profile switch in KFD routine.
>
> Change-Id: I41e53762cdc7504285de89f30e3e6e2bb396b953
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 8 +++--
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 36 +++
> .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 ++
> 3 files changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index 43b11879713d..9c5dcaa8fa48 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -672,8 +672,12 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd,
> bool idle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
>
> - if (adev->powerplay.pp_funcs &&
> - adev->powerplay.pp_funcs->switch_power_profile)
> + if (is_support_sw_smu(adev))
> + smu_switch_power_profile(>smu,
> + PP_SMC_POWER_PROFILE_COMPUTE,
> + !idle);
> + else if (adev->powerplay.pp_funcs &&
> + adev->powerplay.pp_funcs->switch_power_profile)
> amdgpu_dpm_switch_power_profile(adev,
> PP_SMC_POWER_PROFILE_COMPUTE,
> !idle);
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index d99a8aa0defb..55ccb4e6a6fb 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1447,6 +1447,42 @@ int smu_handle_task(struct smu_context *smu,
> return ret;
> }
>
> +int smu_switch_power_profile(struct smu_context *smu,
> + enum PP_SMC_POWER_PROFILE type,
> + bool en)
> +{
> + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> + long workload;
> + uint32_t index;
> +
> + if (!smu->pm_enabled)
> + return -EINVAL;
> +
> + if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
> + return -EINVAL;
> +
> + mutex_lock(>mutex);
> +
> + if (!en) {
> + smu->workload_mask &= ~(1 << smu->workload_prority[type]);
> + index = fls(smu->workload_mask);
> + index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 :
> 0;
> + workload = smu->workload_setting[index];
> + } else {
> + smu->workload_mask |= (1 << smu->workload_prority[type]);
> + index = fls(smu->workload_mask);
> + index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
> + workload = smu->workload_setting[index];
> + }
> +
> + if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
> + smu_set_power_profile_mode(smu, , 0);
> +
> + mutex_unlock(>mutex);
> +
> + return 0;
> +}
> +
> enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
> {
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 9c0a53ef93c4..1b44414cec3b 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -973,6 +973,9 @@ extern int smu_dpm_set_power_gate(struct smu_context
> *smu,uint32_t block_type, b
> extern int smu_handle_task(struct smu_context *smu,
> enum amd_dpm_forced_level level,
> enum amd_pp_task task_id);
> +int smu_switch_power_profile(struct smu_context *smu,
> + enum PP_SMC_POWER_PROFILE type,
> + bool en);
> int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version,
> uint32_t *smu_version);
> int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type
> clk_type,
> uint16_t level, uint32_t *value);
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/amdgpu/powerplay: provide the interface to disable uclk switch for DAL
It's looks fine for me.
Reviewed-by: Kevin Wang
Best Regards,
Kevin
On 7/30/19 2:01 PM, Kenneth Feng wrote:
> provide the interface for DAL to disable uclk switch on navi10.
> in this case, the uclk will be fixed to maximum.
> this is a workaround when display configuration causes underflow issue.
>
> Signed-off-by: Kenneth Feng
> ---
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 14
> drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 25
> ++
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 ++
> 4 files changed, 51 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index 7bc7abc..583f8fb 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -802,6 +802,19 @@ enum pp_smu_status
> pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
> return PP_SMU_RESULT_OK;
> }
>
> +enum pp_smu_status pp_nv_set_pstate_handshake_support(
> + struct pp_smu *pp, BOOLEAN pstate_handshake_supported)
> +{
> + const struct dc_context *ctx = pp->dm;
> + struct amdgpu_device *adev = ctx->driver_context;
> + struct smu_context *smu = >smu;
> +
> + if (smu_display_disable_memory_clock_switch(smu,
> !pstate_handshake_supported))
> + return PP_SMU_RESULT_FAIL;
> +
> + return PP_SMU_RESULT_OK;
> +}
> +
> enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
> enum pp_smu_nv_clock_id clock_id, int mhz)
> {
> @@ -917,6 +930,7 @@ void dm_pp_get_funcs(
> funcs->nv_funcs.get_maximum_sustainable_clocks =
> pp_nv_get_maximum_sustainable_clocks;
> /*todo compare data with window driver */
> funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
> + funcs->nv_funcs.set_pstate_handshake_support =
> pp_nv_set_pstate_handshake_support;
> break;
> #endif
> default:
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 33d2d75..8242cd1 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -549,6 +549,8 @@ struct smu_context
> #define WATERMARKS_EXIST(1 << 0)
> #define WATERMARKS_LOADED (1 << 1)
> uint32_t watermarks_bitmap;
> + uint32_t hard_min_uclk_req_from_dal;
> + bool disable_uclk_switch;
>
> uint32_t workload_mask;
> uint32_t workload_prority[WORKLOAD_POLICY_MAX];
> @@ -632,6 +634,7 @@ struct pptable_funcs {
> int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t
> *clocks_in_khz, uint32_t *num_states);
> int (*set_default_od_settings)(struct smu_context *smu, bool
> initialize);
> int (*set_performance_level)(struct smu_context *smu, enum
> amd_dpm_forced_level level);
> + int (*display_disable_memory_clock_switch)(struct smu_context *smu,
> bool disable_memory_clock_switch);
> };
>
> struct smu_funcs
> @@ -884,6 +887,8 @@ struct smu_funcs
> ((smu)->ppt_funcs->get_clock_by_type_with_voltage ?
> (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
> #define smu_display_clock_voltage_request(smu, clock_req) \
> ((smu)->funcs->display_clock_voltage_request ?
> (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
> +#define smu_display_disable_memory_clock_switch(smu,
> disable_memory_clock_switch) \
> + ((smu)->ppt_funcs->display_disable_memory_clock_switch ?
> (smu)->ppt_funcs->display_disable_memory_clock_switch((smu),
> (disable_memory_clock_switch)) : -EINVAL)
> #define smu_get_dal_power_level(smu, clocks) \
> ((smu)->funcs->get_dal_power_level ?
> (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
> #define smu_get_perf_level(smu, designation, level) \
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index c873228..a8c98c4 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1655,6 +1655,30 @@ static int navi10_get_thermal_temperature_range(struct
> smu_context *smu,
> return 0;
> }
>
> +static int navi10_display_disable_memory_clock_switch(struct smu_context
> *smu,
> + bool
> disable_memo
Re: [PATCH] drm/amdgpu/powerplay: provide the interface to disable uclk switch for DAL
On 7/30/19 12:09 PM, Kenneth Feng wrote:
> provide the interface for DAL to disable uclk switch on navi10.
> in this case, the uclk will be fixed to maximum.
> this is a workaround when display configuration causes underflow issue.
>
> Signed-off-by: Kenneth Feng
> ---
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 17 +++
> drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 25
> ++
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 ++
> 4 files changed, 54 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index 7bc7abc..5b4323b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -802,6 +802,22 @@ enum pp_smu_status
> pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
> return PP_SMU_RESULT_OK;
> }
>
> +enum pp_smu_status pp_nv_set_pstate_handshake_support(struct pp_smu *pp,
> +
> BOOLEAN pstate_handshake_supported)
[kevin]:
please take care of code format.
> +{
> + const struct dc_context *ctx = pp->dm;
> + struct amdgpu_device *adev = ctx->driver_context;
> + struct smu_context *smu = >smu;
> +
> + if (!smu->ppt_funcs)
> + return PP_SMU_RESULT_UNSUPPORTED;
> +
> + if (smu_display_disable_memory_clock_switch(smu,
> !pstate_handshake_supported))
> + return PP_SMU_RESULT_FAIL;
> +
> + return PP_SMU_RESULT_OK;
> +}
> +
> enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
> enum pp_smu_nv_clock_id clock_id, int mhz)
> {
> @@ -917,6 +933,7 @@ void dm_pp_get_funcs(
> funcs->nv_funcs.get_maximum_sustainable_clocks =
> pp_nv_get_maximum_sustainable_clocks;
> /*todo compare data with window driver */
> funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
> + funcs->nv_funcs.set_pstate_handshake_support =
> pp_nv_set_pstate_handshake_support;
> break;
> #endif
> default:
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 33d2d75..642a1b1 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -549,6 +549,8 @@ struct smu_context
> #define WATERMARKS_EXIST(1 << 0)
> #define WATERMARKS_LOADED (1 << 1)
> uint32_t watermarks_bitmap;
> + uint32_t hard_min_uclk_req_from_dal;
> + bool disable_uclk_switch;
>
> uint32_t workload_mask;
> uint32_t workload_prority[WORKLOAD_POLICY_MAX];
> @@ -632,6 +634,7 @@ struct pptable_funcs {
> int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t
> *clocks_in_khz, uint32_t *num_states);
> int (*set_default_od_settings)(struct smu_context *smu, bool
> initialize);
> int (*set_performance_level)(struct smu_context *smu, enum
> amd_dpm_forced_level level);
> + int (*display_disable_memory_clock_switch)(struct smu_context *smu,
> bool disable_memory_clock_switch);
> };
>
> struct smu_funcs
> @@ -884,6 +887,8 @@ struct smu_funcs
> ((smu)->ppt_funcs->get_clock_by_type_with_voltage ?
> (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
> #define smu_display_clock_voltage_request(smu, clock_req) \
> ((smu)->funcs->display_clock_voltage_request ?
> (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
> +#define smu_display_disable_memory_clock_switch(smu,
> disable_memory_clock_switch) \
> + ((smu)->ppt_funcs->display_disable_memory_clock_switch ?
> (smu)->ppt_funcs->display_disable_memory_clock_switch((smu),
> (disable_memory_clock_switch)) : 0)
[kevin]:
could you replace 0 with -EINVAL as default return value. if so, you can
call this function directly, and not check "!smu->ppt_funct".
> #define smu_get_dal_power_level(smu, clocks) \
> ((smu)->funcs->get_dal_power_level ?
> (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
> #define smu_get_perf_level(smu, designation, level) \
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index c873228..a8c98c4 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1655,6 +1655,30 @@ static int navi10_get_thermal_temperature_range(struct
> smu_context *smu,
> return 0;
> }
>
> +static int navi10_display_disable_memory_clock_switch(struct smu_context
> *smu,
> + bool
> disable_memory_clock_switch)
> +{
> + int ret = 0;
> + struct smu_11_0_max_sustainable_clocks
Re: [PATCH 18/30] drm/amd/powerplay: init arcturus SMU metrics table on bootup
On 7/30/19 4:14 AM, Alex Deucher wrote:
> From: Evan Quan
>
> Initialize arcturus SMU metrics table.
>
> Signed-off-by: Evan Quan
> Reviewed-by: Kevin Wang
> Reviewed-by: Alex Deucher
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index a0644ef267a9..5f911f092311 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -267,6 +267,8 @@ static int arcturus_get_workload_type(struct smu_context
> *smu, enum PP_SMC_POWER
>
> static int arcturus_tables_init(struct smu_context *smu, struct smu_table
> *tables)
> {
> + struct smu_table_context *smu_table = >smu_table;
> +
> SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
> PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>
> @@ -276,6 +278,11 @@ static int arcturus_tables_init(struct smu_context *smu,
> struct smu_table *table
> SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
> PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>
> + smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
> [kevin]: where is do free operation in driver code ?
> + if (!smu_table->metrics_table)
> + return -ENOMEM;
> + smu_table->metrics_time = 0;
> +
> return 0;
> }
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 16/30] drm/amd/powerplay: correct Navi10 VCN powergate control
On 7/30/19 4:14 AM, Alex Deucher wrote:
> From: Evan Quan
>
> No VCN DPM bit check as that's different from VCN PG. Also
> no extra check for possible double enablement/disablement
> as that's already done by VCN.
>
> Signed-off-by: Evan Quan
> Reviewed-by: Kenneth Feng
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 --
> 1 file changed, 9 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 9dd96d8b8dd5..01d534c8442e 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -591,27 +591,19 @@ static int navi10_set_default_dpm_table(struct
> smu_context *smu)
> static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
> {
> int ret = 0;
> - struct smu_power_context *smu_power = >smu_power;
> - struct smu_power_gate *power_gate = _power->power_gate;
>
> - if (enable && power_gate->uvd_gated) {
> - if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
> - ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_PowerUpVcn, 1);
> - if (ret)
> - return ret;
> - }
> - power_gate->uvd_gated = false;
> + if (enable) {
> + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
> + if (ret)
> + return ret;
> } else {
> - if (!enable && !power_gate->uvd_gated) {
> - if (smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_UVD_BIT)) {
> - ret = smu_send_smc_msg(smu,
> SMU_MSG_PowerDownVcn);
> - if (ret)
> - return ret;
> - }
> - power_gate->uvd_gated = true;
> - }
> + ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
> + if (ret)
> + return ret;
> }
>
> + smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
[kevin]:
you should check return value, this should not be based on some assumptions.
> +
> return 0;
> }
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/powerplay: fix temperature granularity error in smu11
the previous patch already submitted, so need this patch to fix. thanks. Best Regards, Kevin On 7/24/19 10:34 AM, Quan, Evan wrote: > Better to combine this with previous ptach(drm/amd/powerplay: add callback > function of get_thermal_temperature_range) as one. > Since this issue to fix was actually introduced by that patch. > > But if the original patch was already submitted, it's OK to commit this > separately. > > Either way, this way is Reviewed-by: Evan Quan > > Regards, > Evan >> -Original Message- >> From: Wang, Kevin(Yang) >> Sent: Tuesday, July 23, 2019 8:08 PM >> To: amd-gfx@lists.freedesktop.org >> Cc: Feng, Kenneth ; Huang, Ray >> ; Quan, Evan ; Wang, >> Kevin(Yang) >> Subject: [PATCH] drm/amd/powerplay: fix temperature granularity error in >> smu11 >> >> in this patch, >> drm/amd/powerplay: add callback function of >> get_thermal_temperature_range the driver missed temperature granularity >> change on other temperature. >> >> Signed-off-by: Kevin Wang >> --- >> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 +- >> 1 file changed, 9 insertions(+), 9 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c >> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c >> index 745b35a1600d..735802bb07b9 100644 >> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c >> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c >> @@ -1229,15 +1229,15 @@ static int >> smu_v11_0_start_thermal_control(struct smu_context *smu) >> return ret; >> } >> >> -adev->pm.dpm.thermal.min_temp = range.min; >> -adev->pm.dpm.thermal.max_temp = range.max; >> -adev->pm.dpm.thermal.max_edge_emergency_temp = >> range.edge_emergency_max; >> -adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min; >> -adev->pm.dpm.thermal.max_hotspot_crit_temp = >> range.hotspot_crit_max; >> -adev->pm.dpm.thermal.max_hotspot_emergency_temp = >> range.hotspot_emergency_max; >> -adev->pm.dpm.thermal.min_mem_temp = range.mem_min; >> -adev->pm.dpm.thermal.max_mem_crit_temp = >> range.mem_crit_max; >> -adev->pm.dpm.thermal.max_mem_emergency_temp = >> range.mem_emergency_max; >> +adev->pm.dpm.thermal.min_temp = range.min * >> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> +adev->pm.dpm.thermal.max_temp = range.max * >> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> +adev->pm.dpm.thermal.max_edge_emergency_temp = >> range.edge_emergency_max * >> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> +adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * >> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> +adev->pm.dpm.thermal.max_hotspot_crit_temp = >> range.hotspot_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> +adev->pm.dpm.thermal.max_hotspot_emergency_temp = >> range.hotspot_emergency_max * >> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> +adev->pm.dpm.thermal.min_mem_temp = range.mem_min * >> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> +adev->pm.dpm.thermal.max_mem_crit_temp = >> range.mem_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> +adev->pm.dpm.thermal.max_mem_emergency_temp = >> range.mem_emergency_max >> +* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> adev->pm.dpm.thermal.min_temp = range.min * >> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> adev->pm.dpm.thermal.max_temp = range.max * >> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; >> >> -- >> 2.22.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 6/9] drm/amdgpu: add reset_method asic callback for navi
Reviewed-by: Kevin Wang
On 7/24/19 1:00 PM, Alex Deucher wrote:
> Navi uses either mode1 or baco depending on various
> conditions.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 15 ++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 6c59b64b9bb1..bf4cbcdeef78 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -289,6 +289,18 @@ static int nv_asic_mode1_reset(struct amdgpu_device
> *adev)
>
> return ret;
> }
> +
> +static enum amd_reset_method
> +nv_asic_reset_method(struct amdgpu_device *adev)
> +{
> + struct smu_context *smu = >smu;
> +
> + if (smu_baco_is_support(smu))
> + return AMD_RESET_METHOD_BACO;
> + else
> + return AMD_RESET_METHOD_MODE1;
> +}
> +
> static int nv_asic_reset(struct amdgpu_device *adev)
> {
>
> @@ -303,7 +315,7 @@ static int nv_asic_reset(struct amdgpu_device *adev)
> int ret = 0;
> struct smu_context *smu = >smu;
>
> - if (smu_baco_is_support(smu))
> + if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
> ret = smu_baco_reset(smu);
> else
> ret = nv_asic_mode1_reset(adev);
> @@ -500,6 +512,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
> .read_bios_from_rom = _read_bios_from_rom,
> .read_register = _read_register,
> .reset = _asic_reset,
> + .reset_method = _asic_reset_method,
> .set_vga_state = _vga_set_state,
> .get_xclk = _get_xclk,
> .set_uvd_clocks = _set_uvd_clocks,
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/powerplay: fix deadlock around smu_handle_task V2
Reviewed-by: Kevin Wang
Best Regards,
Kevin
On 7/16/19 11:01 AM, Quan, Evan wrote:
> Ping..
>
>> -Original Message-
>> From: Evan Quan
>> Sent: Friday, July 12, 2019 1:51 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Wang, Kevin(Yang) ; Quan, Evan
>>
>> Subject: [PATCH] drm/amd/powerplay: fix deadlock around
>> smu_handle_task V2
>>
>> As the lock was already held on the entrance to smu_handle_task.
>>
>> - V2: lock in small granularity
>>
>> Change-Id: I5388aa917ef0e330974e26c59db42d1354b6a865
>> Signed-off-by: Evan Quan
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 --
>> 1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>> index 961f4e54ed18..eb255a6bd3a9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>> @@ -3049,11 +3049,9 @@ void amdgpu_pm_compute_clocks(struct
>> amdgpu_device *adev)
>> if (is_support_sw_smu(adev)) {
>> struct smu_context *smu = >smu;
>> struct smu_dpm_context *smu_dpm =
>>> smu.smu_dpm;
>> -mutex_lock(&(smu->mutex));
>> smu_handle_task(>smu,
>> smu_dpm->dpm_level,
>> AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
>> -mutex_unlock(&(smu->mutex));
>> } else {
>> if (adev->powerplay.pp_funcs->dispatch_tasks) {
>> if (!amdgpu_device_has_dc_support(adev)) {
>> --
>> 2.21.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
