On Mon, Dec 10, 2018 at 10:58:20AM -0500, Alex Deucher wrote:
> On Mon, Dec 10, 2018 at 5:04 AM Daniel Vetter wrote:
> >
> > It's not a core function, and the matching atomic functions are also
> > not in the core. Plus the suspend/resume helper is also already there.
> >
> > Needs a tiny bit of
Reviewed-by: Leo Li
On 2018-12-07 1:14 p.m., Alex Deucher wrote:
> Acked-by: Alex Deucher
> On Fri, Dec 7, 2018 at 10:07 AM Nicholas Kazlauskas
> wrote:
>>
>> [Why]
>> These properties aren't being carried over when the atomic state.
>> This tricks atomic check and commit tail into performing
On Tue, Dec 11, 2018 at 10:53 AM Sean Paul wrote:
>
> On Mon, Dec 10, 2018 at 10:58:20AM -0500, Alex Deucher wrote:
> > On Mon, Dec 10, 2018 at 5:04 AM Daniel Vetter
> > wrote:
> > >
> > > It's not a core function, and the matching atomic functions are also
> > > not in the core. Plus the
Yeah, completely correct explained.
I was unfortunately really busy today, but going to give that a look as
soon as I have time.
Christian.
Am 11.12.18 um 17:01 schrieb Grodzovsky, Andrey:
A I understand you say that by the time the fence callback runs the job
might have already been
A I understand you say that by the time the fence callback runs the job
might have already been released,
but how so if the job gets released from drm_sched_job_finish work
handler in the normal flow - so, after the HW
fence (s_fence->parent) cb is executed. Other 2 flows are error use
cases
I see, so ok for me . You can added
Reviewed-by :Shaoyun.liu
-Original Message-
From: Lou, Wentao
Sent: Monday, December 10, 2018 11:54 PM
To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org;
Grodzovsky, Andrey ; Kuehling, Felix
Subject: RE: [PATCH] drm/amdgpu: kfd_pre_reset outside
Reviewed-by: Leo Li
On 2018-12-07 1:10 p.m., Deucher, Alexander wrote:
> Acked-by: Alex Deucher
>
>
> *From:* amd-gfx on behalf of
> Nicholas Kazlauskas
> *Sent:* Friday, December 7, 2018 12:15:01 PM
> *To:*
From: Leo Li
Lots of patches this time around, my appologies :) I've been falling
behind on preparing these, so doing some catch-up here.
Summary of change:
* Fix display corruption on some systems running Polaris
* Remove/demote some error messages to warnings
* Architectural refactors and
From: Eric Bernstein
1) Rename and make public definition of input CSC matrix struct.
2) Make wm_read_state() function an interface of hubbub, and check
if watermark registers exist before read/write to them.
3) Check if OTG_INTERLACE_CONTROL register exists before updating
4) Add dummy
On Tue, Dec 11, 2018 at 2:24 PM Nathan Chancellor
wrote:
> On Tue, Dec 11, 2018 at 02:07:31PM -0800, Nick Desaulniers wrote:
> > On Tue, Dec 11, 2018 at 1:42 PM Nathan Chancellor
> > wrote:
> > >
> > > On Tue, Dec 11, 2018 at 01:25:00PM -0800, Nick Desaulniers wrote:
> > > > On Mon, Dec 10,
On Tue, Dec 11, 2018 at 1:42 PM Nathan Chancellor
wrote:
>
> On Tue, Dec 11, 2018 at 01:25:00PM -0800, Nick Desaulniers wrote:
> > On Mon, Dec 10, 2018 at 3:42 PM Nathan Chancellor
> > wrote:
> > >
> > > Clang warns when an expression that equals zero is used as a null
> > > pointer constant (in
On Tue, Dec 11, 2018 at 01:25:00PM -0800, Nick Desaulniers wrote:
> On Mon, Dec 10, 2018 at 3:42 PM Nathan Chancellor
> wrote:
> >
> > Clang warns when an expression that equals zero is used as a null
> > pointer constant (in lieu of NULL):
> >
> >
On Tue, Dec 11, 2018 at 3:13 PM Andrey Grodzovsky
wrote:
>
> I retested GPU recovery with Bonaire ASIC and it works.
>
> Signed-off-by: Andrey Grodzovsky
Reviewed-by: Alex Deucher
Care to enable it in the kernel as well?
Alex
> ---
> tests/amdgpu/deadlock_tests.c | 3 ++-
> 1 file
np
Andrey
On 12/11/2018 03:18 PM, Alex Deucher wrote:
> On Tue, Dec 11, 2018 at 3:13 PM Andrey Grodzovsky
> wrote:
>> I retested GPU recovery with Bonaire ASIC and it works.
>>
>> Signed-off-by: Andrey Grodzovsky
> Reviewed-by: Alex Deucher
>
> Care to enable it in the kernel as well?
>
>
On 2018-12-05 2:59 p.m., Nicholas Kazlauskas wrote:
> [Why]
> Legacy cursor plane updates from drm helpers go through the full
> atomic codepath. A high volume of cursor updates through this slow
> code path can cause subsequent page-flips to skip vblank intervals
> since each individual update
On Tue, Dec 11, 2018 at 02:07:31PM -0800, Nick Desaulniers wrote:
> On Tue, Dec 11, 2018 at 1:42 PM Nathan Chancellor
> wrote:
> >
> > On Tue, Dec 11, 2018 at 01:25:00PM -0800, Nick Desaulniers wrote:
> > > On Mon, Dec 10, 2018 at 3:42 PM Nathan Chancellor
> > > wrote:
> > > >
> > > > Clang
From: Dale Zhao
[Why]
In 99% user case, edp will be post by vbios.
In 1% / current case: Lenovo don't light up edp panel in vbios
post stage, vbios won't be lit up. Thus in dal when we init DCN
10 hw, we power up edp, then we start detect_sink, but internal
time is too short, when we detect
From: Lewis Huang
[Why]
Driver didn't check plane size and surface size is mismatch.
It will cause pitch data incorrect.
[How]
Add condition to check is plane change and update surface
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Leo Li
[Why]
It's not being used anywhere.
[How]
Remove it.
Signed-off-by: Leo Li
Reviewed-by: David Francis
---
drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
From: Eric Yang
[Why]
Skipping initial link training will result in no verified link cap for
mode enumeration. Some versions of the BIOS seem to have PHY programming
sequence issue as well if initial link training is skipped, resulting in
a softlock in BIOS command table.
[How]
Identify the
From: Wenjing Liu
[why]
Some components depend on dc to constuct
but need to assign callback functions to dc.
[how]
Instead of assigning dc callback functions in dc_create,
decouple the callback init to a standlone function after dc_create. This
is currently a no-op.
Signed-off-by: Wenjing Liu
From: Jun Lei
[why]
dc_stream_state containing a pointer to sink is poor design.
Sink describes the display, and the specifications or capabilities
it has. That information is irrelevant for dc_stream_state, which describes
hardware state, and is generally used for hardware programming. It
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: David Francis
[Why]
Backlight is conceptually a property of links, not streams.
All backlight programming is done on links, but there is a
stream property bl_pwm_level that is used to restore backlight
on dpms on and s3 resume. This is unnecessary, as backlight
is already restored by
From: Imad Syed
They're not being used, so remove them.
Signed-off-by: Imad Syed
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
From: SivapiriyanKumarasamy
[WHY]
There is an extra null check for fs_params in the
build_freesync_hdr function detected by Smatch.
[HOW]
1) Remove the extra null check since it is checked in the
caller.
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
From: David Francis
[Why]
DC warns when a REG_WAIT takes a while and full-on errors
with stack dump on REG_WAIT timeout. Most of the time it isn't
a real issue.
[How]
Make DC cool its jets - taking a while is a debug message (because
it is not something that normal users should need to be
From: Fatemeh Darbehani
[Why]
To make sure future changes in DAL for SMU msgs will not change the current
behaviour
and to make sure clock registeres are programmed correctly based on SMU msgs
that DAL sends.
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
From: Hugo Hu
[Why]
So that we can adjust fclk for debugging purposes.
[How]
Add option to force adjust fclk request to pplib.
Signed-off-by: Hugo Hu
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
From: Eric Yang
[Why]
YCbCr420 packing format uses two chanels for luma, and 1
channel for both chroma component. Our previous implementation
did not account for this and results in every other pixel having
very high luma value, showing greyish color instead of black.
YCbCr444 = ; .
From: Roman Li
[Why]
The visual corruption due to low display clock value observed on some
systems
[How]
There was earlier patch for dspclk:
'drm/amd/display: Raise dispclk value for dce_update_clocks'
Adding +15% workaround also to to dce112_update_clocks
Signed-off-by: Roman Li
Reviewed-by:
From: Krunoslav Kovac
[Why]
We are not correctly handling the wrap around case.
VLine interrupt is relative to position of VUpdate interrupt.
Both VUpdate interrupt and VLine interrupt could possibly
be in front porch or back porch.
[How]
Fix wraparound case by checking for line number that is
From: Dmytro Laktyushkin
DV have made updates to DCN dml which we need to pull in
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 7 --
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
From: David Francis
[Why]
ABM enablement testing can be automated if a way of reading
target and current hardware backlight is available
[How]
Expand debugfs interface with two new entries.
Hook directly into dc interface. Units are as
a fraction of 0x1000 = 100%
Use the built-in amdgpu
From: Leo Li
[Why]
context->bw.dce.dispclk_khz is being cached into unpatched_clock, then
restored at end of function call. This is needlessly complex
[How]
Instead, use a local patched_clock variable. Leave
context->bw.dce.dispclk_khz alone.
No functional change is intended.
Signed-off-by:
From: Leo Li
[Why]
When XGMI is enabled, the DP reference clock needs to be adjusted
according to the XGMI spread spectrum percentage and mode. But first,
we need the ability to fetch this info.
[How]
Within the BIOS parser, Read from vBIOS when XGMI SS info is requested.
In addition, diags
From: Dmytro Laktyushkin
This is a dual channel format and should be treated like other
video formats
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Leo Li
[Why]
When XGMI is enabled, we need to adjust the dprefclk according to the
WAFL link's spread spectrum info. This is for VG20 (DCE121) only.
[How]
dce_clk_mgr already stores SS info, currently being used by audio clock.
Therefore, patch the clk_mgr's SS info with the xGMI SS info,
From: David Francis
[Why]
The function dc_commit_updates_for_stream had a parameter called
plane_states. It was never used. It was getting in the way
of some cleanup work
[How]
Remove it
Signed-off-by: David Francis
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
From: Ken Chalmers
[Why]
Users would like more accurate pixel clocks, especially for fractional
"TV" frame rates like 59.94 Hz.
[How]
Store and communicate pixel clocks with 100 Hz accuracy from
dc_crtc_timing through to BIOS command table setpixelclock call.
Signed-off-by: Ken Chalmers
From: SivapiriyanKumarasamy
[WHY]
Currently, when the VSP infopacket is rebuilt in DM, it is not updated
when being programmed in encoder.
[HOW]
Add new VSP case for update_info_frame
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Anthony Koo
Acked-by: Krunoslav Kovac
Acked-by: Leo Li
From: Leo Li
[Why]
We'll need a way to differentiate Vega 20 in DC
[How]
Add a DCE_VERSION_12_1 enum, which will be returned as the DC version if
the ASIC used is a Vega 20.
Signed-off-by: Leo Li
Reviewed-by: David Francis
---
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c | 1
From: Yongqiang Sun
[Why]
passive update planes still spends a litte more
time on some cases.
[How]
Remove unnecessary trace which involving in some register read.
Disable debug output for release build.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Jun Lei
Signed-off-by: Jun Lei
Reviewed-by: Nevenko Stupar
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
From: Dmytro Laktyushkin
Remove braces around single-line conditionals
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
Acked-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++
1 file changed, 2 insertions(+), 4
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Shahin Khayyer
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Eric Yang
[why]
There was a recent fix in the BW spreadsheet to allow timing with very
large vblank. Need to be ported into driver.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c |
From: Dmytro Laktyushkin
An earlier change added update of interdependent dlg/ttu params for pipes
not being updated in the current call. The code fails to check if the other
pipes are actually active yet causing an assert.
This change adds a check for surface presence on the pipes before
From: Eric Bernstein
Expose this function for future use.
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 2 ++
2 files
From: Jun Lei
[why]
stream ID allows DMs to avoid memory address comparisons to compare
stream equality.
otg_instance allows DC to more rigorously define when otg_instance
can change. specifically, it is now defined to be only mutable when
dc_stream_state
changes. This is better than a "get
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Wenjing Liu
[why]
DP LL CTS1.4 4.3.2.1 test failure.
[how]
The failure is caused by not handling DP link loss
hpd short pusle during set mode. The change is to read link status
before set mode link training. If link is lost, re-verify link caps.
Signed-off-by: Wenjing Liu
Reviewed-by:
From: Ken Chalmers
[Why]
For more informative debugging.
[How]
Add timing generator and PLL ids to output, to make it clear which pixel
clock is being set.
Signed-off-by: Ken Chalmers
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 8
From: Dmytro Laktyushkin
This will allow us to program dscclk to required value
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 7
From: Leo Li
[Why]
This fixes an regression introduced by:
drm/amd/display: add stream ID and otg instance in dc_stream_state
During driver initialization, a null pointer deref is raised. This is
caused by searching for a stream status in the dc->current_state before
the dc_state swap
From: Wenjing Liu
[why]
Some dongle doesn't have a valid extended dongle caps,
but we still set the extended dongle caps to be valid.
This causes validation fails for all timing.
[how]
If no dp_hdmi_max_pixel_clk is provided,
don't use extended dongle caps.
Signed-off-by: Wenjing Liu
From: Paul Hsieh
[WHY]
On customer board, there is one pluse (1v , < 1ms) on
DDC_CLK pin when plug / unplug DP cable. Driver will read
it and config DP to HDMI/DVI dongle.
[HOW]
If there is a real dongle, DDC_CLK should be always pull high.
Try to read again to recovery this special case. Retry
From: Eric Bernstein
[Why]
There are different reasons for Validation failure error during
atomic_check
[How]
Add better logging of the reason for validation failure
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
From: Harry Wentland
[Why]
In certain configurations, such as PX configs or some Vega20 parts
DC gets created without connectors.
[How]
Drop the dm_error print when no connectors.
Signed-off-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
Acked-by: Leo Li
---
From: Fatemeh Darbehani
[Why]
PPLib has impelemented the new pp_smu interface
[How]
Use the new functions if available instead of the old interface
'set_display_requirement' and 'dcn1_pplib_apply_display_requirements'.
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Fatemeh Darbehani
Acked-by:
I retested Bonaire (gfx7 dGPU) and it works fine.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 42111d5..71a9e18
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Andrey
Grodzovsky
Sent: Tuesday, December 11, 2018 3:35:16 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Grodzovsky, Andrey
Subject: [PATCH] drm/amdgpu: Enable GPU recovery by default for CI
Patch is
Reviewed-by: Boyuan Zhang
Regards,
Boyuan
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Liu,
Leo
Sent: December-11-18 4:04 PM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Liu, Leo
Subject: [PATCH libdrm]
On Mon, Dec 10, 2018 at 3:42 PM Nathan Chancellor
wrote:
>
> Clang warns when an expression that equals zero is used as a null
> pointer constant (in lieu of NULL):
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4435:3:
> warning: expression which evaluates to zero treated as a
Hi Daniel and Chris,
Could you take a look on all the patches? Can we get your RB or AB on all
patches including igt patch before we submit to drm-misc?
We already fix all existing issues, and also add test case in IGT as your
required.
Btw, the patch set is tested by below tests:
a. vulkan
As two more SDMA page queue rings are added on Vega20.
Change-Id: I8a3d8fbc924f7c24aaebf17b3f329a4a38fe5a56
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
We need new invalidation engine layout due to new SDMA page
queues added.
Change-Id: I2f3861689bffb9828c9eae744a7a0de4963ac2b6
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
Vega20 uses ring id 1 for page queues EOP irq while previous
ASICs take ring id 3.
Change-Id: Id837fa934ab4a60f0360a33216413a8fc9987c56
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
Page queue is supported on Vega20 with SDMA firmware
122 onwards.
Change-Id: I78d2c4a7ad9d200d89177fae2ad6073955e6bd8b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
From: Christian König
Lockless container implementation similar to a dma_fence_array, but with
only two elements per node and automatic garbage collection.
v2: properly document dma_fence_chain_for_each, add dma_fence_chain_find_seqno,
drop prev reference during garbage collection if it's
v2: adapt to new one transfer ioctl
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu-symbol-check | 3 ++
amdgpu/amdgpu.h| 51
amdgpu/amdgpu_cs.c | 68 ++
3 files changed, 122 insertions(+)
diff --git
Signed-off-by: Chunming Zhou
---
include/drm/amdgpu_drm.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 1ceec56d..a3c067dd 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -517,6 +517,8 @@ struct
v2: drop export/import
Signed-off-by: Chunming Zhou
---
xf86drm.c | 44
xf86drm.h | 6 ++
2 files changed, 50 insertions(+)
diff --git a/xf86drm.c b/xf86drm.c
index 71ad54ba..9816b3b2 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4277,3 +4277,47
v2: drop not implemented IOCTLs and flags
v3: add transfer/signal ioctls
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
include/drm/drm.h | 35 +++
1 file changed, 35 insertions(+)
diff --git a/include/drm/drm.h b/include/drm/drm.h
index
Clang warns when an expression that equals zero is used as a null
pointer constant (in lieu of NULL):
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4435:3:
warning: expression which evaluates to zero treated as a null pointer
constant of type 'const enum color_transfer_func *'
v2: adapt to new transfer ioctl
Signed-off-by: Chunming Zhou
---
include/drm-uapi/drm.h | 33 ++
lib/igt_syncobj.c| 206
lib/igt_syncobj.h| 19 +
tests/meson.build|1 +
tests/syncobj_timeline.c | 1032 ++
5 files
v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
fix some warnings
v3: add export/import and cpu signal testing cases
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
tests/amdgpu/Makefile.am | 3 +-
tests/amdgpu/amdgpu_test.c | 12 ++
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu.h| 22 ++
amdgpu/amdgpu_cs.c | 16
2 files changed, 38 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 5536d2d5..48e28aef 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1638,6
v2: use one transfer ioctl
Signed-off-by: Chunming Zhou
---
xf86drm.c | 33 +
xf86drm.h | 6 ++
2 files changed, 39 insertions(+)
diff --git a/xf86drm.c b/xf86drm.c
index 9816b3b2..2a089616 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4278,6 +4278,21 @@
v2: symbos are stored in lexical order.
v3: drop export/import and extra query indirection
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
amdgpu/amdgpu-symbol-check | 2 ++
amdgpu/amdgpu.h| 39 ++
amdgpu/amdgpu_cs.c | 23
we need to import/export timeline point.
v2: unify to one transfer ioctl
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/drm_internal.h | 2 +
drivers/gpu/drm/drm_ioctl.c| 2 +
drivers/gpu/drm/drm_syncobj.c | 74 ++
include/uapi/drm/drm.h | 10
syncobj wait/signal operation is appending in command submission.
v2: separate to two kinds in/out_deps functions
Signed-off-by: Chunming Zhou
Cc: Daniel Rakos
Cc: Jason Ekstrand
Cc: Bas Nieuwenhuizen
Cc: Dave Airlie
Cc: Christian König
Cc: Chris Wilson
---
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8de55f7f1a3a..cafafdb1d03f 100644
---
points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.
v3:
userspace can specify two kinds waits::
a. Wait for time point to be completed.
b. and wait for time point to become available
v4:
rebase
v5:
add comment for
v2: individually allocate chain array, since chain node is free independently.
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/drm_internal.h | 2 +
drivers/gpu/drm/drm_ioctl.c| 2 +
drivers/gpu/drm/drm_syncobj.c | 81 ++
include/uapi/drm/drm.h |
From: Christian König
Implement finding the right timeline point in drm_syncobj_find_fence.
v2: return -EINVAL when the point is not submitted yet.
v3: fix reference counting bug, add flags handling as well
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 43
From: Christian König
Use the dma_fence_chain object to create a timeline of fence objects
instead of just replacing the existing fence.
v2: rebase and cleanup
v3: fix garbage collection parameters
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 37
user mode can query timeline payload.
v2: check return value of copy_to_user
v3: handle querying entry by entry
v4: rebase on new chain container, simplify interface
Signed-off-by: Chunming Zhou
Cc: Daniel Rakos
Cc: Jason Ekstrand
Cc: Bas Nieuwenhuizen
Cc: Dave Airlie
Cc: Christian König
From: Christian König
This completes "drm/syncobj: Drop add/remove_callback from driver
interface" and cleans up the implementation a bit.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 91 ---
include/drm/drm_syncobj.h | 21
2
Since this is not needed any more on the latest SMC firmware.
Change-Id: Id8a34261ba04381f6141ee18cd56b1c4a72c01bd
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Acked-by: Feifei Xu
-Original Message-
From: Evan Quan
Sent: Wednesday, December 12, 2018 3:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei ; Feng, Kenneth ; Quan,
Evan
Subject: [PATCH] drm/amdgpu: drop fclk/gfxclk ratio setting
Since this is not needed any more on the latest
Am 11.12.18 um 01:12 schrieb Kuehling, Felix:
This is a nice improvement from the last version. I still see some
potential problems. See inline ...
I'm skipping over the CS and GEM parts. I hope Christian can review
those parts.
Going to do this as soon as you have sorted out all the issues
Acked-by: Christian König
Am 10.12.18 um 22:46 schrieb Grodzovsky, Andrey:
Acked-by: Andrey Grodzovsky
Andrey
On 12/10/2018 04:29 PM, Kuehling, Felix wrote:
This function was renamed in a previous commit. Update the stub
function name for builds with CONFIG_HSA_AMD disabled.
Fixes:
I retested GPU recovery with Bonaire ASIC and it works.
Signed-off-by: Andrey Grodzovsky
---
tests/amdgpu/deadlock_tests.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index 6bd36aa..a6c2635 100644
---
Just make them properly i.e. put 0 to the Nop reg
Signed-off-by: Leo Liu
---
tests/amdgpu/vcn_tests.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index d9f05af8..859ec496 100644
---
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Liu, Leo
Sent: Tuesday, December 11, 2018 4:03 PM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Liu, Leo
Subject: [PATCH libdrm] tests/amdgpu/vcn: fix the nop command in IBs
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