Hi,
ARTIQ 2.2 is available, and contains bugfixes (SPI and some compiler
corner cases) and a relicensing under LGPL. The new license resolves
concerns about experiments being potentially considered derived works
under the GPL. We encourage all users to update to 2.2.
Sébastien
Hi,
ARTIQ 2.1 is out and is a simple bugfix release. We recommend that all
2.0 users upgrade.
Sébastien
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
Testing new Mailman options that hopefully will stop triggerring the
NIST/Microsoft email spoofing detector. Can someome from NIST reply to
this message and confirm that they don't get "This sender failed our
fraud detection checks" messages anymore?
--- Begin Message ---
Another test
On Thursday, December 01, 2016 01:24 PM, Sébastien Bourdeauducq via
ARTIQ wrote:
Testing new Mailman options that hopefully will stop triggerring the
NIST/Microsoft email spoofing detector. Can someome from NIST reply to
this message and confirm
On Monday, December 19, 2016 10:08 PM, Slichter, Daniel H. (Fed) via
ARTIQ wrote:
It seems that JQI would be a good potential location because:
Sounds good. Jonathan, Joe, Jason - what do you think about hosting such
a meeting?
* Would you present something?
Depending on the structure and
Hi,
Before DRTIO can operate, the clock chip (HMC* on Sayma and AD9516 on
KC705) needs to be running.
This setup should be done by the comms CPU on the DRTIO master, and the
management CPU on a DRTIO satellite.
For initialization, the comms or management CPU would configure the
clock
Hi,
The idea of organizing an in-person meeting for current and prospective
ARTIQ users has been floating for a while. We'd like to get a
conversation started on this topic. Some of this email is taken from
Joe's GitHub issue #582.
* Venue? some ideas: NIST, JQI, DESY, Oxford, CERN, Warsaw
On Saturday, December 17, 2016 12:02 PM, Sébastien Bourdeauducq via
ARTIQ wrote:
Before DRTIO can operate, the clock chip (HMC* on Sayma and AD9516 on
KC705) needs to be running.
Strictly speaking: this is needed only for the two-KC705 system. But we
might as well use the same scheme
Hi,
RTIOCollision is a bit tedious to implement with DRTIO, since the master
does not know if a given channel should do replace or collision. The
satellite would need to report this information for each of its channels
(and this also needs to be passed from the gateware scripts to the
On Friday, March 17, 2017 07:34 AM, Grzegorz Kasprowicz via ARTIQ wrote:
look here
https://cloud.githubusercontent.com/assets/4325054/24015076/98f7653a-0a87-11e7-93d2-7df1831b2422.jpg
Looks nice! Thanks for all your work!
___
ARTIQ mailing list
Hi,
ARTIQ 2.3 is available and fixes various bugs that were present in 2.2.
We encourage all users to update to 2.3. When using conda, make sure to
add the conda-forge channel before updating, as ARTIQ now depends on the
new pyqtgraph 0.10 package available there.
Sébastien
Hi,
On Wednesday, March 08, 2017 06:11 AM, Neal Pisenti via ARTIQ wrote:
* For ARTIQ core device, we would ideally jump straight to using a
Kasli, but as that isn't likely to be done in the next few months, I was
planning to use a KC705 as the core.
The "EEM" DDS/synth Kasli extensions may
Please see the attached PDF.
2017-August.pdf
Description: Adobe PDF document
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
Joe,
Why is this better than the mailing list? And why add another place to
get support?
On Sunday, August 13, 2017 05:10 PM, Joe Britton via ARTIQ wrote:
- news and topics of community-wide interest
(https://ssl.serverraum.org/lists/listinfo/artiq)
The mailing list was never intended for
On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote:
Have we settled on the 50T as the FPGA for the first version of Kasli,
and what speed grade?
I would advocate for the 50T in -2 speed grade for two main reasons:
a) I don't think we need that much FPGA resources for the 100T to be
On Friday, June 30, 2017 07:54 PM, Grzegorz Kasprowicz via ARTIQ wrote:
additional 30$ does not make any difference.
OK, fine.
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
On Thursday, June 29, 2017 06:16 PM, Thomas Harty via ARTIQ wrote:
The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4
on the BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is
an added benefit.
Kasli was meant to be a simple and low-cost board without a backplane,
Hi,
I would like to relay the information about this upcoming conference on
trapped ions organized at NIST Boulder. M-Labs will be participating
with an exhibit (including some Sinara boards) and the hosting of a
networking event and panel discussion at Sanitas Brewery one evening.
The panel
On Saturday, October 07, 2017 09:13 AM, Arpit Agrawal via ARTIQ wrote:
return Instance("IOBUFDS",
i_I=self.i, o_O=self.o, i_T=self.oe,
OE means "output enable". T means "tristate", i.e. not driving. You need
to invert that signal.
Sébastien
Please see the attached PDF.
2017-September.pdf
Description: Adobe PDF document
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
Hello,
We have just released ARTIQ 2.5 and new conda packages are available.
This is a bugfix release that you can use if you do not wish to move to
ARTIQ-3 yet.
Sébastien
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
Hello,
After a year since the last major release, we are pleased to announce
ARTIQ 3.0.
There were ~1300 commits since 2.0, for many different features such as
RTIO DMA that can dramatically improve the throughput of long pulse
sequences, and asynchronous RPCs to speed up the reporting
Please see the attached PDF.
2017-October.pdf
Description: Adobe PDF document
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
Hi,
to implement scans on the core device
(https://github.com/m-labs/artiq/issues/118) in the best way possible,
we need some information about how ARTIQ is used and will be used:
* are Python generators (i.e. using "yield") something that you know
about, use, and would like to see supported
Hi,
Judging from the absence of replies to this email, we will not support
generators on the core device nor MultiScanManager.
Sébastien
On Tuesday, October 10, 2017 02:34 PM, Sébastien Bourdeauducq wrote:
Hi,
to implement scans on the core device
Hi Greg,
just a quick note about the SFP/SATA cable that is necessary to connect
Ethernet on a Sayma directly. I suggest building them from a passive SFP
copper cable (e.g. http://www.fs.com/products/36649.html) cut in half,
with a male (motherboard or disk) connector soldered at the end.
Please disregard this message.
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
Please see the attached PDF.
2017-November.pdf
Description: Adobe PDF document
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
On Friday, October 20, 2017 12:36 AM, Slichter, Daniel H. (Fed) wrote:
Judging from the absence of replies to this email, we will not
support generators on the core device nor MultiScanManager.
My main question with this is about time efficiency -- if you were to
go to the effort to support
Please see the attached PDF.
2018-May.pdf
Description: Adobe PDF document
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
On Thursday, May 24, 2018 02:16 AM, Joe Britton wrote:
Has M-Labs tested SAWG on Sayma since the DRAM, Ethernet, gateware bug
patching in recent months?
Sure, I did it just before sending the board to Duke two weeks ago. Why?
___
ARTIQ mailing list
Hi,
any objections to supporting only the RTIO clock frequency (currently
150MHz) at the Sayma input, instead of 100MHz?
Are you using non-programmable 100MHz references?
Sébastien
___
ARTIQ mailing list
Hi everyone,
We have completed the ARTIQ core development for Kasli in single-board
configurations (i.e. without DRTIO). This includes DDR3 support, and
1000BASE-X Ethernet PHY using Artix-7 GTP transceivers. The full ARTIQ
runtime works properly on the board and is ready to execute kernels
Hi,
We have released ARTIQ 3.4 to fix an intermittent core device crash (#902).
Sébastien
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
Here is the current report. Happy new year everyone!
Sébastien
2018-January.pdf
Description: Adobe PDF document
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
On Thursday, August 09, 2018 03:15 AM, Thomas Harty via ARTIQ wrote:
it's a big FPGA and IIRC we're not
really pushing the resources limits yet (but maybe I'm wrong about
that?), so it's not clear that's actually a problem. I get that
multi-hour compile times are death, but at least we haven't
Please see the attached PDF.
2018-August.pdf
Description: Adobe PDF document
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
On Thursday, August 09, 2018 03:12 PM, Thomas Harty wrote:
So, the questions are: how much do we need to simplify the SAWG to make
it okay to debug and maintain at the 1GSPS data rate? and, what's the
way of doing that, which has the least impact on users?
"In anything at all, perfection is
On Wednesday, July 11, 2018 04:59 AM, Thomas Harty via ARTIQ wrote:
My view is that we shouldn't give up the flexibility of being able to
fine-tune the DUC frequency unless there is a good reason to do so.
For example: if the complexity/compile times of the current code make
Hi,
I'm trying to determine what is the best way forward to support sample
rates better than the current 600MHz with the Sayma DAC and SAWG.
What sample rate(s) would you like to see and why?
With high sample rates, there are two ways to ease the FPGA resource burden:
* use the DAC
Please see the attached PDF.
2018-March.pdf
Description: Adobe PDF document
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
On 10/01/2018 10:30 PM, Hanhijärvi Kalle via ARTIQ wrote:
On Kasli, I'm using SFP0 port for the fiber.
Is the LED next to SFP0 turned on? That's the Ethernet connection status
indicator.
___
ARTIQ mailing list
Hi,
The attached PDF covers the work since the last report sent on October 9th.
Sébastien
2018-November-December.pdf
Description: Adobe PDF document
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
Hi,
The Grabber card is not compatible with CoaXpress.
Using CoaXpress with Kasli should be possible via its SATA connector,
but requires nontrivial development in hardware and gateware.
Sébastien
On 2/1/19 12:02 AM, Harry Parke via ARTIQ wrote:
Dear ARTIQ list members,
Does anybody
Hi,
I have set up a web-based forum as another place (that some may find
friendlier and easier to use) to discuss all things ARTIQ, (n)Migen,
MiSoC and HeavyX with the community.
Visit it here: https://forum.m-labs.hk/
Sébastien
___
ARTIQ mailing
On 9/12/19 11:05 PM, Andrew Risinger via ARTIQ wrote:
> Is there a timeline for the release of ARTIQ 5?
https://github.com/m-labs/artiq/milestone/14
The main item is Sayma v2 support.
> Also, is there any reason that the conda builds only still support
> python >=3.5.3 <3.6, when Nix supports
Hi,
ARTIQ-5 is released today. To update, follow the stable branch manual at
https://m-labs.hk/artiq/manual/installing.html.
Highlights of this new release (compared to 4.0):
* Performance improvements:
- Faster RTIO event submission (1.5x improvement in pulse rate test)
See:
Hi,
since nobody is using these mailing lists anymore (these days the
preferred channels seem to be GitHub/Gitea issues, IRC/mattermost, and
the forum), I will close them next week, Dec 24th - unless someone objects.
Sébastien
___
ARTIQ mailing
48 matches
Mail list logo
