Rob,
My experience was that executing the MVC or CLC twice (first with
length 0) is better than to branch over it.
I doubt that doing something little and then full is faster than doing
it full the first time
If you observed major difference I do suspect that it is because
the first
On Mon, Jan 16, 2012 at 9:48 PM, John Gilmore
johnwgilmore0...@gmail.com wrote:
Binary search of an ORDERED linked list is in fact possible if one
knows/keeps track of how many elements the list contains.
You make me curious, but maybe we're just talking about different things.
To me a linked
Having the CLC near the EX helps for cache. I also like to assemble it
in-line because the right USINGs apply. We noticed that it is
attractive to run over the CLC (with the length byte 0 as assembled)
and then EX behind your back to do the real thing. More attractive
than branch over the
Rob,
My point was the truism that if pointer chasing is cheap and
comparisons are not cheap then pointer chasing is advantageous.
Let n be the number of elements in a list and m = 1 + n /2 be the
serial number of a middling element. Then chasing pointers (without
making comparisons) to find
On Tue, Jan 17, 2012 at 1:31 PM, Fred van der Windt
fred.van.der.wi...@mail.ing.nl wrote:
Having the CLC near the EX helps for cache. I also like to assemble it
in-line because the right USINGs apply. We noticed that it is
attractive to run over the CLC (with the length byte 0 as assembled)
At this shop, using CPU costs money. Using I/O doesn't. Wall clock doesn't.
Therefore, so long as SLAs are met, it is better to decrease CPU time at the
expense of __anything__ else. Yes, even productivity. I must say no more.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
On Tue, Jan 17, 2012 at 1:41 PM, John Gilmore
johnwgilmore0...@gmail.com wrote:
Rob,
My point was the truism that if pointer chasing is cheap and
comparisons are not cheap then pointer chasing is advantageous.
Let n be the number of elements in a list and m = 1 + n /2 be the
serial number
On Jan 16, 2012, at 22:30, robin wrote:
From: Paul Gilmartin paulgboul...@aim.com
Sent: Tuesday, 17 January 2012 7:33 AM
CDC 3600/3800 had a Modify following instruction instruction
The S/360 and subsequent machines have one like that also.
In the case of MVC/CLC instructions :-
stc
On Jan 16, 2012, at 08:21, Kerry wrote:
Performance is one of the strongest reasons for coding in assembler and
this discussion characterizes some of the low hanging fruit available for
the attainment thereof.
Others have said here that performance is a strong reason
for _not_ coding in
On 1/17/2012 6:40 AM, Paul Gilmartin wrote:
I forget; is the target of EX treated as a data access or as an instruction
access for cacne management?
The 256-byte cache line containing the target instruction is loaded into
I-cache.
--
Edward E Jaffe
Phoenix Software International, Inc
831
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
l...@listserv.uga.edu] On Behalf Of Paul Gilmartin
Sent: Tuesday, January 17, 2012 10:32 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: How bad is the EX instruction?
On Jan 16, 2012, at 08:21, Kerry
From: Farley, Peter x23353 peter.far...@broadridge.com
IMHO, COBOL generated code is so bad that if I was on the COBOL
code-generation development team I would be embarrassed to admit it.
The cobol code generator appears to be the beneficiary of benign neglect.
The net result of using only
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Paul Gilmartin
Sent: Tuesday, January 17, 2012 9:32 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: How bad is the EX instruction?
On Jan 16, 2012, at 08:21, Kerry wrote:
On Tue, 17 Jan 2012 08:26:29 -0700 Paul Gilmartin paulgboul...@aim.com
wrote:
:In some contexts, z/OS name/token services might be the best
:choice -- they've likely done all the optimizing for you.
The last time I looked it was implemented as a linked list.
--
Binyamin Dissen
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Farley,
Peter x23353
Sent: Tuesday, January 17, 2012 10:06 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: How bad is the EX instruction?
snip
Notoriously NOT for the
On 1/17/2012 8:06 AM, Farley, Peter x23353 wrote:
Others have said here that performance is a strong reason
for _not_ coding in assembler:
o Compiler developers have done the research on instruction
timings and know better than most end users what sequences
fit the pipelines optimally.
Peter Farley wrote:
begin snippet
. . . I plead ignorance for the PL/1 and Fortran compilers, but the
C/C++ compiler is the nly current compiler in my personal experience
that actually exhibits a knowledge of instruction timings and latency
and AGI interrupts, etc., for current and recent
On Jan 17, 2012, at 10:07, Edward Jaffe wrote:
The PL/X compiler also generates 'poor' code. (It's one reason it's been
difficult to convince the 'powers that be' to establish a new Architectural
Level Set for z/OS.)
The balance between cost of development and cost of execution may
be biased
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
l...@listserv.uga.edu] On Behalf Of Paul Gilmartin
Sent: Tuesday, January 17, 2012 12:20 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: How bad is the EX instruction?
Snipped
On Jan 17, 2012, at 10:11,
On 17 January 2012 08:09, Fred van der Windt
fred.van.der.wi...@mail.ing.nl wrote:
I did a very QD test and...
J *+10
CLC 0(1,R10),8(R10)
EXRL R1,*-6
...is about 25% faster than...
CLC 0(1,R10),8(R10)
EXRL R1,*-6
So on a z196 the jump seems to be faster than the
I knew there were VSE folks on those boxes, which is why I chose my
models carefully. ;)
On 2012-01-16 13:43, Tony Thigpen wrote:
I doubt anyone is still running ES 9000 boxes.
I have paying customers on 9672s, MP2000, MP3000, etc.
VSE, not z/OS.
Tony Thigpen
-Original Message -
On 2012-01-17 07:44, Edward Jaffe wrote:
On 1/17/2012 6:40 AM, Paul Gilmartin wrote:
I forget; is the target of EX treated as a data access or as an
instruction access for cacne management?
The 256-byte cache line containing the target instruction is loaded into
I-cache.
So, this would seem
I apologize before hand if this is too off-topic. But, if you are a user
of HLASM on z/Linux, I have a question. Not about the assembler,
however. I am wondering what you use to edit your source code. On z/OS,
I use ISPF and set tabs at 10, 16, 35, and 72. I would like to edit my
HLASM source on
CMS XEDIT and punch the source to Linux with the VMUR package.
David Kreuter
Original Message
Subject: OT? Question to user(s) of HLASM on z/Linux
From: John McKown joa...@swbell.net
Date: Tue, January 17, 2012 9:10 pm
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
I apologize before
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