Ref: Your note of Wed, 27 Nov 2019 13:16:33 -0500
> My point is that XA took away 7 bits that were used for various purposes.
> Taking all 8 wouldn't have been a lot more painful.
>
> sas
Are you serious? The main problem with going from 24-bit to
32-bit addressing was that the standard
Actually, my real point is that XA could have been the transition that got
us completely away from "dirty" addresses.
And btw, a 'LLG24' instruction would be nice to have. The total cost of
changing GET/PUT/READ/WRITE to using SR/ICM must world-wide represent the
waste of dozens of dollars in
I must fall back on "I know very little about Intel architecture". They do
have different modes, which are actually more involved than just
addressing. I get the impression some of the older ones have been
abandoned.
They have far less assembler code to worry about carrying forward.
Regardless,
On 2019-11-27, at 10:26:35, Seymour J Metz wrote:
>
> TSS/360 used an explicit length at offset -4 from the parameter list, so the
> end-of-list bit wasn't an issue.
>
> The addresses transition from 7FFF_ to 8000_ is a
> z/OS issue rather than an architectural issue.
>
On Wed, 27 Nov 2019 12:47:44 -0500, Steve Smith wrote:
>Notwithstanding all the expert opinions, from my point of view, XA would
>have better gone to 32-bit addressing from the get-go. I don't see the
>benefit of the amode being part of the address. Seems to me it's been a
>lot of unnecessary
Good grief. I really wonder why the BX* instructions don't use logical
compares, like I assumed they did. In any case, that quote is almost
nonsense, as address wrap-around has been a feature since the dawn of
time. 2^31-1 + 1 = 0, for addressing purposes. And yet the BX*
instructions treat
On Wed, 27 Nov 2019 17:26:35 +, Seymour J Metz wrote:
>TSS/360 used an explicit length at offset -4 from the parameter list, so the
>end-of-list bit wasn't an issue.
>The addresses transition from 7FFF_ to 8000_ is a z/OS
>issue rather than an architectural issue.
TSS/360 used an explicit length at offset -4 from the parameter list, so the
end-of-list bit wasn't an issue.
The addresses transition from 7FFF_ to 8000_ is a z/OS
issue rather than an architectural issue.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
On Tue, 26 Nov 2019 10:29:32 -0700, Paul Gilmartin wrote:
>I believe the greater accommodation was the hardware architecture's
>expanding from 24-bit addressing to only 31 rather than 32 because
>software so pervasively uses the sign bit for a flag.
I don't think so. I don't have any information
I believe the greater accommodation was the hardware architecture's
expanding from 24-bit addressing to only 31 rather than 32 because software
so pervasively uses the sign bit for a flag.
My guess was that "2 GB of addressability is all that anyone could ever
possibly need!"
Charles
z/OS does never allocate virtual addresses from 0x8000 to 0x.
Not quite true. Never say never :-) .
History: XA architecture in effect introduced the "line", an obvious
differentiating point between 24-bit and 31-bit storage at 16M.
z/OS (not z/Architecture) introduced the "bar", a
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