On 5/24/2024 8:58 AM, David Clark wrote:
Can't find that macro, either. Now what? ;-)
The "Macro and Copy Code Source Summary" on the HLASM listing shows from
which library every macro and copy code member was read.
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive
On 5/12/2024 11:02 PM, Yves Colliard wrote:
Dear Dan,
many thanks. I did a comparable excel - if you're interested take a look, could
also be an altenative.
https://magentacloud.de/s/7wJAZmS65DFY2zy
Best regards
Yves Colliard
Nice work!
--
Phoenix Software International
Edward E. Jaffe
On 5/9/2024 5:41 AM, Binyamin Dissen wrote:
Have your EODAD do
LFI R1,c'EODA'
BR R14
Or my favorite value: LFI R1,X'FE0D'
Then you can DOEXIT CIJ,R1,LT,0 to exit the loop if negative...
--
Phoenix Software International
Edward E. Jaffe
831 Parkview
On 5/1/2024 9:58 AM, Paul Gilmartin wrote:
The desire to accept redefinition with identical value appears
to arise from undisciplined design and use of header files.
But we had a register equates macro that came to conflict with
IATYREGS when we added JES3 support. Many JES3 headers used
On 4/18/2024 12:45 PM, Ngan, Robert (DXC Luxoft) wrote:
Assuming you have an assembly listing, you just need to look at the "R-Loc"
(i.e. offset) value.
We use two LOCTR's for data, one for data that needs to be within 4K of the
base register, and another for data referenced with relative
On 12/19/2023 9:27 AM, Mike Shaw wrote:
Doug used to work in ISPF development at IBM. His code is using knowledge
he had of the TLD format that us mere mortals don't have. Looks like the
TLD may have changed under z/OS V3R1?
Oh no! In our software, we are using a "trick" given to us years ago
On 12/2/2023 7:19 AM, Peter Relson wrote:
In the RMODE=SPLIT case you can end up with one part of the executable in one
RMODE and the other part in another RMODE and V-Con's between the two parts are
resolved at module fetch time.
Which is BTW ultra-cool functionality! (Too bad they don't
On 12/1/2023 1:06 PM, João Reginato wrote:
But I have a program that can or not call TPUT.
If it calls, so I'd like to set RMODE 24, otherwise 31.
We issue TPUT all over the place in 31-bit mode (AMODE/RMODE).
If I did have a function that required RMODE(24), I would not force an
entire
On 12/1/2023 11:27 AM, Jon Perryman wrote:
On Fri, 1 Dec 2023 11:06:16 -0300, João Reginato wrote:
How can I reset RMODE without receive
ASMA186E AMODE/RMODE already set for this ESD item
Once set, such attributes cannot be changed. It makes no sense to change
them.
--
Phoenix Software
On 11/21/2023 2:09 PM, Jon Perryman wrote:
I'm sorry Tom. My bad. It was Ed Jaffe who codes BAKR for each CSECT and save
areas for called functions.
No. We don't use BAKR. We use BASSM/BSM when calling services external
to the current CSECT/MODULE.
We don't use traditional save areas
BAKR/PR provides wonderful capabilities, but it's slower than a
traditional save/restore into already-acquired storage.
BAKR/PR is faster than acquiring storage for a save area.
Generally, our programs use a save area stack acquired by the mainline
at initialization time. For such programs:
On 11/13/2023 7:23 AM, Schmitt, Michael wrote:
As long no one ever uses DISP=MOD
...or checkpoints. Checkpoints can cause short blocks to be written.
What about CLOSE TYPE=T? Would that flush the current block?
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El
On 11/10/2023 1:19 AM, Martin Trübner wrote:
The determination whether jumpable or no is done in a SETC exit and
not in the macro. This made the determination easier.
That is very, Very, VERY cool! ijs...
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El
On 11/9/2023 10:26 AM, Dave Clark wrote:
Thanks, but the IEABRCX macro doesn't exist in the z/VSE world.
ISTR Martin Trübner wrote an equivalent macro for z/VSE.
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
On 11/9/2023 4:06 AM, Seymour J Metz wrote:
The relative instructions are invaluable for large csects, but in this case I
believe that they are overkill. All he needs is the judicious placement of DROP.
OTOH, they are definitely instructions worth his time to learn.
In addition to extending
On 10/18/2023 10:14 AM, Farley, Peter wrote:
Build the parameter list once using this form:
CALL (15),(PARM1,PARM2,PARM2,BLOCK,PARM5),VL,MF=(E,PARMB), X
LINKINST=NOPR,LINKOP='0'
Nice!
I remember when LINKINST was added (and have used it for both BASR and
BASSM).
On 10/18/2023 9:48 AM, Dave Clark wrote:
Well, the other issue is performance. I potentially call this
program hundreds of times. So, I can build the parameter list just once
I have used CALL to build a parameter list and do nothing else in a
manner similar to:
CALL
On 9/26/2023 2:27 PM, Mike Shaw wrote:
The doc does not say what that memory object's pages contain just after
IARV64 REQUEST=GETSTOR is issued. Does anyone on the list know?
Assuming you're referring to pageable memory, the object is completely
empty waiting for you to reference something.
On 9/22/2023 2:06 PM, Farley, Peter wrote:
Is z/XDC available to you? The authorized version might be able to help you
out there, but I suspect only Dave Cole could tell you that for sure, and if
so, how to do it.
CCB implies a z/VSE (or VSEn) system and AFAIK there is no z/XDC for
that
On 6/7/2023 10:22 AM, Phil Smith III wrote:
So where does this "Logical" come from? I'm sure it's something obvious!
In this context "logical" simply means it's an unsigned comparison.
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
On 6/1/2023 9:24 AM, Phil Smith III wrote:
Thoughts? (Yes, I *said* it was theology, so I'm prepared for religious
arguments!)
The latter seems great when the field names are super short like
PSATOLD-PSA or TCBJSCB-TCB as in your example.
Modern control block field names are often much,
On 5/12/2023 9:14 AM, Tony Thigpen wrote:
Ed,
Is there a 2107 manual that can be legally acquired by vendors or
non-vendors?
I assume the answer is yes. It would be difficult for hardware vendors
like Hitachi and Dell/EMC to certify their products adhere to the 2107
specification if such
On 5/12/2023 3:51 AM, Seymour J Metz wrote:
I've got a 2105 manual on DVD but that's probably too old to help.
Correct. The 2107 manual is what's needed...
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/
On 5/11/2023 3:54 PM, Tony Thigpen wrote:
I don't know if it should be on this list, or IBM-Main, but I am
looking for some good documentation on current command codes used in
CCWs.
For example, I am helping a customer with a issue with VSE cause by a
vendor program that is using a command
On 5/4/2023 9:14 PM, Ed Jaffe wrote:
Approximately 128 bytes average saved for each additional sub-module
involved...
Actually, the above was my average savings across the whole library
calculated by pasting the ISPF member display into an Excel spreadsheet
and using HEX2DEC to convert
On 5/4/2023 5:19 PM, Peter Relson wrote:
Page alignment is what you'd expect.
That's too bad. I was hoping module fetch had been enhanced at some
point over the last quarter century to take advantage the
StartBdy/ContBdy keywords available on GETMAIN/STORAGE (since 1998).
My example was
On 5/4/2023 1:19 PM, Peter Relson wrote:
Ed,
What you really want is not to dive so deeply into the weeds.
Bind with COMPAT=ZOSV2R1.
It does not work. Here is a trivial example.
I'm compiling with SECTALGN(256) and specifying no binder input other
than a NAME statement:
//LKED.SYSIN DD
We have been using SECTALGN(256) with our programs for many years to
ensure they are loaded on a cache line boundary. This causes the
resulting load modules to be page-aligned (and padded to a 4K boundary
which is a waste of storage).
In an effort to trim this waste down, we tried using
On 3/29/2023 5:21 PM, Keith Moe wrote:
Already exists from IBM: Prime PSA.
Specifically:
////
//* *//
//* THIS PROCEDURE WILL PRIME THE RESTART OLD PSW, THE *//
//* MACHINE CHECK
On 2/13/2023 9:27 AM, Charles Mills wrote:
Any reliance on the visible glyph as an unambiguous indication of the
underlying bit pattern is going to be fraught.
I know for absolute fact that my 3270 emulators and ISPF are properly
synchronized to correctly process and display characters using
On 12/7/2022 9:12 AM, Gord Tomlin wrote:
Maybe replace CLHHSI with CHHSI, which is designed for signed values:
Duh! I would have suggested that myself had I read PoOp more carefully...
Thanks, Gord!
--
Phoenix Software International
Edward E. Jaffe
Chief Technology Officer
831 Parkview
On 12/7/2022 8:20 AM, Seymour J Metz wrote:
When you code an immediate operand, it has semantics beyond the generated code.
An operand of -1 is signed and not equivalent to X'', even though they have
the same value. The instruction is compare logical half half storage immediate,
thus the
We decided to replace many SS instructions with their SIL counterparts.
One common case is frustrating.
D501 C01E C020 CLC HWord,=H'-1' Is it negative one?
A784 000C JE NegOne Branch if yes
replaced with:
E555 C01E CLHHSI HWord,-1 Is
On 11/15/2022 1:19 PM, Paul Gilmartin wrote:
Is the hardware smart enough to bypass setting the condition code when
it's
not needed but might slow the pipeline? Maybe next year's model.
It's not so much setting the condition code that slows the pipeline,
it's waiting to check the
On 11/15/2022 7:38 AM, Martin Trübner wrote:
Prettty sure that some developer within(!) IBM stumbled over some
coding in a macro (or module) that needed adaption to situations where
more than 4095 is needed (LA R,inc(,R)) or a negative value.
For the low halves, there is always LAY.
ALSIHN
On 9/17/2022 2:06 AM, Abe Kornelis wrote:
Starting with reentrant programming seems a pretty tough call.
Not sure why re-entrant programming should be considered heavy lifting.
Would not any assembler course teach about USING?
A typical non-reentrant program has a single code/data segment
On 6/8/2022 6:06 AM, Jonathan Scott wrote:
Please note that there is already an instruction with the
mnemonic MVCRL, "Move right to left", used to shift up data to
make a gap for inserting new data.
Destructive overlap is often quite useful (for clearing fields, etc),
but it's a PITA when you
On 5/26/2022 2:23 PM, Schmitt, Michael wrote:
I want to replace all '*' with a space in a field. That's a TR instruction,
right? But when I search through our 40 years of assembler code, I see no uses
of TR for such a purpose.
I thinking this is because of difficulty in building the TR table.
On 4/19/2022 7:13 PM, Bob Raicer wrote:
Having the ability to assemble quadword aligned 128-bit items for
use with these instructions would be helpful.
We define quadword-aligned storage areas all the time. For example:
Field1 DC LQ'0'
Field2 DC LQ'0'
Of course, you need to specify the
On 4/17/2022 1:12 AM, Martin Trübner wrote:
what would LBEAR do other than a LG Rn,X'110' ?
Martin, X'110' is not the BEAR. The BEAR is a special register that
holds the last Breaking Event Address (BEA). X'110' is simply the place
where the BEAR is automatically stored when an interrupt
On 4/17/2022 7:25 AM, tom_russell tom_russell wrote:
Hello,
I'm still missing the newest publication. I'm interested to read about
the next instructions. Does someone know where to find it?
Regards
Yves Colliard
ResourceLink has the latest - SA22-7832-12. Go to
We just applied this APAR to our systems:
https://www.ibm.com/support/pages/apar/PH39324
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/
On 4/15/2022 1:49 AM, David Cole wrote:
Thanks for the correction, Ed. I didn't know that. -Dave
"If your product still supports z/OS 2.3 or less, you must dual-path CTX
as well."
And this is precisely the reason CTX hasn't had the widespread adoption
unrealistically expected by the
On 4/14/2022 10:35 AM, David Cole wrote:
Note, "dual path'ing" your code applies to TX, not to CTX.
That's true if your minimum supported z/OS release is z/OS 2.4. Not even
IBM is that aggressive!
If your product still supports z/OS 2.3 or less, you must dual-path CTX
as well.
--
On 4/7/2022 9:16 AM, Paul Gilmartin wrote:
On Apr 7, 2022, at 09:57:35, Ed Jaffe wrote:
z/Architecture does *not* require an alternative path around TBEGINC/TEND.
How, then, does z/Architecture defend against such as Spectre?
Does it balance paths so all exhibit the worst-case timing
On 4/7/2022 8:07 AM, Tony Harminc wrote:
It appears that, like the zArch implementation, Intel's requires
programs to provide an alternative path around TSX.
z/Architecture does *not* require an alternative path around TBEGINC/TEND.
The only reason a developer might provide an alternate
On 4/3/2022 2:38 PM, Charles Mills wrote:
HLASM always (?) chooses the smallest offset when it has multiple choices.
And when the offsets are equal, it chooses the higher-numbered register...
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
On 3/6/2022 5:33 AM, Peter Relson wrote:
* If the page is available on aux, OS would generally suspend the program,
bring in the page from aux by some asynchronous process (it can be synchronous
for such cases as DREF or SCM in which case suspend/resume would not be
needed)...
It never
On 3/5/2022 7:28 AM, Philippe Leite wrote:
You can use TPROT for this purpose but it's a privileged instruction.
Not only is it privileged, but it does not do what the OP has asked for.
He is not concerned only about storage that happens to be paged in, he
wants the answer for storage that
On 3/4/2022 12:38 PM, Charles Mills wrote:
https://www-03.ibm.com/services/supline/products/ExtendedSupport/SystemZ_EOS.pdf
would seem to support my assertion that V2R2 is still in extended support,
until September 2023.
Haha! We don't count the three-year service extensions. We code to
On 3/4/2022 11:24 AM, Charles Mills wrote:
... My rule is to support the
oldest version of z/OS still in extended support, which I believe is
currently V2R2, and the oldest hardware that it supports, which is the z10.
The oldest supported OS is currently z/OS 2.3 and the oldest hardware it
On 3/4/2022 9:31 AM, Dave Clark wrote:
"IBM Mainframe Assembler List" wrote on
03/04/2022 12:19:51 PM:
IIRC, STFLE is newer than the Long Displacement Facility. LOL
It wouldn't appear so. STFLE is facility 7 and LDF is facility 18.
I went back and checked:
o Long-displacement
On 3/4/2022 9:31 AM, Dave Clark wrote:
It wouldn't appear so. STFLE is facility 7 and LDF is facility 18.
Thanks for the clarification.
For the record, I would never, Ever, EVER test the long-displacement
facility bit and code two different paths in my code.
Doing so would be ridiculous...
IIRC, STFLE is newer than the Long Displacement Facility. LOL
On 3/4/2022 9:16 AM, Philippe Leite wrote:
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/
On 3/4/2022 9:01 AM, Dave Clark wrote:
So, I looked at the original email again and did some research
into the LAY instruction. That is when I read about the Long Displacement
Facility (LDF) having to be installed for this instruction to work
(otherwise: operation exception). So,
On 3/1/2022 8:34 AM, esst...@juno.com wrote:
I am able to issue both of the above RAROUTE macros against a
facility profile with individual users. However when a individual is part of a
Group
must I issue a second RACROUTE REQUEST=AUTH|FASTAUTH ?
Definitely NOT!
The group to which such
On 2/22/2022 2:44 PM, Tom Harper wrote:
As you may have guessed, SRST and SRSTU are almost certainly milli-coded
instructions and probably not very fast.
In our benchmark testing, SRST reined supreme as the fastest
single-character linear search BY FAR until we discovered how to use the
On 2/21/2022 9:19 AM, Dave Clark wrote:
Yep, that is why REXX is "restructured." "Restructured" from
what? you might ask... As I understand it, an IBMer was dissatisfied with
CMS EXEC and CMS EXEC2 and wrote CMS REXX to supersede them both.
Not just "an IBMer." The one and only Mike
On 2/13/2022 7:37 AM, Seymour J Metz wrote:
That translates, but it doesn't validate. Drop the NILL and use a 16 byte
literal: =C'?? - - '
I was under the impression he did not care about invalid values and was
merely looking for a quick way of handling positive vs negative. As
On 2/11/2022 10:00 AM, Dave Clark wrote:
I know that x'F1' and x'C1' are positive and that x'D1' is
negative. But what if I find x'A1', x'B1', or x'E1' for overpunch values?
What is the shortest way (in terms of assembler instructions) to validate
these into just two classes --
On 2/10/2022 11:40 AM, David Cole wrote:
(FWIW, I find both books to be abysmal documents!)
(There. That ought to create a firestorm!)
So, among other things, you're asserting the PoO is as "poopy" as its
acronym implies?
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive
On 1/27/2022 11:20 AM, Tony Thigpen wrote:
The question has nothing to do with "what if +4 is zeros." It is "what
if +4 has one of the standard literals."
I gotta ask...
From a purely practical standpoint, would you or anyone really want to
maintain bifurcated code that took different
On 1/27/2022 8:56 AM, Tony Thigpen wrote:
Ed,
By the 'rules' express in this thread, if the caller places one of the
literals at x'04', he then *must* place the back-pointer at offset
x'80'. Is that not what you and others have been saying?
Ugh. I quickly "ripped off" a silly (and stupid)
On 1/27/2022 8:31 AM, Tom Marchant wrote:
On Thu, 27 Jan 2022 08:05:32 -0800, Ed Jaffe
wrote:
It is easy to get confused, isn't it? +4 is set by the program that
obtained the save area, not the programs that use it.
Good point. +4 in your caller's save area describes how HE saved HIS
On 1/27/2022 6:24 AM, Tony Thigpen wrote:
The answer seems to be that, while not fully known, if one of the
literals is present, the called program can safely know that they have
at least the x'08' to x'7F' are to start double-word registers. Do you
at least agree to that conclusion?
On 1/26/2022 9:13 AM, Martin Trübner wrote:
>> Can the REXX folks say anything about whether any changes to
savearea size also affect VSE? It sounds like not.
I am pretty deep into VSE as well as REXX... there hasn't been any
word about 64 bits for programs - and now that 21 CSW is handling
On 1/26/2022 8:17 AM, Tom Marchant wrote:
Thanks for the correction, Ed. I'm surprised there weren't more errors in it.
Actually, I did present a SHARE session on this twice. Once in 2012 and again
in 2018, titled, Saving Your Caller's Registers - Not Your Father's Save Area.
My bad for not
On 1/26/2022 8:03 AM, Mark Boonie wrote:
This provides the cornerstone of a GREAT SHARE presentation you oughtta
give wunna these days!
Funny, I'm looking at a SHARE presentation, from August 2012, that I refer
to when I have questions about how this stuff works. It's by some guy
named --
t should say "E". We knew what you meant.
This provides the cornerstone of a GREAT SHARE presentation you oughtta
give wunna these days!
Thanks,
Ed Jaffe
On 1/25/2022 6:04 PM, Tom Marchant wrote:
Shmuel,
I'm not clear which text and sample code you are looking at. I'm also not clear
On 1/25/2022 9:31 AM, Paul Gilmartin wrote:
On Jan 25, 2022, at 09:24:10, Peter Relson wrote:
The REXX team indicates that the current savearea size for a called
routine is 72 bytes.
This will get documented. Thanks Shmuel for submitting the update request.
Fixing it should take precedence
On 1/7/2022 10:15 AM, Dave Clark wrote:
Not disagreeing... Just didn't know about this list. Happy to be
here. ;-)
And we're happy to have you...
Welcome aboard!
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
On 12/20/2021 10:03 AM, industryn...@winwholesale.com wrote:
AHI ,()*-1
Or you could simply use:
AHI ,-()
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/
On 12/8/2021 1:57 PM, Phil Smith III wrote:
Peter, I expect I'm not the only one who's amazed by this. Not that I know
enough to have a valid opinion, just that in this modren age of cheap memory
etc., it seems surprising that these would overlap. Do you know why this was
done? Is it something
On 11/17/2021 1:36 AM, Jonathan Scott wrote:
We have just shipped the PTFs for APAR PH42050 which allows a
dependent USING instruction to be resolved using a 20-bit signed
displacement provided that the specified OPTABLE is one which
supports instructions with that capability.
|
On 11/9/2021 9:55 AM, Seymour J Metz wrote:
LOCTR may not help with literals, but it can help with macros that generate a
DC. Instead of branching around the constant, put a LOCTR before and after it.
There is no guarantee a existing USING is in place for a literal or DC
in a given LOCTR.
On 11/8/2021 1:45 AM, Tony Thigpen wrote:
I decided to put the constant in-line and use BRAS to acquire it's
address:
AIF (''(1,1) NE ).N0004
BRAS ,N2
SETC ''(2,K')
N1 DC CL''
N2 DS 0H
AGO .N0099
.N0004 ANOP
Back in the day, it was quite common
On 11/8/2021 8:05 AM, Charles Mills wrote:
Ship an additional required macro, TTLTORG, that pushes the current LOCTR,
switches to "your" data LOCTR, issues a LTORG, and then pops the LOCTR.
He already has a trivially-easy solution (JAS around an in-line
constant) that is guaranteed to be 100%
On 10/30/2021 1:13 PM, Charles Mills wrote:
Seriously, your note reminded me of those virus scare SPAMs that we used to get back in
the nineties: "Bill Gates says this is the worst virus ever. It will totally destroy
your hard drive ..."
Haha! Excellent point, Charles!
Some bad actors won't
On 10/30/2021 11:50 AM, Charles Mills wrote:
The general term for this sort of thing is "magic PC routine."
If you have one installed then your system is potentially toast.
Unless the system runs under z/VM, a "magic" SVC or PC on any system
(even a sandbox) is a Trojan Horse some bad actor
On 5/8/2021 6:05 AM, Peter Relson wrote:
You haven't had to bifurcate your code like this since z/OS 2.2 which
has the z11 as it's minimum requirement.
Actually, there was no z/OS release that had z196 as its minimum
requirement.
z/OS 2.2's minimum is z10.
z/OS 2.3's minimum is zEC12 (so
On 5/7/2021 3:42 PM, Keven Hall wrote:
Based on my reading of the description of the Interlocked Access Facility 2,
I'm led to assume that the following code paths are functionally equivalentt in
a multi-threaded/mutli-processing application. If I assume in error, please
feel at liberty to
On 11/11/2020 1:17 PM, Dan Greiner wrote:
I was just informed that the document "The Enhanced-Sort Facility for
z/Architecture" (SA22-1082-00) is available for download. See
https://www-01.ibm.com/servers/resourcelink/lib03010.nsf/0/ADDD4A7958501EBD852585E3005679F7/$file/SA22-1082-00.pdf
(you
On 10/29/2020 1:47 PM, Tony Thigpen wrote:
Trying to debug a program I am porting from z/VSE to z/OS.
Unfortunately, the debug process on z/OS is a lot different from z/VSE.
With all due respect, this forum is for questions about ASSEMBLER
LANGUAGE. BAL. HLASM. Whatever you'd like to call
On 10/20/2020 1:06 PM, Tony Thigpen wrote:
While we are talking about macros, a while back, someone posted they
liked to fill eye-catchers using MVCIN so that scans of the dump for a
tag only found the real eye-catcher, not the literal used to fill the
eye-catcher.
So, instead of:
MVC
On 10/21/2020 10:36 AM, Seymour J Metz wrote:
Which? Either is subject to an access violation crossing page boundaries. For MVCL, I
don't know of any special significance to 256KiB. For MVCOS, assuming no page fault,
256 < 4096, but I don't know of any significance of 256 rather than, e.g.,
On 10/21/2020 8:22 AM, Seymour J Metz wrote:
4K is indeed an architected limit for MVCOS, but for MVCLE it's "CPU-determined
number of bytes".
But nicely it will always complete the move if it is <=256 bytes. So you
don't need the loop for short moves.
--
Phoenix Software International
On 10/20/2020 8:54 AM, Charles Mills wrote:
@Ed, can you elaborate a little on your reasoning? (Not doubting it; just
curious.) Is it that the interruptibility provides a significant improvement
over MVCL? Or the support for lengths greater than 16M? Or ... ?
MVCL with anything other than zero
We've switched almost exclusively to MVCLE except for short,
fixed-length moves.
On 10/20/2020 5:42 AM, Tony Thigpen wrote:
I have several programs that work with buffers and moving random
length data around using MVCLs. I am considering writing a
'conditional MVCL' macro that, at runtime,
On 9/4/2020 10:46 AM, Seymour J Metz wrote:
VM uses a token of 8X'FF' at the end of the (R1) parameter list. I don't recall
what the convention is for the (R0) extended parameter list introduced by VM/SP.
We've adopted "eight bytes of foxes" as an end marker for
variable-length parameter
Clever...
On 8/11/2020 10:57 AM, Tony Thigpen wrote:
I came across the following code today. The program can either be
called by JCL or from either an HLL or assembler program. While I
included some extra code for clarity, the code I am asking for
comments on is the code that 'fixes' R14 so
On 8/8/2020 5:18 AM, Tony Thigpen wrote:
Anybody have any doc, even rough, self-made partial notes on the dasd
ccw command:
x'F7' - Define Subsystem Operation
The subject line says 47, the body says F7. Which is it?
Locate Record normally follows Define Extent which has subsystem
operation
On 6/7/2020 9:23 AM, Farley, Peter x23353 wrote:
Is there any chance you could provide (maybe eventually in a SHARE session
presentation?) a set of good examples of using the vector instructions as you
say you do?
Peter,
There was a thread called "Count Words" into which at one time I
On 6/7/2020 7:11 AM, Peter Relson wrote:
That limitation is not the case for z/Architecture vector operations.
I erred in writing that. Shmuel was of course correct. The "vector
register" is 128 bits (one quadword).
The extent of the "vectorization" depends on the size of the operands.
We
On 6/5/2020 12:15 PM, Seymour J Metz wrote:
The S/370 PoOps mentions the vector facility and says "Vector operations are
described in the publication IBM System/370 Vector Operations, SA22-7125."
You can download it from
On 5/16/2020 12:30 PM, Dave Wade wrote:
CLOSEMAC CLOSE (),MF=L
I would code it this way:
CLOSEMAC CLOSE (*-*),MF=L
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Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/
On 5/1/2020 8:13 AM, Gary Weinhold wrote:
The programmer at our place who used this convention once said that he
learned much of his assembler programming style from JES2 source.
Does anyone know if JES2 used the *-* convention?
I just scanned SHASSRC on our system. It had 932
On 4/20/2020 9:40 AM, Paul Gilmartin wrote:
For such a case, I will always code:
DC CL8' '
Does that truncate properly, but quietly if:
o is 8 bytes?
o is 9 bytes? (Should warn.)
Your "should warn" above is an incorrect assertion.
DC CL8'12345678901234567890' is perfectly legal and
On 4/19/2020 11:24 PM, Windt, W.K.F. van der (Fred) wrote:
DCCL8''
For such a case, I will always code:
DC CL8' '
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Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/
On 1/30/2020 12:42 PM, Keith Moe wrote:
A big disadvantage of SPIE/ESPIE is that it cannot be used in supervisor state.
So you have to use ESTAE even if you know that you want to quickly recover with
no dump, LOGREC, etc., from PIC-4/10/11 (such as when chasing system control
blocks unlocked)
On 12/3/2019 11:07 AM, Paul Gilmartin wrote:
Are cross-CSECT relative branches supported? That feels like an
invitation to disaster: errors that can not be detected before
execution.
They have been supported since z/OS 1.7 or 1.8. Very handy to have!!!
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