From: "Steve Smith"
Sent: Tuesday, August 11, 2020 11:07 AM
The worst way to zero a register is more interesting. JCTG Rx,* is my
favorite. If Rx is already 0, guess how long that will take.
How about:
BCT1,*
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On 8/10/20, Steve Smith wrote:
> The worst way to zero a register is more interesting. JCTG Rx,* is my
> favorite. If Rx is already 0, guess how long that will take.
I believe that sort of thing is called Pessimal Programing.
--
Bob Netzlof a/k/a Sweet Old Bob
From: "Steve Smith"
Sent: Tuesday, August 11, 2020 11:07 AM
The worst way to zero a register is more interesting. JCTG Rx,* is my
favorite. If Rx is already 0, guess how long that will take.
Sorry, wouldn't
M r,=F'0'
take even longer?
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From: "Steve Smith"
Sent: Tuesday, August 11, 2020 11:07 AM
For the whole register, LGHI, LLILL (or HL, LH, or HH) are best. LLILF,
LLIHF take up more space. XGR, SGR, SLGR set the CC.
For only the low half, XR, SR, SLR have the shortness advantage, and LHI
the non-CC advantage.
From: "Rupert Reynolds"
Sent: Tuesday, August 11, 2020 11:03 AM
I've not seen SLR, but my comment based on 1990s knowledge is that it's
best to keep it simple. Don't access storage unnecessarily (such as L
Rn,=F'0') and any of the more obvious methods (such as "LA Rn,0" "SR Rn,Rn"
or "XR
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Tuesday, August 11, 2020 8:51 AM
On 2020-08-10, at 16:28:28, Steve Smith wrote:
The only difference between SR & SLR is how they set the condition code.
If that could produce a
From: "Gary Weinhold"
Sent: Tuesday, August 11, 2020 7:49 AM
it may go back to the idea that SR might require an extra step to
set/propagate the sign while SLR wouldn't.
Subtraction requires that the second operand is complemented,
unity is added, and the operands are summed.
The sign is
On 2020-08-10, at 15:38:14, Gary Weinhold wrote:
>
> i use digests for high-traffic listservs, but not assembler list.
>
For an experiment I wanted a small digest. It appears that
ASSEMBLER-LIST publishes digests daily at 00:00.
> Thunderbird on PC seems to know to reply to the list and but
For the whole register, LGHI, LLILL (or HL, LH, or HH) are best. LLILF,
LLIHF take up more space. XGR, SGR, SLGR set the CC.
For only the low half, XR, SR, SLR have the shortness advantage, and LHI
the non-CC advantage.
Chances are that the CC setting is irrelevant in timing on modern CPUs.
I've not seen SLR, but my comment based on 1990s knowledge is that it's
best to keep it simple. Don't access storage unnecessarily (such as L
Rn,=F'0') and any of the more obvious methods (such as "LA Rn,0" "SR Rn,Rn"
or "XR Rn,Rn") is likely to be optimised as a special case. XR and SR use
less
Several recent z Models include a feature that recognizes some instructions
that zero a register (or portion thereof) and bypass certain pipeline stages
for faster execution. I don't recall which models or which instructions, but
LHI, LGHI, SR, SGR, XR, and XGR seem to ring a bell.
If this
On 2020-08-10, at 16:28:28, Steve Smith wrote:
>
> The only difference between SR & SLR is how they set the condition code.
> If that could produce a measurable difference in a trillion executions, I'd
> love to see it.
>
However, the newer z models have a whole family of new
instructions which
The only hardware I can imagine that it could possibly make a timing
difference is on very early 360 models. And I haven't had access to one
in a long time.
On 2020-08-10 6:28 p.m., Steve Smith wrote:
The only difference between SR & SLR is how they set the condition code.
If that could
The only difference between SR & SLR is how they set the condition code.
If that could produce a measurable difference in a trillion executions, I'd
love to see it.
sas
On Mon, Aug 10, 2020 at 5:49 PM Gary Weinhold wrote:
> it may go back to the idea that SR might require an extra step to
>
Thanks!
LHI also has the advantage that it accepts equates (as does LA, of course).
You can code
Return_Okay EQU 0
Return_Error EQU 8
...
LHI R15,Return_Okay
And it is a little clearer what you are doing than with SR R15,R15
Charles
-Original Message-
From: IBM Mainframe
it may go back to the idea that SR might require an extra step to
set/propagate the sign while SLR wouldn't. But I don't know if that
actually ever made a timing difference on any machine.
On 2020-08-10 4:08 p.m., Schmitt, Michael wrote:
Arrgh! You're right, I said SRA but meant SLR.
That's
i use digests for high-traffic listservs, but not assembler list.
Thunderbird on PC seems to know to reply to the list and but then you
have to do a lot of deleting. But the redundancy within digests in
email reply chains is time-consuming to scroll through.
gary
On 2020-08-10 5:06 p.m.,
Most interesting answer.
Thank you Charles
-Original Message-
From: IBM Mainframe Assembler List On
Behalf Of Charles Mills
Sent: Monday, August 10, 2020 2:05 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Clearing a register
A. There is no answer to the question. Instructions no
Is "by never signing up for a digest" a valid answer to your question?
I hate digests because my entire exposure to them is from people who reply
to the whole digest, mucking up the Listserve threads.
Charles
-Original Message-
From: IBM Mainframe Assembler List
A. There is no answer to the question. Instructions no longer have "timing"
in isolation. Because of pipelining and out-of-order execution, with any
luck one of those non-storage instructions takes no time at all. Really,
literally no time at all. You could benchmark a loop, stick an SR into the
As an experiment I set my subscription to ASSMBLER-LIST to
DIGEST for one day. MacOS Mail.app shows the digest as
a single stream of messages with unrendered Quoted-printable.
There seems to be no way to reply to a single message, only
to the entire digest.
Thunderbird does somewhat better I can
Arrgh! You're right, I said SRA but meant SLR.
That's how IBM documents standard return logic in the Assembler Services Guide:
SLR 15,15 Set return code of zero
So that question remains: I wonder why they use SLR instead of SR.
-Original Message-
From: IBM Mainframe
My 360/67 functional characteristics says
XR 1.25 microsec
SR0.65 microsec
SLR 0.65 microsec
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Schmitt, Michael
Sent: Monday, August 10, 2020 2:56 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Clearing a
I wish IBM would add the LZR instruction just so this question could stop
being asked.
sas
Yes, only clear low 32-bits of 64-bit registers.
I've seen method #3 in IBM code or documentation, which makes one wonder why
they used it instead of SR.
I forgot about LA Rn,0.
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Mike Hochee
Sent: Monday, August 10,
I tend to use XR or XGR and LLIHF or LLILF. SRA does not operate against all
32 bits, and sometimes I do not want to think about extras like sign extension
with LHI. (I know, it's not much to have to think about)
I suppose if you want compatibility with machines of 30/40 years ago you might
Was this question for a RVA (RAMAC Virtual Array) or an ESS (Enterprise Storage
Server, or is ESS now an 'Elastic Storage Server')?
I wouldn't think the RVA and ESS are the same, but I don't really know.
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Dave Kreiss
There’s also LA/LAY which are probably as fast as the XR & SR options.
Keven
On Mon, Aug 10, 2020 at 2:36 PM -0500, "Gary Weinhold" wrote:
I'll make a stab at some principles behind the answer(s): Have the
preceding
I believe that options 1 & 2 are ‘hardware optimized’ for that
operation.
I personally I prefer the exclusive OR method.
Keven
On Mon, Aug 10, 2020 at 2:13 PM -0500, "Schmitt, Michael"
wrote:
There are many ways to set a
Fun Question. Looking forward to answers. I use XR a lot. Not worried
about efficiency or speed. It just looks cool and if someone sees it and
does not know what it does they could guess it is clearing the register,
like X'ing it out.
Duffy Nightingale
Sound
I'll make a stab at some principles behind the answer(s): Have the
preceding instructions touched/changed Rn? That could affect the how
long the pipeline may have to idle before changing the register. If the
following instructions will check the condition code or the contents of
the register,
There are many ways to set a register to binary zero. My question is, which is
the most efficient?
1. XR Rn,Rn
2. SR Rn,RN
3. SRA Rn,Rn
4. LHI Rn,0
5. Other instruction
6. Depends on hardware
7. Depends on other factors. (What?)
8. They are have equal performance
9.
Tony,
Try Chapter 4 - RAMAC Array Subsystem Channel Commands under 4.4.2
Define Subsystem Operation in - GC26-7006-01. Its in "boo" format at
this URL
https://www-05.ibm.com/e-business/linkweb/publications/servlet/pbi.wss?SSN=20HJS0001728662643=ONL=GC26-7006-01=TXTSRH
Dave
On Mon, Aug 10,
Sorry. Typo in the subject. It's CCW command F7. Define Subsystem Operation.
Tony Thigpen
Ed Jaffe wrote on 8/9/20 11:43 PM:
On 8/8/2020 5:18 AM, Tony Thigpen wrote:
Anybody have any doc, even rough, self-made partial notes on the dasd
ccw command:
x'F7' - Define Subsystem Operation
The
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