-Original Message-
From: IBM Mainframe Assembler List
[mailto:assembler-l...@listserv.uga.edu] On Behalf Of Steve Comstock
Sent: Friday, August 20, 2010 8:17 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
snip
THEPROG CSECT
On Fri, 20 Aug 2010 08:26:28 -0500, McKown, John wrote:
THEPROG CSECT
STM14,12,12(13)
LR 12,15
USING THEPROG,12,11,10
LAY11,4096(,12)
LAY10,4096(,11)
I realize that the STM implies that the program is not in 64-bit mode, but a
better
On Aug 20, 2010, at 07:51, McKown, John wrote:
Good point on the pipeline. I am constantly forgetting about pipeline delays.
Is there a tool to analyze and report these? I recall
that decades ago there was such for CDC 6600.
-- gil
McKown, John wrote:
-Original Message-
From: IBM Mainframe Assembler List
[mailto:assembler-l...@listserv.uga.edu] On Behalf Of Steve Comstock
Sent: Friday, August 20, 2010 8:17 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
snip
On 8/20/2010 9:16 AM, Steve Comstock wrote:
THEPROG CSECT
STM 14,12,12(13)
LR 12,15
USING THEPROG,12,11,10
BAS 2,*+8
DC F'4096'
L 2,0(2)
LA 11,0(2,12)
LA 10,0(2,11)
My program start macros use:
LR R12,R15
LA R10,2048
LA R11,2048(R10,R12)
LA
:27:30 AM
Subject: Re: CDS and alignment question
On Aug 18, 2010, at 17:30, John R. Ehrman (408-463-3543 T/543-) wrote:
(-- Referenced Note Follows )
Sent: Wednesday, August 18, 2010 3:51 PM
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LR
Ensuring the base registers are 4096 apart is important when using based
USINGs for items within the referenced area. A 4095 increment requires
separate USINGs for each register, resulting in separate USING ranges. A
4096 increment allows a single USING statement and a contiguous USING range.
If
and code properly.
Lloyd
- Original Message
From: Tom Marchant m42tom-ibmm...@yahoo.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Thu, August 19, 2010 9:12:46 AM
Subject: Re: CDS and alignment question
On Thu, 19 Aug 2010 05:32:15 -0700, Lloyd Fuller wrote:
And BOTH of the LA commands
On Wed, 18 Aug 2010 23:27:30 -0600, Paul Gilmartin wrote:
On Aug 18, 2010, at 17:30, John R. Ehrman (408-463-3543 T/543-) wrote:
I think the original posting was pointing out that you lose only
a single byte of addressability by adding 4095, and that you save
one instruction. The added byte
On Aug 19, 2010, at 07:25, David Bond wrote:
Ensuring the base registers are 4096 apart is important when using based
USINGs for items within the referenced area. A 4095 increment requires
separate USINGs for each register, resulting in separate USING ranges. A
4096 increment allows a single
On Thu, 19 Aug 2010 08:48:34 -0600, Paul Gilmartin wrote:
If for instance, a DCB crosses base registers and the DCB fields are to be
referenced via a based USING on the IHADCB DSECT, the difference between
the two matters. It works only if the single USING statement is employed.
I have run
On Aug 19, 2010, at 09:12, David Bond wrote:
Given:
USING DSA,R13,R12
or:
USING DSA,R13
USING DSA+4096,R12
with:
USING (IHADCB,IHADCB+DCBLNGQS),SYSPRINT
MVC DCBDDNAM,=CL8'SYSOUT'
...
DSA DSECT
...
SYSPRINT DCB ... (generated DCB starts
Gil,
(or should I use Paul?)
Is there any form of USING for multiple base registers and long
displacements,
Multiple is (per documentation) 4096 and then the next.
or is it merely unthinkable that any DSECT would
require multiple base registers with long displacements?
that would be a
WORKAREA,R13
Is this not the way to do it?
-Original Message-
From: IBM Mainframe Assembler List
[mailto:assembler-l...@listserv.uga.edu] On Behalf Of glen
herrmannsfeldt
Sent: Tuesday, August 17, 2010 1:56 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
, August 18, 2010 3:51 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
I have always used something like this:
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LRR11,R15
USING QMGREX01,R11,R12
LAR12,4095(R11)
LAR12,1(R12
On Wed, 18 Aug 2010 16:16:58 -0500, McKown, John wrote:
-Original Message-
I have always used something like this:
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LRR11,R15
USING QMGREX01,R11,R12
LAR12,4095(R11)
LAR12,1(R12)
I think the original posting was pointing out that you lose only
a single byte of addressability by adding 4095, and that you save
one instruction. The added byte is rarely an issue; whether or not
the extra instruction is important depends on the application.
John Ehrman
(--
It is the typical way to do it. However, long ago, someone pointed out
that this sequence burns 4 bytes to add 1 byte of addressability.
Which, to Mr Spock, makes no sense.
Furthermore, it is incorrect to put a USING statement before it is valid
(although it is fairly common). It should be
On Wed, 18 Aug 2010 22:33:27 -0400, Steve Smith sasd...@gmail.com wrote:
It is the typical way to do it. However, long ago, someone pointed out
that this sequence burns 4 bytes to add 1 byte of addressability.
And to preserve the sanity of any poor soul who has to look at the resultant
On Aug 18, 2010, at 17:30, John R. Ehrman (408-463-3543 T/543-) wrote:
I think the original posting was pointing out that you lose only
a single byte of addressability by adding 4095, and that you save
one instruction. The added byte is rarely an issue; whether or not
the extra instruction is
On Aug 18, 2010, at 20:33, Steve Smith wrote:
Furthermore, it is incorrect to put a USING statement before it is valid
(although it is fairly common). It should be moved after your commented
line. The USING for R13 is also obviously premature.
What do you do when you're marching through
-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
Yes, STGHEAD is in a DSECT:
STGPOOL DSECT
STGSIZE DS F
STGHEAD DS A
STGCNTDS F
STGERRDSF
As I said in the original e-mail, the easy thing to do would be to
rearrange the dsect so that STGHEAD
It is the address in memory that matters.
This reminds me of programs with two base registers, using LA
to set the registers such that the offset of the second is 4095
from the first. All instruction addresses (an branch instructions)
will then have an odd offset, legal but it looks funny.
On
...@listserv.uga.edu]
On Behalf Of Mark Hammack
Sent: Tuesday, August 17, 2010 7:33 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
Yes, STGHEAD is in a DSECT:
STGPOOL DSECT
STGSIZE DS F
STGHEAD DS A
STGCNTDS F
STGERRDS
Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Mark Hammack
Sent: Tuesday, August 17, 2010 7:33 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
Yes, STGHEAD is in a DSECT:
STGPOOL DSECT
STGSIZE DS F
STGHEAD
Why does the data for a CDS need to be on a doubleword anyway?
It just does
Or if you want the more gory explanation... it has to do with storage operand
consistency rules. CDS is built on top of the hardware memory architecture and
so it has to play within the same rules as other storage
Subject: Re: CDS and alignment question
Thanks! However, I think you meant ACONTROL FLAG(NOALIGN)/ACONTROL
FLAG(ALIGN). At least that is what worked for me.
Thanks again,
Mark Hammack
Senior Technical Specialist
Systemware, Inc.
On Mon, Aug 16, 2010 at 1:00 PM, Binyamin Dissen
bdis
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