awski, Shawn (National VM Capability)"
Subject: Ensuring LRL 2nd operand alignment
Trying to use the LRL(32) instruction ('C4D' / 'C4xD' opcode).
But running into: DMSABE141T Operation exception
-> 00DF5124 LRL C45D6832
*** 00DF5124 PROG0001 ->
...@phoenixsoftware.com]
Sent: Tuesday, May 4, 2021 9:48 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Ensuring LRL 2nd operand alignment
Here is how I code a similar instruction:
CNOP 2,4
LLILF R14,0
ORG *-4
DC A(symbol+X’8000’)
BASSM R14,R15
So
Here is how I code a similar instruction:
CNOP 2,4
LLILF R14,0
ORG *-4
DC A(symbol+X’8000’)
BASSM R14,R15
So that the second operand can be an ADCON or VCON.
You could do the same with LRL.
Sent from my iPhone
> On May 4, 2021, at 9:18 AM, Peter
Tony H asked about a use case for LRL:
one obvious one is a non-reentrant module.
Or, as Shmuel mentioned, it might have been needed for cases where there
is no binder support for fullword immediate relocatable expressions.
As to the OP's actual question, there are limited choices that come to
Re LRL: The architecture doesn't enforce non-modifiabilty of your code, and
not all instructions have to be equally useful. HLASM dies allow more
flexiblity in defining a storage constant than it does for an immediate
operand, but that's no excuse. Sorry, that's all I've got; generally I
agree
On 2021-05-03, at 12:14:07, Ngan, Robert wrote:
>
> Or: DC 0F
>
No. Read what Charles wrote and envision an operation exception.
> -Original Message-
> From: Paul Gilmartin
> Sent: Friday, April 30, 2021 19:48
>
> On 2021-04-30, at 16:17:06, Charles Mills wrote:
>>...
>> And #3
PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Ensuring LRL 2nd operand alignment
Or: DC 0F
Robert Ngan
HCL Technologies
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Paul Gilmartin
Sent: Friday, April 30, 2021 19:48
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject
Or: DC 0F
Robert Ngan
HCL Technologies
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Paul Gilmartin
Sent: Friday, April 30, 2021 19:48
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Ensuring LRL 2nd operand alignment
On 2021-04-30, at 16:17:06, Charles Mills
@LISTSERV.UGA.EDU
Subject: Re: Ensuring LRL 2nd operand alignment
On a more general topic, why does LRL exist in the first place? Why
would any programmer (or compiler) use LRL in preference to IILF or
one of the other immediate instructions? (And why is there LGFI but no
LFI?)
Surely immediate instructions
On a more general topic, why does LRL exist in the first place? Why
would any programmer (or compiler) use LRL in preference to IILF or
one of the other immediate instructions? (And why is there LGFI but no
LFI?)
Surely immediate instructions are generally faster than relative ones.
Some of them
@LISTSERV.UGA.EDU
Subject: Re: Ensuring LRL 2nd operand alignment
Yes, LRL should work on a z15. Now I suspect that the LRL is not the
instruction causing the interrupt.
of Stanislawski, Shawn (National VM Capability) [shaw...@dxc.com]
Sent: Monday, May 3, 2021 10:26 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Ensuring LRL 2nd operand alignment
Our problem is on a z15.
But z15 should have the long-displacement facility / LRL instruction installed,
yes?
--Shawn S
: Re: Ensuring LRL 2nd operand alignment
My guess is that you are running on a processor that does not have the
long-displacement facility.
--
Shmuel (Seymour J.) Metz
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Tony Harminc
Sent: Friday, April 30, 2021 3:50 PM
If you know whether your instruction is aligned on a fullword or not, if
the number of halfwords specified in the instruction is even, the
displacement is an integral number of fullwords, if not, not.
On 2021-04-30 3:35 p.m., Stanislawski, Shawn (National VM Capability) wrote:
Guessing
On 2021-04-30, at 16:17:06, Charles Mills wrote:
> ...
> And #3 the
> DS 0F has a 50-50 (or 3 in 4, depending on how you look at it) chance of
> generating a couple of garbage-filled slack bytes.
>
That's what CNOP is for.
-- gil
IST@LISTSERV.UGA.EDU]
On Behalf Of Stanislawski, Shawn (National VM Capability)
Sent: Friday, April 30, 2021 12:36 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Ensuring LRL 2nd operand alignment
Trying to use the LRL(32) instruction ('C4D' / 'C4xD' opcode).
But running into: DMSABE141T Operation except
, Shawn (National VM Capability) [shaw...@dxc.com]
Sent: Friday, April 30, 2021 3:35 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Ensuring LRL 2nd operand alignment
Trying to use the LRL(32) instruction ('C4D' / 'C4xD' opcode).
But running into: DMSABE141T Operation exception
-> 00DF5124
On Fri, 30 Apr 2021 at 15:36, Stanislawski, Shawn (National VM
Capability) wrote:
>
> Trying to use the LRL(32) instruction ('C4D' / 'C4xD' opcode).
> But running into: DMSABE141T Operation exception
>
> -> 00DF5124 LRL C45D6832
>
> *** 00DF5124 PROG0001 -> 0139B660
Your guess is incorrect. The notes you were reading explain what causes an
operation exception and what causes a specification exception. As shown,
your instruction would not get a specification exception, as the relative
address is full-word aligned.
Regardless, instructions only require
Trying to use the LRL(32) instruction ('C4D' / 'C4xD' opcode).
But running into: DMSABE141T Operation exception
-> 00DF5124 LRL C45D6832
*** 00DF5124 PROG0001 -> 0139B660OPERATION
Reading in the "zArchitecture Principles of Operation" (SA22-7832-12) = "For
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