Re: [Beignet] [PATCH] do constant folding for kernel struct args

In current implementation, only loadi and add are considered. In the example, since %22 is dst of MOV, it will not be recorded. It is recorded and so impacts the IR only if %22 is dst of ADD. -Original Message- From: Yang, Rong R Sent: Tuesday, June 13, 2017 4:59 PM To: Guo, Yejun

Re: [Beignet] [PATCH] do constant folding for kernel struct args

I just tried such kernel, and the generated GEN IR is INDIRECT_MOV, it has nothing to do with this patch. Thanks Yejun -Original Message- From: Yang, Rong R Sent: Tuesday, June 13, 2017 3:54 PM To: Guo, Yejun; Wang, Rander; Pan, Xiuli; beignet@lists.freedesktop.org Subject: RE

Re: [Beignet] [PATCH] do constant folding for kernel struct args

, Yejun; beignet@lists.freedesktop.org Cc: Guo, Yejun Subject: RE: [Beignet] [PATCH] do constant folding for kernel struct args Yes, so I may be able to give some advice -Original Message- From: Pan, Xiuli Sent: Thursday, June 8, 2017 1:09 PM To: Guo, Yejun ; beignet@lists.freedesktop.org Cc

[Beignet] [PATCH] do constant folding for kernel struct args

General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library. If not, see <http://www.gnu.org/licenses/>. + * + * Author: Guo Yejun + */ + +#include +#include "ir/context.hpp" +#include "ir

[Beignet] [PATCH] keep GEN IR as SSA style

--- backend/src/llvm/llvm_gen_backend.cpp | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp index 831666e..31b8bf2 100644 --- a/backend/src/llvm/llvm_gen_backend.cpp +++ b/backend/src/llvm/llvm

Re: [Beignet] [PATCH] Backend: Fix llvm40 assert about literal structs

Looks fine to me, thanks. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Pan, Xiuli Sent: Wednesday, May 17, 2017 3:15 PM To: beignet@lists.freedesktop.org Subject: Re: [Beignet] [PATCH] Backend: Fix llvm40 assert about literal structs Ping f

[Beignet] [PATCH] refresh DAG when an arg has both direct and indirect read

when the return value is ARG_INDIRECT_READ, there is still possible that some IRs read it directly, and will be handled in buildConstantPush() so we need to refresh the dag afer function buildConstantPush another method is to update DAG accordingly, but i don't think it is easy compared with the r

Re: [Beignet] [PATCH] defer dead insn removal since lowerIndirectRead still needs them

Please ignore this patch, there is still something not correct. Thanks. -Original Message- From: Guo, Yejun Sent: Wednesday, April 26, 2017 4:43 PM To: beignet@lists.freedesktop.org Cc: Guo, Yejun Subject: [PATCH] defer dead insn removal since lowerIndirectRead still needs them

[Beignet] [PATCH] defer dead insn removal since lowerIndirectRead still needs them

--- backend/src/ir/lowering.cpp | 54 ++--- 1 file changed, 26 insertions(+), 28 deletions(-) diff --git a/backend/src/ir/lowering.cpp b/backend/src/ir/lowering.cpp index 93bd96a..53aafa4 100644 --- a/backend/src/ir/lowering.cpp +++ b/backend/src/ir/lowerin

[Beignet] [PATCH] search llvm-config first

in a system with multiple llvm/clang versions, we can create soft link llvm-config to the desired version. Signed-off-by: Guo, Yejun --- CMake/FindLLVM.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMake/FindLLVM.cmake b/CMake/FindLLVM.cmake index 6129909

[Beignet] [PATCH] fix UNTYPED_WRITE function parameters for Gen75Encoder::UNTYPED_WRITE

Signed-off-by: Guo, Yejun --- backend/src/backend/gen75_encoder.cpp | 2 +- backend/src/backend/gen75_encoder.hpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/backend/src/backend/gen75_encoder.cpp b/backend/src/backend/gen75_encoder.cpp index 725c774..b82cc43 100644

[Beignet] [PATCH V2] add sends support for oword/media block write

v2: should also change the virtual function prototype for gen7 Signed-off-by: Guo, Yejun --- backend/src/backend/gen7_encoder.cpp | 2 +- backend/src/backend/gen7_encoder.hpp | 2 +- backend/src/backend/gen9_encoder.cpp | 57 ++ backend/src/backend

Re: [Beignet] [PATCH] add sends support for oword/media block write

nice catch, will send v2, thanks. -Original Message- From: Pan, Xiuli Sent: Wednesday, December 28, 2016 2:04 PM To: Guo, Yejun; beignet@lists.freedesktop.org Cc: Guo, Yejun Subject: RE: [Beignet] [PATCH] add sends support for oword/media block write It seems you missed the gen7_encoder

[Beignet] [PATCH] enable sends to write SLM for workgroup op

Signed-off-by: Guo, Yejun --- backend/src/backend/gen8_context.cpp | 12 +++ backend/src/backend/gen_context.cpp| 8 ++--- backend/src/backend/gen_insn_selection.cpp | 50 +- backend/src/backend/gen_insn_selection.hpp | 5 ++- 4 files changed, 49

[Beignet] [PATCH V2] output more detail of GEN IR for workgroup op

v2: the src number changes for different ops Signed-off-by: Guo, Yejun --- backend/src/ir/instruction.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp index 0687dbf..f0c3957 100644 --- a/backend/src/ir

[Beignet] [PATCH] output more detail of GEN IR for workgroup op

Signed-off-by: Guo, Yejun --- backend/src/ir/instruction.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp index 0687dbf..12ffbdb 100644 --- a/backend/src/ir/instruction.cpp +++ b/backend/src/ir

[Beignet] [PATCH] add sends support for oword/media block write

Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 57 ++ backend/src/backend/gen9_encoder.hpp | 2 ++ backend/src/backend/gen_context.cpp| 6 ++-- backend/src/backend/gen_encoder.cpp| 4 +-- backend/src/backend

Re: [Beignet] [PATCH V4] Backend: Refine block read/write instruction selection

LGTM, thanks. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Xiuli Pan Sent: Monday, December 19, 2016 3:58 PM To: beignet@lists.freedesktop.org Cc: Pan, Xiuli Subject: [Beignet] [PATCH V4] Backend: Refine block read/write instruction selecti

[Beignet] [PATCH] add sends support for printf

Signed-off-by: Guo, Yejun --- backend/src/backend/gen_context.cpp| 21 +++-- backend/src/backend/gen_context.hpp| 2 +- backend/src/backend/gen_insn_selection.cpp | 25 - backend/src/backend/gen_insn_selection.hpp | 1 + 4 files changed

[Beignet] [PATCH V2 2/5] support sends for long write

Signed-off-by: Guo, Yejun --- backend/src/backend/gen_insn_selection.cpp | 28 +++- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 1cd6137..f46207f 100644 --- a

[Beignet] [PATCH V2 5/5] enable sends for typed write

v2: use GBE_ASSERT Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 22 + backend/src/backend/gen9_encoder.hpp | 1 + backend/src/backend/gen_context.cpp| 3 ++- backend/src/backend/gen_encoder.cpp| 2 +- backend/src/backend

[Beignet] [PATCH V2 1/5] refine code to change insn.extra.splitSend as encoder funtion parameter

it makes possible to switch send and sends within the encoder function. v2: use GBE_ASSERT etc. Signed-off-by: Guo, Yejun --- backend/src/backend/gen8_context.cpp | 14 ++--- backend/src/backend/gen8_encoder.cpp | 2 +- backend/src/backend/gen8_encoder.hpp | 2 +- backend/src/backend

[Beignet] [PATCH V2 4/5] refine code starting from header in typedwrite

With this refine, the virtual reg and physical reg will be logically 1:1 mapping, and it helps the later instruction sends v2: use macro NOT_SUPPORTED Signed-off-by: Guo, Yejun --- backend/src/backend/gen_insn_selection.cpp | 145 - 1 file changed, 78 insertions

[Beignet] [PATCH V2 3/5] add sends for atomic operation, only for ocl 1.2

v2: use GBE_ASSERT etc Signed-off-by: Guo, Yejun --- backend/src/backend/gen75_encoder.cpp | 2 +- backend/src/backend/gen75_encoder.hpp | 2 +- backend/src/backend/gen8_encoder.cpp | 2 +- backend/src/backend/gen8_encoder.hpp | 2 +- backend/src/backend

Re: [Beignet] [PATCH 3/5] add sends for atomic operation, only for ocl 1.2

From: Pan, Xiuli Sent: Wednesday, December 14, 2016 4:48 PM To: Guo, Yejun; beignet@lists.freedesktop.org Cc: Guo, Yejun Subject: RE: [Beignet] [PATCH 3/5] add sends for atomic operation, only for ocl 1.2 We have GBE_ASSERT and NOT_IMPLEMENTED NOT_SUPPORTED macro for GBE. Maybe we should not use a

Re: [Beignet] [PATCH] Backend: Refine block read/write instruction selection

two comments, thanks. 1. for header register, we can call: const GenRegister header = GenRegister::ud8grf(sel.reg(ir::FAMILY_REG)); instead of: const GenRegister header = GenRegister::retype(GenRegister::f8grf(sel.reg(FAMILY_REG)), GEN_TYPE_UD); 2. how about separate the logic for SIMD8 and SI

Re: [Beignet] [PATCH 02/19] Runtime: fix clEnqueueMigrateMemObjects fail.

this [PATCH 02/19] looks good to me, thanks. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Yang Rong Sent: Monday, November 28, 2016 7:32 PM To: beignet@lists.freedesktop.org Cc: Yang, Rong R Subject: [Beignet] [PATCH 02/19] Runtime: fix clEn

Re: [Beignet] [PATCH] fix cts issue for clEnqueueMigrateMemObjects

sure. -Original Message- From: Yang, Rong R Sent: Wednesday, December 14, 2016 10:37 AM To: Guo, Yejun; beignet@lists.freedesktop.org Cc: Guo, Yejun Subject: RE: [Beignet] [PATCH] fix cts issue for clEnqueueMigrateMemObjects I have send a same patch " [PATCH 02/19] Runtime

[Beignet] [PATCH] fix cts issue for clEnqueueMigrateMemObjects

test case: test_buffers image_migrate according to spec, the input parameter is valid with mem object Signed-off-by: Guo, Yejun --- src/cl_api_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cl_api_mem.c b/src/cl_api_mem.c index 054c37a..7314a48 100644 --- a/src

[Beignet] [PATCH 5/5] enable sends for typed write

Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 22 + backend/src/backend/gen9_encoder.hpp | 1 + backend/src/backend/gen_context.cpp| 3 ++- backend/src/backend/gen_encoder.cpp| 2 +- backend/src/backend/gen_encoder.hpp

[Beignet] [PATCH 4/5] refine code starting from header in typedwrite

With this refine, the virtual reg and physical reg will be logically 1:1 mapping, and it helps the later instruction sends Signed-off-by: Guo, Yejun --- backend/src/backend/gen_insn_selection.cpp | 145 - 1 file changed, 78 insertions(+), 67 deletions(-) diff --git

[Beignet] [PATCH 3/5] add sends for atomic operation, only for ocl 1.2

Signed-off-by: Guo, Yejun --- backend/src/backend/gen75_encoder.cpp | 2 +- backend/src/backend/gen75_encoder.hpp | 2 +- backend/src/backend/gen8_encoder.cpp | 2 +- backend/src/backend/gen8_encoder.hpp | 2 +- backend/src/backend/gen9_encoder.cpp | 28

[Beignet] [PATCH 2/5] support sends for long write

Signed-off-by: Guo, Yejun --- backend/src/backend/gen_insn_selection.cpp | 28 +++- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 1cd6137..f46207f 100644 --- a

[Beignet] [PATCH 1/5] refine code to change insn.extra.splitSend as encoder funtion parameter

it makes possible to switch send and sends within the encoder function. Signed-off-by: Guo, Yejun --- backend/src/backend/gen8_context.cpp | 14 ++--- backend/src/backend/gen8_encoder.cpp | 2 +- backend/src/backend/gen8_encoder.hpp | 2 +- backend/src/backend/gen9_encoder.cpp | 16

Re: [Beignet] [PATCH V2] Backend: Initialize the extra value for selection instruction

good catch, looks fine to me, thanks. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Xiuli Pan Sent: Friday, December 09, 2016 11:09 AM To: beignet@lists.freedesktop.org Cc: Pan, Xiuli Subject: [Beignet] [PATCH V2] Backend: Initialize the extr

Re: [Beignet] [PATCH 3/3] enable sends for typed write

. thanks yejun -Original Message----- From: Guo, Yejun Sent: Wednesday, December 07, 2016 7:10 PM To: beignet@lists.freedesktop.org Cc: Guo, Yejun Subject: [PATCH 3/3] enable sends for typed write Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 20 +++ back

[Beignet] [PATCH 2/3] change interface for TYPED_WRITE, preparing for sends

Signed-off-by: Guo, Yejun --- backend/src/backend/gen_context.cpp | 2 +- backend/src/backend/gen_encoder.cpp | 2 +- backend/src/backend/gen_encoder.hpp | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend

[Beignet] [PATCH 3/3] enable sends for typed write

Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 20 +++ backend/src/backend/gen9_encoder.hpp | 1 + backend/src/backend/gen_context.cpp| 5 - backend/src/backend/gen_insn_selection.cpp | 31 -- backend/src

[Beignet] [PATCH 1/3] refine code starting from header in typedwrite

With this refine, the virtual reg and physical reg will be logically 1:1 mapping, and it helps the later instruction sends Signed-off-by: Guo, Yejun --- backend/src/backend/gen_insn_selection.cpp | 145 - 1 file changed, 78 insertions(+), 67 deletions(-) diff --git

[Beignet] [PATCH] enable sends for skl

the previous code expected to enable for skl enables kbl Signed-off-by: Guo, Yejun --- backend/src/backend/gen_insn_selection.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 27f3059..6624337

Re: [Beignet] [PATCH 1/2] Backend: Add RegisterFamily for ir

this [PATCH 1/2] looks good, it helps the logical 1:1 mapping between virtual register and physical register. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Xiuli Pan Sent: Thursday, November 24, 2016 5:53 PM To: beignet@lists.freedesktop.org

[Beignet] [PATCH] save host_ptr when create sub buffer from CL_MEM_ALLOC_HOST_PTR

it fixes issue at https://bugs.freedesktop.org/show_bug.cgi?id=98490 Signed-off-by: Guo, Yejun --- src/cl_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cl_mem.c b/src/cl_mem.c index 798daaf..afce315 100644 --- a/src/cl_mem.c +++ b/src/cl_mem.c @@ -636,7 +636,7

[Beignet] [PATCH V2] disable CMRT as default, since no real case reported

and this feature also sometimes introduces build issue. v2: add option INVOKE_CMRT to enable CMRT if necessary Signed-off-by: Guo, Yejun --- CMakeLists.txt | 4 1 file changed, 4 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 713cfa9..503c609 100644 --- a/CMakeLists.txt

Re: [Beignet] [PATCH] disable CMRT as default, since no real case reported

sure, let me send a v2 patch to add a new cmake option -Original Message- From: Yang, Rong R Sent: Wednesday, November 30, 2016 4:33 PM To: Guo, Yejun; beignet@lists.freedesktop.org Subject: RE: [Beignet] [PATCH] disable CMRT as default, since no real case reported If disable it, can

[Beignet] [PATCH] add sends for atomic operation, only for ocl 1.2

Signed-off-by: Guo, Yejun --- backend/src/backend/gen8_encoder.cpp | 2 +- backend/src/backend/gen8_encoder.hpp | 2 +- backend/src/backend/gen9_encoder.cpp | 26 ++ backend/src/backend/gen9_encoder.hpp | 1 + backend/src/backend/gen_context.cpp

[Beignet] [PATCH] support sends for long write

Signed-off-by: Guo, Yejun --- backend/src/backend/gen_insn_selection.cpp | 28 +++- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 8090250..9722423 100644 --- a

[Beignet] [PATCH 1/2] move function setDPByteScatterGather into class GenEncoder

setDPByteScatterGather will be reused by gen9 sends. As for the same function in gen8encoder, just leave it untill the reuse case appears (now, just change the function name to pass build) Signed-off-by: Guo, Yejun --- backend/src/backend/gen8_encoder.cpp | 6 +++--- backend/src/backend

[Beignet] [PATCH 2/2] add sends support for byte write

Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 47 ++ backend/src/backend/gen9_encoder.hpp | 2 ++ backend/src/backend/gen_context.cpp| 15 +++--- backend/src/backend/gen_encoder.cpp| 14 - backend/src

[Beignet] [PATCH V3 2/3] prepare gen9 sends binary format and enable the ASM dump for sends

v2: output dst register for sends v3: check dst reg file when output dst register Signed-off-by: Guo, Yejun --- backend/src/backend/gen/gen_mesa_disasm.c | 31 ++-- backend/src/backend/gen9_instruction.hpp | 84 +++ backend/src/backend/gen_defs.hpp

[Beignet] [PATCH V3 3/3] support sends (split send) for untyped write

stage, only enabeld as default for skylake now. v2: add function setSendsOperands v3: reuse function setDPUntypedRW Signed-off-by: Guo, Yejun --- backend/src/backend/gen75_encoder.cpp | 2 +- backend/src/backend/gen75_encoder.hpp | 2 +- backend/src/backend/gen8_context.cpp | 21

[Beignet] [PATCH 1/3] do not touch src1 when setting instruction header

Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 1 + backend/src/backend/gen_encoder.cpp | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen9_encoder.cpp b/backend/src/backend/gen9_encoder.cpp index 80df50d..e66ae08 100644 --- a

[Beignet] [PATCH] revert clCreateCommandQueue* from ocl2.0 back to 1.2 in utests

since utests is designed to be a general stand-alone application, it is better to use ocl1.2 version API, otherwise, link error on some platforms with only ocl1.2. Signed-off-by: Guo, Yejun --- utests/profiling_exec.cpp | 3 +-- utests/utest_helper.cpp | 4 ++-- 2 files changed, 3 insertions

[Beignet] [PATCH 3/3] support sends (split send) for untyped write

stage, only enabeld as default for skylake now. v2: add function setSendsOperands v3: reuse function setDPUntypedRW Signed-off-by: Guo, Yejun --- backend/src/backend/gen75_encoder.cpp | 2 +- backend/src/backend/gen75_encoder.hpp | 2 +- backend/src/backend/gen8_context.cpp | 21

[Beignet] [PATCH 2/3] prepare gen9 sends binary format and enable the ASM dump for sends

v2: output dst register for sends Signed-off-by: Guo, Yejun --- backend/src/backend/gen/gen_mesa_disasm.c | 31 ++-- backend/src/backend/gen9_instruction.hpp | 84 +++ backend/src/backend/gen_defs.hpp | 3 ++ 3 files changed, 114 insertions(+), 4

[Beignet] [PATCH 1/3] do not touch src1 when setting instruction header

Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 1 + backend/src/backend/gen_encoder.cpp | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen9_encoder.cpp b/backend/src/backend/gen9_encoder.cpp index 80df50d..e66ae08 100644 --- a

[Beignet] [PATCH] fix build issue when HAS_BO_SET_SOFTPIN is false

Signed-off-by: Guo, Yejun --- src/cl_mem.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/cl_mem.c b/src/cl_mem.c index 2b783b9..6a4729d 100644 --- a/src/cl_mem.c +++ b/src/cl_mem.c @@ -801,9 +801,10 @@ void* cl_mem_svm_allocate(cl_context ctx, cl_svm_mem_flags

Re: [Beignet] [PATCH 2/4] support sends (split send) for untyped write

please hold on my v2 patch. let me first try to refine code starting from GenEncoder::setMessageDescriptor. -Original Message- From: Song, Ruiling Sent: Thursday, November 24, 2016 8:15 PM To: Guo, Yejun; beignet@lists.freedesktop.org Subject: RE: [Beignet] [PATCH 2/4] support sends

Re: [Beignet] [PATCH] Backend: Add help function to get a reg in selection

...@lists.freedesktop.org] On Behalf Of Xiuli Pan Sent: Friday, November 18, 2016 12:56 PM To: beignet@lists.freedesktop.org Cc: Guo, Yejun; Pan, Xiuli Subject: [Beignet] [PATCH] Backend: Add help function to get a reg in selection From: Pan Xiuli We now can get a reg as header or tmp register for

[Beignet] [PATCH V2 4/4] add sends support for byte write

v2: use function setSendsOperands Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 48 ++ backend/src/backend/gen9_encoder.hpp | 2 ++ backend/src/backend/gen_context.cpp| 15 +++--- backend/src/backend/gen_encoder.cpp

[Beignet] [PATCH V2 2/4] support sends (split send) for untyped write

stage, only enabeld as default for skylake now. v2: add function setSendsOperands() Signed-off-by: Guo, Yejun --- backend/src/backend/gen75_encoder.cpp | 2 +- backend/src/backend/gen75_encoder.hpp | 2 +- backend/src/backend/gen8_context.cpp | 21 ++--- backend/src/backend

[Beignet] [PATCH V2 1/4] prepare gen9 sends binary format and enable the ASM dump for sends

v2: output dst register for sends Signed-off-by: Guo, Yejun --- backend/src/backend/gen/gen_mesa_disasm.c | 31 +++-- backend/src/backend/gen9_instruction.hpp | 112 ++ backend/src/backend/gen_defs.hpp | 3 + 3 files changed, 142 insertions(+), 4

Re: [Beignet] [PATCH 2/4] support sends (split send) for untyped write

[Yejun] Actually, I'm refining the code locally with setSendsOperand(dst, src0, src1). What's your opinion? -Original Message- From: Song, Ruiling Sent: Wednesday, November 23, 2016 10:15 PM To: Guo, Yejun; beignet@lists.freedesktop.org Cc: Guo, Yejun Subject: RE: [Beignet] [PATCH

Re: [Beignet] [PATCH 1/4] prepare gen9 sends binary format and enable the ASM dump for sends

ok -Original Message- From: Song, Ruiling Sent: Thursday, November 24, 2016 10:33 AM To: Guo, Yejun; beignet@lists.freedesktop.org Subject: RE: [Beignet] [PATCH 1/4] prepare gen9 sends binary format and enable the ASM dump for sends > -Original Message- > From: Guo,

Re: [Beignet] [PATCH 1/4] prepare gen9 sends binary format and enable the ASM dump for sends

ednesday, November 23, 2016 10:15 PM To: Guo, Yejun; beignet@lists.freedesktop.org Cc: Guo, Yejun Subject: RE: [Beignet] [PATCH 1/4] prepare gen9 sends binary format and enable the ASM dump for sends > -Original Message- > From: Beignet [mailto:beignet-boun...@lists.freedesktop.or

[Beignet] [PATCH 4/4] add sends support for byte write

Signed-off-by: Guo, Yejun --- backend/src/backend/gen9_encoder.cpp | 58 ++ backend/src/backend/gen9_encoder.hpp | 2 ++ backend/src/backend/gen_context.cpp| 15 +--- backend/src/backend/gen_encoder.cpp| 14 +++- backend/src

[Beignet] [PATCH 2/4] support sends (split send) for untyped write

stage, only enabeld as default for skylake now. Signed-off-by: Guo, Yejun --- backend/src/backend/gen75_encoder.cpp | 2 +- backend/src/backend/gen75_encoder.hpp | 2 +- backend/src/backend/gen8_context.cpp | 21 +++ backend/src/backend/gen8_encoder.cpp | 2

[Beignet] [PATCH 3/4] support sends for long write

Signed-off-by: Guo, Yejun --- backend/src/backend/gen_insn_selection.cpp | 28 +++- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index deebafa..ea385ac 100644 --- a

[Beignet] [PATCH 1/4] prepare gen9 sends binary format and enable the ASM dump for sends

Signed-off-by: Guo, Yejun --- backend/src/backend/gen/gen_mesa_disasm.c | 28 ++-- backend/src/backend/gen9_instruction.hpp | 112 ++ backend/src/backend/gen_defs.hpp | 3 + 3 files changed, 139 insertions(+), 4 deletions(-) create mode 100644

[Beignet] [PATCH 2/2] do not care dst for printf

acutally, the dst of printf means nothing, don't need to touch it. Signed-off-by: Guo, Yejun --- backend/src/backend/gen_context.cpp| 14 ++ backend/src/backend/gen_insn_selection.cpp | 20 +--- 2 files changed, 11 insertions(+), 23 deletions(-) diff --

[Beignet] [PATCH 1/2] remove some redundant code for printf

tmp0 is added into src in selection stage, and just ignored at context stage, it is redundant. Signed-off-by: Guo, Yejun --- backend/src/backend/gen_context.cpp| 2 -- backend/src/backend/gen_insn_selection.cpp | 54 +- 2 files changed, 15 insertions(+), 41

Re: [Beignet] [PATCH] disable CMRT as default, since no real case reported

ping for review, thanks. -Original Message- From: Guo, Yejun Sent: Tuesday, October 25, 2016 3:33 PM To: beignet@lists.freedesktop.org Cc: Guo, Yejun Subject: [PATCH] disable CMRT as default, since no real case reported and this feature also sometimes introduces build issue. Signed-off

[Beignet] [PATCH] disable CMRT as default, since no real case reported

and this feature also sometimes introduces build issue. Signed-off-by: Guo, Yejun --- CMakeLists.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index d839f3f..039f9cd 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -170,7 +170,9

Re: [Beignet] [PATCH] Fix build failure with CMRT enabled

LGTM, thanks. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Rebecca N. Palmer Sent: Thursday, October 13, 2016 6:15 AM To: beignet@lists.freedesktop.org Subject: [Beignet] [PATCH] Fix build failure with CMRT enabled 2baff9c moved mem->magic

Re: [Beignet] [PATCH] buildsys: Use CMRT_LIBDIR instead of CMRT_LIBRARY_DIRS

That's great, thanks. -Original Message- From: Armin K. [mailto:kre...@email.com] Sent: Monday, October 10, 2016 12:57 AM To: Guo, Yejun; beignet@lists.freedesktop.org Subject: Re: [Beignet] [PATCH] buildsys: Use CMRT_LIBDIR instead of CMRT_LIBRARY_DIRS On 09.10.2016 04:34, Guo,

Re: [Beignet] [PATCH] buildsys: Use CMRT_LIBDIR instead of CMRT_LIBRARY_DIRS

thanks Armin, the patch looks good to me. could you also send a patch to fix CMRT_INCLUDE_DIRS? thanks. thanks yejun -Original Message- From: Armin K. [mailto:kre...@email.com] Sent: Saturday, October 08, 2016 4:50 PM To: Guo, Yejun; beignet@lists.freedesktop.org Subject: Re: [Beignet

Re: [Beignet] [PATCH] buildsys: Use CMRT_LIBDIR instead of CMRT_LIBRARY_DIRS

Hi Armin, thanks for your patch. We use pkg_check_modules(CMRT libcmrt) in path_of_beignet/CMakeList.txt Line 173 to detect libcmrt. CMRT_INCLUDE_DIRS and CMRT_LIBRARY_DIRS are the expected macro to use, see https://cmake.org/cmake/help/v3.0/module/FindPkgConfig.html or https://cmake.org/cm

[Beignet] [PATCH 2/2] change PCI_CHIP_BROXTON_P to PCI_CHIP_BROXTON_0 to unify the naming

Signed-off-by: Guo Yejun --- src/cl_device_data.h | 4 ++-- src/cl_device_id.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cl_device_data.h b/src/cl_device_data.h index 3e6ac91..4ee4ca3 100644 --- a/src/cl_device_data.h +++ b/src/cl_device_data.h @@ -297,13

[Beignet] [PATCH 1/2] add bxt with pciid 0x1A85

contributor: Curfman, Matthew C Signed-off-by: Guo Yejun --- src/cl_device_data.h | 4 +++- src/cl_device_id.c | 34 ++ src/intel/intel_driver.c | 3 ++- src/intel/intel_gpgpu.c | 3 ++- 4 files changed, 25 insertions(+), 19 deletions(-) diff --git

[Beignet] [PATCH] correct the kernel name

Signed-off-by: Guo Yejun --- src/cl_command_queue_gen7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cl_command_queue_gen7.c b/src/cl_command_queue_gen7.c index 5ad3b8b..9cdeb4c 100644 --- a/src/cl_command_queue_gen7.c +++ b/src/cl_command_queue_gen7.c @@ -354,7

[Beignet] [PATCH] add bxt with pciid 0x1A84

Signed-off-by: Guo Yejun --- src/cl_device_data.h | 4 +++- src/cl_device_id.c | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/cl_device_data.h b/src/cl_device_data.h index 30366ea..a237b0e 100644 --- a/src/cl_device_data.h +++ b/src/cl_device_data.h @@ -299,10

[Beignet] [PATCH] enlarge scratch size for bxt 0x5a85

Signed-off-by: Guo Yejun --- src/intel/intel_gpgpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c index 3314ab4..f8eac56 100644 --- a/src/intel/intel_gpgpu.c +++ b/src/intel/intel_gpgpu.c @@ -1537,8 +1537,8

[Beignet] [PATCH] enlarge stack size for chv since its EU might be masked

Signed-off-by: Guo Yejun --- src/intel/intel_driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/intel_driver.c b/src/intel/intel_driver.c index ec2fb31..0766ca3 100644 --- a/src/intel/intel_driver.c +++ b/src/intel/intel_driver.c @@ -468,7 +468,7

[Beignet] [PATCH V2] add another broxton pciid 0x5A85

v2: split the code relative to chv to another patch Signed-off-by: Guo Yejun --- src/cl_command_queue_gen7.c | 11 ++- src/cl_device_data.h| 4 +++- src/cl_device_id.c | 23 ++- src/cl_driver.h | 4 src/cl_driver_defs.c| 1

Re: [Beignet] [PATCH] add another broxton pciid 0x5A85

to be precise, I'll separate the patch into two, one for bxt, and another one for chv. -Original Message- From: Pan, Xiuli Sent: Monday, September 12, 2016 10:57 AM To: Guo, Yejun; beignet@lists.freedesktop.org Subject: RE: [Beignet] [PATCH] add another broxton pciid 0x5A85 I thin

Re: [Beignet] [PATCH] add another broxton pciid 0x5A85

thanks, and the stack size bug need to be fixed to get 100% passrate of utest for this pciid, that's the reason I merge them into one patch. -Original Message- From: Pan, Xiuli Sent: Monday, September 12, 2016 10:36 AM To: Guo, Yejun; beignet@lists.freedesktop.org Cc: Guo, Yejun Su

[Beignet] [PATCH] add another broxton pciid 0x5A85

Signed-off-by: Guo Yejun --- src/cl_command_queue_gen7.c | 11 ++- src/cl_device_data.h| 4 +++- src/cl_device_id.c | 23 ++- src/cl_driver.h | 4 src/cl_driver_defs.c| 1 + src/intel/intel_driver.c| 10 ++ 6

Re: [Beignet] [PATCH] Backend: Increase stack size for CHV device

after sync with Xiuli, I'll merge it to another patch and send out later -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Xiuli Pan Sent: Friday, September 09, 2016 1:38 PM To: beignet@lists.freedesktop.org Cc: Pan, Xiuli Subject: [Beignet] [PAT

[Beignet] [PATCH] fix w of image when simulate image1dbuffer with image2d

and also change the utest to hit the potential case Signed-off-by: Guo Yejun --- src/cl_mem.c | 1 - utests/image_1D_buffer.cpp | 6 +++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/cl_mem.c b/src/cl_mem.c index 06e7c18..ad1c8c2 100644 --- a/src/cl_mem.c

[Beignet] [PATCH] avoid too many messages when the driver could not find good values for local_size

Signed-off-by: Guo Yejun --- src/cl_api.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/cl_api.c b/src/cl_api.c index d0d4dc5..a7c78f0 100644 --- a/src/cl_api.c +++ b/src/cl_api.c @@ -3032,8 +3032,17 @@ clEnqueueNDRangeKernel(cl_command_queue command_queue

[Beignet] [PATCH V2] fix the condition to check if there are built-in kernels

an empty string is returned if no built-in kernels are supported by the device, and so the returned size is 1, not 0. v2: output "Skip!" to make the result clear Signed-off-by: Guo Yejun --- utests/builtin_kernel_max_global_size.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletio

[Beignet] [PATCH] use OCL_MAP_BUFFER_GTT to map climage

Signed-off-by: Guo Yejun --- utests/runtime_cmrt.cpp | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/utests/runtime_cmrt.cpp b/utests/runtime_cmrt.cpp index 837f09a..92bd368 100644 --- a/utests/runtime_cmrt.cpp +++ b/utests/runtime_cmrt.cpp @@ -236,8 +236,8

[Beignet] [PATCH] fix the condition to check if there are built-in kernels

an empty string is returned if no built-in kernels are supported by the device, and so the returned size is 1, not 0. Signed-off-by: Guo Yejun --- utests/builtin_kernel_max_global_size.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/utests

[Beignet] [PATCH] add help for 'make package'

Signed-off-by: Guo Yejun --- docs/Beignet.mdwn | 4 1 file changed, 4 insertions(+) diff --git a/docs/Beignet.mdwn b/docs/Beignet.mdwn index 9345bfa..914cbce 100644 --- a/docs/Beignet.mdwn +++ b/docs/Beignet.mdwn @@ -104,6 +104,10 @@ your library installation directory. It installs the

[Beignet] [PATCH] only check beignet special test cases on beignet

with other implementation, do not check the result for the beignet special test cases Signed-off-by: Guo Yejun --- utests/get_cl_info.cpp | 85 -- 1 file changed, 47 insertions(+), 38 deletions(-) diff --git a/utests/get_cl_info.cpp b/utests

[Beignet] [PATCH] use different pointer alignment for different implementation

beignet only requirs 64 bytes alignment while other implementations might require 4096 alignment. and also change function cl_check_beignet for better output message. Signed-off-by: Guo Yejun --- utests/compiler_time_stamp.cpp| 4 +++- utests/runtime_use_host_ptr_image.cpp | 8

[Beignet] [PATCH] remove "\n" in output message when test is failed

otherwise, "[FAILED]" and the test name is not in the same line. Signed-off-by: Guo Yejun --- utests/builtin_lgamma.cpp | 2 +- utests/builtin_lgamma_r.cpp | 2 +- utests/builtin_tgamma.cpp | 2 +- utests/image_1D_buffer.cpp | 2 +- 4 files changed, 4 insertions(+), 4 deletion

[Beignet] [PATCH] utests: only check -dump-spir-binary on beignet implementation

Signed-off-by: Guo Yejun --- utests/get_cl_info.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/utests/get_cl_info.cpp b/utests/get_cl_info.cpp index bdd7e0c..bd557c3 100644 --- a/utests/get_cl_info.cpp +++ b/utests/get_cl_info.cpp @@ -465,12 +465,14 @@ void

[Beignet] [PATCH] utests: change tolerance check for lgamma

according to spec section 7.4: The ULP values for built-in math functions lgamma and lgamma_r is currently undefined, let's use 16*ULP for lgamma result. Signed-off-by: Guo Yejun --- utests/utest_math_gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/u

Re: [Beignet] [PATCH V3] Utset: Add check for workgroup tests

looks good to me, thanks. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Xiuli Pan Sent: Wednesday, July 27, 2016 10:11 AM To: beignet@lists.freedesktop.org Cc: Pan, Xiuli Subject: [Beignet] [PATCH V3] Utset: Add check for workgroup tests Fro

Re: [Beignet] [PATCH] Runtime: fix a userptr bug.

LGTM, thanks. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Yang Rong Sent: Tuesday, July 26, 2016 4:50 PM To: beignet@lists.freedesktop.org Cc: Yang, Rong R Subject: [Beignet] [PATCH] Runtime: fix a userptr bug. Userptr also require size ca

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