Hi there
I think building a multicast receiver is non-trivial. Doing multicast the
right way requires that hosts implement IGMP (Internet Group Management
Protocol).
If you are running sshd or telnetd on the roach you can connect to
those over the 10GbE
interface attached to the FPGA. It
Hi Casperites,
Does anybody have experience with this Intel card???
I would like to buy a new one but the two listed in the CASPER Wiki
(https://casper.berkeley.edu/wiki/Recommended_10_GbE_Hardware) are not
available
on local sellers.
Do you have tested any other cards?
Thanks to all.
Andrea
The timing was so bad that it didn't get beyond the mapping stage.
Follow the instructions in the error message:
Please use the Timing Analyzer (GUI) or TRCE (command line) with the
Mapped NCD
so run the $XILINX/settings64.sh and then timingan and use the open
design option to open the
Hi all,
I'm compiling a model file for ROACH1 but I have to solve some timing
constraints which are not met. Unfortunately, the system.twx file to
be opened with the timing analyzer which should be found in
XPS_R..BASE/implementations/ is missing.
Hmm. If it got as far as the snapshot
Hi Casperites,
Does anybody have experience with this Intel card???
I would like to buy a new one but the two listed in the CASPER Wiki
(https://casper.berkeley.edu/wiki/Recommended_10_GbE_Hardware) are not
available
on local sellers.
Do you have tested any other cards?
Hi Andrea.
We
Hey Andrea,
I think (http://www.xilinx.com/support/answers/23165.html) the ngc
file is all you're going to get, unless you run the compile again with
the XIL_TIMING_ALLOW_IMPOSSIBLE variable set to 1.
Your error is some specific component that has impossible timing
constraints -- it's not just
I'm sure, the directory is correct, because I do that very often, but
in this case the system.twx is really missing. The only file readable
from the timingan is a ngc file but I don't know how to investigate
timing with that.
Can be an issue related to the ADC or some resources ended? This is
the
Thanks Jack,
can be a z^-2048 delay??
Andrea
2013/10/2 Jack Hickish jackhick...@gmail.com:
Hey Andrea,
I think (http://www.xilinx.com/support/answers/23165.html) the ngc
file is all you're going to get, unless you run the compile again with
the XIL_TIMING_ALLOW_IMPOSSIBLE variable set to
mmm yes I think that's the problem, I have read the system generator
reference manual at the delay block page and should be definitely a
problem to have big delay coupled with big data bus width.
Thanks,
I will try i a different way and will report the improvements (hopefully).
Andrea
2013/10/2
Yes, this license includes ISE and I have just confirmed that it is working
fine.
Thanks,
Nimish
On Tue, Oct 1, 2013 at 6:05 PM, Gary, Dale E. dale.e.g...@njit.edu wrote:
I just updated our old license, which had ended in Dec. 2012, by entering
a request on XUP (Xilinx University Program),
Hi, Jason,
On Oct 1, 2013, at 11:13 PM, Jason Manley wrote:
Pretty much all the layer 2+ switches (all the 10GbE unit that CASPERites
are using, to the best of my knowledge) support proper multicasting through
IGMP snooping. I figure we can do this setup part through the PPC without
Hi, Andrea,
We used a dual port CX-4 Intel NIC for the previous PAPER correlator X engines:
http://www.intel.com/content/dam/doc/product-brief/10-gigabit-cx4-dual-port-server-adapter-brief.pdf
That NIC's PCIe interface only ran at 2.5 GT/s and x8 width, which works out to
an 8/10B encoded data
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