2) Can multiple clock rates be set/used in the ROACH2 board? For example,
can we use the ADC clock for ADC captures and a (much) faster clock for the
data processing portion of the algorithm?
Most of the CASPER DSP blocks are designed to run synchronously with the ADC.
So short of
If you do large reads (ie single request), I've managed 8Mbps using KATCP. Our
RATTY1 design does 16384x64b channels every 500ms, which is 2Mbps. The key is
to do lots of big reads rather than lots of little ones.
However, I would stress that the KATCP path is designed for control and
Hello
The path FGA-PPC-ethernet-python hasn't been
optimised for speed. So if you can get hold of a
PCI(e) CX4 ethernet card for your capture machine
then you will save yourself a considerable amount
of effort and get way better max transfer rates
However: If this isn't an option, there are a
Thanks everyone for the input.
I've been trying not to move towards the 10 gb option if possible for
a couple of reasons but I might have to bite the bullet.
I'm also going to look at another option which is with the mmap kernel I
have access to the FPGA memory in /dev/roach/mem. I think it
Hi Dave,
Boot the board, stop in U-Boot, write to the DMA registers
directly, and probe the bus to see what the maximum rate possible
is ... then you can decide whether to write a device driver to use
the DMA controller under Linux.
Oh, yeah, trying to use the DMA controllers on the PPC side
Hi Guys,
Thanks - I'm initially going to pursue the mmap option. I
think quite a few of the issues are tcp latencies and by removing
those I can make the link more reliable. I'm looking at a max of
about 5Mb/s through the FPGA--PPC interface. I should fairly soon be
able to check what speed I
So I just did a very quick test where I read 10 an ADC snapshot
(8192 Bytes) via mmap(boost::iostreams::mapped_file) using
std::copy(). This took about 52 seconds which is about 15MB/s or
120Mb/s - Sound to fast???
Ross
On Wed, Oct 16, 2013 at 11:47 AM, Ross Williamson
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