Re: [casper] PL data to PS DDR4 (AXI) {External}

DMA isn't always the best answer. It's sometimes best to just leave the data in the PL and have the processor access it directly. If the processor reads the data directly, it's just accessed once, and only the data you need is accessed. If you transfer via DMA, it's read once by the DMA from

[casper] New FFT released

Hi Casperites, I’d like to announce my BxBFFT 4.0 release, with new academic pricing: $1000 each for small academic projects. This is not a free FFT, so why use it? The main reason so far has been power savings. It’s saved several people several watts when they use the BxBFFT instead of

Re: [casper] RFSoC4x2 App

, 2023, 7:44 AM 'Ross Martin' via casper@lists.berkeley.edu > wrote: > >> Hi Casperites! >> >> I’m happy to announce that I’m releasing a free app for academic users of >> the RFSoC4x2 board. The app can display ADC frequency spectrums, display >> time waveforms, me

[casper] RFSoC4x2 App

Hi Casperites! I’m happy to announce that I’m releasing a free app for academic users of the RFSoC4x2 board. The app can display ADC frequency spectrums, display time waveforms, measure transfer functions between ADC inputs, and generate rudimentary test waveforms out the DACs. It runs

Re: [casper] Doubts about clocking in RFSOC4x2

Hi Sebastian, I have an app that I'd like to port to the RFSoC4x2 that might help -- when I can get some help porting it. It currently works on several boards including the ZCU208, which has the same clock chips as the RFSoC4x2. The app allows you to set the ADC clocks to almost any desirable

Re: [casper] very recent results from monitoring masers

I assume you removed the linear before performing the sine fit? On Fri, Dec 30, 2022, 6:09 PM Dr Gordon MacLeod wrote: > Hi Andrew, > > Hope you are enjoying your Christmas break, Merry Christmas! > > I thought I'd share with you an image I've recently created on excited-OH > masers at 6.035

Re: [casper] wideband real FFT with Xilinx Vector FFT

the Astron FFT, which only supports a partially-natural data order out. > > If you know of any other Verilog or VHDL SSR FFTs that I can get code for, > I’d be happy to benchmark those also. These are the ones I could find. > > Regards, > > Ross > > >> On Feb 24,

Re: [casper] wideband real FFT with Xilinx Vector FFT

be happy to benchmark those also. These are the ones I could find. Regards, Ross > On Feb 24, 2022, at 4:39 AM, Jack Hickish wrote: > > > > On Thu, 24 Feb 2022 at 05:05, 'Ross Martin' via casper@lists.berkeley.edu > <mailto:casper@lists.berkeley.edu> <mailto:casper

Re: [casper] wideband real FFT with Xilinx Vector FFT

Hi Jack, Yes, the Xilinx SSR FFT is good, but there are some caveats. In my testing, its performance degrades severely if the FFT size is greater than 8192 or if the SSR is greater than 8. It’s very good on both DSP and BRAM utilization, but it’s mediocre on LUT usage and power consumption.

Re: [EXTERNAL] Re: [casper] Inverting the Polyphase Filter Bank

Hi Nikhil, What you want to look for is non-critically-sampled PFBs and their inverses. Unfortunately they go by many names, such as PFBs, analysis/synthesis filter banks, WOLA filters, Channelizers, FFT Filter Banks, etc. The issues that Jon and Matt raised are specific to critically-sampled

Re: [casper] AD9207 FMC board

Hi Jack, I notice that on this board from Analog Devices with FMC+, the AD9207 is listed as a compatible part. So there must be something from Analog Devices that connects them? Maybe you can pursue that through their sales/support.