Thanks for all the info.
Well, it turns out that the clock chip was the culprit. Although it met
the 50 PPM Ethernet frequency stability requirement, it had a LOT of
jitter. I replaced it with a $1.98 ECS crystal oscillator (as opposed to
the MEMS oscillator, and it Just Worked. I am amazed and
Jean,
You're right. Getting the pinout wrong on the ethernet connectors probably
leads to false pairing rather than to loss of one wire in the pair.
Regards,
Ross
On Wed, Feb 19, 2020, 3:09 AM Borsenberger Jean
wrote:
> Hello
>
> Incorrect cabling would lead to force to dowgrade giga to
Hi John,
Another thing to check for is a missing or incorrect timing constraint -
Vivado constraints wizard may pick up something (tsu, th, tco).
Best
HK
On Wed, Feb 19, 2020 at 12:09 PM Borsenberger Jean <
jean.borsenber...@obspm.fr> wrote:
> Hello
>
> Incorrect cabling would lead to force
Hello
Incorrect cabling would lead to force to dowgrade giga to fast, or no
connection at all.
With that hi level of CRC, I would first address a connector weakness (contact
not complete), or a lack of shielding in a perturbated area, and most unlikely
false pairing inside the cable ( all
Hi John,
I'll throw out a possibility. Perhaps the cabling isn't correct and you're
only getting connectivity on one of the two wires in the differential
pair. This would work *sometimes*, which is about what you're seeing.
This might happen if you wired your own cables or connectors and laid t
On Friday, February 14, 2020 at 12:45:21 AM UTC-7, henno wrote:
>
> Hi John,
>
> I have a few questions / remarks / suggestions:
>
> Do you observer CRC errors in both directions or is it only from FPGA to
> PC?
>
I think it is in both directions, but I haven't exhaustively tested the PC
to FP
Hi John,
I have a few questions / remarks / suggestions:
Do you observer CRC errors in both directions or is it only from FPGA to PC?
In RGMII, the TX and RX clocks are not synced, but in loopback mode it is,
which might point to a metastability issue when you connect to the PC.
Is the PCB a cu
Hi all.
I'm designing an FPGA based instrument control system with a gigabit
Ethernet port. It should be easy to make this work, but alas, it's giving
me fits.
I have a Xilinx Artix-7 FPGA on the board, driving a TI PHY using the RGMII
interface from the Xilinx tri-mode Ethernet MAC core. It mo
8 matches
Mail list logo
