Re: [casper] Help with timing constraint

Hi Heystek. Basically, what the error is saying, is that you have specified that the logic contained in the design should be able to run at a certain clock frequency, but that the compiler has not been able to place the logic in the FPGA and find routes between, that will allow the design to make

Re: [casper] Help with timing constraint

Hi Heystek, One other question: How fast is the clock rate you are trying to compile? For ROACH2, if you're above a 200MHz clock (and definitely if you're above 250MHz), or if you have a very full design, I've often found that you need to use PlanAhead to make the design meet timing. A (very outd

Re: [casper] Help with timing constraint

Hi, Heystek, I think the build will generate a timing report in a file that ends with ".twr". If it's not, you can generate one using the "trce" utility (part of ISE). This will tell you how many nets failed timing and show details of the N worst offenders (I think N defaults to 3 or maybe 10

Re: [casper] Help with timing constraint

Hey Andrew and James and everyone. After probed around and the following timing constraint is not met: TS_sys_clk_n I assume that my system clock is not running at an appropriate frequency? Thanks for the help! Heystek On Wed, Aug 26, 2020 at 10:59 AM Andrew Martens wrote: > Hi Heystek >

Re: [casper] Help with timing constraint

Hi Heystek Output reports and their location change over versions, between ISE and Vivado etc. I think the output reports for ISE are located in the 'implementation' folder. I think the timing related ones have 'timing' in the name... A quick Google search of the error will help. Note that there

Re: [casper] Help with timing constraint

Hi Heystek, It's possible that you then have another issue that causes the build process to exit prior to generating that file. You'll need to debug that first. Regards, Andrew On Wed, Aug 26, 2020 at 10:40 AM Heystek Grobler wrote: > Hey Andrew > > It is strange, I cant seem to locate top_tim

Re: [casper] Help with timing constraint

Hey Andrew It is strange, I cant seem to locate top_timing_summary_routed.rpt I am running Matlab 2012B with ISE 14.7 > On 26 Aug 2020, at 10:27, Andrew van der Byl wrote: > > Hi Heystek, > > 1) Navigate to your project folder > 2) Then go to and open: > /myproj/myproj.runs/impl_1/top_tim

Re: [casper] Help with timing constraint

Hi Heystek, 1) Navigate to your project folder 2) Then go to and open: /myproj/myproj.runs/impl_1/ top_timing_summary_routed.rpt Just a note - this file is usually fairly large as text files go ~20MB. Regards, Andrew On Wed, Aug 26, 2020 at 10:22 AM Heystek Grobler wrote: > Hey James and Andr

Re: [casper] Help with timing constraint

Hey James and Andrew Thank you so much for the advice! @Andrew, this might be a stupid question, but where do I locate the top_timing_summary_routed.rpt file? Heystek > On 26 Aug 2020, at 10:17, Andrew van der Byl wrote: > > Hi Heystek, > > Have a look in top_timing_summary_routed.rpt a

Re: [casper] Help with timing constraint

Hi Heystek, Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED' - this usually shows up which paths are hurting your design. Then, as James said, start pipeling your design. Hope this helps. Regards, Andrew On Wed, Aug 26, 2020 at 10:13 AM James Smith wrote: > Hello Heystek

Re: [casper] Help with timing constraint

Hello Heystek, You will have to go through the timing reports and see which signal path is failing timing, and by how much. Once you have an idea, you will need to sprinkle delay blocks and / or adjust latencies in your logic to get to a point where the place-and-route can find a layout that sati

[casper] Help with timing constraint

Good day everyone I am running a design but ran into this problem: xflow done! touch __xps/system_routed xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par Analyzing implementation/system.par *