Hi Dave,
Thanks for this great tip.
Can Robert ask about ballpark pricing for this Intel SoC?
Best wishes,
Jonathan Weintroub
> On Feb 3, 2021, at 4:40 PM, 'Hawkins, David W (US 334B)' via
> casper@lists.berkeley.edu wrote:
>
> Hi All,
>
> Robert Jarnot will try to contact the authors
This is very interesting news, David. Thanks for sharing it.
On Tue, Feb 2, 2021, 10:24 PM 'Hawkins, David W (US 334B)' via
casper@lists.berkeley.edu wrote:
> Hi All,
>
>
>
> I know we are all using Xilinx devices, and CASPER is beginning to check
> out the RFSoC devices.
>
>
>
> Intel have
Hi Jonathan,
>> Can Robert ask about ballpark pricing for this Intel SoC?
Sure, but have you ever got a straight answer from an FPGA vendor on their
pricing?
Intel Marketing: Our devices have 10x the bandwidth of the competition, so we
should charge 5x the competitor.
I’ll definitely ask
Hi All,
Robert Jarnot will try to contact the authors of the document you can find on
the Intel page. We will see if they can make some devices available for
spectrometer applications. The video on the web site shows 32GHz of sampled
bandwidth with pretty high SNR … just what we would love to
Hi Kaj,
Okay, at least you are synthesising now - well done! It looks like it can't
find the sysgen entity in your top.v. This can happen if your system
generator did not run correctly.
Please can you do the following for me:
1) zip up your "test_snap" folder under "jasper_library/test_models"
Hi Adam,
Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully
INFO: [Common 17-206] Exiting Vivado at Wed Feb 3 13:27:22 2021...
Created
/home/kjwiik/mlib_devel/jasper_library/test_models/test_snap_adc/outputs/test_snap_adc_2021-02-03_1321.bof
Hi Kaj,
Excellent! :). I am glad you are finally sorted and I was happy to assist
where I could. Looking forward to that beer in better times ;).
I suggest that you go on the CASPER slack group and ask there about ZCU111.
There is a #RFSoC channel, which will provide you all the information on
Hi Kaj,
Good news and bad news. The good news is that when I compile
"test_snap.slx" then I get the same issue as you and yes, sysgen is not
building properly for some reason - hence, the error. This means there is
something not correct with the "test_snap.slx" file. The bad news is that I
am not
Hi Folks,
I’m wondering if any of you have dived into HLS at any length? While
we’ve made good progress with our HLS OPFB, I consistently run into challenges
at the nexus of code style, pipeline vs data flow, and cosim.
Cheers,
-Jeb
——
Dr. J.I. Bailey, III (Jeb) / Project Scientist
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