Re: [casper] casperfpga module error: no module named bitfield

;> >>> What I can suggest doing is the following: >>> >>> Uninstall casperfpga >>> >> pip uninstall casperfpga >>> >>> Then in your git directory, do a >>> >> git checkout py3-merge >>> >>> This will s

[casper] casperfpga module error: no module named bitfield

Greetings Casperites, I'm new to Linux, and I think I must have some simple setting adjusted incorrectly. I'm running ubuntu 16.04 and tried this on a fresh install. I first simply tried "pip install casperfpga", but this gave me the error message: ERROR: Could not find a version that

[casper] Writing data to SD card

Hello all, I'm working on a project that has a Red Pitaya mounted in a drone. It will be monitoring and correlating two antenna inputs. Because the red pitaya will be in a drone, I need to store the processed data coming out of the FPGA onto the SD card. Is this something anyone has worked

[casper] Red Pitaya SDRlab 122-16

Hello Casperites, I was looking at the new Red Pitaya board that has come out recently: https://www.redpitaya.com/Catalog/p52/sdrlab-122-16-standard-kit?cat=c102 It features wider out-of-the box bandwidth (no front end filtering), a bigger FPGA, and 16-bit ADCs. Are there any plans to add

[casper] Red Pitaya access registers of snap blocks from PS

Hi all, I'm trying to determine how I would go about finding/using the addresses of the memory mapped registers being used by the FPGA, from the PS side of the Red Pitaya. For example, in the spectrometer tutorial, there are several registers used to control the design, and others to pull data

Re: [casper] Red Pitaya access registers of snap blocks from PS

g file that you uploaded and the > header will contain the memory map. You can also see the memory map in a > file called coreinfo.tab in your build directory. > > Hope this helps. > > Wesley New > South African SKA Project > +2721 506 7300 > www.ska.ac.za >

Re: [casper] Red Pitaya access registers of snap blocks from PS

all full blown casperfpga to > your red pitaya, and connect via localhost using the scripts you already > have. Unless your performance requirements are such that python is out of > the question, this is probably the easiest thing to do. > > Cheers > Jack > > > On Sun, 31 May

[casper] Removing front end filter from Red Pitaya

Greetings Casperites, I'm working on a project with the Red Pitaya that will be sampling higher nyquist zones. The ADC on the red pitaya, the LTC2145-14, has the specs to do what I need, but the Red Pitaya itself has a 62.5MHz low pass filter on the front end and I will need to bypass this.

[casper] A bug in the Xilinx FFT frame sync

I'm working on a design where the input sources to the Red Pitaya are switched at ~4Hz for calibration purposes. I was implementing functionality to prevent data from one calibration state ending up in the accumulator during the next calibration state, and I started getting some strange