[PATCH] D108886: Add RISC-V sifive-s51 cpu

evandro added a comment. In D108886#2978169 , @apivovarov wrote: > Add Cortex-A78C Support for Clang and LLVM > > is similar to this patch. As we can see

[PATCH] D108886: Add RISC-V sifive-s51 cpu

evandro added a comment. In D108886#2978038 , @apivovarov wrote: > Evandro, similar notes have been made in the past for Release Notes 12.x and > 11.x for Arm and RISC-V processors: >

[PATCH] D108886: Add RISC-V sifive-s51 cpu

evandro added a comment. I don't think that such a minor change makes sense to be added to the release notes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108886/new/ https://reviews.llvm.org/D108886

[PATCH] D108886: Add RISC-V sifive-s51 cpu

evandro accepted this revision. evandro added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108886/new/ https://reviews.llvm.org/D108886

[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

evandro added a comment. Also, when the V spec becomes official, it'll be labeled v2.0. Therefore, as long as v0.9 or v1.0 is implemented, V is only available as an experimental feature. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94583/new/

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

evandro updated this revision to Diff 310044. evandro marked 2 inline comments as done. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92715/new/ https://reviews.llvm.org/D92715 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/AST/Type.h

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

evandro marked 7 inline comments as done. evandro added inline comments. Comment at: clang/include/clang/Basic/RISCVVTypes.def:32 +// - ElBits is the size of one element in bits (SEW). +// +// - IsSigned is true for vectors of signed integer elements and

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

evandro updated this revision to Diff 309750. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92715/new/ https://reviews.llvm.org/D92715 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/AST/Type.h clang/include/clang/AST/TypeProperties.td

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

evandro updated this revision to Diff 309749. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92715/new/ https://reviews.llvm.org/D92715 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/AST/Type.h clang/include/clang/AST/TypeProperties.td

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

evandro created this revision. evandro added reviewers: Hsiang-Kai, craig.topper, rogfer01, frasercrmck. Herald added subscribers: dexonsmith, NickHung, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck,

[PATCH] D88759: [RISCV] Add SiFive cores to the CPU option

This revision was automatically updated to reflect the committed changes. Closed by commit rG5d6d8a2769b3: [RISCV] Add SiFive cores to the CPU option (authored by evandro). Herald added subscribers: cfe-commits, jrtc27. Herald added a project: clang. Changed prior to commit:

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

evandro added a comment. Just a couple of nits, but otherwise it LGTM. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:776 } -return ""; +llvm_unreachable("Unknown SEW."); } I'd rather the first case be the `default` case and

[PATCH] D81213: [RISCV] Support experimental v extension v0.9.

evandro accepted this revision. evandro added a comment. This revision is now accepted and ready to land. It LGTM after D80802 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81213/new/

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

evandro added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; HsiangKai wrote: > evandro wrote: > > HsiangKai

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

evandro added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; HsiangKai wrote: > evandro wrote: > > Methinks

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

evandro added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; Methinks that these constraints `WidenV`,

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

evandro added a comment. Again, the `clang` part should be split in another patch and be made a child of D81188 . Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:297 +LMUL_F8 = 5, +LMUL_F4 = 6, +LMUL_F2 = 7

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

evandro added a comment. It looks pretty GTM. At this point, I'd be fine with accepting this patch as the major issues seem to have already been addressed. Should there be any other minor issue, it could be addressed later. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D78129: Add Marvell ThunderX3T110 support

evandro added a comment. In D78129#2023772 , @joelkevinjones wrote: > list UnsupportedFeatures = !listconcat(SVEUnsupported.F, > PAUnsupported.F); > Agree. Methinks that this is easier to read. Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D57497: [RISCV] Passing small data limitation value to RISCV backend

evandro added inline comments. Comment at: clang/docs/ClangCommandLineReference.rst:2958 + +Put global and static data smaller than the limitation into a special section (RISC-V only) + ``` s/arg/limit/ s/limitation/limit/ ``` Comment at:

[PATCH] D71124: [RISCV] support clang driver to select cpu

evandro added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:164 + +static constexpr llvm::StringLiteral ValidRV32CPUNames[] = {{"generic-rv32"}, +{"rocket-rv32"}}; Strange formatting...

[PATCH] D60287: [IR] Refactor attribute methods in Function class (NFC)

evandro added a comment. If anyone could give me a tip on how to avoid the review to be collapsed to just the part of whichever repo was hit first by a commit, I'd appreciate it. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60287/new/

[PATCH] D60287: [IR] Refactor attribute methods in Function class (NFC)

This revision was automatically updated to reflect the committed changes. Closed by commit rC357731: [IR] Refactor attribute methods in Function class (NFC) (authored by evandro, committed by ). Herald added a project: clang. Herald added a subscriber: cfe-commits. Changed prior to commit:

[PATCH] D59852: [IR] Create new method in the Function class (NFC)

This revision was automatically updated to reflect the committed changes. Closed by commit rC357638: [IR] Create new method in `Function` class (NFC) (authored by evandro, committed by ). Herald added a project: clang. Herald added a subscriber: cfe-commits. Changed prior to commit:

[PATCH] D44222: [AArch64] Add vmulxh_lane FP16 intrinsics

evandro accepted this revision. evandro added a comment. This revision is now accepted and ready to land. Looks pretty straightforward to me. https://reviews.llvm.org/D44222 ___ cfe-commits mailing list cfe-commits@lists.llvm.org