[PATCH] D157953: [CGCall][RISCV] Handle function calls with parameter of RVV tuple type

kito-cheng added a comment. Herald added a subscriber: sunshaoce. LGTM, but I would like to wait few more days to make sure no other comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157953/new/ https://reviews.llvm.org/D157953

[PATCH] D157663: [Driver] Default riscv*- triples to -fdebug-default-version=4

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, I am OK with that, actually our downstream toolchain has downgrade the dwarf version to 4 too, because binutils/gdb not well support before... Repository: rG LLVM Github

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, and the change seems like is fewer than my exception :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156221/new/

[PATCH] D156223: [RISCV] Resolve a few bugs in RISCVVIntrinsicUtils.cpp

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:136 case Invalid: + case Undefined: llvm_unreachable("Unhandled type."); 4vtomat

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/test/Driver/riscv-features.c:41 +// DEFAULT: "-target-feature" "-unaligned-scalar-mem" +// DEFAULT-NOT: "-target-feature"

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

kito-cheng added inline comments. Comment at: clang/lib/Headers/riscv_ntlh.h:28 + __builtin_riscv_ntl_load((PTR), __RISCV_NTLH_ALL) +#define SELECT_NTL_LOAD(_1, _2, NAME, ...) NAME + `__SELECT_NTL_LOAD` Comment at:

[PATCH] D156394: [Clang][RISCV] Bump rvv intrinsics version to v0.12

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156394/new/ https://reviews.llvm.org/D156394

[PATCH] D156223: [RISCV] Resolve a few bugs in RISCVVIntrinsicUtils.cpp

kito-cheng added a comment. Does it possible to add a precommit test case to show that we accept unexpected combination of the type? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156223/new/ https://reviews.llvm.org/D156223

[PATCH] D155674: [RISCV] Update zihintntl to 1p0

kito-cheng added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:149 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izihintntl0p2 -x c -E -dM %s \ +// RUN: -march=rv32izihintntl1p0 -x c -E

[PATCH] D154706: [RISCV] Add XLEN width integer type: riscv_int.h

kito-cheng marked an inline comment as done. kito-cheng added inline comments. Comment at: clang/lib/Headers/riscv_int.h:10 + +#ifndef __RISCV_INT_H + craig.topper wrote: > Don't you have to `#define __RISCV_INT_H` after this to make this a complete > include

[PATCH] D154706: [RISCV] Add XLEN width integer type: riscv_int.h

kito-cheng updated this revision to Diff 538497. kito-cheng added a comment. Changes: - Define __RISCV_INT_H Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154706/new/ https://reviews.llvm.org/D154706 Files: clang/lib/Headers/CMakeLists.txt

[PATCH] D154706: [RISCV] Add XLEN width integer type: riscv_int.h

kito-cheng updated this revision to Diff 538094. kito-cheng added a comment. Chagnes: - Update header comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154706/new/ https://reviews.llvm.org/D154706 Files: clang/lib/Headers/CMakeLists.txt

[PATCH] D154706: [RISCV] Add XLEN width integer type: riscv_int.h

kito-cheng created this revision. kito-cheng added a reviewer: asb. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng,

[PATCH] D154572: [RISCV] Use 'long' in aes64 Zknd/Zkne builtin tests. NFC

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154572/new/ https://reviews.llvm.org/D154572

[PATCH] D152996: [RISCV][POC] Model frm control for vfadd

kito-cheng accepted this revision. kito-cheng added a comment. LGTM, Give my blessing, thanks for moving this forward :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152996/new/ https://reviews.llvm.org/D152996

[PATCH] D154171: [RISCV] Mark zvkn* and zvks* extensions as enabled when all their subextensions are.

kito-cheng accepted this revision. kito-cheng added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154171/new/ https://reviews.llvm.org/D154171 ___ cfe-commits mailing list

[PATCH] D154050: [Clang][RISCV] Fix RISC-V vector / SiFive intrinsic inclusion in SemaLookup

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks for quick fix! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154050/new/ https://reviews.llvm.org/D154050

[PATCH] D152070: [2/11][Clang][RISCV] Expand all variants of RVV intrinsic tuple types

kito-cheng added inline comments. Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:819 - // LMUL x NF must be less than or equal to 8. - if ((Log2LMUL >= 1) && (1 << Log2LMUL) * NF > 8) -return std::nullopt; Keep as assert? Repository: rG LLVM

[PATCH] D151730: [RISCV] Support target attribute for function

kito-cheng added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv-func-attr-target.c:10 +// CHECK-ASM: .option pop +__attribute__((target("arch=rv64g,+c,+v"))) void test1 () {} + It's ext list or full arch, can't mixed together. ``` ARCH-ATTR :=

[PATCH] D151730: [RISCV] Support target attribute for function

kito-cheng added a comment. Testcase for backend? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151730/new/ https://reviews.llvm.org/D151730 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

kito-cheng added a comment. GCC ins't implement yet, but planed, so add it later I think? @4vtomat already drop -march=help, @MaskRay did you mind take a look again? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146054/new/

[PATCH] D149642: [RISCV] Support vreinterpret intrinsics between vector boolean type and m1 vector integer type

kito-cheng added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c:1 -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// NOTE: Assertions have been autogenerated by

[PATCH] D146987: [Assignment Tracking] Enable by default

kito-cheng added a comment. Got crash for RISC-V on top of trunk: [kitoc@hsinchu02 build]$ cat x.c typedef __rvv_uint32m4_t a; void b() { a c; } [kitoc@hsinchu02 build]$ bin/clang -target riscv64-elf x.c -O -g clang-14:

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

kito-cheng accepted this revision. kito-cheng added a comment. LGTM, consider about the GNU compatibility, I would that has -march=help form for that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146054/new/ https://reviews.llvm.org/D146054

[PATCH] D148680: [RISCV] Split out part of riscv_vector.td to riscv_vector_common.td

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148680/new/ https://reviews.llvm.org/D148680

[PATCH] D148308: [RISCV] Split out SiFive VCIX C intrinsics from riscv_vector.td

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148308/new/ https://reviews.llvm.org/D148308

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

kito-cheng accepted this revision. kito-cheng added a comment. LGTM, but IMO the title should still contain [RISCV][clang] Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148223/new/ https://reviews.llvm.org/D148223

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

kito-cheng added inline comments. Comment at: clang/tools/driver/cc1_main.cpp:187-188 +/// Print supported extensions of the given target. +static int PrintSupportedExtensions(std::string TargetStr) { + llvm::riscvMarchHelp(); + Plz make sure only RISC-V print

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

kito-cheng accepted this revision. kito-cheng added a comment. I am really happy to see this happen, binutils has relaxed for a while in more relaxed way[1] - only require must start with `rv[32|64][e|i|g]`, personally I would like to relax the order at all like binutils did for GCC, but I

[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

This revision was automatically updated to reflect the committed changes. Closed by commit rGda4fcb0c0b28: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple. (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, let it go Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149314/new/ https://reviews.llvm.org/D149314

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D133863/new/ https://reviews.llvm.org/D133863

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

kito-cheng added a comment. > My concern would be that as we don't gate CSR names on enabling the relevant > extension, people could start using CSR names and encodings that could > change, without opting in via -menable-experimental-extensions, perhaps not > realising that they're using the

[PATCH] D148962: [RISCV] Make Zicntr and Zihpm imply Zicsr.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148962/new/ https://reviews.llvm.org/D148962

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

kito-cheng added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2408 + +OperandMatchResultTy RISCVAsmParser::parseZcSpimm(OperandVector ) { + if (getLexer().is(AsmToken::Minus)) `parseZcSpimm` -> `parseZcmpSpimm`

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

kito-cheng added inline comments. Comment at: llvm/test/CodeGen/RISCV/O0-pipeline.ll:66-67 ; CHECK-NEXT: Stack Frame Layout Analysis +; CHECK-NEXT: RISC-V Zce move merging pass +; CHECK-NEXT: RISC-V Zce Push/Pop optimization pass ; CHECK-NEXT: RISC-V

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:903 +return createStringError(errc::invalid_argument, + "zcmt is not allowed when c is specified"); + craig.topper wrote: > Extension names should be

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

kito-cheng added inline comments. Comment at: lld/ELF/InputSection.h:404 -static_assert(sizeof(InputSection) <= 152, "InputSection is too big"); +static_assert(sizeof(InputSection) <= 160, "InputSection is too big"); Why we need this change? Repository:

[PATCH] D148308: [RISCV] Split out SiFive VCIX C intrinsics from riscv_vector.td

kito-cheng added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:15 -//===--===// -// Instruction definitions

[PATCH] D98012: [RFC][doc] Document that RISC-V's __fp16 has different behavior

kito-cheng abandoned this revision. kito-cheng added a comment. Herald added subscribers: pcwang-thead, VincentWu, arichardson. Herald added a project: All. RISC-V using `_Float16` as official half-precision type. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

kito-cheng created this revision. kito-cheng added reviewers: asb, craig.topper, luismarques. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01,

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

kito-cheng added a comment. You need to update `llvm/docs/RISCVUsage.rst` too. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148066/new/ https://reviews.llvm.org/D148066 ___ cfe-commits mailing list

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

kito-cheng added a comment. I would support have `-march=help`, but I know it's really not make scene to alias `-march=help` to `--print-supported-extensions` for other targets, what about redirect that in `Driver.cpp` for RISC-V only? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to S11

kito-cheng added a comment. Sorry for cross post, but I guess some people might not follow closely in discourse (like me :P): Another proposal from me is using gp as platform register: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/371 Some advantage on taking gp as platform

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

kito-cheng added inline comments. Comment at: clang/lib/Driver/Driver.cpp:4231-4235 + // marchs and quits. + if (Args.getLastArg(options::OPT_print_supported_marchs)) { +RISCVMarchHelp(); +exit(0); + } Plz did the similar action like what

[PATCH] D145074: [clang][RISCV] Fix ABI lowering for _Float16 for FP ABIs

kito-cheng added a comment. LGTM, just a nit :) Comment at: clang/test/CodeGen/RISCV/riscv64-abi.c:1909 - NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -// LP64F: {{.*}} This seems removed accidentally, I

[PATCH] D145164: [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux

This revision was automatically updated to reflect the committed changes. Closed by commit rGbe437f3bb8b6: [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D145164: [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux

kito-cheng created this revision. kito-cheng added reviewers: asb, luismarques, jrtc27, MaskRay, craig.topper, reames. Herald added subscribers: luke, VincentWu, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, pengfei, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult,

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

kito-cheng accepted this revision. kito-cheng added a comment. LGTM, Verified with GCC and two clang w/ and w/o this patch, clang with this patch is matching GCC's behavior. Also created an PR on psABI to clarify that: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/365 CHANGES

[PATCH] D143051: [Clang][RISCV] Bump rvv intrinsics version to v0.11

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, it's great to having a version number to distinguish different interface version Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D142697: [3/3][Clang][RISCV] Add `__riscv_` for overloaded intrinsics

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142697/new/ https://reviews.llvm.org/D142697

[PATCH] D142644: [2/3][Clang][RISCV] Add `__riscv_` for non-overloaded intrinsics

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142644/new/ https://reviews.llvm.org/D142644

[PATCH] D142085: [1/3][Clang][RISCV] Add `__riscv_` prefix for vread, vwrite, vlenb, vsetvl, and vsetvlmax

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142085/new/ https://reviews.llvm.org/D142085

[PATCH] D142094: [Clang][Doc] Add release note for changes for the RVV intrinsics

kito-cheng added a comment. As a RISC-V GCC maintainer: GCC 14 is targeting on RVV intrinsic 1.0, but segment load store and rounding mode stuff might not meet the release, so the status will be pretty close to clang/LLVM (with @eopXD's changes, `__riscv_` prefix and those simplification

[PATCH] D142085: [Clang][RISCV] Add `__riscv_` prefix for all RVV intrinsics

kito-cheng added a comment. Agree with @jrtc27 about the test function name, we could keep the function name in the test file, that's also reduce lots of diff which is not really necessary. e.g. `vint8mf8_t test_vaadd_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl)` keep same name rather

[PATCH] D142085: [Clang][RISCV] Add `__riscv_` prefix for all RVV intrinsics

kito-cheng added a comment. > I don't have a preference here, is any of __riscv_RVV_CSR/ > __riscv_rvv_csr_type / __riscv_rvv_csr_t suitable? Either is fine to me at this stage, I expect they will be drop soon. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D142016: [Clang][RISCV] Simplify RVV intrinsic policy suffix

kito-cheng accepted this revision. kito-cheng added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142016/new/ https://reviews.llvm.org/D142016 ___ cfe-commits mailing list

[PATCH] D141754: [5/15][Clang][RISCV][NFC] Remove extra attribute Policy::IntrinsicWithoutMU by reusing HasTailPolicy and HasMaskPolicy

kito-cheng accepted this revision. kito-cheng added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141754/new/ https://reviews.llvm.org/D141754 ___ cfe-commits mailing list

[PATCH] D141666: [RISCV] Proper support of extensions Zicsr and Zifencei

kito-cheng added a comment. Maybe multi-lib handling should split into another patch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141666/new/ https://reviews.llvm.org/D141666 ___ cfe-commits mailing

[PATCH] D142085: [Clang][RISCV] Add `__riscv_` prefix for all RVV intrinsics

kito-cheng added a comment. Could you split testcase update to a separated patch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142085/new/ https://reviews.llvm.org/D142085 ___ cfe-commits mailing list

[PATCH] D141754: [5/15][Clang][RISCV][NFC] Remove extra attribute Policy::IntrinsicWithoutMU by reusing HasTailPolicy and HasMaskPolicy

kito-cheng added a comment. Wait, I fell HasTailPolicy and HasMaskPolicy should be part of Policy object, and then it's the Omit to present it's no policy. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141754/new/ https://reviews.llvm.org/D141754

[PATCH] D141768: [11/15][Clang][RISCV][NFC] Remove Policy::PolicyType::Omit

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141768/new/ https://reviews.llvm.org/D141768

[PATCH] D141767: [10/15][Clang][RISCV][NFC] Don't need to check for `MaskPolicy` in `isTAPolicy` and `isTUPolicy`

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141767/new/ https://reviews.llvm.org/D141767

[PATCH] D141764: [9/15][Clang][RISCV][NFC] Use correct type for `RVVTypeCache::computeTypes` under RISCVVEmitter.cpp

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141764/new/ https://reviews.llvm.org/D141764

[PATCH] D141762: [8/15][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141762/new/ https://reviews.llvm.org/D141762

[PATCH] D141759: [7/15][Clang][RISCV][NFC] Correct the default value for Policy to TAMU

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141759/new/ https://reviews.llvm.org/D141759

[PATCH] D141754: [5/15][Clang][RISCV][NFC] Remove extra attribute Policy::IntrinsicWithoutMU by reusing HasTailPolicy and HasMaskPolicy

kito-cheng added inline comments. Herald added a subscriber: luke. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:388 + bool HasVL, PolicyScheme Scheme, const bool HasTailPolicy, + const bool HasMaskPolicy, bool SupportOverloading,

[PATCH] D141756: [6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke. LGTM, the condition of those predictor function more reasonable now Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D141575: [3/15][Clang][RISCV][NFC] Clarify edge cases of RVVIntrinsic::getSupportedMaskedPolicies for clarity

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141575/new/ https://reviews.llvm.org/D141575

[PATCH] D141574: [2/15][Clang][RISCV][NFC] Rename Policy::IsPolicyNone to IsUnspecifed

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke. LGTM, this made the code more expressive. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141574/new/

[PATCH] D141573: [1/15][Clang][RISCV][NFC] Extract common utility to RISCVVIntrinsicUtils

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141573/new/ https://reviews.llvm.org/D141573

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. kito-cheng marked 2 inline comments as done. Closed by commit rGf601039e8165: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march (authored by

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng marked 6 inline comments as done. kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:86 +// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" +// MCPU-ABI-SIFIVE-S21: "-target-feature" "+64bit" // MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64"

[PATCH] D141459: [RISCV] Use Zvl*b as a lower bound for VScaleRange.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141459/new/ https://reviews.llvm.org/D141459

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng marked 3 inline comments as done. kito-cheng added a comment. > (I probably need to update my > https://maskray.me/blog/2022-08-28-march-mcpu-mtune) At least the behavior of RISC-V GCC need to update: Architecture extension: - Take from -march if present. - Take from -mcpu if

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 488656. kito-cheng added a comment. Changes: - Address Craig's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140693/new/ https://reviews.llvm.org/D140693 Files: clang/docs/ReleaseNotes.rst

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:13 +// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" +// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "-64bit" // MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32" Need to break this

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 488175. kito-cheng added a comment. Changes: - Trim unexpected change by clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140693/new/ https://reviews.llvm.org/D140693 Files:

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 488173. kito-cheng added a comment. Herald added subscribers: llvm-commits, hiraditya. Herald added a project: LLVM. Changes: - Add release note to mention the behavior change for `-march` and `-mcpu`. - New way to implement this behavior, passing all

[PATCH] D136817: [RISCV] Add H extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf4c887c3a840: [RISCV] Add H extension (authored by kito-cheng). Changed prior to commit: https://reviews.llvm.org/D136817?vs=485360=487624#toc

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng planned changes to this revision. kito-cheng added a comment. - @craig.topper has suggested we could pass all extension with `-` or `+` to neutralize the effect of the `-target-cpu`, that's less intrusive way. - Add release note to mention the behavior change. Repository: rG LLVM

[PATCH] D136817: [RISCV] Add H extension

kito-cheng added a comment. ping :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:5457 + // RISC-V will handle -mcpu option in Clang::AddRISCVTargetArgs. + if (!Triple.isRISCV()) { +// Add the target cpu craig.topper wrote: > kito-cheng wrote: > >

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 485674. kito-cheng added a comment. Changes: - Stop calling getRISCVTargetCPU in getCPUName. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140693/new/ https://reviews.llvm.org/D140693 Files:

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:5457 + // RISC-V will handle -mcpu option in Clang::AddRISCVTargetArgs. + if (!Triple.isRISCV()) { +// Add the target cpu craig.topper wrote: > I wonder if we should stop

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added a comment. > So if I read this correctly, the effect of this is that we never pass > -target-cpu to the backend after this patch and will only pass > -target-feature and -tune-cpu? Yes, that's prevent us taking any extensions from `-target-cpu`, so always pass

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Go ahead, thanks for clean up! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140662/new/ https://reviews.llvm.org/D140662

[PATCH] D140692: [RISCV] Add Svpbmt extension support.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140692/new/ https://reviews.llvm.org/D140692

[PATCH] D140692: [RISCV] Add Svbmpt extension support.

kito-cheng added a comment. You are typo on title and commit log, it should be `Svpbmt` not `Svbmpt`, but the code changes are right, and you need to update `llvm/docs/RISCVUsage.rst` too. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140692/new/

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng created this revision. kito-cheng added reviewers: craig.topper, asb, reames. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D136817: [RISCV] Add H extension

kito-cheng updated this revision to Diff 485360. kito-cheng added a comment. Changes: - Rebase to main - Add negative test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files:

[PATCH] D140389: [NFC][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

kito-cheng added a comment. Could you rebase with D140361 ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140389/new/ https://reviews.llvm.org/D140389 ___ cfe-commits

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks for clean up this! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140361/new/ https://reviews.llvm.org/D140361

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

kito-cheng added a comment. Ken has updated spec to clarify requirements of those vector crypto extensions: https://github.com/riscv/riscv-crypto/commit/40695306f628e6dc764d1d0f35392eac792d2c3b These Vector Crypto Extensions can be built on any RISC-V base. However, XLEN=32 implementations

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139995/new/ https://reviews.llvm.org/D139995

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

kito-cheng added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:100 + bool MU = false; + bool MA = false; + bool IntrinsicWithoutMU = false; Maybe use enum value for tail/mask policy? *U and *A are mutually exclusive, so I

[PATCH] D138930: [RISCV] Add macro to imply compiler availability on RISC-V Vector intrinsics version

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM. I am thinking that we should use same way to define both `__riscv_v_intrinsic_overloading`[1] and `__riscv_v_intrinsic`, `__riscv_v_intrinsic_overloading` is defined in

[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. kito-cheng marked 2 inline comments as done. Closed by commit rG3fe89be80159: [clang][RISCV][NFC] Prevent data race in RVVType::computeType (authored by kito-cheng).

[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

kito-cheng marked 3 inline comments as done. kito-cheng added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:284 + +class RVVTypeCache { +private: khchen wrote: > nit: maybe we could add some comments to said the motivation for

[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

kito-cheng updated this revision to Diff 477406. kito-cheng added a comment. Changes: - Add comment for RVVTypeCache - computeRVVTypeHashValue become a local function rather than static function of RVVTypeCache. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

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