[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

luismarques added inline comments. Comment at: clang/test/CodeGen/RISCV/abi-empty-structs.c:21-22 // Fields containing empty structs or unions are ignored when flattening // structs for the hard FP ABIs, even in C++. -// FIXME: This isn't currently respected.

[PATCH] D145164: [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux

luismarques added a comment. From Kito's comment in D144174 : https://github.com/gcc-mirror/gcc/commit/3cd08f7168c196d7a481b9ed9f4289fd1f14eea8 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145164/new/

[PATCH] D131141: [RISCV] Add MC support of RISCV Zcb Extension

luismarques accepted this revision. luismarques added a comment. LGTM, with some in-line caveats. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td:1 +//===-- RISCVInstrInfoZc.td - RISC-V 'Zc' instructions -*- tablegen -*-===// +// `Zc` -> `Zc*`

[PATCH] D131141: [RISCV] Add MC support of RISCV Zcb Extension

luismarques added a comment. Possibly we want to add this change to the release notes? Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:304-308 + "'Zcb' (Shortened format for basic bit manipulation instructions)", +

[PATCH] D142326: [clang][RISCV][test] Add test cases for empty structs and the FP calling conventions

luismarques added inline comments. Comment at: clang/test/CodeGen/RISCV/abi-empty-structs.c:1 +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --full-function-signature --filter "^define |^entry:" +// RUN: %clang_cc1

[PATCH] D142373: [Utils] Add --full-function-signature to update_cc_test_checks.py to match return type as well as args

luismarques added a comment. I'm probably not the best person to review this but, for what it's worth, it LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142373/new/ https://reviews.llvm.org/D142373

[PATCH] D142373: [Utils] Add --full-function-signature to update_cc_test_checks.py to match return type as well as args

luismarques added a comment. Do we actually want to include the `dso_local` in the full signature? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142373/new/ https://reviews.llvm.org/D142373 ___

[PATCH] D142326: [clang][RISCV][test] Add test cases for empty structs and the FP calling conventions

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM but others should also chime in. Comment at: clang/test/CodeGen/RISCV/abi-empty-structs.c:101 + +struct s5 { struct empty e[1]; float f; }; +

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGMT. Comment at: clang/lib/CodeGen/TargetInfo.cpp:591 if (isa(RT->getDecl()) && - (WasArray || !FD->hasAttr())) + (WasArray || (!FD->hasAttr() &&

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

luismarques added a comment. Regarding the overkill of "RISCVInstrInfoZawrs.td", how about having a "RISCVInstrInfoExtra.td" (or "RISCVInstrInfoExt.td") as a grab bag for everything that doesn't merit its own .td file? I think this is fine regarding the versioning issue. Seems to only be

[PATCH] D132192: [RISCV] Add '32bit' feature to rv32 only builtins.

luismarques added a comment. Overall LGTM. I have one concern, though. The old error message was more user friendly. Referring to RV32 as an extension is... weird. You're already massaging the error with the `OF = "RV64"` / `OF = "RV32"`. Can't you special case this feature check error

[PATCH] D122370: Split up large test files under clang/test/CodeGen/RISCV

luismarques added a comment. What's the timeout value that is being exceeded? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D122370/new/ https://reviews.llvm.org/D122370 ___ cfe-commits mailing list

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

luismarques added a comment. Assuming this will be merged soon, do you want to submit a backport request for the 14.0 branch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

luismarques added a comment. I think this would benefit from increased test coverage, namely to show that the mattr command-line options are properly handled. Some possible ideas: - Tests with the correct extension versions (maybe add a test file that exercises the version for all extensions).

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

luismarques added a comment. > enable 'm' extension with passing mattr=+m After this patch, it would be > -mattr=+m2p0. It's not obvious to me that support for extension versions should mean or has to mean that we always explicitly specify the version. Why can't we keep supporting the option

[PATCH] D110669: [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110669/new/ https://reviews.llvm.org/D110669

[PATCH] D109727: [Driver] Remove unneeded *-suse-* triples

luismarques added a comment. In D109727#3004125 , @MaskRay wrote: > The code change of D74399 should be > reverted. The test can stay, but I won't think we need too many > riscv64-$distro-linux-gnu tests. Makes sense.

[PATCH] D109727: [Driver] Remove unneeded *-suse-* triples

luismarques added a comment. Regarding D74399 , cmake on a fedora RISC-V host still detects a generic triple: -- LLVM host triple: riscv64-unknown-linux-gnu -- LLVM default target triple: riscv64-unknown-linux-gnu as opposed to the `gcc -dumpmachine` triple

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

luismarques added a comment. I was trying to put this patch through its paces but it no longer applies. Can you please rebase it? It seems this is nearly there. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

This revision was automatically updated to reflect the committed changes. Closed by commit rG34e055d33e37: [Clang][RISCV] Implement getConstraintRegister for RISC-V (authored by luismarques). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108624/new/

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

luismarques added inline comments. Comment at: clang/test/Sema/inline-asm-validate-riscv.c:27-28 + register long x10 asm("x10"); + asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm clobber list}} + asm volatile("" :: "r"(x10) : "a0"); //

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

luismarques updated this revision to Diff 368323. luismarques added a comment. Nit: remove nop. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108624/new/ https://reviews.llvm.org/D108624 Files: clang/lib/Basic/Targets/RISCV.h

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

luismarques created this revision. luismarques added reviewers: asb, thopre. Herald added subscribers: vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217,

[PATCH] D106888: [RISC-V] Implement jump tables for CFI-icall

luismarques added a comment. In D106888#2954788 , @twd2 wrote: > Hi, you can check here: > https://buildkite.com/llvm-project/premerge-checks/builds/49755#814fd222-2e5a-4400-824d-d1a1f1293c01 > The clang-tidy failed due to the invalid case style for

[PATCH] D106888: [RISC-V] Implement jump tables for CFI-icall

luismarques added a comment. In D106888#2954425 , @asb wrote: > Is it possible to write a test case for this? Good question. I had checked that the AArch64 implementation had included a test, but I think that was only for new target-specific stuff,

[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. Still LGTM. BTW, I liked that in the old version the help string included "In GCC =0 is the same as =1". Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

luismarques added inline comments. Comment at: llvm/test/CodeGen/RISCV/loop-alignment.ll:3-4 +; RUN: llc < %s -mtriple=riscv64 | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s -check-prefix=ALIGN_16 +; RUN: llc < %s -mtriple=riscv64

[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

luismarques added a comment. LGTM. I'll let someone familiar with the old option explicitly approve it. Comment at: clang/test/Driver/falign-loops.c:6-7 +// RUN: %clang -### -falign-loops=5 %s 2>&1 | FileCheck %s --check-prefix=CHECK-5 +// RUN: %clang -### -falign-loops=8 %s

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

luismarques added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vfredusum-rv32.ll:1 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \

[PATCH] D105254: [RISCV] Support machine constraint "S"

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. In D105254#2852489 , @luismarques wrote: > Makes sense. Let's wait for the GCC Bugzilla feedback. With 'S' now documented on the GNU side,

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

luismarques added a comment. This patch is nearly there! Just address the remaining review comments and it LGTM. BTW, please mark all addressed inline comments as done. I think a few were missed, and it's helpful for a large patch like this. Comment at:

[PATCH] D98113: [Driver] Also search FilePaths for compiler-rt before falling back

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98113/new/ https://reviews.llvm.org/D98113

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

luismarques added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:1 +//===-- RISCVArchStringParser.h - RISCV Arch String Parser --*- C++ -*-===// +// Incorrect header name. Comment at:

[PATCH] D105254: [RISCV] Support machine constraint "S"

luismarques added a comment. Makes sense. Let's wait for the GCC Bugzilla feedback. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105254/new/ https://reviews.llvm.org/D105254 ___ cfe-commits mailing

[PATCH] D103878: [clang][RISCV][test] Add more tests of the -mabi and -march options

luismarques added a comment. In D103878#2807118 , @benshi001 wrote: > 1. there is no tests for mabi=ilp32e, and my patch covers that. > 2. the tests in riscv-abi.c will show default abi changes for special archs, > especially for the arch with F but

[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

luismarques added a comment. In D102839#2784275 , @ksyx wrote: > Thanks for mentioning that! Now, I changed the effect of `no-div` option into > choosing a proper extension and implemented the `Zmmul` subextension. Is this > solution acceptable or are

[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

luismarques added a comment. In D102839#2783636 , @ksyx wrote: > So it seems the better way to do this would definitely by adding a > subextension as the spec had changed. But I'd like also to ask how will GCC > deal with this option, and should we

[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

luismarques added a comment. In D102839#2782557 , @kito-cheng wrote: > We have Zmmul extension in the ISA spec now, that's equivalent to `-mno-div` > , so I suggest we should go forward to implement that extension rather than > `-mno-div`. >

[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

luismarques added inline comments. Comment at: clang/include/clang/Driver/Options.td:3149-3152 +def mno_div : Flag<["-"], "mno-div">, Group, + HelpText<"Disable hardware integral division instructions in M extension">; +def mdiv : Flag<["-"], "mdiv">, Group, + HelpText<"Enable

[PATCH] D101876: [clang] Support -fpic -fno-semantic-interposition for RISCV

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D101876/new/ https://reviews.llvm.org/D101876

[PATCH] D99108: [RISCV] Add XFAIL riscv32 for known issue with the old pass manager

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGa8cf32baf57d: [RISCV] Add XFAIL riscv32 for known issue with the old pass manager (authored by luismarques). Repository: rG LLVM Github Monorepo

[PATCH] D99108: [RISCV] Add XFAIL riscv32 for known issue with the old pass manager

luismarques created this revision. luismarques added a reviewer: asb. Herald added subscribers: vkmr, evandro, sameer.abuasal, s.egerton, Jim, benna, psnobl, rogfer01, shiva0217, kito-cheng, simoncook. luismarques requested review of this revision. Herald added a project: clang. Herald added a

[PATCH] D98113: [Driver] Also search FilePaths for compiler-rt before falling back

luismarques added a comment. I just looked at this again and I don't have the full context in my mind right now but won't the test just exercise the BareMetal toolchain and not your changes? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

luismarques added a comment. This still doesn't report that the multilib configuration came from GCC when it succeeds, does it? I suppose that's not a deal-breaker, but it would be nice to have. Would it be difficult to implement? Regarding the Windows test issue, aren't there other test cases

[PATCH] D98113: [Driver] Also search FilePaths for compiler-rt before falling back

luismarques added a comment. This makes sense to me but I'm not quite sure about the implications, especially when we consider compatibility. I think we need more eyes on this patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98113/new/

[PATCH] D98610: [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'

luismarques added inline comments. Comment at: llvm/test/CodeGen/RISCV/patchable-function-entry.ll:1-3 +;; Test the function attribute "patchable-function-entry". +; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=CHECK,32 +; RUN: llc -mtriple=riscv64 < %s |

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

luismarques added a comment. This patch seems to be in pretty good shape now. One thing that might be useful (important?) to add is additional diagnostics when run in verbose mode. Currently `clang -v` will indicate that it found the GCC installation and will list the multilibs but there will

[PATCH] D98610: [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. Overall LGTM. I just don't understand what you mean with "1-byte NOPs" in the patchable prefix case. Regular NOPs are emitted. Please clarify the comment/patch as needed.

[PATCH] D97896: [Clang][RISCV][RFC] Add byval parameter attribute?

luismarques created this revision. luismarques added reviewers: asb, mundaym. Herald added subscribers: vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217,

[PATCH] D92403: [LSan][RISCV] Enable LSan for RISCV64

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2de4f19ecdb2: [LSan][RISCV] Enable LSan for RISCV64 (authored by luismarques). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D92403: [LSan][RISCV] Enable LSan for RISCV64

luismarques updated this revision to Diff 320375. luismarques added a comment. Herald added a subscriber: vkmr. Rebase and address formatting issues. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92403/new/ https://reviews.llvm.org/D92403 Files:

[PATCH] D91278: [Clang][CodeGen][RISCV] Fix hard float ABI for struct with empty struct and complex

luismarques updated this revision to Diff 309991. luismarques added a comment. Add float Complex case, for regression test completeness. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91278/new/ https://reviews.llvm.org/D91278 Files:

[PATCH] D91270: [Clang][CodeGen][RISCV] Fix hard float ABI test cases with empty struct

luismarques updated this revision to Diff 309981. luismarques added a comment. Address review feedback. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91270/new/ https://reviews.llvm.org/D91270 Files: clang/lib/CodeGen/TargetInfo.cpp

[PATCH] D92403: [LSan][RISCV] Enable LSan for RISCV64

luismarques updated this revision to Diff 308737. luismarques added a comment. Fix formatting. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92403/new/ https://reviews.llvm.org/D92403 Files: clang/lib/Driver/ToolChains/Linux.cpp

[PATCH] D92403: [LSan][RISCV] Enable LSan for RISCV64

luismarques created this revision. luismarques added reviewers: asb, lenary, vitalybuka, eugenis, EccoTheDolphin. Herald added subscribers: Sanitizers, cfe-commits, NickHung, evandro, sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, rogfer01, shiva0217, kito-cheng, simoncook, fedor.sergeev,

[PATCH] D91784: [RISCV] Set __GCC_HAVE_SYNC_COMPARE_AND_SWAP_x defines

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG28de0fb4863a: [RISCV] Set __GCC_HAVE_SYNC_COMPARE_AND_SWAP_x defines (authored by luismarques). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D91315: [RISCV] Handle zfh in the arch string.

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91315/new/ https://reviews.llvm.org/D91315

[PATCH] D91278: [Clang][CodeGen][RISCV] Fix hard float ABI for struct with empty struct and complex

luismarques updated this revision to Diff 304554. luismarques added a comment. Fix bad test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91278/new/ https://reviews.llvm.org/D91278 Files: clang/lib/CodeGen/TargetInfo.cpp

[PATCH] D91278: [Clang][CodeGen][RISCV] Fix hard float ABI for struct with empty struct and complex

luismarques created this revision. luismarques added reviewers: asb, lenary, rjmccall, efriedma. Herald added subscribers: cfe-commits, frasercrmck, NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01,

[PATCH] D91270: [Clang][CodeGen][RISCV] Fix hard float ABI test cases with empty struct

luismarques created this revision. luismarques added reviewers: asb, lenary, rjmccall, efriedma. Herald added subscribers: cfe-commits, frasercrmck, NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01,

[PATCH] D91269: [Clang][CodeGen][RISCV] Add hard float ABI tests with empty struct

luismarques created this revision. luismarques added reviewers: asb, lenary, rjmccall, efriedma. Herald added subscribers: cfe-commits, frasercrmck, NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01,

[PATCH] D89025: [RISCV] Add -mtune support

luismarques added a comment. In D89025#2324334 , @khchen wrote: > RISCV supports `-mcpu` with default empty arch to align gcc's `-mtune` > behavior since clang didn't support `-mtune` before. But now clang has > `-mtune`, is it a good idea to remove

[PATCH] D89025: [RISCV] Add -mtune support

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM, but I would like other people to also review this, if possible. (Just be sure to check/fix the clang-format warnings and the inline comments). Comment at:

[PATCH] D79770: [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64

luismarques added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:10241-10242 // Pass floating point values via FPRs if possible. - if (IsFixed && Ty->isFloatingType() && FLen >= Size && ArgFPRsLeft) { + if (IsFixed && Ty->isFloatingType() &&

[PATCH] D75061: [RISCV] Fix sysroot tests without GCC on RISC-V hosts with GCC

This revision was automatically updated to reflect the committed changes. Closed by commit rG91f7f0d8e3ef: [RISCV] Fix sysroot tests without GCC on RISC-V hosts with GCC (authored by luismarques). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D75061: [RISCV] Fix sysroot tests without GCC on RISC-V hosts with GCC

luismarques created this revision. luismarques added reviewers: edward-jones, lenary. Herald added subscribers: cfe-commits, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, zzheng, jrtc27, shiva0217,

[PATCH] D74847: [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

This revision was automatically updated to reflect the committed changes. Closed by commit rG0781e93a6eaa: [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V (authored by luismarques). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D74847: [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

luismarques updated this revision to Diff 245881. luismarques edited the summary of this revision. luismarques added a comment. Herald added a subscriber: fedor.sergeev. As suggested by @efriedma, the patch was reworked to have one target with native atomics, and one without. No RUN run with a

[PATCH] D74847: [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

luismarques added a comment. In D74847#1883028 , @efriedma wrote: > I'm not really a big fan of running tests with the host target triple, > anyway; it seems to create work with almost no benefit. I'd be happy to just > run the test with one target

[PATCH] D74847: [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

luismarques created this revision. luismarques added reviewers: jyknight, eli.friedman, lenary. Herald added subscribers: cfe-commits, evandro, sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, jfb, rkruppe, rogfer01, shiva0217, kito-cheng, simoncook. Herald added a project: clang. By default

[PATCH] D69869: [clang-tools-extra] fix the check for if '-latomic' is necessary

This revision was automatically updated to reflect the committed changes. Closed by commit rG1d40c4150630: [clang-tools-extra] fix the check for if -latomic is necessary (authored by gokturk, committed by luismarques). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D69869: [clang-tools-extra] fix the check for if '-latomic' is necessary

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. Whether or not GCC behaves the way it should behave regarding atomics, this seems like a sensible patch to make things work given the current situation. LGTM. Repository: rG LLVM

[PATCH] D74399: [Driver][RISCV] Add RedHat Linux RISC-V triple

This revision was automatically updated to reflect the committed changes. Closed by commit rG9816e726e747: [Driver][RISCV] Add RedHat Linux RISC-V triple (authored by luismarques). Herald added a subscriber: jrtc27. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D74399: [Driver][RISCV] Add RedHat Linux RISC-V triple

luismarques updated this revision to Diff 244211. luismarques added a comment. Correct paths. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D74399/new/ https://reviews.llvm.org/D74399 Files: clang/lib/Driver/ToolChains/Gnu.cpp

[PATCH] D74399: [Driver][RISCV] Add RedHat Linux RISC-V triple

luismarques updated this revision to Diff 244187. luismarques added a comment. Herald added subscribers: apazos, pzheng, jocewei, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, niosHD, sabuasal, johnrusso, rbar. Adds a test (using the RISC-V Fedora 31 paths). CHANGES SINCE LAST ACTION

[PATCH] D74399: [Driver][RISCV] Add RedHat Linux RISC-V triple

luismarques created this revision. luismarques added reviewers: lenary, asb, dlj. Herald added subscribers: cfe-commits, evandro, sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, rkruppe, rogfer01, shiva0217, kito-cheng, simoncook. Herald added a project: clang. Adds the RedHat Linux triple

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68362/new/ https://reviews.llvm.org/D68362 ___ cfe-commits mailing list

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

luismarques added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:36 +// The only physical register that isn't saved is x2 (SP), which is used by the +// processor when the interrupt happens. + Nitpick: "the interrupt happens" -> "an

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69383/new/ https://reviews.llvm.org/D69383

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

luismarques added a comment. @simoncook: your commit doesn't include handling the case of TLS lowering when `-ffixed-x4` is used. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67185/new/ https://reviews.llvm.org/D67185

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

luismarques requested changes to this revision. luismarques added inline comments. This revision now requires changes to proceed. Comment at: libunwind/include/__libunwind_config.h:26 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31 +#define

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

luismarques added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:97 RISCVABI::ABI getTargetABI() const { return TargetABI; } + bool isRegisterReservedByUser(size_t i) const { +return UserReservedRegister[i]; This should take a

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

luismarques added inline comments. Comment at: libunwind/src/Registers.hpp:3545 + void setSP(uint64_t value) { _registers[2] = value; } + uint64_t getIP() const { return _registers[1]; } + void setIP(uint64_t value) { _registers[1] = value; }

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

luismarques added inline comments. Comment at: libunwind/src/Registers.hpp:3756 +inline double Registers_riscv::getFloatRegister(int regNum) const { +#ifdef __riscv_float_abi_double + assert(validFloatRegister(regNum)); lenary wrote: > mhorne wrote: > > lenary

[PATCH] D68391: [RISCV] Improve sysroot computation if no GCC install detected

luismarques added a comment. This is indeed an issue that would be nice to fix, I've often been annoyed by clang just defaulting to the root when some misconfiguration occurs. I have to wonder though, this patch only changes the clang RISC-V toolchain driver, but the problem isn't specific to

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

luismarques added a comment. The priority for this patch is to address the issues reported by @apazos but after that please check the clang-format output. There are some cases in this patch where it might make sense to use a different formatting than clang-format indicates, but the remaining

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. Overall LGTM. Caveats: - Address the issues in the inline comments; - Shouldn't the TLS lowering also complain when `-ffixed-x4` is used? - Is there a way to ensure we don't forget

[PATCH] D66591: [RISCV] Correct Logic around ilp32e macros

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66591/new/ https://reviews.llvm.org/D66591

[PATCH] D66003: [RISCV] Make -march=rv{32, 64}gc the default in RISC-V Linux

luismarques accepted this revision. luismarques added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66003/new/ https://reviews.llvm.org/D66003

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

luismarques added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:386 + else +return Triple.getArch() == llvm::Triple::riscv32 ? "ilp32" : "lp64"; } luismarques wrote: > When I compile a bare metal GNU toolchain (using >

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

luismarques added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:386 + else +return Triple.getArch() == llvm::Triple::riscv32 ? "ilp32" : "lp64"; } When I compile a bare metal GNU toolchain (using

[PATCH] D66002: [RISCV] Move architecture parsing code into its own function

luismarques added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66002/new/ https://reviews.llvm.org/D66002 ___ cfe-commits mailing list cfe-commits@lists.llvm.org