[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

HsiangKai added a comment. Thanks for your review, @fpallares. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80802/new/ https://reviews.llvm.org/D80802 ___ cfe-commits mailing list

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

fpallares added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:542 defm VMSGT_V : VALU_IV_X_I<"vmsgt", 0b01>; +} Minor nit: Add comment here (for the other `let RVVConstraint = NoConstraint` blocks below as well). Repository:

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

fpallares accepted this revision. fpallares added a comment. This revision is now accepted and ready to land. Aside from the minor nit below this patch LGTM. Thanks a lot for all the changes @HsiangKai. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

fpallares added a comment. Thanks for the update @HsiangKai. I've noticed that we aren't handling the exceptions that state that the `V0` constraint shouldn't be enforced for instructions that generate masks or for reductions. For instance the following (valid) instructions are rejected:

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

HsiangKai added a comment. In D80802#2155802 , @fpallares wrote: > Apologies we didn't identify this earlier but with the change of the mask > register layout (`MLEN=1`) the overlap constraints involving the mask > register were modified: > >

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

evandro added a comment. Just a couple of nits, but otherwise it LGTM. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:776 } -return ""; +llvm_unreachable("Unknown SEW."); } I'd rather the first case be the `default` case and

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

simoncook added a comment. In D80802#2156221 , @HsiangKai wrote: > The modification is put in D81213 . Ah ok, missed that, thanks for pointing it out Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

HsiangKai added a comment. In D80802#2155432 , @simoncook wrote: > Since this patch replaces 0.8 support with 0.9, it should include an update > to the version check in `clang/lib/Driver/ToolChains/Arch/RISCV.cpp` to match. The modification is put in

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

fpallares added a comment. Apologies we didn't identify this earlier but with the change of the mask register layout (`MLEN=1`) the overlap constraints involving the mask register were modified: //**RVV-0.8, Section 5.3. Vector Masking:**// > The destination vector register group for a masked

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

simoncook added a comment. Since this patch replaces 0.8 support with 0.9, it should include an update to the version check in `clang/lib/Driver/ToolChains/Arch/RISCV.cpp` to match. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80802/new/

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

HsiangKai marked an inline comment as done. HsiangKai added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:99 // load vd, (rs1), vm class VUnitStrideLoad fpallares wrote: > I believe that with the changes introduced in the encoding of

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

fpallares added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:99 // load vd, (rs1), vm class VUnitStrideLoad I believe that with the changes introduced in the encoding of the loads and stores we can do without the `mop` parameter in

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

HsiangKai marked an inline comment as done. HsiangKai added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2386 +CheckReg = Inst.getOperand(3).getReg(); } +if (DestReg == CheckReg) fpallares wrote: > fpallares

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

fpallares added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2386 +CheckReg = Inst.getOperand(3).getReg(); } +if (DestReg == CheckReg) fpallares wrote: > With the suggestion above, this could be further

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

asb added a comment. I've gone through and can't see any obvious issues. I defer to one of the RISC-V Vector extension usual suspects for giving a LGTM on the detail of the altered instructions etc. Once we have that, this looks good to land IMHO. Repository: rG LLVM Github Monorepo

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

fpallares added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2367 +Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM || +Opcode == RISCV::VSBC_VXM) { + if (DestReg == RISCV::V0) I think we might not

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

fpallares added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2362 + } + if (TargetFlags & RISCV::VMConstraint) { +// vadc, vsbc are special cases. Given that this constraint has no effect when `DestReg != RISCV::V0`, we

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

rogfer01 added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:796 } return ""; } Minor nit that we missed in the patch of 0.8: can you replace this return with ```lang=cpp llvm_unreachable(); ``` as recommended in

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

fpallares added a comment. Hi @HsiangKai, thanks for the patch. So far everything looks good aside from a couple of minor nits. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1638 + + if (getLexer().getKind() == AsmToken::EndOfStatement) { +

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

evandro added a comment. Again, the `clang` part should be split in another patch and be made a child of D81188 . Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:297 +LMUL_F8 = 5, +LMUL_F4 = 6, +LMUL_F2 = 7

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

HsiangKai updated this revision to Diff 267447. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80802/new/ https://reviews.llvm.org/D80802 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/test/Driver/riscv-arch.c

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

MaskRay added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1213 SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); -return Error(ErrorLoc, - "operand must be

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

HsiangKai updated this revision to Diff 267239. Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80802/new/ https://reviews.llvm.org/D80802 Files: