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Closed by commit rGc4e574323210: [PowerPC] Implement low-order Vector Modulus
Builtins, and add Vector… (authored by amyk).
Changed prior to commit:
bsaleil accepted this revision.
bsaleil added a comment.
This revision is now accepted and ready to land.
Thanks for the explanation. LGTM.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D82576/new/
https://reviews.llvm.org/D82576
amyk marked an inline comment as done.
amyk added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:28
+ return vec_mul(vulla, vullb);
+}
+
bsaleil wrote:
> Are the tests for `vec_mul` with `v4i32` missing ?
I should probably reword the
bsaleil added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:28
+ return vec_mul(vulla, vullb);
+}
+
Are the tests for `vec_mul` with `v4i32` missing ?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
amyk updated this revision to Diff 274679.
amyk edited the summary of this revision.
amyk added a parent revision: D82584: [PowerPC][Power10] Exploit the High Order
Vector Multiply Instructions on Power10.
amyk added a comment.
Rebased patch.
Repository:
rG LLVM Github Monorepo
CHANGES
amyk created this revision.
amyk added reviewers: power-llvm-team, PowerPC, Conanap, saghir, nemanjai, lei.
amyk added projects: LLVM, clang, PowerPC.
Herald added a subscriber: shchenz.
This patch aims to add the following function prototypes:
vector signed int vec_mod (vector signed int a,
