[PATCH] D33893: Align definition of DW_OP_plus with DWARF spec [2/3]

sdesmalen created this revision. Herald added a subscriber: aprantl. This patch is part of 3 patches that together form a single patch, but must be introduced in stages in order not to break things.   The way that LLVM interprets DW_OP_plus in DIExpression nodes is basically that of the

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen added a comment. Just a gentle reminder that this patch still needs to be accepted (the LLVM support for it has been merged). https://reviews.llvm.org/D41698 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen updated this revision to Diff 129943. sdesmalen added a comment. Refactoring based on @aprantl's suggestions. https://reviews.llvm.org/D41698 Files: lib/CodeGen/CGDebugInfo.cpp lib/CodeGen/CGDebugInfo.h lib/CodeGen/CGDecl.cpp lib/CodeGen/CodeGenFunction.cpp

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen marked 3 inline comments as done. sdesmalen added inline comments. Comment at: lib/CodeGen/CGDebugInfo.cpp:2358 +if (auto *SizeNode = getVLASizeExpressionForType(EltTy)) + Subscripts.push_back(DBuilder.getOrCreateSubrange(0, SizeNode)); +else

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen updated this revision to Diff 131990. sdesmalen marked 4 inline comments as done. sdesmalen added a comment. Herald added a subscriber: jholewinski. - Changed return type of getVLASize() to a struct with named members. - EmitDeclare and EmitDeclareOfAutoVariable now return a

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen added inline comments. Comment at: lib/CodeGen/CGDebugInfo.h:474 + CGBuilderTy , + llvm::Metadata **MetadataDecl = nullptr); aprantl wrote: > same here. Why not just use a return value? Initially I thought it would

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen added inline comments. Comment at: lib/CodeGen/CGDecl.cpp:990 + D.getLocation(), D.getLocation(), , QT, + getContext().CreateTypeSourceInfo(QT), SC_Auto); + aprantl wrote: > sdesmalen wrote: > > aprantl wrote: > > > I think it does,

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen marked an inline comment as done. sdesmalen added a comment. Thanks for your review @aprantl! https://reviews.llvm.org/D41698 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen updated this revision to Diff 132275. sdesmalen added a comment. - Now always emit an alloca for a VLA dimension expression (regardless of whether -g is passed). - Fixed up some more tests since it now also triggers for all tests with variable length arrays that don't pass -g. -

[PATCH] D43189: [DebugInfo] Avoid name conflict of generated VLA expression variable.

sdesmalen created this revision. sdesmalen added reviewers: CarlosAlbertoEnciso, probinson, aprantl. Herald added a subscriber: JDevlieghere. This patch also adds the 'DW_AT_artificial' flag to the generated variable. https://reviews.llvm.org/D43189 Files: lib/CodeGen/CGDecl.cpp

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen created this revision. sdesmalen added reviewers: echristo, aprantl, dexonsmith, clayborg, pcc, kristof.beyls. Herald added a subscriber: JDevlieghere. This patch enables debugging of C99 VLA types by generating more precise LLVM Debug metadata, using the extended DISubrange 'count'

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen updated this revision to Diff 173831. sdesmalen added a comment. - Removed `_aarch64_vector_pcs` and `__aarch64_vector_pcs` keywords in favour of supporting only `__attribute__(aarch64_vector_pcs))`. https://reviews.llvm.org/D54425 Files: include/clang-c/Index.h

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen marked an inline comment as done. sdesmalen added inline comments. Comment at: include/clang/Basic/Attr.td:1792 + let Spellings = [GNU<"aarch64_vector_pcs">, + CXX11<"clang", "aarch64_vector_pcs">, + Keyword<"__aarch64_vector_pcs">,

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen created this revision. sdesmalen added reviewers: ributzka, rjmccall, rnk, aaron.ballman. Herald added subscribers: arphaman, kristof.beyls, javed.absar. This is the Clang patch to complement the following LLVM patches: https://reviews.llvm.org/D51477

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen added inline comments. Comment at: lib/CodeGen/CGDebugInfo.cpp:1101 case CC_AAPCS: + case CC_AArch64VectorCall: return llvm::dwarf::DW_CC_LLVM_AAPCS; I wasn't really sure whether this requires a corresponding DW_CC_LLVM_AAVPCS record in LLVM,

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen updated this revision to Diff 175236. sdesmalen added a comment. - resolved editorial comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54425/new/ https://reviews.llvm.org/D54425 Files: include/clang-c/Index.h include/clang/Basic/Attr.td

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen updated this revision to Diff 174574. sdesmalen marked an inline comment as done. sdesmalen added a comment. Thanks all for the suggestions and comments! I've updated the patch with a better description of the attribute's behaviour (thanks @rjmccall for the starting point!) and added

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen added a subscriber: keith.walker.arm. sdesmalen added inline comments. Comment at: lib/CodeGen/CGDebugInfo.cpp:1101 case CC_AAPCS: + case CC_AArch64VectorCall: return llvm::dwarf::DW_CC_LLVM_AAPCS; rjmccall wrote: > rnk wrote: > > sdesmalen

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen added a comment. Just to double check before committing, @aaron.ballman are you happy with the tests? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54425/new/ https://reviews.llvm.org/D54425 ___ cfe-commits mailing list

[PATCH] D66302: [SVE][Inline-Asm] Support for SVE asm operands

sdesmalen added a comment. Thanks for this change @kmclaughlin. Comment at: docs/LangRef.rst:3816 +- ``x``: Like w, but restricted to registers 0 to 15 inclusive. +- ``y``: Like w, but restricted to registers 0 to 7 inclusive. I noticed this comment does not

[PATCH] D67095: [SVE][Inline-Asm] Fix -Wimplicit-fallthrough in AArch64ISelLowering.cpp

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67095/new/ https://reviews.llvm.org/D67095 ___

[PATCH] D66302: [SVE][Inline-Asm] Support for SVE asm operands

sdesmalen added inline comments. Comment at: lib/Target/AArch64/AArch64AsmPrinter.cpp:618 +bool hasAltName; +const TargetRegisterClass *RegClass; The use of `hasAltName` is confusing me here. When I look at the declaration and definition of

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

sdesmalen added inline comments. Comment at: lib/IR/InlineAsm.cpp:188 + unsigned char C = static_cast(*I); + assert(isdigit(C) && "Not a single digit!"); + int N = C - '0'; `"Expected a digit"` seems more appropriate, since this code is only

[PATCH] D66302: [SVE][Inline-Asm] Support for SVE asm operands

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks for making these changes @kmclaughlin, LGTM! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66302/new/ https://reviews.llvm.org/D66302

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

sdesmalen added inline comments. Comment at: include/llvm/IR/DerivedTypes.h:500 +default: + assert(0 && "Cannot create narrower fp vector element type"); + break; nit: Use `llvm_unreachable("message")` instead of `assert(0 && "message")`

[PATCH] D65404: [AArch64] Disable __ARM_FEATURE_SVE without ACLE.

sdesmalen added a comment. Thanks, I see your argument for having the feature enabled even when the ACLE is still partially supported. At the moment however, LLVM still only support the assembler/disassembler and inline asm. We'll be working to add support for the ACLE soon, but for now having

[PATCH] D65404: [AArch64] Disable __ARM_FEATURE_SVE without ACLE.

sdesmalen created this revision. sdesmalen added reviewers: c-rhodes, chill, rengolin, rovka. Herald added subscribers: kristof.beyls, tschuett, javed.absar. The Arm C Language Extensions for SVE document specifies that __ARM_FEATURE_SVE should be set when the compiler supports SVE and

[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64739/new/ https://reviews.llvm.org/D64739 ___ cfe-commits mailing list

[PATCH] D64739: [SVE][Inline-Asm] Add support to clang for SVE inline assembly

sdesmalen added a comment. Functionally the patch looks good, but the title suggests this adds full inline-asm support for SVE (which would require the ACLE types proposed in D62960 , as well as other changes), where this patch only adds support to specify SVE

[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

sdesmalen added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:1 +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -target-feature +sve -o - %s | FileCheck %s + rovka wrote: > Can you also add a test without +sve, to make

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

sdesmalen added a comment. Thanks for the changes @kmclaughlin! Just a few more nits from me, but looks good otherwise. Comment at: include/llvm/IR/DerivedTypes.h:493 +llvm_unreachable("Cannot create narrower fp vector element type"); +break; + }

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks, LGTM! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67549/new/ https://reviews.llvm.org/D67549 ___ cfe-commits mailing

[PATCH] D53137: Scalable vector core instruction support + size queries

sdesmalen accepted this revision. sdesmalen added a comment. Thanks @huntergr , I think this interface looks really nice. LGTM! Comment at: llvm/include/llvm/IR/DataLayout.h:456 + TypeSize getTypeStoreSize(Type *Ty) const { +auto BaseSize = getTypeSizeInBits(Ty); +

[PATCH] D69378: [AArch64][SVE] Implement masked store intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. Nice one! LGTM! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69378/new/ https://reviews.llvm.org/D69378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D69800: [AArch64][SVE] Implement remaining floating-point arithmetic intrinsics

sdesmalen added inline comments. Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll:767 ; -; FSCALE +; FNEG ; Why are you moving this test and changing fscale -> fneg here? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D69858: [AArch64][SVE] Implement floating-point comparison & reduction intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks, LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69858/new/ https://reviews.llvm.org/D69858

[PATCH] D69707: [AArch64][SVE] Implement additional floating-point arithmetic intrinsics

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:10064 + SDNodeXFormgetTargetConstant((N->getSExtValue() / 90), SDLoc(N), MVT::i64); +}]>> { should the target constant

[PATCH] D69800: [AArch64][SVE] Implement remaining floating-point arithmetic intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll:767 ; -; FSCALE +; FNEG ; kmclaughlin wrote: > sdesmalen wrote: > > Why are

[PATCH] D71167: [Driver] Default to -momit-leaf-frame-pointer for AArch64

sdesmalen added a comment. The patch looks structurally fine, but I'm missing the argumentation for changing the default and related, the history of why the default is to //not// omit the frame pointer on leaf functions. Can you provide some insight here? Repository: rG LLVM Github Monorepo

[PATCH] D71556: [AArch64][SVE] Implement intrinsic for non-faulting loads

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:329 + +def non_faulting_load : + PatFrag<(ops node:$ptr, node:$pred, node:$def), This duplicates a lot of code, maybe it makes sense to combine this into a multiclass.

[PATCH] D71556: [AArch64][SVE] Implement intrinsic for non-faulting loads

sdesmalen added a comment. In D71556#1786465 , @efriedma wrote: > I'm not sure it's legal to transform a non-faulting load to a load with a > non-faulting flag? At least, we'd need to consider the implications of that > very carefully. In particular,

[PATCH] D69378: [AArch64][SVE] Implement masked store intrinsics

sdesmalen added a comment. Thanks for the changes to the tests. Comment at: llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll:9 +; CHECK-LABEL: masked_trunc_store_nxv2i8: +; CHECK: st1b { [[IN:z[0-9]]].d }, [[PG:p[0-9]]], [x1] + %trunc = trunc %val to I

[PATCH] D69567: [AArch64][SVE] Implement additional integer arithmetic intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks, LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69567/new/ https://reviews.llvm.org/D69567

[PATCH] D70253: [AArch64][SVE2] Implement remaining SVE2 floating-point intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks @kmclaughlin , LGTM. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:898 + llvm_i32_ty], +[IntrNoMem]>; +

[PATCH] D70437: [AArch64][SVE] Implement shift intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70437/new/ https://reviews.llvm.org/D70437 ___ cfe-commits mailing list

[PATCH] D70253: [AArch64][SVE2] Implement remaining SVE2 floating-point intrinsics

sdesmalen added inline comments. Herald added a reviewer: efriedma. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:898 + llvm_i32_ty], +[IntrNoMem]>; + efriedma wrote: > kmclaughlin wrote: > > sdesmalen wrote: > > > I'd

[PATCH] D69657: [AArch64][SVE] Implement several floating-point arithmetic intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks @kmclaughlin, LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69657/new/ https://reviews.llvm.org/D69657

[PATCH] D70180: [AArch64][SVE] Implement floating-point conversion intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Herald added a reviewer: efriedma. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70180/new/ https://reviews.llvm.org/D70180

[PATCH] D70253: [AArch64][SVE2] Implement remaining SVE2 floating-point intrinsics

sdesmalen added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:898 + llvm_i32_ty], +[IntrNoMem]>; + I'd expect the `llvm_i32_ty` to be an immediate for these instructions, right? If so you'll need to add

[PATCH] D70437: [AArch64][SVE] Implement shift intrinsics

sdesmalen added a comment. Herald added a reviewer: efriedma. Two small comments, but overall looks good! Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:835 + LLVMMatchType<0>, + llvm_i32_ty], +[IntrNoMem]>;

[PATCH] D69707: [AArch64][SVE] Implement additional floating-point arithmetic intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks, LGTM! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69707/new/ https://reviews.llvm.org/D69707 ___ cfe-commits mailing

[PATCH] D67830: [AArch64][SVE] Implement punpk[hi|lo] intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM. Looks like a straightforward fix and support for `punpk(hi|lo)` intrinsics. Comment at: llvm/lib/IR/Function.cpp:1213 // If this is a forward reference,

[PATCH] D67551: [AArch64][SVE] Implement sdot and udot (lane) intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67551/new/ https://reviews.llvm.org/D67551 ___ cfe-commits mailing list

[PATCH] D74222: [AArch64][SVE] Add mul/mla/mls lane & dup intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D74222/new/ https://reviews.llvm.org/D74222

[PATCH] D71698: [AArch64][SVE] Add intrinsic for non-faulting loads

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM [with the caveat that we need to revisit the modelling of the `FFR` register and get rid fo the `PseudoInstExpansion` at a later point, as discussed during the previous sync-up

[PATCH] D75470: [SVE] Auto-generate builtins and header for svld1.

sdesmalen updated this revision to Diff 248432. sdesmalen marked 11 inline comments as done. sdesmalen added a comment. - Renamed CK and BaseTS - Refactored switch statementsd in SVEType::getTypeFlags() CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75470/new/

[PATCH] D75470: [SVE] Auto-generate builtins and header for svld1.

sdesmalen added inline comments. Comment at: clang/include/clang/Basic/arm_sve.td:121 +// Load one vector (scalar base) +def SVLD1 : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad]>; SjoerdMeijer wrote: > This encoding, e.g, this is "csilUcUsUiUlhfd",

[PATCH] D75298: [Clang][SVE] Parse builtin type string for scalable vectors

sdesmalen added a comment. In D75298#1901578 , @efriedma wrote: > How are you planning to handle them with your current approach? Each prototype will get a `arm_sve_alias` attribute that specifies which builtin it relates to. For example:

[PATCH] D75298: [Clang][SVE] Parse builtin type string for scalable vectors

sdesmalen updated this revision to Diff 247659. sdesmalen marked an inline comment as done. sdesmalen added a comment. - Added comment describing `q` for scalable vectors to Builtins.def - Use `getKnownMinSize()` for calculating `LargestVectorWidth` CHANGES SINCE LAST ACTION

[PATCH] D75298: [Clang][SVE] Parse builtin type string for scalable vectors

sdesmalen added a comment. In D75298#1898770 , @efriedma wrote: > Can we avoid a gigantic, expensive to parse arm_sve.h somehow? Given that > the compiler has to know the signatures for all these buitins anyway, can we > just make including arm_sve.h

[PATCH] D75470: [SVE] Auto-generate builtins and header for svld1.

sdesmalen marked an inline comment as done. sdesmalen added inline comments. Comment at: clang/include/clang/Basic/AArch64SVETypeFlags.h:1 +//===- SveEmitter.cpp - Generate arm_sve.h for use with clang -*- C++ -*-===// +// I just see that this comment will need

[PATCH] D75470: [SVE] Auto-generate builtins and header for svld1.

sdesmalen created this revision. sdesmalen added reviewers: efriedma, rovka, SjoerdMeijer, rsandifo-arm. Herald added subscribers: psnobl, rkruppe, mgrang, kristof.beyls, tschuett, mgorny. Herald added a reviewer: rengolin. Herald added a project: clang. sdesmalen added a parent revision: D75298:

[PATCH] D75298: [Clang][SVE] Parse builtin type string for scalable vectors

sdesmalen created this revision. sdesmalen added reviewers: efriedma, rjmccall, rovka, rsandifo-arm. Herald added subscribers: psnobl, rkruppe, kristof.beyls, tschuett, mgorny. Herald added a reviewer: rengolin. Herald added a project: clang. This patch adds 'q' to mean 'scalable vector' in the

[PATCH] D72467: Remove "mask" operand from shufflevector.

sdesmalen added a comment. Thanks @efriedma for working on this. The overall approach seems good to me! Mostly added some nits, with the exception of one question on what to do with a shufflevector with fixed-width mask and scalable source vectors. Comment at:

[PATCH] D73719: [AArch64][SVE] Add SVE2 intrinsics for widening DSP operations

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73719/new/ https://reviews.llvm.org/D73719

[PATCH] D73903: [AArch64][SVE] Add remaining SVE2 intrinsics for widening DSP operations

sdesmalen added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1852 -// SVE2 MLA LANE. -def int_aarch64_sve_smlalb_lane : SVE2_3VectorArg_Indexed_Intrinsic; nit: why are you moving these? Repository: rG LLVM Github Monorepo

[PATCH] D73636: [AArch64][SVE] SVE2 intrinsics for complex integer arithmetic

sdesmalen added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1758 +def int_aarch64_sve_sqcadd_x : AdvSIMD_2VectorArgIndexed_Intrinsic; +def int_aarch64_sve_cmla_x : AdvSIMD_3VectorArgIndexed_Intrinsic; +def int_aarch64_sve_cmla_lane_x

[PATCH] D73551: [AArch64][SVE] Add remaining SVE2 intrinsics for uniform DSP operations

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73551/new/ https://reviews.llvm.org/D73551

[PATCH] D73636: [AArch64][SVE] SVE2 intrinsics for complex integer arithmetic

sdesmalen added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1116 + LLVMMatchType<0>, + llvm_i32_ty], +[IntrNoMem]>; missing ImmArg Comment at:

[PATCH] D74724: [AArch64][SVE] CodeGen of ACLE Builtin Types

sdesmalen created this revision. sdesmalen added reviewers: rsandifo-arm, rovka, rjmccall, efriedma. Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added projects: clang, LLVM. This patch adds codegen support for the ACLE builtin types added

[PATCH] D73903: [AArch64][SVE] Add remaining SVE2 intrinsics for widening DSP operations

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1100 [IntrNoMem]>; + class SVE2_2VectorArg_Narrowing_Intrinsic nit:

[PATCH] D74724: [AArch64][SVE] CodeGen of ACLE Builtin Types

sdesmalen updated this revision to Diff 245127. sdesmalen added a comment. - Inlined function into switch statement - Removed changes to IRTranslator.cpp from this patch. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D74724/new/ https://reviews.llvm.org/D74724 Files:

[PATCH] D74724: [AArch64][SVE] CodeGen of ACLE Builtin Types

This revision was automatically updated to reflect the committed changes. Closed by commit rG49b307e96d47: [AArch64][SVE] CodeGen of ACLE Builtin Types (authored by sdesmalen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D74724/new/

[PATCH] D73636: [AArch64][SVE] SVE2 intrinsics for complex integer arithmetic

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks @kmclaughlin , LGTM. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1115 class AdvSIMD_SVE_LOGB_Intrinsic : AdvSIMD_SVE_CNT_Intrinsic; + class

[PATCH] D74550: [AArch64][SVE] Add SVE index intrinsic

sdesmalen added a comment. Nice, thanks for adding those tests @kmclaughlin. LGTM! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D74550/new/ https://reviews.llvm.org/D74550 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D74912: [AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1226 + // intrinsic currently, where NumVecs is always 2 + unsigned NumVecs = 2; + nit: You can just as well inline this value now. Comment at:

[PATCH] D74833: [AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D74833/new/ https://reviews.llvm.org/D74833

[PATCH] D74734: [AArch64][SVE] Add the SVE dupq_lane intrinsic

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7495 + // DUPQ can be used when idx is in range. + auto CIdx = dyn_cast(Idx128); + if (CIdx &&

[PATCH] D74550: [AArch64][SVE] Add SVE index intrinsic

sdesmalen added inline comments. Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll:35 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.index.nxv2i64(i64 -14, i64 15) + ret %out Is there a reason you're not testing for -16, 15 for all of these

[PATCH] D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:1099 +class AsmVectorIndexOpnd +: Operand, ComplexPattern", []> { let ParserMatchClass = mc; @efriedma @rengolin The idea here is to use a ComplexPattern to

[PATCH] D73025: [AArch64][SVE] Add first-faulting load intrinsic

sdesmalen accepted this revision. sdesmalen added inline comments. This revision is now accepted and ready to land. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11248 -static SDValue performLDNF1Combine(SDNode *N, SelectionDAG ) { +static SDValue

[PATCH] D71698: [AArch64][SVE] Add intrinsic for non-faulting loads

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12460 - if ((SignExtSrcVT != GLD1SrcMemVT) || !Src.hasOneUse()) + unsigned OpNum = NewOpc == AArch64ISD::LDNF1S ? 3 : 4; + EVT LD1SrcMemVT = cast(Src->getOperand(OpNum))->getVT();

[PATCH] D71698: [AArch64][SVE] Add intrinsic for non-faulting loads

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:5333 + // We need a layer of indirection because early machine code passes balk at + // physical register (i.e. FFR) uses that have no previous definition. + let hasSideEffects = 1,

[PATCH] D75298: [Clang][SVE] Parse builtin type string for scalable vectors

sdesmalen added a comment. In D75298#1918489 , @efriedma wrote: > Changing the way we expose the builtins isn't going to affect most of the > code related to the SVE intrinsics. I'm fine sticking with a known working > approach, and trying to address

[PATCH] D75298: [Clang][SVE] Parse builtin type string for scalable vectors

sdesmalen updated this revision to Diff 249966. sdesmalen added a comment. - Updated license header for the arm_sve.h file to use the LLVM license instead of MIT. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75298/new/ https://reviews.llvm.org/D75298 Files:

[PATCH] D75470: [SVE] Auto-generate builtins and header for svld1.

sdesmalen marked an inline comment as done. sdesmalen added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:5292 + { #NameBase, SVE::BI__builtin_sve_##NameBase, 0, 0, TypeModifier } +static const NeonIntrinsicInfo AArch64SVEIntrinsicMap[] = { +#define

[PATCH] D75470: [SVE] Auto-generate builtins and header for svld1.

sdesmalen updated this revision to Diff 249312. sdesmalen added a comment. s/NeonIntrinsicInfo/ARMVectorIntrinsicInfo/ s/findNeonIntrinsicInMap/findARMVectorIntrinsicInMap/ CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75470/new/ https://reviews.llvm.org/D75470 Files:

[PATCH] D75470: [SVE] Auto-generate builtins and header for svld1.

sdesmalen marked an inline comment as done. sdesmalen added a comment. Herald added a subscriber: danielkiss. In D75470#1907562 , @SjoerdMeijer wrote: > Adding @simon_tatham in case he feels wants to have a look too. Thanks Sjoerd! @simon_tatham and I

[PATCH] D75298: [Clang][SVE] Parse builtin type string for scalable vectors

sdesmalen added a subscriber: simon_tatham. sdesmalen added a comment. Herald added a subscriber: danielkiss. In D75298#1904561 , @efriedma wrote: > > Do you happen to know which method in Sema does this? I had a look before, > > but couldn't find where

[PATCH] D75861: [SVE] Generate overloaded functions for ACLE intrinsics.

sdesmalen updated this revision to Diff 249370. sdesmalen edited the summary of this revision. sdesmalen added a comment. - Rebased patch on top of D75850 . - Removed `__clang_arm_sve_alias` in favour of `__clang_arm_builtin_alias` CHANGES SINCE LAST ACTION

[PATCH] D75861: [SVE] Generate overloaded functions for ACLE intrinsics.

sdesmalen updated this revision to Diff 249404. sdesmalen added a comment. - Refactored condition to check for valid builtins (split up checks for Arm and AArch64) CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75861/new/ https://reviews.llvm.org/D75861 Files:

[PATCH] D75861: [SVE] Generate overloaded functions for ACLE intrinsics.

sdesmalen created this revision. sdesmalen added reviewers: SjoerdMeijer, miyuki, efriedma, simon_tatham. Herald added subscribers: cfe-commits, danielkiss, dmgreen, psnobl, rkruppe, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. The SVE ACLE allows

[PATCH] D75850: [ARM, CDE] Generalize MVE intrinsics infrastructure to support CDE

sdesmalen added a comment. In D75850#1912685 , @simon_tatham wrote: > > Renames the 'clang_arm_mve_alias' attribute into 'clang_arm_builtin_alias' > > (it will be used with CDE intrinsics as well as MVE intrinsics) > > You might talk to @sdesmalen, who

[PATCH] D75858: [AArch64][SVE] Add SVE intrinsics for address calculations

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75858/new/ https://reviews.llvm.org/D75858

[PATCH] D75470: [SVE] Auto-generate builtins and header for svld1.

This revision was automatically updated to reflect the committed changes. Closed by commit rG8b409eabaf75: [SVE] Auto-generate builtins and header for svld1. (authored by sdesmalen). Changed prior to commit: https://reviews.llvm.org/D75470?vs=249312=250509#toc Repository: rG LLVM Github

[PATCH] D78131: [SVE] Fix unsigned is always >= 0

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM, thanks for fixing @ctetreau! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78131/new/ https://reviews.llvm.org/D78131

[PATCH] D77940: [AArch64] Add NVIDIA Carmel support

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64.td:607 + FeatureSVE + ]>; + Not sure how accurate the link you referenced is, but it doesn't mention SVE or Crypto

[PATCH] D77596: [SveEmitter] Add IsOverloadNone flag and builtins for svpfalse and svcnt[bhwd]_pat

sdesmalen updated this revision to Diff 257824. sdesmalen retitled this revision from "[SveEmitter] Add NoOverload flag and builtin for svpfalse" to "[SveEmitter] Add IsOverloadNone flag and builtins for svpfalse and svcnt[bhwd]_pat". sdesmalen edited the summary of this revision. sdesmalen

[PATCH] D78238: [SveEmitter] Add builtins for svwhilerw/svwhilewr

sdesmalen created this revision. sdesmalen added reviewers: SjoerdMeijer, efriedma. Herald added a subscriber: tschuett. Herald added a project: clang. sdesmalen added a parent revision: D77595: [SveEmitter] Add builtins for svwhile. sdesmalen added a child revision: D78239: [SveEmitter] Add

[PATCH] D78239: [SveEmitter] Add builtins for FP conversions

sdesmalen created this revision. sdesmalen added reviewers: SjoerdMeijer, efriedma. Herald added a subscriber: tschuett. Herald added a project: clang. sdesmalen added a parent revision: D78238: [SveEmitter] Add builtins for svwhilerw/svwhilewr. sdesmalen added a child revision: D77597:

  1   2   3   4   5   >