[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

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DiggerLin added inline comments.



Comment at: clang/lib/CodeGen/BackendUtil.cpp:520
   Options.DataSections = CodeGenOpts.DataSections;
-  Options.IgnoreXCOFFVisibility = CodeGenOpts.IgnoreXCOFFVisibility;
   Options.UniqueSectionNames = CodeGenOpts.UniqueSectionNames;

hubert.reinterpretcast wrote:
> DiggerLin wrote:
> > sfertile wrote:
> > > DiggerLin wrote:
> > > > sfertile wrote:
> > > > > DiggerLin wrote:
> > > > > > jasonliu wrote:
> > > > > > > DiggerLin wrote:
> > > > > > > > DiggerLin wrote:
> > > > > > > > > jasonliu wrote:
> > > > > > > > > > DiggerLin wrote:
> > > > > > > > > > > jasonliu wrote:
> > > > > > > > > > > > DiggerLin wrote:
> > > > > > > > > > > > > jasonliu wrote:
> > > > > > > > > > > > > > Instead of just removing this line, should this get 
> > > > > > > > > > > > > > replaced with the new LangOpts option?
> > > > > > > > > > > > > I do not think we need a CodeGenOp of 
> > > > > > > > > > > > > ignore-xcoff-visibility in clang, we only need the 
> > > > > > > > > > > > > LangOpt of the ignore-xcoff-visilbity to control 
> > > > > > > > > > > > > whether we will  generate the visibility in the IR,  
> > > > > > > > > > > > > when the LangOpt of ignore-xcoff-visibility do not 
> > > > > > > > > > > > > generate the visibility attribute of GV in the IR. it 
> > > > > > > > > > > > > do not need CodeGenOp of ignore-xcoff-visibility any 
> > > > > > > > > > > > > more for the clang .
> > > > > > > > > > > > > 
> > > > > > > > > > > > > we have still CodeGen ignore-xcoff-visibility op in  
> > > > > > > > > > > > > llc.
> > > > > > > > > > > > We removed the visibility from IR level with this 
> > > > > > > > > > > > patch. But there is also visibility settings coming 
> > > > > > > > > > > > from CodeGen part of clang, which needs to get ignore 
> > > > > > > > > > > > when we are doing the code gen in llc. So I think you 
> > > > > > > > > > > > still need to set the options correct for llc.
> > > > > > > > > > > yes we have the set the options correct for llc in the 
> > > > > > > > > > > code.
> > > > > > > > > > > 
> > > > > > > > > > > in the source file llvm/lib/CodeGen/CommandFlags.cpp, we 
> > > > > > > > > > > have (in the patch https://reviews.llvm.org/D87451 add 
> > > > > > > > > > > new option -mignore-xcoff-visibility) , the function
> > > > > > > > > > > TargetOptions 
> > > > > > > > > > > codegen::InitTargetOptionsFromCodeGenFlags() {
> > > > > > > > > > > 
> > > > > > > > > > > Options.IgnoreXCOFFVisibility = 
> > > > > > > > > > > getIgnoreXCOFFVisibility(); 
> > > > > > > > > > > ...}
> > > > > > > > > > > 
> > > > > > > > > > What I'm saying is... 
> > > > > > > > > > I think we need a line like this:
> > > > > > > > > > `Options.IgnoreXCOFFVisibility = 
> > > > > > > > > > LangOpts.IgnoreXCOFFVisibility;`
> > > > > > > > > > so that when you invoke clang, backend would get the 
> > > > > > > > > > correct setting as well. 
> > > > > > > > > I do not think so, from the clang FE, we do not generated the 
> > > > > > > > > visibility in the IR. so there is no need these line.
> > > > > > > > or we can say that because we do not set the hidden visibility 
> > > > > > > > into the GlobalValue , so we do not need the 
> > > > > > > > Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;
> > > > > > > I think I mentioned this before, we could have extra visibility 
> > > > > > > settings in clang/lib/CodeGen that's not depending on the 
> > > > > > > existing visibility setting in the IR. (You could search for 
> > > > > > > `setVisibility` there.) That was the reason we did it in llc 
> > > > > > > first. 
> > > > > > I will add Options.IgnoreXCOFFVisibility = 
> > > > > > LangOpts.IgnoreXCOFFVisibility;  here.
> > > > > > I think I mentioned this before, we could have extra visibility 
> > > > > > settings in clang/lib/CodeGen that's not depending on the existing 
> > > > > > visibility setting in the IR. (You could search for setVisibility 
> > > > > > there.) That was the reason we did it in llc first.
> > > > > 
> > > > >  A lot of these are in places we wouldn't encounter with AIX, like 
> > > > > for Objective-C code gen. But are others like [[ 
> > > > > https://github.com/llvm/llvm-project/blob/b03ea054db1bcf9452b3a70e21d3372b6e58759a/clang/lib/CodeGen/ItaniumCXXABI.cpp#L2507
> > > > >  | this]]  an issue? Should they be addressed in this patch?
> > > > after I added the Options.IgnoreXCOFFVisibility = 
> > > > LangOpts.IgnoreXCOFFVisibility , even there is  
> > > > GV->setVisibility(llvm::GlobalValue::HiddenVisibility);  it do not 
> > > > effect our output.
> > > > 
> > > > there is following code in the function void 
> > > > PPCAIXAsmPrinter::emitLinkage(const GlobalValue *GV,
> > > >MCSymbol *GVSym) const
> > > > {
> > > >  . 
> > > >   if (!TM.getIgnoreXCOFFVisibility()) {
> > > > switch (GV->getVisibility()) {
> > > > 
> > > > // TODO: "exported" and 

[PATCH] D89684: [AIX] Add mabi=vec-extabi options to enable the AIX extended and default vector ABIs.

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DiggerLin accepted this revision.
DiggerLin added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D89684: [AIX] Add mvecnvol and mnovecnvol options to enable the AIX extended and default vector ABIs.

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DiggerLin added inline comments.



Comment at: clang/docs/ClangCommandLineReference.rst:2870
+
+.. option:: -mvecnvol, -mnovecnvol
+

I think it should be 

```.. option:: -mvecnvol, -mnovecnvol
  Only supported On AIX. Specify usage of volatile and nonvolatile vector 
registers, the extended vector ABI on AIX. Defaults to '-mnovecnvol' when 
Altivec is enabled.
```




Comment at: clang/lib/Driver/ToolChains/Clang.cpp:4591
+
+if (A->getOption().matches(options::OPT_mnovecnvol) && haveMaltivec)
+  D.Diag(diag::err_aix_default_altivec_abi);

Xiangling_L wrote:
> Since we are defaulting to default altivec ABI, so I think the logic here 
> should be if (HasAltivec && !Args.getLastArg(options::OPT_mvecnvol)), then we 
> emit `D.Diag(diag::err_aix_default_altivec_abi)` error?
I think we do not need a new variable here. we can write as 
if (A->getOption().matches(options::OPT_mnovecnvol)  && 
Args.getLastArg(OPT_maltivec) 


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[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 301029.
DiggerLin added a comment.

remove REQUIRES: powerpc-registered-target  from test case


Repository:
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Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/LangOptions.def
  clang/lib/AST/Decl.cpp
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/CodeGen/aix-visibility-inlines-hidden.cpp

Index: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large \
+// RUN:-fvisibility-inlines-hidden -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden \
+// RUN:-fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -mignore-xcoff-visibility -emit-llvm \
+// RUN:-fvisibility-inlines-hidden -fvisibility default -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
+int x = 66;
+__attribute__((__noinline__)) inline void f() {
+  x = 55;
+}
+
+#pragma GCC visibility push(hidden)
+__attribute__((__noinline__)) inline void foo() {
+  x = 55;
+}
+#pragma GCC visibility pop
+
+int bar() {
+  f();
+  foo();
+  return x;
+}
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z1fv()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z1fv()
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z3foov()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z3foov()
Index: clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
===
--- clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
+++ clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
@@ -1,24 +1,8 @@
-// REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -o - -x c++ -S  %s  |\
-// RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -emit-llvm -o - -x c++ %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -emit-llvm -o - -x c++ %s  | \
 // RUN: FileCheck -check-prefix=VISIBILITY-IR %s
@@ -70,28 +54,11 @@
 // VISIBILITY-IR:define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
 // VISIBILITY-IR:define hidden void @_Z7prambarv()
 
-// VISIBILITY-ASM: .globl  _Z5foo_hPi[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z5foo_hPi,hidden
-// VISIBILITY-ASM: .globl  _Z3barv[DS],protected
-// VISIBILITY-ASM: .globl  ._Z3barv,protected
-// VISIBILITY-ASM: .weak   _ZNK9TestClass5valueEv[DS],hidden
-// VISIBILITY-ASM: .weak   ._ZNK9TestClass5valueEv,hidden
-// VISIBILITY-ASM: .weak   _ZN5basicIiE7getdataEv[DS],protected
-// VISIBILITY-ASM: .weak   ._ZN5basicIiE7getdataEv,protected
-// VISIBILITY-ASM: .globl  _Z7prambarv[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z7prambarv,hidden
-// VISIBILITY-ASM: .globl  b,protected
-// VISIBILITY-ASM: .globl  pramb,hidden
-
-// IGNOREVISIBILITY-ASM: .globl  _Z5foo_hPi[DS]
-// IGNOREVISIBILITY-ASM: .globl  ._Z5foo_hPi
-// IGNOREVISIBILITY-ASM: .globl  _Z3barv[DS]
-// IGNOREVISIBILITY-ASM: .globl  ._Z3barv
-// IGNOREVISIBILITY-ASM: .weak   _ZNK9TestClass5valueEv[DS]
-// IGNOREVISIBILITY-ASM: .weak   ._ZNK9TestClass5valueEv
-// IGNOREVISIBILITY-ASM: .weak   

[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 301020.
DiggerLin marked an inline comment as done.

Repository:
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Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/LangOptions.def
  clang/lib/AST/Decl.cpp
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/CodeGen/aix-visibility-inlines-hidden.cpp

Index: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
@@ -0,0 +1,39 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large \
+// RUN:-fvisibility-inlines-hidden -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden \
+// RUN:-fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -mignore-xcoff-visibility -emit-llvm \
+// RUN:-fvisibility-inlines-hidden -fvisibility default -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
+int x = 66;
+__attribute__((__noinline__)) inline void f() {
+  x = 55;
+}
+
+#pragma GCC visibility push(hidden)
+__attribute__((__noinline__)) inline void foo() {
+  x = 55;
+}
+#pragma GCC visibility pop
+
+int bar() {
+  f();
+  foo();
+  return x;
+}
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z1fv()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z1fv()
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z3foov()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z3foov()
Index: clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
===
--- clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
+++ clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
@@ -1,24 +1,10 @@
 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -o - -x c++ -S  %s  |\
-// RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
 
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -emit-llvm -o - -x c++ %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -emit-llvm -o - -x c++ %s  | \
 // RUN: FileCheck -check-prefix=VISIBILITY-IR %s
@@ -70,28 +56,11 @@
 // VISIBILITY-IR:define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
 // VISIBILITY-IR:define hidden void @_Z7prambarv()
 
-// VISIBILITY-ASM: .globl  _Z5foo_hPi[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z5foo_hPi,hidden
-// VISIBILITY-ASM: .globl  _Z3barv[DS],protected
-// VISIBILITY-ASM: .globl  ._Z3barv,protected
-// VISIBILITY-ASM: .weak   _ZNK9TestClass5valueEv[DS],hidden
-// VISIBILITY-ASM: .weak   ._ZNK9TestClass5valueEv,hidden
-// VISIBILITY-ASM: .weak   _ZN5basicIiE7getdataEv[DS],protected
-// VISIBILITY-ASM: .weak   ._ZN5basicIiE7getdataEv,protected
-// VISIBILITY-ASM: .globl  _Z7prambarv[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z7prambarv,hidden
-// VISIBILITY-ASM: .globl  b,protected
-// VISIBILITY-ASM: .globl  pramb,hidden
-
-// IGNOREVISIBILITY-ASM: .globl  _Z5foo_hPi[DS]
-// IGNOREVISIBILITY-ASM: .globl  ._Z5foo_hPi
-// IGNOREVISIBILITY-ASM: .globl  _Z3barv[DS]
-// IGNOREVISIBILITY-ASM: .globl  ._Z3barv
-// IGNOREVISIBILITY-ASM: .weak   _ZNK9TestClass5valueEv[DS]
-// IGNOREVISIBILITY-ASM: .weak   ._ZNK9TestClass5valueEv
-// IGNOREVISIBILITY-ASM: .weak   

[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

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DiggerLin marked an inline comment as done.
DiggerLin added inline comments.



Comment at: clang/lib/CodeGen/BackendUtil.cpp:520
   Options.DataSections = CodeGenOpts.DataSections;
-  Options.IgnoreXCOFFVisibility = CodeGenOpts.IgnoreXCOFFVisibility;
   Options.UniqueSectionNames = CodeGenOpts.UniqueSectionNames;

sfertile wrote:
> DiggerLin wrote:
> > sfertile wrote:
> > > DiggerLin wrote:
> > > > jasonliu wrote:
> > > > > DiggerLin wrote:
> > > > > > DiggerLin wrote:
> > > > > > > jasonliu wrote:
> > > > > > > > DiggerLin wrote:
> > > > > > > > > jasonliu wrote:
> > > > > > > > > > DiggerLin wrote:
> > > > > > > > > > > jasonliu wrote:
> > > > > > > > > > > > Instead of just removing this line, should this get 
> > > > > > > > > > > > replaced with the new LangOpts option?
> > > > > > > > > > > I do not think we need a CodeGenOp of 
> > > > > > > > > > > ignore-xcoff-visibility in clang, we only need the 
> > > > > > > > > > > LangOpt of the ignore-xcoff-visilbity to control whether 
> > > > > > > > > > > we will  generate the visibility in the IR,  when the 
> > > > > > > > > > > LangOpt of ignore-xcoff-visibility do not generate the 
> > > > > > > > > > > visibility attribute of GV in the IR. it do not need 
> > > > > > > > > > > CodeGenOp of ignore-xcoff-visibility any more for the 
> > > > > > > > > > > clang .
> > > > > > > > > > > 
> > > > > > > > > > > we have still CodeGen ignore-xcoff-visibility op in  llc.
> > > > > > > > > > We removed the visibility from IR level with this patch. 
> > > > > > > > > > But there is also visibility settings coming from CodeGen 
> > > > > > > > > > part of clang, which needs to get ignore when we are doing 
> > > > > > > > > > the code gen in llc. So I think you still need to set the 
> > > > > > > > > > options correct for llc.
> > > > > > > > > yes we have the set the options correct for llc in the code.
> > > > > > > > > 
> > > > > > > > > in the source file llvm/lib/CodeGen/CommandFlags.cpp, we have 
> > > > > > > > > (in the patch https://reviews.llvm.org/D87451 add new option 
> > > > > > > > > -mignore-xcoff-visibility) , the function
> > > > > > > > > TargetOptions codegen::InitTargetOptionsFromCodeGenFlags() {
> > > > > > > > > 
> > > > > > > > > Options.IgnoreXCOFFVisibility = getIgnoreXCOFFVisibility(); 
> > > > > > > > > ...}
> > > > > > > > > 
> > > > > > > > What I'm saying is... 
> > > > > > > > I think we need a line like this:
> > > > > > > > `Options.IgnoreXCOFFVisibility = 
> > > > > > > > LangOpts.IgnoreXCOFFVisibility;`
> > > > > > > > so that when you invoke clang, backend would get the correct 
> > > > > > > > setting as well. 
> > > > > > > I do not think so, from the clang FE, we do not generated the 
> > > > > > > visibility in the IR. so there is no need these line.
> > > > > > or we can say that because we do not set the hidden visibility into 
> > > > > > the GlobalValue , so we do not need the 
> > > > > > Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;
> > > > > I think I mentioned this before, we could have extra visibility 
> > > > > settings in clang/lib/CodeGen that's not depending on the existing 
> > > > > visibility setting in the IR. (You could search for `setVisibility` 
> > > > > there.) That was the reason we did it in llc first. 
> > > > I will add Options.IgnoreXCOFFVisibility = 
> > > > LangOpts.IgnoreXCOFFVisibility;  here.
> > > > I think I mentioned this before, we could have extra visibility 
> > > > settings in clang/lib/CodeGen that's not depending on the existing 
> > > > visibility setting in the IR. (You could search for setVisibility 
> > > > there.) That was the reason we did it in llc first.
> > > 
> > >  A lot of these are in places we wouldn't encounter with AIX, like for 
> > > Objective-C code gen. But are others like [[ 
> > > https://github.com/llvm/llvm-project/blob/b03ea054db1bcf9452b3a70e21d3372b6e58759a/clang/lib/CodeGen/ItaniumCXXABI.cpp#L2507
> > >  | this]]  an issue? Should they be addressed in this patch?
> > after I added the Options.IgnoreXCOFFVisibility = 
> > LangOpts.IgnoreXCOFFVisibility , even there is  
> > GV->setVisibility(llvm::GlobalValue::HiddenVisibility);  it do not effect 
> > our output.
> > 
> > there is following code in the function void 
> > PPCAIXAsmPrinter::emitLinkage(const GlobalValue *GV,
> >MCSymbol *GVSym) const
> > {
> >  . 
> >   if (!TM.getIgnoreXCOFFVisibility()) {
> > switch (GV->getVisibility()) {
> > 
> > // TODO: "exported" and "internal" Visibility needs to go here.
> > case GlobalValue::DefaultVisibility:
> >   break;
> > case GlobalValue::HiddenVisibility:
> >   VisibilityAttr = MAI->getHiddenVisibilityAttr();
> >   break;
> > case GlobalValue::ProtectedVisibility:
> >   VisibilityAttr = MAI->getProtectedVisibilityAttr();
> >   break;
> > }
> >   }
> > 
> > ...
> > }
> > it do not effect our output.
> It can if we set 

[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 300972.
DiggerLin marked 3 inline comments as done.
DiggerLin added a comment.

address comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89986/new/

https://reviews.llvm.org/D89986

Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/LangOptions.def
  clang/lib/AST/Decl.cpp
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/CodeGen/aix-visibility-inlines-hidden.cpp

Index: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
@@ -0,0 +1,39 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden \
+   -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden \
+// RUN:-fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -mignore-xcoff-visibility -emit-llvm \
+// RUN:-fvisibility-inlines-hidden -fvisibility default -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
+int x = 66;
+__attribute__((__noinline__)) inline void f() {
+  x = 55;
+}
+
+#pragma GCC visibility push(hidden)
+__attribute__((__noinline__)) inline void foo() {
+  x = 55;
+}
+#pragma GCC visibility pop
+
+int bar() {
+  f();
+  foo();
+  return x;
+}
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z1fv()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z1fv()
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z3foov()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z3foov()
Index: clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
===
--- clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
+++ clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
@@ -1,24 +1,10 @@
 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -o - -x c++ -S  %s  |\
-// RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
 
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -emit-llvm -o - -x c++ %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -emit-llvm -o - -x c++ %s  | \
 // RUN: FileCheck -check-prefix=VISIBILITY-IR %s
@@ -70,28 +56,11 @@
 // VISIBILITY-IR:define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
 // VISIBILITY-IR:define hidden void @_Z7prambarv()
 
-// VISIBILITY-ASM: .globl  _Z5foo_hPi[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z5foo_hPi,hidden
-// VISIBILITY-ASM: .globl  _Z3barv[DS],protected
-// VISIBILITY-ASM: .globl  ._Z3barv,protected
-// VISIBILITY-ASM: .weak   _ZNK9TestClass5valueEv[DS],hidden
-// VISIBILITY-ASM: .weak   ._ZNK9TestClass5valueEv,hidden
-// VISIBILITY-ASM: .weak   _ZN5basicIiE7getdataEv[DS],protected
-// VISIBILITY-ASM: .weak   ._ZN5basicIiE7getdataEv,protected
-// VISIBILITY-ASM: .globl  _Z7prambarv[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z7prambarv,hidden
-// VISIBILITY-ASM: .globl  b,protected
-// VISIBILITY-ASM: .globl  pramb,hidden
-
-// IGNOREVISIBILITY-ASM: .globl  _Z5foo_hPi[DS]
-// IGNOREVISIBILITY-ASM: .globl  ._Z5foo_hPi
-// IGNOREVISIBILITY-ASM: .globl  _Z3barv[DS]
-// IGNOREVISIBILITY-ASM: .globl  ._Z3barv
-// IGNOREVISIBILITY-ASM: .weak   _ZNK9TestClass5valueEv[DS]
-// IGNOREVISIBILITY-ASM: .weak   

[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

[Digger via Phabricator via cfe-commits]

DiggerLin marked 9 inline comments as done.
DiggerLin added inline comments.



Comment at: clang/lib/CodeGen/BackendUtil.cpp:520
   Options.DataSections = CodeGenOpts.DataSections;
-  Options.IgnoreXCOFFVisibility = CodeGenOpts.IgnoreXCOFFVisibility;
   Options.UniqueSectionNames = CodeGenOpts.UniqueSectionNames;

sfertile wrote:
> DiggerLin wrote:
> > jasonliu wrote:
> > > DiggerLin wrote:
> > > > DiggerLin wrote:
> > > > > jasonliu wrote:
> > > > > > DiggerLin wrote:
> > > > > > > jasonliu wrote:
> > > > > > > > DiggerLin wrote:
> > > > > > > > > jasonliu wrote:
> > > > > > > > > > Instead of just removing this line, should this get 
> > > > > > > > > > replaced with the new LangOpts option?
> > > > > > > > > I do not think we need a CodeGenOp of ignore-xcoff-visibility 
> > > > > > > > > in clang, we only need the LangOpt of the 
> > > > > > > > > ignore-xcoff-visilbity to control whether we will  generate 
> > > > > > > > > the visibility in the IR,  when the LangOpt of 
> > > > > > > > > ignore-xcoff-visibility do not generate the visibility 
> > > > > > > > > attribute of GV in the IR. it do not need CodeGenOp of 
> > > > > > > > > ignore-xcoff-visibility any more for the clang .
> > > > > > > > > 
> > > > > > > > > we have still CodeGen ignore-xcoff-visibility op in  llc.
> > > > > > > > We removed the visibility from IR level with this patch. But 
> > > > > > > > there is also visibility settings coming from CodeGen part of 
> > > > > > > > clang, which needs to get ignore when we are doing the code gen 
> > > > > > > > in llc. So I think you still need to set the options correct 
> > > > > > > > for llc.
> > > > > > > yes we have the set the options correct for llc in the code.
> > > > > > > 
> > > > > > > in the source file llvm/lib/CodeGen/CommandFlags.cpp, we have (in 
> > > > > > > the patch https://reviews.llvm.org/D87451 add new option 
> > > > > > > -mignore-xcoff-visibility) , the function
> > > > > > > TargetOptions codegen::InitTargetOptionsFromCodeGenFlags() {
> > > > > > > 
> > > > > > > Options.IgnoreXCOFFVisibility = getIgnoreXCOFFVisibility(); 
> > > > > > > ...}
> > > > > > > 
> > > > > > What I'm saying is... 
> > > > > > I think we need a line like this:
> > > > > > `Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;`
> > > > > > so that when you invoke clang, backend would get the correct 
> > > > > > setting as well. 
> > > > > I do not think so, from the clang FE, we do not generated the 
> > > > > visibility in the IR. so there is no need these line.
> > > > or we can say that because we do not set the hidden visibility into the 
> > > > GlobalValue , so we do not need the 
> > > > Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;
> > > I think I mentioned this before, we could have extra visibility settings 
> > > in clang/lib/CodeGen that's not depending on the existing visibility 
> > > setting in the IR. (You could search for `setVisibility` there.) That was 
> > > the reason we did it in llc first. 
> > I will add Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;  
> > here.
> > I think I mentioned this before, we could have extra visibility settings in 
> > clang/lib/CodeGen that's not depending on the existing visibility setting 
> > in the IR. (You could search for setVisibility there.) That was the reason 
> > we did it in llc first.
> 
>  A lot of these are in places we wouldn't encounter with AIX, like for 
> Objective-C code gen. But are others like [[ 
> https://github.com/llvm/llvm-project/blob/b03ea054db1bcf9452b3a70e21d3372b6e58759a/clang/lib/CodeGen/ItaniumCXXABI.cpp#L2507
>  | this]]  an issue? Should they be addressed in this patch?
after I added the Options.IgnoreXCOFFVisibility = 
LangOpts.IgnoreXCOFFVisibility , even there is  
GV->setVisibility(llvm::GlobalValue::HiddenVisibility);  it do not effect our 
output.

there is following code in the function void 
PPCAIXAsmPrinter::emitLinkage(const GlobalValue *GV,
   MCSymbol *GVSym) const
{
 . 
  if (!TM.getIgnoreXCOFFVisibility()) {
switch (GV->getVisibility()) {

// TODO: "exported" and "internal" Visibility needs to go here.
case GlobalValue::DefaultVisibility:
  break;
case GlobalValue::HiddenVisibility:
  VisibilityAttr = MAI->getHiddenVisibilityAttr();
  break;
case GlobalValue::ProtectedVisibility:
  VisibilityAttr = MAI->getProtectedVisibilityAttr();
  break;
}
  }

...
}



Comment at: clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp:1
 // REQUIRES: powerpc-registered-target
 

sfertile wrote:
> You shouldn't need this requires anymore.
please  see the 
https://reviews.llvm.org/rGa15bd0bfc20c2b2955c59450a67b6e8efe89c708



Comment at: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp:1
+// REQUIRES: powerpc-registered-target
+

jasonliu wrote:
> sfertile wrote:
> > 

[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 300766.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89986/new/

https://reviews.llvm.org/D89986

Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/LangOptions.def
  clang/lib/AST/Decl.cpp
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/CodeGen/aix-visibility-inlines-hidden.cpp

Index: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
@@ -0,0 +1,43 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden \
+// RUN:-fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,VISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -mignore-xcoff-visibility -fvisibility-inlines-hidden \ 
+// RUN:-fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+int x = 66;
+__attribute__((__noinline__)) inline void f() {
+  x = 55;
+}
+
+#pragma GCC visibility push(hidden)
+__attribute__((__noinline__)) inline void foo() {
+  x = 55;
+}
+#pragma GCC visibility pop
+
+int bar() {
+  f();
+  foo();
+  return x;
+}
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z1fv()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z1fv()
+// COMMON-IR-NEXT:  entry:
+// COMMON-IR-NEXT:store i32 55, i32* @x, align 4
+// COMMON-IR-NEXT:ret void
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z3foov()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z3foov()
+// COMMON-IR-NEXT:  entry:
+// COMMON-IR-NEXT:store i32 55, i32* @x, align 4
Index: clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
===
--- clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
+++ clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
@@ -1,24 +1,10 @@
 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -o - -x c++ -S  %s  |\
-// RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
 
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -emit-llvm -o - -x c++ %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -emit-llvm -o - -x c++ %s  | \
 // RUN: FileCheck -check-prefix=VISIBILITY-IR %s
@@ -70,28 +56,12 @@
 // VISIBILITY-IR:define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
 // VISIBILITY-IR:define hidden void @_Z7prambarv()
 
-// VISIBILITY-ASM: .globl  _Z5foo_hPi[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z5foo_hPi,hidden
-// VISIBILITY-ASM: .globl  _Z3barv[DS],protected
-// VISIBILITY-ASM: .globl  ._Z3barv,protected
-// VISIBILITY-ASM: .weak   _ZNK9TestClass5valueEv[DS],hidden
-// VISIBILITY-ASM: .weak   ._ZNK9TestClass5valueEv,hidden
-// VISIBILITY-ASM: .weak   _ZN5basicIiE7getdataEv[DS],protected
-// VISIBILITY-ASM: .weak   ._ZN5basicIiE7getdataEv,protected
-// VISIBILITY-ASM: .globl  _Z7prambarv[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z7prambarv,hidden
-// VISIBILITY-ASM: .globl  b,protected
-// VISIBILITY-ASM: .globl  pramb,hidden
-
-// IGNOREVISIBILITY-ASM: .globl  _Z5foo_hPi[DS]
-// IGNOREVISIBILITY-ASM: .globl  ._Z5foo_hPi
-// IGNOREVISIBILITY-ASM: .globl  _Z3barv[DS]
-// IGNOREVISIBILITY-ASM: 

[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

[Digger via Phabricator via cfe-commits]

DiggerLin added inline comments.



Comment at: clang/lib/CodeGen/BackendUtil.cpp:520
   Options.DataSections = CodeGenOpts.DataSections;
-  Options.IgnoreXCOFFVisibility = CodeGenOpts.IgnoreXCOFFVisibility;
   Options.UniqueSectionNames = CodeGenOpts.UniqueSectionNames;

jasonliu wrote:
> DiggerLin wrote:
> > DiggerLin wrote:
> > > jasonliu wrote:
> > > > DiggerLin wrote:
> > > > > jasonliu wrote:
> > > > > > DiggerLin wrote:
> > > > > > > jasonliu wrote:
> > > > > > > > Instead of just removing this line, should this get replaced 
> > > > > > > > with the new LangOpts option?
> > > > > > > I do not think we need a CodeGenOp of ignore-xcoff-visibility in 
> > > > > > > clang, we only need the LangOpt of the ignore-xcoff-visilbity to 
> > > > > > > control whether we will  generate the visibility in the IR,  when 
> > > > > > > the LangOpt of ignore-xcoff-visibility do not generate the 
> > > > > > > visibility attribute of GV in the IR. it do not need CodeGenOp of 
> > > > > > > ignore-xcoff-visibility any more for the clang .
> > > > > > > 
> > > > > > > we have still CodeGen ignore-xcoff-visibility op in  llc.
> > > > > > We removed the visibility from IR level with this patch. But there 
> > > > > > is also visibility settings coming from CodeGen part of clang, 
> > > > > > which needs to get ignore when we are doing the code gen in llc. So 
> > > > > > I think you still need to set the options correct for llc.
> > > > > yes we have the set the options correct for llc in the code.
> > > > > 
> > > > > in the source file llvm/lib/CodeGen/CommandFlags.cpp, we have (in the 
> > > > > patch https://reviews.llvm.org/D87451 add new option 
> > > > > -mignore-xcoff-visibility) , the function
> > > > > TargetOptions codegen::InitTargetOptionsFromCodeGenFlags() {
> > > > > 
> > > > > Options.IgnoreXCOFFVisibility = getIgnoreXCOFFVisibility(); 
> > > > > ...}
> > > > > 
> > > > What I'm saying is... 
> > > > I think we need a line like this:
> > > > `Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;`
> > > > so that when you invoke clang, backend would get the correct setting as 
> > > > well. 
> > > I do not think so, from the clang FE, we do not generated the visibility 
> > > in the IR. so there is no need these line.
> > or we can say that because we do not set the hidden visibility into the 
> > GlobalValue , so we do not need the 
> > Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;
> I think I mentioned this before, we could have extra visibility settings in 
> clang/lib/CodeGen that's not depending on the existing visibility setting in 
> the IR. (You could search for `setVisibility` there.) That was the reason we 
> did it in llc first. 
I will add Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;  
here.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D89986/new/

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[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

[Digger via Phabricator via cfe-commits]

DiggerLin marked an inline comment as done.
DiggerLin added inline comments.



Comment at: clang/lib/CodeGen/BackendUtil.cpp:520
   Options.DataSections = CodeGenOpts.DataSections;
-  Options.IgnoreXCOFFVisibility = CodeGenOpts.IgnoreXCOFFVisibility;
   Options.UniqueSectionNames = CodeGenOpts.UniqueSectionNames;

DiggerLin wrote:
> jasonliu wrote:
> > DiggerLin wrote:
> > > jasonliu wrote:
> > > > DiggerLin wrote:
> > > > > jasonliu wrote:
> > > > > > Instead of just removing this line, should this get replaced with 
> > > > > > the new LangOpts option?
> > > > > I do not think we need a CodeGenOp of ignore-xcoff-visibility in 
> > > > > clang, we only need the LangOpt of the ignore-xcoff-visilbity to 
> > > > > control whether we will  generate the visibility in the IR,  when the 
> > > > > LangOpt of ignore-xcoff-visibility do not generate the visibility 
> > > > > attribute of GV in the IR. it do not need CodeGenOp of 
> > > > > ignore-xcoff-visibility any more for the clang .
> > > > > 
> > > > > we have still CodeGen ignore-xcoff-visibility op in  llc.
> > > > We removed the visibility from IR level with this patch. But there is 
> > > > also visibility settings coming from CodeGen part of clang, which needs 
> > > > to get ignore when we are doing the code gen in llc. So I think you 
> > > > still need to set the options correct for llc.
> > > yes we have the set the options correct for llc in the code.
> > > 
> > > in the source file llvm/lib/CodeGen/CommandFlags.cpp, we have (in the 
> > > patch https://reviews.llvm.org/D87451 add new option 
> > > -mignore-xcoff-visibility) , the function
> > > TargetOptions codegen::InitTargetOptionsFromCodeGenFlags() {
> > > 
> > > Options.IgnoreXCOFFVisibility = getIgnoreXCOFFVisibility(); 
> > > ...}
> > > 
> > What I'm saying is... 
> > I think we need a line like this:
> > `Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;`
> > so that when you invoke clang, backend would get the correct setting as 
> > well. 
> I do not think so, from the clang FE, we do not generated the visibility in 
> the IR. so there is no need these line.
or we can say that because we do not set the hidden visibility into the 
GlobalValue , so we do not need the 
Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;


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[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

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DiggerLin added inline comments.



Comment at: clang/lib/CodeGen/BackendUtil.cpp:520
   Options.DataSections = CodeGenOpts.DataSections;
-  Options.IgnoreXCOFFVisibility = CodeGenOpts.IgnoreXCOFFVisibility;
   Options.UniqueSectionNames = CodeGenOpts.UniqueSectionNames;

jasonliu wrote:
> DiggerLin wrote:
> > jasonliu wrote:
> > > DiggerLin wrote:
> > > > jasonliu wrote:
> > > > > Instead of just removing this line, should this get replaced with the 
> > > > > new LangOpts option?
> > > > I do not think we need a CodeGenOp of ignore-xcoff-visibility in clang, 
> > > > we only need the LangOpt of the ignore-xcoff-visilbity to control 
> > > > whether we will  generate the visibility in the IR,  when the LangOpt 
> > > > of ignore-xcoff-visibility do not generate the visibility attribute of 
> > > > GV in the IR. it do not need CodeGenOp of ignore-xcoff-visibility any 
> > > > more for the clang .
> > > > 
> > > > we have still CodeGen ignore-xcoff-visibility op in  llc.
> > > We removed the visibility from IR level with this patch. But there is 
> > > also visibility settings coming from CodeGen part of clang, which needs 
> > > to get ignore when we are doing the code gen in llc. So I think you still 
> > > need to set the options correct for llc.
> > yes we have the set the options correct for llc in the code.
> > 
> > in the source file llvm/lib/CodeGen/CommandFlags.cpp, we have (in the patch 
> > https://reviews.llvm.org/D87451 add new option -mignore-xcoff-visibility) , 
> > the function
> > TargetOptions codegen::InitTargetOptionsFromCodeGenFlags() {
> > 
> > Options.IgnoreXCOFFVisibility = getIgnoreXCOFFVisibility(); 
> > ...}
> > 
> What I'm saying is... 
> I think we need a line like this:
> `Options.IgnoreXCOFFVisibility = LangOpts.IgnoreXCOFFVisibility;`
> so that when you invoke clang, backend would get the correct setting as well. 
I do not think so, from the clang FE, we do not generated the visibility in the 
IR. so there is no need these line.


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[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

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DiggerLin added inline comments.



Comment at: clang/lib/CodeGen/BackendUtil.cpp:520
   Options.DataSections = CodeGenOpts.DataSections;
-  Options.IgnoreXCOFFVisibility = CodeGenOpts.IgnoreXCOFFVisibility;
   Options.UniqueSectionNames = CodeGenOpts.UniqueSectionNames;

jasonliu wrote:
> DiggerLin wrote:
> > jasonliu wrote:
> > > Instead of just removing this line, should this get replaced with the new 
> > > LangOpts option?
> > I do not think we need a CodeGenOp of ignore-xcoff-visibility in clang, we 
> > only need the LangOpt of the ignore-xcoff-visilbity to control whether we 
> > will  generate the visibility in the IR,  when the LangOpt of 
> > ignore-xcoff-visibility do not generate the visibility attribute of GV in 
> > the IR. it do not need CodeGenOp of ignore-xcoff-visibility any more for 
> > the clang .
> > 
> > we have still CodeGen ignore-xcoff-visibility op in  llc.
> We removed the visibility from IR level with this patch. But there is also 
> visibility settings coming from CodeGen part of clang, which needs to get 
> ignore when we are doing the code gen in llc. So I think you still need to 
> set the options correct for llc.
yes we have the set the options correct for llc in the code.

in the source file llvm/lib/CodeGen/CommandFlags.cpp, we have (in the patch 
https://reviews.llvm.org/D87451 add new option -mignore-xcoff-visibility) , the 
function
TargetOptions codegen::InitTargetOptionsFromCodeGenFlags() {

Options.IgnoreXCOFFVisibility = getIgnoreXCOFFVisibility(); 
...}



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[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

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DiggerLin added inline comments.



Comment at: clang/lib/CodeGen/BackendUtil.cpp:520
   Options.DataSections = CodeGenOpts.DataSections;
-  Options.IgnoreXCOFFVisibility = CodeGenOpts.IgnoreXCOFFVisibility;
   Options.UniqueSectionNames = CodeGenOpts.UniqueSectionNames;

jasonliu wrote:
> Instead of just removing this line, should this get replaced with the new 
> LangOpts option?
I do not think we need a CodeGenOp of ignore-xcoff-visibility in clang, we only 
need the LangOpt of the ignore-xcoff-visilbity to control whether we will  
generate the visibility in the IR,  when the LangOpt of ignore-xcoff-visibility 
do not generate the visibility attribute of GV in the IR. it do not need 
CodeGenOp of ignore-xcoff-visibility any more for the clang .

we have still CodeGen ignore-xcoff-visibility op in  llc.


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[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

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DiggerLin updated this revision to Diff 300421.
DiggerLin added a comment.

delete asm test case from clang/test


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Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/LangOptions.def
  clang/lib/AST/Decl.cpp
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/CodeGen/aix-visibility-inlines-hidden.cpp

Index: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
@@ -0,0 +1,43 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden \
+// RUN:-fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,VISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -mignore-xcoff-visibility -fvisibility-inlines-hidden \ 
+// RUN:-fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+int x = 66;
+__attribute__((__noinline__)) inline void f() {
+  x = 55;
+}
+
+#pragma GCC visibility push(hidden)
+__attribute__((__noinline__)) inline void foo() {
+  x = 55;
+}
+#pragma GCC visibility pop
+
+int bar() {
+  f();
+  foo();
+  return x;
+}
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z1fv()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z1fv()
+// COMMON-IR-NEXT:  entry:
+// COMMON-IR-NEXT:store i32 55, i32* @x, align 4
+// COMMON-IR-NEXT:ret void
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z3foov()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z3foov()
+// COMMON-IR-NEXT:  entry:
+// COMMON-IR-NEXT:store i32 55, i32* @x, align 4
Index: clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
===
--- clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
+++ clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
@@ -1,24 +1,10 @@
 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -o - -x c++ -S  %s  |\
-// RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
 
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=IGNOREVISIBILITY-ASM %s
-
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -emit-llvm -o - -x c++ %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -emit-llvm -o - -x c++ %s  | \
 // RUN: FileCheck -check-prefix=VISIBILITY-IR %s
@@ -70,28 +56,12 @@
 // VISIBILITY-IR:define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
 // VISIBILITY-IR:define hidden void @_Z7prambarv()
 
-// VISIBILITY-ASM: .globl  _Z5foo_hPi[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z5foo_hPi,hidden
-// VISIBILITY-ASM: .globl  _Z3barv[DS],protected
-// VISIBILITY-ASM: .globl  ._Z3barv,protected
-// VISIBILITY-ASM: .weak   _ZNK9TestClass5valueEv[DS],hidden
-// VISIBILITY-ASM: .weak   ._ZNK9TestClass5valueEv,hidden
-// VISIBILITY-ASM: .weak   _ZN5basicIiE7getdataEv[DS],protected
-// VISIBILITY-ASM: .weak   ._ZN5basicIiE7getdataEv,protected
-// VISIBILITY-ASM: .globl  _Z7prambarv[DS],hidden
-// VISIBILITY-ASM: .globl  ._Z7prambarv,hidden
-// VISIBILITY-ASM: .globl  b,protected
-// VISIBILITY-ASM: .globl  pramb,hidden
-
-// IGNOREVISIBILITY-ASM: .globl  _Z5foo_hPi[DS]
-// IGNOREVISIBILITY-ASM: .globl  ._Z5foo_hPi
-// 

[PATCH] D89986: [AIX]ignore the option -fvisibility-inlines-hidden when there is no option -fvisibility=*

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DiggerLin updated this revision to Diff 300383.
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address comment


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Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/LangOptions.def
  clang/lib/AST/Decl.cpp
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/CodeGen/aix-visibility-inlines-hidden.cpp

Index: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
@@ -0,0 +1,68 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden \
+// RUN:-fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,VISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -mignore-xcoff-visibility -fvisibility-inlines-hidden \ 
+// RUN:-fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -o - -x c++ -S  %s  |\
+// RUN:   FileCheck --check-prefixes=NOP-ASM,COMMON-ASM %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden -o - -x c++ -S %s  | \
+// RUN: FileCheck --check-prefixes=NOP-ASM,COMMON-ASM %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden \
+// RUN:-fvisibility default -o - -x c++ -S %s  | \
+// RUN: FileCheck --check-prefix=COMMON-ASM %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -mignore-xcoff-visibility \
+// RUN:-fvisibility-inlines-hidden  -fvisibility default -o - -x c++ -S %s  | \
+// RUN: FileCheck --check-prefixes=NOP-ASM,COMMON-ASM %s
+int x = 66;
+__attribute__((__noinline__)) inline void f() {
+  x = 55;
+}
+
+#pragma GCC visibility push(hidden)
+__attribute__((__noinline__)) inline void foo() {
+  x = 55;
+}
+#pragma GCC visibility pop
+
+int bar() {
+  f();
+  foo();
+  return x;
+}
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z1fv()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z1fv()
+// COMMON-IR-NEXT:  entry:
+// COMMON-IR-NEXT:store i32 55, i32* @x, align 4
+// COMMON-IR-NEXT:ret void
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z3foov()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z3foov()
+// COMMON-IR-NEXT:  entry:
+// COMMON-IR-NEXT:store i32 55, i32* @x, align 4
+
+// COMMON-ASM: mflr 0
+// COMMON-ASM-NEXT:stw 0, 8(1)
+// COMMON-ASM-NEXT:stwu 1, -64(1)
+// COMMON-ASM-NEXT:bl ._Z1fv
+// NOP-ASM-NEXT:   nop
+// COMMON-ASM-NEXT:bl ._Z3foov
+// NOP-ASM-NEXT:   nop
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden  -fvisibility default -o - -x c++ -S %s  | \
+// RUN: FileCheck --check-prefix=CHECK %s
+/// CHECK-NOT: nop
Index: clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
===
--- clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
+++ clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
@@ -17,8 +17,11 @@
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -o - -x c++ -S %s  | \
 // RUN: FileCheck -check-prefix=VISIBILITY-ASM %s
 
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
+
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -mignore-xcoff-visibility -fvisibility default -emit-llvm -o - -x c++ %s  | \
-// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+// RUN: FileCheck -check-prefix=NOVISIBILITY-IR %s
 
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -fvisibility default -emit-llvm -o - -x c++ %s  | \
 // RUN: FileCheck -check-prefix=VISIBILITY-IR %s
@@ -70,6 +73,15 @@
 // VISIBILITY-IR:define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
 // VISIBILITY-IR:define hidden void @_Z7prambarv()
 
+// NOVISIBILITY-IR:@b = global i32 0
+// NOVISIBILITY-IR:@pramb = global i32 0
+// NOVISIBILITY-IR:define void @_Z5foo_hPi(i32* %p)
+// NOVISIBILITY-IR:declare void @_Z12zoo_extern_hv()
+// NOVISIBILITY-IR:define void @_Z3barv()
+// NOVISIBILITY-IR:define linkonce_odr i32 

[PATCH] D89986: [AIX]ignore the option -fvisibility-inlines-hidden when there is no option -fvisibility=*

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DiggerLin added inline comments.



Comment at: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp:30-34
+// COMMON-ASM: mflr 0
+// COMMON-ASM-NEXT:stw 0, 8(1)
+// COMMON-ASM-NEXT:stwu 1, -64(1)
+// COMMON-ASM-NEXT:bl ._Z1fv
+// NOP-ASM-NEXT:   nop

nemanjai wrote:
> rsmith wrote:
> > Generally we strongly prefer for frontend tests to test only the frontend; 
> > in this case, that means testing only the IR that Clang is producing and 
> > not the assembly that comes out of LLVM for that IR. This should also 
> > remove the need to require PPC as a registered target.
> +1
> The asm test can go into `llvm/test/CodeGen/PowerPC`.
If I put the ASM test as separate test case in the llvm/test/CodeGen/PowerPC 
.it will have error as :

ine 1: %clang_cc1: command not found


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[PATCH] D89986: [AIX]ignore the option -fvisibility-inlines-hidden when there is no option -fvisibility=*

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in AIX OS, we will ignore the option -fvisibility-inlines-hidden when there is 
no option -fvisibility=*


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Files:
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-visibility-inlines-hidden.cpp


Index: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -o - -x c++ -S  
%s  |\
+// RUN:   FileCheck --check-prefixes=NOP-ASM,COMMON-ASM %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large 
-fvisibility-inlines-hidden -o - -x c++ -S %s  | \
+// RUN: FileCheck --check-prefixes=NOP-ASM,COMMON-ASM %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large 
-fvisibility-inlines-hidden  -fvisibility default -o - -x c++ -S %s  | \
+// RUN: FileCheck --check-prefix=COMMON-ASM %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -emit-llvm -o - 
-x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large 
-fvisibility-inlines-hidden -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large 
-fvisibility-inlines-hidden -fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,VISIBILITY-IR %s
+
+int x = 66;
+__attribute__((__noinline__)) inline void f() {
+  x = 55;
+}
+int bar() {
+  f();
+  return x;
+}
+
+// COMMON-ASM: mflr 0
+// COMMON-ASM-NEXT:stw 0, 8(1)
+// COMMON-ASM-NEXT:stwu 1, -64(1)
+// COMMON-ASM-NEXT:bl ._Z1fv
+// NOP-ASM-NEXT:   nop
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z1fv()
+// NOVISIBILITY-IR:   define linkonce_odr void @_Z1fv()
+// COMMON-IR-NEXT:  entry:
+// COMMON-IR-NEXT:store i32 55, i32* @x, align 4
+// COMMON-IR-NEXT:ret void
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large 
-fvisibility-inlines-hidden  -fvisibility default -o - -x c++ -S %s  | \
+// RUN: FileCheck --check-prefix=CHECK %s
+/// CHECK-NOT: nop
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -2779,8 +2779,12 @@
 Opts.setTypeVisibilityMode(Opts.getValueVisibilityMode());
   }
 
-  if (Args.hasArg(OPT_fvisibility_inlines_hidden))
-Opts.InlineVisibilityHidden = 1;
+  if (Args.hasArg(OPT_fvisibility_inlines_hidden)) {
+if (T.isOSAIX() && !Args.hasArg(OPT_fvisibility))
+  Opts.InlineVisibilityHidden = 0;
+else
+  Opts.InlineVisibilityHidden = 1;
+  }
 
   if (Args.hasArg(OPT_fvisibility_inlines_hidden_static_local_var))
 Opts.VisibilityInlinesHiddenStaticLocalVar = 1;


Index: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-visibility-inlines-hidden.cpp
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -o - -x c++ -S  %s  |\
+// RUN:   FileCheck --check-prefixes=NOP-ASM,COMMON-ASM %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden -o - -x c++ -S %s  | \
+// RUN: FileCheck --check-prefixes=NOP-ASM,COMMON-ASM %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden  -fvisibility default -o - -x c++ -S %s  | \
+// RUN: FileCheck --check-prefix=COMMON-ASM %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,NOVISIBILITY-IR %s
+
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -mcmodel=large -fvisibility-inlines-hidden -fvisibility default -emit-llvm -o - -x c++ %s  | \
+// RUN: FileCheck -check-prefixes=COMMON-IR,VISIBILITY-IR %s
+
+int x = 66;
+__attribute__((__noinline__)) inline void f() {
+  x = 55;
+}
+int bar() {
+  f();
+  return x;
+}
+
+// COMMON-ASM: mflr 0
+// COMMON-ASM-NEXT:stw 0, 8(1)
+// COMMON-ASM-NEXT:stwu 1, -64(1)
+// COMMON-ASM-NEXT:bl ._Z1fv
+// NOP-ASM-NEXT:   nop
+
+// VISIBILITY-IR: define linkonce_odr hidden void @_Z1fv()
+// NOVISIBILITY-IR:   define linkonce_odr 

[PATCH] D88737: [AIX] Turn -fdata-sections on by default in Clang

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LGTM


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[PATCH] D87451: add new option -mignore-xcoff-visibility

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This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
DiggerLin marked an inline comment as done.
Closed by commit rG92bca1284308: [AIX] add new option -mignore-xcoff-visibility 
(authored by DiggerLin).

Changed prior to commit:
  https://reviews.llvm.org/D87451?vs=296267=296953#toc

Repository:
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/Driver/ignore-xcoff-visibility.cpp
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetMachine.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.ll

Index: llvm/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.ll
@@ -0,0 +1,48 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec  < %s | \
+; RUN:   FileCheck --check-prefix=VISIBILITY-ASM %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -ignore-xcoff-visibility < %s | \
+; RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | \
+; RUN:   FileCheck --check-prefix=VISIBILITY-ASM %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -ignore-xcoff-visibility < %s | \
+; RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
+
+@foo_p = global void ()* @zoo_extern_h, align 4
+@b = protected global i32 0, align 4
+
+define hidden void @foo_h(i32* %p) {
+entry:
+  %p.addr = alloca i32*, align 4
+  store i32* %p, i32** %p.addr, align 4
+  %0 = load i32*, i32** %p.addr, align 4
+  %1 = load i32, i32* %0, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* %0, align 4
+  ret void
+}
+
+declare hidden void @zoo_extern_h()
+
+define protected void @bar() {
+entry:
+  call void @foo_h(i32* @b)
+  %0 = load void ()*, void ()** @foo_p, align 4
+  call void %0()
+  ret void
+}
+
+; VISIBILITY-ASM: .globl  foo_h[DS],hidden
+; VISIBILITY-ASM: .globl  .foo_h,hidden
+; VISIBILITY-ASM: .globl  bar[DS],protected
+; VISIBILITY-ASM: .globl  .bar,protected
+; VISIBILITY-ASM: .globl  b,protected
+
+; IGNOREVISIBILITY-ASM: .globl  foo_h[DS]
+; IGNOREVISIBILITY-ASM: .globl  .foo_h
+; IGNOREVISIBILITY-ASM: .globl  bar[DS]
+; IGNOREVISIBILITY-ASM: .globl  .bar
+; IGNOREVISIBILITY-ASM: .globl  b
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1702,17 +1702,19 @@
   assert(LinkageAttr != MCSA_Invalid && "LinkageAttr should not MCSA_Invalid.");
 
   MCSymbolAttr VisibilityAttr = MCSA_Invalid;
-  switch (GV->getVisibility()) {
+  if (!TM.getIgnoreXCOFFVisibility()) {
+switch (GV->getVisibility()) {
 
-  // TODO: "exported" and "internal" Visibility needs to go here.
-  case GlobalValue::DefaultVisibility:
-break;
-  case GlobalValue::HiddenVisibility:
-VisibilityAttr = MAI->getHiddenVisibilityAttr();
-break;
-  case GlobalValue::ProtectedVisibility:
-VisibilityAttr = MAI->getProtectedVisibilityAttr();
-break;
+// TODO: "exported" and "internal" Visibility needs to go here.
+case GlobalValue::DefaultVisibility:
+  break;
+case GlobalValue::HiddenVisibility:
+  VisibilityAttr = MAI->getHiddenVisibilityAttr();
+  break;
+case GlobalValue::ProtectedVisibility:
+  VisibilityAttr = MAI->getProtectedVisibilityAttr();
+  break;
+}
   }
 
   OutStreamer->emitXCOFFSymbolLinkageWithVisibility(GVSym, LinkageAttr,
Index: llvm/lib/CodeGen/CommandFlags.cpp
===
--- llvm/lib/CodeGen/CommandFlags.cpp
+++ llvm/lib/CodeGen/CommandFlags.cpp
@@ -74,6 +74,7 @@
 CGOPT(bool, RelaxELFRelocations)
 CGOPT_EXP(bool, DataSections)
 CGOPT_EXP(bool, FunctionSections)
+CGOPT(bool, IgnoreXCOFFVisibility)
 CGOPT(std::string, BBSections)
 CGOPT(unsigned, TLSSize)
 CGOPT(bool, EmulatedTLS)
@@ -333,6 +334,13 @@
   cl::init(false));
   CGBINDOPT(FunctionSections);
 
+  static cl::opt IgnoreXCOFFVisibility(
+  "ignore-xcoff-visibility",
+  cl::desc("Not emit the visibility attribute for asm in AIX OS or give "
+   "all 

[PATCH] D87451: add new option -mignore-xcoff-visibility

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DiggerLin added inline comments.



Comment at: llvm/include/llvm/Target/TargetOptions.h:126
   FunctionSections(false), DataSections(false),
-  UniqueSectionNames(true), UniqueBasicBlockSectionNames(false),
-  TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0),
-  EmulatedTLS(false), ExplicitEmulatedTLS(false), EnableIPRA(false),
+  IgnoreXCOFFVisibility(false), UniqueSectionNames(true),
+  UniqueBasicBlockSectionNames(false), TrapUnreachable(false),

jasonliu wrote:
> Should the default be true for this option?
> As this is an XCOFF only option, and the default for clang is true, so it 
> would be better for llc to match as well?
we can implement it in another separate patch. 


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[PATCH] D88737: [AIX] Turn -fdata-sections on by default in Clang

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Comment at: clang/test/Driver/aix-data-sections.c:7
+// RUN:   | FileCheck %s
+// CHECK: "-fdata-sections"

may be good to check the whether other OS platform behavior be changed or not? 


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Comment at: clang/include/clang/Basic/CodeGenOptions.def:46
  ///< aliases to base ctors when possible.
-CODEGENOPT(DataSections  , 1, 0) ///< Set when -fdata-sections is enabled.
+CODEGENOPT(DataSections  , 1, 0) ///< Set by default, or when 
-f[no-]data-sections.
+CODEGENOPT(HasExplicitDataSections, 1, 0) ///< Set when -f[no-]data-sections 
is set.

DiggerLin wrote:
> turn on by default , it should be changed to CODEGENOPT(DataSections  , 
> 1, 1) ?
> 
please  ignore above comment.  DataSection is set by default only on AIX OS . 
the comment maybe need to be modified?


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[PATCH] D87451: add new option ignore-xcoff-visibility

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DiggerLin updated this revision to Diff 296267.
DiggerLin marked 3 inline comments as done.
DiggerLin added a comment.

address comment


Repository:
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/Driver/ignore-xcoff-visibility.cpp
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetMachine.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.ll

Index: llvm/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.ll
@@ -0,0 +1,48 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec  < %s | \
+; RUN:   FileCheck --check-prefix=VISIBILITY-ASM %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -ignore-xcoff-visibility < %s | \
+; RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | \
+; RUN:   FileCheck --check-prefix=VISIBILITY-ASM %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -ignore-xcoff-visibility < %s | \
+; RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
+
+@foo_p = global void ()* @zoo_extern_h, align 4
+@b = protected global i32 0, align 4
+
+define hidden void @foo_h(i32* %p) {
+entry:
+  %p.addr = alloca i32*, align 4
+  store i32* %p, i32** %p.addr, align 4
+  %0 = load i32*, i32** %p.addr, align 4
+  %1 = load i32, i32* %0, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* %0, align 4
+  ret void
+}
+
+declare hidden void @zoo_extern_h()
+
+define protected void @bar() {
+entry:
+  call void @foo_h(i32* @b)
+  %0 = load void ()*, void ()** @foo_p, align 4
+  call void %0()
+  ret void
+}
+
+; VISIBILITY-ASM: .globl  foo_h[DS],hidden
+; VISIBILITY-ASM: .globl  .foo_h,hidden
+; VISIBILITY-ASM: .globl  bar[DS],protected
+; VISIBILITY-ASM: .globl  .bar,protected
+; VISIBILITY-ASM: .globl  b,protected
+
+; IGNOREVISIBILITY-ASM: .globl  foo_h[DS]
+; IGNOREVISIBILITY-ASM: .globl  .foo_h
+; IGNOREVISIBILITY-ASM: .globl  bar[DS]
+; IGNOREVISIBILITY-ASM: .globl  .bar
+; IGNOREVISIBILITY-ASM: .globl  b
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1702,17 +1702,19 @@
   assert(LinkageAttr != MCSA_Invalid && "LinkageAttr should not MCSA_Invalid.");
 
   MCSymbolAttr VisibilityAttr = MCSA_Invalid;
-  switch (GV->getVisibility()) {
+  if (!TM.getIgnoreXCOFFVisibility()) {
+switch (GV->getVisibility()) {
 
-  // TODO: "exported" and "internal" Visibility needs to go here.
-  case GlobalValue::DefaultVisibility:
-break;
-  case GlobalValue::HiddenVisibility:
-VisibilityAttr = MAI->getHiddenVisibilityAttr();
-break;
-  case GlobalValue::ProtectedVisibility:
-VisibilityAttr = MAI->getProtectedVisibilityAttr();
-break;
+// TODO: "exported" and "internal" Visibility needs to go here.
+case GlobalValue::DefaultVisibility:
+  break;
+case GlobalValue::HiddenVisibility:
+  VisibilityAttr = MAI->getHiddenVisibilityAttr();
+  break;
+case GlobalValue::ProtectedVisibility:
+  VisibilityAttr = MAI->getProtectedVisibilityAttr();
+  break;
+}
   }
 
   OutStreamer->emitXCOFFSymbolLinkageWithVisibility(GVSym, LinkageAttr,
Index: llvm/lib/CodeGen/CommandFlags.cpp
===
--- llvm/lib/CodeGen/CommandFlags.cpp
+++ llvm/lib/CodeGen/CommandFlags.cpp
@@ -74,6 +74,7 @@
 CGOPT(bool, RelaxELFRelocations)
 CGOPT_EXP(bool, DataSections)
 CGOPT_EXP(bool, FunctionSections)
+CGOPT(bool, IgnoreXCOFFVisibility)
 CGOPT(std::string, BBSections)
 CGOPT(unsigned, TLSSize)
 CGOPT(bool, EmulatedTLS)
@@ -333,6 +334,13 @@
   cl::init(false));
   CGBINDOPT(FunctionSections);
 
+  static cl::opt IgnoreXCOFFVisibility(
+  "ignore-xcoff-visibility",
+  cl::desc("Not emit the visibility attribute for asm in AIX OS or give "
+   "all symbols 'unspecified' visibility in xcoff object file"),
+  cl::init(false));
+  CGBINDOPT(IgnoreXCOFFVisibility);
+
   static cl::opt BBSections(
   "basic-block-sections",
   cl::desc("Emit basic blocks into separate 

[PATCH] D87451: add new option ignore-xcoff-visibility

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DiggerLin marked 7 inline comments as done.
DiggerLin added inline comments.



Comment at: clang/docs/ClangCommandLineReference.rst:2622
+
+Do not emit any visibility attribute for asm on AIX or give all symbols 
'unspecified' visibility in xcoff object file(XCOFF only)
+

daltenty wrote:
> daltenty wrote:
> > nit: add a space before parens
> I don't think the object file writing case was handled yet? This makes it 
> sound like it is.
yes, we do not implement the visibility of the object file in the 
XCoffObjectWriter.cpp



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:5242
 
+  if (const Arg *A = Args.getLastArg(options::OPT_mignore_xcoff_visibility)) {
+if (Triple.isOSAIX())

daltenty wrote:
> Use `Args.hasFlag` instead, since this option doesn't have a value we need to 
> check.
we need to get the value here 
 D.Diag(diag::err_drv_unsupported_opt_for_target)
  << A->getAsString(Args) << TripleStr;



Comment at: clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp:72
+
+// ERROR: unsupported option '-mignore-xcoff-visibility' for target 
'powerpc-unknown-linux'
+

daltenty wrote:
> This isn't being checked anymore, also probably belongs in the other file
thanks


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Comment at: clang/include/clang/Basic/CodeGenOptions.def:46
  ///< aliases to base ctors when possible.
-CODEGENOPT(DataSections  , 1, 0) ///< Set when -fdata-sections is enabled.
+CODEGENOPT(DataSections  , 1, 0) ///< Set by default, or when 
-f[no-]data-sections.
+CODEGENOPT(HasExplicitDataSections, 1, 0) ///< Set when -f[no-]data-sections 
is set.

turn on by default , it should be changed to CODEGENOPT(DataSections  , 1, 
1) ?



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[PATCH] D87451: add new option ignore-xcoff-visibility

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DiggerLin updated this revision to Diff 295838.
DiggerLin marked an inline comment as done.
DiggerLin added a comment.

address comment and merger the patch https://reviews.llvm.org/D88234 into the 
patch


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/Driver/ignore-xcoff-visibility.cpp
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetMachine.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.ll

Index: llvm/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.ll
@@ -0,0 +1,48 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec  < %s | \
+; RUN:   FileCheck --check-prefix=VISIBILITY-ASM %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -ignore-xcoff-visibility < %s | \
+; RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | \
+; RUN:   FileCheck --check-prefix=VISIBILITY-ASM %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -ignore-xcoff-visibility < %s | \
+; RUN:   FileCheck --check-prefix=IGNOREVISIBILITY-ASM %s
+
+@foo_p = global void ()* @zoo_extern_h, align 4
+@b = protected global i32 0, align 4
+
+define hidden void @foo_h(i32* %p) {
+entry:
+  %p.addr = alloca i32*, align 4
+  store i32* %p, i32** %p.addr, align 4
+  %0 = load i32*, i32** %p.addr, align 4
+  %1 = load i32, i32* %0, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* %0, align 4
+  ret void
+}
+
+declare hidden void @zoo_extern_h()
+
+define protected void @bar() {
+entry:
+  call void @foo_h(i32* @b)
+  %0 = load void ()*, void ()** @foo_p, align 4
+  call void %0()
+  ret void
+}
+
+; VISIBILITY-ASM: .globl  foo_h[DS],hidden
+; VISIBILITY-ASM: .globl  .foo_h,hidden
+; VISIBILITY-ASM: .globl  bar[DS],protected
+; VISIBILITY-ASM: .globl  .bar,protected
+; VISIBILITY-ASM: .globl  b,protected
+
+; IGNOREVISIBILITY-ASM: .globl  foo_h[DS]
+; IGNOREVISIBILITY-ASM: .globl  .foo_h
+; IGNOREVISIBILITY-ASM: .globl  bar[DS]
+; IGNOREVISIBILITY-ASM: .globl  .bar
+; IGNOREVISIBILITY-ASM: .globl  b
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1702,17 +1702,19 @@
   assert(LinkageAttr != MCSA_Invalid && "LinkageAttr should not MCSA_Invalid.");
 
   MCSymbolAttr VisibilityAttr = MCSA_Invalid;
-  switch (GV->getVisibility()) {
+  if (!TM.getIgnoreXCOFFVisibility()) {
+switch (GV->getVisibility()) {
 
-  // TODO: "exported" and "internal" Visibility needs to go here.
-  case GlobalValue::DefaultVisibility:
-break;
-  case GlobalValue::HiddenVisibility:
-VisibilityAttr = MAI->getHiddenVisibilityAttr();
-break;
-  case GlobalValue::ProtectedVisibility:
-VisibilityAttr = MAI->getProtectedVisibilityAttr();
-break;
+// TODO: "exported" and "internal" Visibility needs to go here.
+case GlobalValue::DefaultVisibility:
+  break;
+case GlobalValue::HiddenVisibility:
+  VisibilityAttr = MAI->getHiddenVisibilityAttr();
+  break;
+case GlobalValue::ProtectedVisibility:
+  VisibilityAttr = MAI->getProtectedVisibilityAttr();
+  break;
+}
   }
 
   OutStreamer->emitXCOFFSymbolLinkageWithVisibility(GVSym, LinkageAttr,
Index: llvm/lib/CodeGen/CommandFlags.cpp
===
--- llvm/lib/CodeGen/CommandFlags.cpp
+++ llvm/lib/CodeGen/CommandFlags.cpp
@@ -74,6 +74,7 @@
 CGOPT(bool, RelaxELFRelocations)
 CGOPT_EXP(bool, DataSections)
 CGOPT_EXP(bool, FunctionSections)
+CGOPT(bool, IgnoreXCOFFVisibility)
 CGOPT(std::string, BBSections)
 CGOPT(unsigned, TLSSize)
 CGOPT(bool, EmulatedTLS)
@@ -333,6 +334,13 @@
   cl::init(false));
   CGBINDOPT(FunctionSections);
 
+  static cl::opt IgnoreXCOFFVisibility(
+  "ignore-xcoff-visibility",
+  cl::desc("Not emit the visibility attribute for asm in AIX OS or give "
+   "all symbols 'unspecified' visibility in xcoff object file"),
+  cl::init(false));
+  CGBINDOPT(IgnoreXCOFFVisibility);
+
   static cl::opt BBSections(
   

[PATCH] D87451: add new option ignore-xcoff-visibility

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DiggerLin added inline comments.



Comment at: clang/test/CodeGen/aix-no-xcoff-visibility.cpp:75
+
+// VISIBILITY-IR:@b = protected global i32 0
+// VISIBILITY-IR:@pramb = hidden global i32 0

jasonliu wrote:
> Not sure if the IR check is really necessary, since we haven't made any IR 
> change here. It's going to be all the same with or without the new -m option. 
IR output will not change in the new option. I think we need to check whether 
the IR be changed in the new option 


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[PATCH] D87451: add new clang option -mno-xcoff-visibility

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Comment at: llvm/include/llvm/Target/TargetMachine.h:265
+  /// corresponding to -mno-xcoff-visibility.
+  bool getNoXCOFFVisibility() const { return Options.NoXCOFFVisibility; }
+

jasonliu wrote:
> DiggerLin wrote:
> > daltenty wrote:
> > > This seems like it needs the corresponding comand-line option for llc 
> > > added and an llc test.
> > I think it will be in another separate  patch.
> I would actually prefer to have that in the same patch, as that would give us 
> a full picture. It's not a huge patch even if we combine them. 
yes, it is not huge patch, one patch for the clang with option 
-mno-xcoff-visibility, another patch for llc option -no-xcoff-visibility , I 
think it is different functionality. and I have post the 
https://reviews.llvm.org/D88234 "add new option -no-xcoff-visibility for llc"


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[PATCH] D87451: add new clang option -mno-xcoff-visibility

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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/aix-no-xcoff-visibility.cpp
  llvm/include/llvm/Target/TargetMachine.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1686,17 +1686,19 @@
   assert(LinkageAttr != MCSA_Invalid && "LinkageAttr should not MCSA_Invalid.");
 
   MCSymbolAttr VisibilityAttr = MCSA_Invalid;
-  switch (GV->getVisibility()) {
+  if (!TM.getNoXCOFFVisibility()) {
+switch (GV->getVisibility()) {
 
-  // TODO: "exported" and "internal" Visibility needs to go here.
-  case GlobalValue::DefaultVisibility:
-break;
-  case GlobalValue::HiddenVisibility:
-VisibilityAttr = MAI->getHiddenVisibilityAttr();
-break;
-  case GlobalValue::ProtectedVisibility:
-VisibilityAttr = MAI->getProtectedVisibilityAttr();
-break;
+// TODO: "exported" and "internal" Visibility needs to go here.
+case GlobalValue::DefaultVisibility:
+  break;
+case GlobalValue::HiddenVisibility:
+  VisibilityAttr = MAI->getHiddenVisibilityAttr();
+  break;
+case GlobalValue::ProtectedVisibility:
+  VisibilityAttr = MAI->getProtectedVisibilityAttr();
+  break;
+}
   }
 
   OutStreamer->emitXCOFFSymbolLinkageWithVisibility(GVSym, LinkageAttr,
Index: llvm/include/llvm/Target/TargetOptions.h
===
--- llvm/include/llvm/Target/TargetOptions.h
+++ llvm/include/llvm/Target/TargetOptions.h
@@ -123,9 +123,10 @@
   EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
   DisableIntegratedAS(false), RelaxELFRelocations(false),
   FunctionSections(false), DataSections(false),
-  UniqueSectionNames(true), UniqueBasicBlockSectionNames(false),
-  TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0),
-  EmulatedTLS(false), ExplicitEmulatedTLS(false), EnableIPRA(false),
+  NoXCOFFVisibility(false), UniqueSectionNames(true),
+  UniqueBasicBlockSectionNames(false), TrapUnreachable(false),
+  NoTrapAfterNoreturn(false), TLSSize(0), EmulatedTLS(false),
+  ExplicitEmulatedTLS(false), EnableIPRA(false),
   EmitStackSizeSection(false), EnableMachineOutliner(false),
   EnableMachineFunctionSplitter(false), SupportsDefaultOutlining(false),
   EmitAddrsig(false), EmitCallSiteInfo(false),
@@ -230,6 +231,9 @@
 /// Emit data into separate sections.
 unsigned DataSections : 1;
 
+/// Do not emit visibility attribute for xcoff.
+unsigned NoXCOFFVisibility : 1;
+
 unsigned UniqueSectionNames : 1;
 
 /// Use unique names for basic block sections.
Index: llvm/include/llvm/Target/TargetMachine.h
===
--- llvm/include/llvm/Target/TargetMachine.h
+++ llvm/include/llvm/Target/TargetMachine.h
@@ -260,6 +260,10 @@
 return Options.FunctionSections;
   }
 
+  /// Return true if visibility attribute should not be emitted in xcoff,
+  /// corresponding to -mno-xcoff-visibility.
+  bool getNoXCOFFVisibility() const { return Options.NoXCOFFVisibility; }
+
   /// If basic blocks should be emitted into their own section,
   /// corresponding to -fbasic-block-sections.
   llvm::BasicBlockSection getBBSectionsType() const {
Index: clang/test/CodeGen/aix-no-xcoff-visibility.cpp
===
--- /dev/null
+++ clang/test/CodeGen/aix-no-xcoff-visibility.cpp
@@ -0,0 +1,110 @@
+// RUN: %clang -target powerpc-unknown-aix -emit-llvm -o - -S  %s  |\
+// RUN:   FileCheck --check-prefix=VISIBILITY-IR %s
+
+// RUN: %clang -target powerpc-unknown-aix -o - -S  %s  |\
+// RUN:   FileCheck --check-prefix=NOVISIBILITY-ASM %s
+
+// RUN: %clang -target powerpc-unknown-linux  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+
+// RUN: %clang -mno-xcoff-visibility -target powerpc-unknown-aix -emit-llvm -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+
+// RUN: %clang -mno-xcoff-visibility -target powerpc-unknown-aix -o - -S %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-ASM %s
+
+// RUN: not %clang -mno-xcoff-visibility -target powerpc-unknown-linux -emit-llvm -o - -S %s  2>&1 | \
+// RUN: FileCheck -check-prefix=ERROR %s
+
+// RUN: %clang 

[PATCH] D87451: add new clang option -mno-xcoff-visibility

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Comment at: clang/lib/Frontend/CompilerInvocation.cpp:2768
   // The type-visibility mode defaults to the value-visibility mode.
   if (Arg *typeVisOpt = Args.getLastArg(OPT_ftype_visibility)) {
 Opts.setTypeVisibilityMode(parseVisibility(typeVisOpt, Args, Diags));

jasonliu wrote:
> Question: how should -mignore-xcoff-visiblity interact with -ftype-visibility?
the -ftype-visibility do not support in the clang,  so there is no interact.


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Comment at: llvm/include/llvm/Target/TargetMachine.h:265
+  /// corresponding to -mno-xcoff-visibility.
+  bool getNoXCOFFVisibility() const { return Options.NoXCOFFVisibility; }
+

daltenty wrote:
> This seems like it needs the corresponding comand-line option for llc added 
> and an llc test.
I think it will be in another separate  patch.


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[PATCH] D87451: add new clang option -mno-xcoff-visibility

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DiggerLin updated this revision to Diff 293571.
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Herald added subscribers: llvm-commits, kbarton, hiraditya, nemanjai.
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address comment


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/Driver/ignore-xcoff-visibility.cpp
  llvm/include/llvm/Target/TargetMachine.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1686,17 +1686,19 @@
   assert(LinkageAttr != MCSA_Invalid && "LinkageAttr should not MCSA_Invalid.");
 
   MCSymbolAttr VisibilityAttr = MCSA_Invalid;
-  switch (GV->getVisibility()) {
+  if (!TM.getNoXCOFFVisibility()) {
+switch (GV->getVisibility()) {
 
-  // TODO: "exported" and "internal" Visibility needs to go here.
-  case GlobalValue::DefaultVisibility:
-break;
-  case GlobalValue::HiddenVisibility:
-VisibilityAttr = MAI->getHiddenVisibilityAttr();
-break;
-  case GlobalValue::ProtectedVisibility:
-VisibilityAttr = MAI->getProtectedVisibilityAttr();
-break;
+// TODO: "exported" and "internal" Visibility needs to go here.
+case GlobalValue::DefaultVisibility:
+  break;
+case GlobalValue::HiddenVisibility:
+  VisibilityAttr = MAI->getHiddenVisibilityAttr();
+  break;
+case GlobalValue::ProtectedVisibility:
+  VisibilityAttr = MAI->getProtectedVisibilityAttr();
+  break;
+}
   }
 
   OutStreamer->emitXCOFFSymbolLinkageWithVisibility(GVSym, LinkageAttr,
Index: llvm/include/llvm/Target/TargetOptions.h
===
--- llvm/include/llvm/Target/TargetOptions.h
+++ llvm/include/llvm/Target/TargetOptions.h
@@ -123,9 +123,10 @@
   EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
   DisableIntegratedAS(false), RelaxELFRelocations(false),
   FunctionSections(false), DataSections(false),
-  UniqueSectionNames(true), UniqueBasicBlockSectionNames(false),
-  TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0),
-  EmulatedTLS(false), ExplicitEmulatedTLS(false), EnableIPRA(false),
+  NoXCOFFVisibility(false), UniqueSectionNames(true),
+  UniqueBasicBlockSectionNames(false), TrapUnreachable(false),
+  NoTrapAfterNoreturn(false), TLSSize(0), EmulatedTLS(false),
+  ExplicitEmulatedTLS(false), EnableIPRA(false),
   EmitStackSizeSection(false), EnableMachineOutliner(false),
   EnableMachineFunctionSplitter(false), SupportsDefaultOutlining(false),
   EmitAddrsig(false), EmitCallSiteInfo(false),
@@ -230,6 +231,9 @@
 /// Emit data into separate sections.
 unsigned DataSections : 1;
 
+/// Do not emit visibility attribute for xcoff.
+unsigned NoXCOFFVisibility : 1;
+
 unsigned UniqueSectionNames : 1;
 
 /// Use unique names for basic block sections.
Index: llvm/include/llvm/Target/TargetMachine.h
===
--- llvm/include/llvm/Target/TargetMachine.h
+++ llvm/include/llvm/Target/TargetMachine.h
@@ -260,6 +260,10 @@
 return Options.FunctionSections;
   }
 
+  /// Return true if visibility attribute should not be emitted in xcoff,
+  /// corresponding to -mno-xcoff-visibility.
+  bool getNoXCOFFVisibility() const { return Options.NoXCOFFVisibility; }
+
   /// If basic blocks should be emitted into their own section,
   /// corresponding to -fbasic-block-sections.
   llvm::BasicBlockSection getBBSectionsType() const {
Index: clang/test/Driver/ignore-xcoff-visibility.cpp
===
--- /dev/null
+++ clang/test/Driver/ignore-xcoff-visibility.cpp
@@ -0,0 +1,110 @@
+// RUN: %clang -target powerpc-unknown-aix -emit-llvm -o - -S  %s  |\
+// RUN:   FileCheck --check-prefix=VISIBILITY-IR %s
+
+// RUN: %clang -target powerpc-unknown-aix -o - -S  %s  |\
+// RUN:   FileCheck --check-prefix=NOVISIBILITY-ASM %s
+
+// RUN: %clang -target powerpc-unknown-linux  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+
+// RUN: %clang -mno-xcoff-visibility -target powerpc-unknown-aix -emit-llvm -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY-IR %s
+
+// RUN: %clang -mno-xcoff-visibility -target powerpc-unknown-aix -o - -S %s  | \
+// RUN: FileCheck -check-prefix=NOVISIBILITY-ASM %s
+
+// RUN: not %clang -mno-xcoff-visibility -target powerpc-unknown-linux 

[PATCH] D87451: add new clang option -mignore-xcoff-visibility

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DiggerLin updated this revision to Diff 291962.
DiggerLin retitled this revision from "add new clang option -fnovisibility." to 
"add new clang option -mignore-xcoff-visibility".

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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/AST/Decl.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/Driver/ignore-xcoff-visibility.cpp

Index: clang/test/Driver/ignore-xcoff-visibility.cpp
===
--- /dev/null
+++ clang/test/Driver/ignore-xcoff-visibility.cpp
@@ -0,0 +1,81 @@
+// RUN: %clang-target powerpc-unknown-aix  -emit-llvm  -o - -S  %s  |\
+// RUN:   FileCheck --check-prefix=IGNOREVISIBILITY %s
+
+// RUN: %clang -target powerpc-unknown-linux  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+// RUN: %clang -mignore-xcoff-visibility -target powerpc-unknown-aix  -emit-llvm -o -  -S %s  | \
+// RUN: FileCheck -check-prefix=IGNOREVISIBILITY %s
+
+// RUN: not %clang -mignore-xcoff-visibility -target powerpc-unknown-linux  -emit-llvm -o - -S %s  2>&1 | \
+// RUN: FileCheck -check-prefix=ERROR %s
+
+// RUN: %clang -fvisibility=default -target powerpc-unknown-aix  -emit-llvm -o -  -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+// RUN: %clang -fvisibility=default -target powerpc-unknown-linux  -emit-llvm -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+// RUN: %clang -mignore-xcoff-visibility -fvisibility=default -target powerpc-unknown-aix  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=IGNOREVISIBILITY %s
+
+// RUN: not %clang -mignore-xcoff-visibility -fvisibility=default -target powerpc-unknown-linux  -emit-llvm -o - -S %s 2>&1 | \
+// RUN: FileCheck -check-prefix=ERROR %s
+
+__attribute__((visibility("hidden"))) void foo_h(int *p) {
+  (*p)++;
+}
+
+__attribute__((visibility("protected"))) int b;
+
+extern __attribute__((visibility("hidden"))) void zoo_extern_h(void);
+
+void (*foo_p)(void) = zoo_extern_h;
+
+__attribute__((visibility("protected"))) void bar() {
+  foo_h();
+  foo_p();
+}
+
+class TestClass {
+public:
+  __attribute__((__visibility__("hidden"))) int value() const noexcept { return 0; }
+};
+
+int main() {
+  TestClass TC;
+  return TC.value();
+}
+
+template 
+class basic {
+public:
+  __attribute__((__visibility__("protected"))) int getdata() { return 1; }
+};
+
+template class basic;
+
+#pragma GCC visibility push(hidden)
+int pramb;
+void prambar() {}
+#pragma GCC visibility pop
+
+// IGNOREVISIBILITY:@b = global i32 0
+// IGNOREVISIBILITY:@pramb = global i32 0
+// IGNOREVISIBILITY:define void @_Z5foo_hPi(i32* %p)
+// IGNOREVISIBILITY:declare void @_Z12zoo_extern_hv()
+// IGNOREVISIBILITY:define void @_Z3barv()
+// IGNOREVISIBILITY:define linkonce_odr i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// IGNOREVISIBILITY:define weak_odr i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+// IGNOREVISIBILITY:define void @_Z7prambarv()
+
+// VISIBILITY:@b = protected global i32 0
+// VISIBILITY:@pramb = hidden global i32 0
+// VISIBILITY:define hidden void @_Z5foo_hPi(i32* %p)
+// VISIBILITY:declare hidden void @_Z12zoo_extern_hv()
+// VISIBILITY:define protected void @_Z3barv()
+// VISIBILITY:define linkonce_odr hidden i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// VISIBILITY:define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+// VISIBILITY:define hidden void @_Z7prambarv()
+
+// ERROR: unsupported option '-mignore-xcoff-visibility' for target 'powerpc-unknown-linux'
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -2749,9 +2749,19 @@
 
   // The value-visibility mode defaults to "default".
   if (Arg *visOpt = Args.getLastArg(OPT_fvisibility)) {
-Opts.setValueVisibilityMode(parseVisibility(visOpt, Args, Diags));
+// In AIX Os, if there is -mignore_xcoff_visibility and -fvisibility=* at
+// sametime, the option "mignore_xcoff_visibility" take effect.
+if (T.isOSAIX() && Args.hasArg(OPT_mignore_xcoff_visibility))
+  Opts.IgnoreXCOFFVisibility = 1;
+else
+  Opts.setValueVisibilityMode(parseVisibility(visOpt, Args, Diags));
   } else {
-Opts.setValueVisibilityMode(DefaultVisibility);
+// In AIX oS, the -mignore_xcoff_visibility is enable by default if there is
+// not -fvisibility=*
+if (T.isOSAIX())
+  Opts.IgnoreXCOFFVisibility = 1;
+else
+  Opts.setValueVisibilityMode(DefaultVisibility);
   }
 
   // The type-visibility mode defaults to the value-visibility 

[PATCH] D87451: add new clang option -fnovisibility.

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DiggerLin updated this revision to Diff 290987.
DiggerLin added a comment.

address comment


Repository:
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/AST/Decl.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/Driver/fnovisibility.cpp

Index: clang/test/Driver/fnovisibility.cpp
===
--- /dev/null
+++ clang/test/Driver/fnovisibility.cpp
@@ -0,0 +1,81 @@
+// RUN: %clang-target powerpc-unknown-aix  -emit-llvm  -o - -S  %s  |\
+// RUN:   FileCheck --check-prefixes=NOVISIBILITY,AIX-NOVISIBILITY %s
+
+// RUN: %clang -fnovisibility -target powerpc-unknown-aix  -emit-llvm -o -  -S %s  | \
+// RUN: FileCheck -check-prefixes=NOVISIBILITY,AIX-NOVISIBILITY %s
+
+// RUN: %clang -fnovisibility -target powerpc-unknown-linux  -emit-llvm -o - -S %s  | \
+// RUN: FileCheck -check-prefixes=NOVISIBILITY,LINUX-NOVISIBILITY %s
+
+// RUN: %clang -fnovisibility -fvisibility=default -target powerpc-unknown-aix  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+// RUN: %clang -target powerpc-unknown-linux  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+// RUN: %clang -fnovisibility -fvisibility=default -target powerpc-unknown-linux  -emit-llvm -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+__attribute__((visibility("hidden"))) void foo_h(int *p) {
+  (*p)++;
+}
+
+__attribute__((visibility("protected"))) int b;
+
+extern __attribute__((visibility("hidden"))) void zoo_extern_h(void);
+
+void (*foo_p)(void) = zoo_extern_h;
+
+__attribute__((visibility("protected"))) void bar() {
+  foo_h();
+  foo_p();
+}
+
+class TestClass {
+public:
+  __attribute__((__visibility__("hidden"))) int value() const noexcept { return 0; }
+};
+
+int main() {
+  TestClass TC;
+  return TC.value();
+}
+
+template 
+class basic {
+public:
+  __attribute__((__visibility__("protected"))) int getdata() { return 1; }
+};
+
+template class basic;
+
+#pragma GCC visibility push(hidden)
+ int pramb;
+ void prambar() {}
+#pragma GCC visibility pop
+
+
+// AIX-NOVISIBILITY:@b = global i32 0
+// LINUX-NOVISIBILITY:  @b = dso_local global i32 0
+// AIX-NOVISIBILITY:@pramb = global i32 0
+// LINUX-NOVISIBILITY:  @pramb = dso_local global i32 0
+// AIX-NOVISIBILITY:define void @_Z5foo_hPi(i32* %p)
+// LINUX-NOVISIBILITY:  define dso_local void @_Z5foo_hPi(i32* %p)
+// NOVISIBILITY:declare void @_Z12zoo_extern_hv()
+// AIX-NOVISIBILITY:define void @_Z3barv()
+// LINUX-NOVISIBILITY:  define dso_local void @_Z3barv()
+// AIX-NOVISIBILITY:define linkonce_odr i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// LINUX-NOVISIBILITY:  define linkonce_odr dso_local i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// AIX-NOVISIBILITY:define weak_odr i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+// LINUX-NOVISIBILITY:  define weak_odr dso_local i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+// AIX-NOVISIBILITY:define void @_Z7prambarv()
+// LINUX-NOVISIBILITY:  define dso_local void @_Z7prambarv()
+
+// VISIBILITY:@b = protected global i32 0
+// VISIBILITY:@pramb = hidden global i32 0
+// VISIBILITY:define hidden void @_Z5foo_hPi(i32* %p)
+// VISIBILITY:declare hidden void @_Z12zoo_extern_hv()
+// VISIBILITY:define protected void @_Z3barv()
+// VISIBILITY:define linkonce_odr hidden i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// VISIBILITY:define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+// VISIBILITY:define hidden void @_Z7prambarv()
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -2752,6 +2752,9 @@
 Opts.setValueVisibilityMode(parseVisibility(visOpt, Args, Diags));
   } else {
 Opts.setValueVisibilityMode(DefaultVisibility);
+// In AIX oS, the -fnovisibility is enable by default.
+if (T.isOSAIX() || Args.hasArg(OPT_fnovisibility))
+  Opts.NoVisibility = 1;
   }
 
   // The type-visibility mode defaults to the value-visibility mode.
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -5198,6 +5198,9 @@
 }
   }
 
+  if (Args.getLastArg(options::OPT_fnovisibility))
+CmdArgs.push_back("-fnovisibility");
+
   Args.AddLastArg(CmdArgs, options::OPT_fvisibility_inlines_hidden);
   Args.AddLastArg(CmdArgs, options::OPT_fvisibility_global_new_delete_hidden);
 
Index: clang/lib/AST/Decl.cpp

[PATCH] D87451: add new clang option -fnovisibility.

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 290978.
DiggerLin added a comment.

add a pragmas test case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87451/new/

https://reviews.llvm.org/D87451

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/AST/Decl.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/Driver/fnovisibility.cpp

Index: clang/test/Driver/fnovisibility.cpp
===
--- /dev/null
+++ clang/test/Driver/fnovisibility.cpp
@@ -0,0 +1,81 @@
+// RUN: %clang-target powerpc-unknown-aix  -emit-llvm  -o - -S  %s  |\
+// RUN:   FileCheck --check-prefixes=NOVISIBILITY,AIX-NOVISIBILITY %s
+
+// RUN: %clang -fnovisibility -target powerpc-unknown-aix  -emit-llvm -o -  -S %s  | \
+// RUN: FileCheck -check-prefixes=NOVISIBILITY,AIX-NOVISIBILITY %s
+
+// RUN: %clang -fnovisibility -target powerpc-unknown-linux  -emit-llvm -o - -S %s  | \
+// RUN: FileCheck -check-prefixes=NOVISIBILITY,LINUX-NOVISIBILITY %s
+
+// RUN: %clang -fnovisibility -fvisibility=default -target powerpc-unknown-aix  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+// RUN: %clang -target powerpc-unknown-linux  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+// RUN: %clang -fnovisibility -fvisibility=default -target powerpc-unknown-linux  -emit-llvm -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+__attribute__((visibility("hidden"))) void foo_h(int *p) {
+  (*p)++;
+}
+
+__attribute__((visibility("protected"))) int b;
+
+extern __attribute__((visibility("hidden"))) void zoo_extern_h(void);
+
+void (*foo_p)(void) = zoo_extern_h;
+
+__attribute__((visibility("protected"))) void bar() {
+  foo_h();
+  foo_p();
+}
+
+class TestClass {
+public:
+  __attribute__((__visibility__("hidden"))) int value() const noexcept { return 0; }
+};
+
+int main() {
+  TestClass TC;
+  return TC.value();
+}
+
+template 
+class basic {
+public:
+  __attribute__((__visibility__("protected"))) int getdata() { return 1; }
+};
+
+template class basic;
+
+#pragma GCC visibility push(hidden)
+ int pramb;
+ void prambar() {}
+#pragma GCC visibility pop
+
+
+// AIX-NOVISIBILITY:@b = global i32 0
+// LINUX-NOVISIBILITY:  @b = dso_local global i32 0
+// AIX-NOVISIBILITY:@pramb = global i32 0
+// LINUX-NOVISIBILITY:  @pramb = dso_local global i32 0
+// AIX-NOVISIBILITY:define void @_Z5foo_hPi(i32* %p)
+// LINUX-NOVISIBILITY:  define dso_local void @_Z5foo_hPi(i32* %p)
+// NOVISIBILITY:declare void @_Z12zoo_extern_hv()
+// AIX-NOVISIBILITY:define void @_Z3barv()
+// LINUX-NOVISIBILITY:  define dso_local void @_Z3barv()
+// AIX-NOVISIBILITY:define linkonce_odr i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// LINUX-NOVISIBILITY:  define linkonce_odr dso_local i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// AIX-NOVISIBILITY:define weak_odr i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+// LINUX-NOVISIBILITY:  define weak_odr dso_local i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+// AIX-NOVISIBILITY:define void @_Z7prambarv()
+// LINUX-NOVISIBILITY:  define dso_local void @_Z7prambarv()
+
+// VISIBILITY:@b = protected global i32 0
+// VISIBILITY:@pramb = hidden global i32 0
+// VISIBILITY:define hidden void @_Z5foo_hPi(i32* %p)
+// VISIBILITY:declare hidden void @_Z12zoo_extern_hv()
+// VISIBILITY:define protected void @_Z3barv()
+// VISIBILITY:define linkonce_odr hidden i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// VISIBILITY:define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+// VISIBILITY:define hidden void @_Z7prambarv()
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -2752,6 +2752,9 @@
 Opts.setValueVisibilityMode(parseVisibility(visOpt, Args, Diags));
   } else {
 Opts.setValueVisibilityMode(DefaultVisibility);
+// In AIX oS, the -fnovisibility is enable by default.
+if (T.isOSAIX() || Args.hasArg(OPT_fnovisibility))
+  Opts.NoVisibility = 1;
   }
 
   // The type-visibility mode defaults to the value-visibility mode.
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -5198,6 +5198,9 @@
 }
   }
 
+  if (Args.getLastArg(options::OPT_fnovisibility))
+CmdArgs.push_back("-fnovisibility");
+
   Args.AddLastArg(CmdArgs, options::OPT_fvisibility_inlines_hidden);
   Args.AddLastArg(CmdArgs, options::OPT_fvisibility_global_new_delete_hidden);
 
Index: clang/lib/AST/Decl.cpp

[PATCH] D87451: add new clang option -fnovisibility.

[Digger via Phabricator via cfe-commits]

DiggerLin created this revision.
DiggerLin added reviewers: hubert.reinterpretcast, jasonliu, daltenty.
Herald added subscribers: cfe-commits, dang, steven.zhang.
Herald added a project: clang.
DiggerLin requested review of this revision.

In IBM compiler Xlclang , there is option -fnovisibiilty. The option is 
description as

  
https://www.ibm.com/support/knowledgecenter/SSGH3R_16.1.0/com.ibm.xlcpp161.aix.doc/compiler_ref/opt_visibility.html
 
   
  we need to add the option -fnovisibiilty for clang in the IBM AIX OS(and the 
option is enabled by default in AIX OS).  
  I will implement the option in the other OS platform.(but the option is 
disabled by default in other OS).
   
  For example, the file test.c
   

bash-4.2$ test.c
 __attribute__((visibility ("protected"))) int b;

1 In AIX OS:

1.1 Compiled with

  clang -fnovisibility-target powerpc-unknown-aix  -emit-llvm  -S test.c

or

  clang -target powerpc-unknown-aix  -emit-llvm  -S test.c  ( the 
-fnovisibility is enabled by default in AIX OS)

Generate IR as :

  @b = global i32 0, align 4
   

1.2 Compiled with

  (If have "-fnovisibility  -fvisibility=*" at the same time.  the compile will 
ignore the -fnovisibility). 
   
  clang -fnovisibility  -fvisibility=default   -target powerpc-unknown-aix   
-emit-llvm  -S test.c

Or

  clang -fvisibility=default   -target powerpc-unknown-aix   -emit-llvm  -S 
test.c
   
  Generate IR as :
  @b = protected global i32 0, align 4
   

2. In Other OS(not AIX) 2.1 clang -fnovisibility-target 
powerpc-unknown-linux  -emit-llvm  -S test.c

  Generate IR as : @b = global i32 0, align 4

  2.2 clang -target powerpc-unknown-linux  -emit-llvm  -S test.c ( the 
-fnovisibility is disabled by default in not AIX OS) Or (if have 
"-fnovisibility  -fvisibility=*" at the same time.  the compile will ignore the 
-fnovisibility). clang -fnovisibility  -fvisibility=default   -target 
powerpc-unknown-linux   -emit-llvm  -S test.c Or clang -fvisibility=default   
-target powerpc-unknown-linux   -emit-llvm  -S test.c

  Generate IR as : @b = protected global i32 0, align 4


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87451

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/AST/Decl.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/Driver/fnovisibility.cpp

Index: clang/test/Driver/fnovisibility.cpp
===
--- /dev/null
+++ clang/test/Driver/fnovisibility.cpp
@@ -0,0 +1,69 @@
+// RUN: %clang-target powerpc-unknown-aix  -emit-llvm  -o - -S  %s  |\
+// RUN:   FileCheck --check-prefixes=NOVISIBILITY,AIX-NOVISIBILITY %s
+
+// RUN: %clang -fnovisibility -target powerpc-unknown-aix  -emit-llvm -o -  -S %s  | \
+// RUN: FileCheck -check-prefixes=NOVISIBILITY,AIX-NOVISIBILITY %s
+
+// RUN: %clang -fnovisibility -target powerpc-unknown-linux  -emit-llvm -o - -S %s  | \
+// RUN: FileCheck -check-prefixes=NOVISIBILITY,LINUX-NOVISIBILITY %s
+
+// RUN: %clang -fnovisibility -fvisibility=default -target powerpc-unknown-aix  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+// RUN: %clang -target powerpc-unknown-linux  -emit-llvm  -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+// RUN: %clang -fnovisibility -fvisibility=default -target powerpc-unknown-linux  -emit-llvm -o - -S %s  | \
+// RUN: FileCheck -check-prefix=VISIBILITY %s
+
+__attribute__((visibility("hidden"))) void foo_h(int *p) {
+  (*p)++;
+}
+
+__attribute__((visibility("protected"))) int b;
+
+extern __attribute__((visibility("hidden"))) void zoo_extern_h(void);
+
+void (*foo_p)(void) = zoo_extern_h;
+
+__attribute__((visibility("protected"))) void bar() {
+  foo_h();
+  foo_p();
+}
+
+class TestClass {
+public:
+  __attribute__((__visibility__("hidden"))) int value() const noexcept { return 0; }
+};
+
+int main() {
+  TestClass TC;
+  return TC.value();
+}
+
+template 
+class basic {
+public:
+  __attribute__((__visibility__("protected"))) int getdata() { return 1; }
+};
+
+template class basic;
+
+// AIX-NOVISIBILITY:@b = global i32 0
+// LINUX-NOVISIBILITY:  @b = dso_local global i32 0
+// AIX-NOVISIBILITY:define void @_Z5foo_hPi(i32* %p)
+// LINUX-NOVISIBILITY:  define dso_local void @_Z5foo_hPi(i32* %p)
+// NOVISIBILITY:declare void @_Z12zoo_extern_hv()
+// AIX-NOVISIBILITY:define void @_Z3barv()
+// LINUX-NOVISIBILITY:  define dso_local void @_Z3barv()
+// AIX-NOVISIBILITY:define linkonce_odr i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// LINUX-NOVISIBILITY:  define linkonce_odr dso_local i32 @_ZNK9TestClass5valueEv(%class.TestClass* %this)
+// AIX-NOVISIBILITY:define weak_odr i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+// LINUX-NOVISIBILITY:  define weak_odr dso_local i32 @_ZN5basicIiE7getdataEv(%class.basic* %this)
+
+// VISIBILITY:@b = 

[PATCH] D84356: [AIX] remove -u from the clang when invoke aix as assembler

[Digger via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG77b61177d7d4: [AIX] remove -u from the clang when invoke aix 
as assembler (authored by DiggerLin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84356/new/

https://reviews.llvm.org/D84356

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c


Index: clang/test/Driver/aix-as.c
===
--- clang/test/Driver/aix-as.c
+++ clang/test/Driver/aix-as.c
@@ -9,7 +9,6 @@
 // CHECK-AS32: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" 
"powerpc-ibm-aix7.1.0.0"
 // CHECK-AS32: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS32: "-a32" 
-// CHECK-AS32: "-u" 
 // CHECK-AS32: "-many" 
 
 // Check powerpc64-ibm-aix7.1.0.0, 64-bit.
@@ -20,7 +19,6 @@
 // CHECK-AS64: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" 
"powerpc64-ibm-aix7.1.0.0"
 // CHECK-AS64: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS64: "-a64" 
-// CHECK-AS64: "-u" 
 // CHECK-AS64: "-many"
 
 // Check powerpc-ibm-aix7.1.0.0, 32-bit. -Xassembler  option. 
@@ -32,7 +30,6 @@
 // CHECK-AS32-Xassembler: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" 
"powerpc-ibm-aix7.1.0.0"
 // CHECK-AS32-Xassembler: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS32-Xassembler: "-a32" 
-// CHECK-AS32-Xassembler: "-u" 
 // CHECK-AS32-Xassembler: "-many"
 // CHECK-AS32-Xassembler: "-w"
 
@@ -45,7 +42,6 @@
 // CHECK-AS64-Wa: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" 
"powerpc64-ibm-aix7.1.0.0"
 // CHECK-AS64-Wa: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS64-Wa: "-a64" 
-// CHECK-AS64-Wa: "-u" 
 // CHECK-AS64-Wa: "-many"
 // CHECK-AS64-Wa: "-v"
 // CHECK-AS64-Wa: "-w"
@@ -60,13 +56,10 @@
 // CHECK-AS32-MultiInput-NOT: warning:
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
Index: clang/lib/Driver/ToolChains/AIX.cpp
===
--- clang/lib/Driver/ToolChains/AIX.cpp
+++ clang/lib/Driver/ToolChains/AIX.cpp
@@ -44,12 +44,6 @@
 CmdArgs.push_back("-a64");
   }
 
-  // Accept an undefined symbol as an extern so that an error message is not
-  // displayed. Otherwise, undefined symbols are flagged with error messages.
-  // FIXME: This should be removed when the assembly generation from the
-  // compiler is able to write externs properly.
-  CmdArgs.push_back("-u");
-
   // Accept any mixture of instructions.
   // On Power for AIX and Linux, this behaviour matches that of GCC for both 
the
   // user-provided assembler source case and the compiler-produced assembler


Index: clang/test/Driver/aix-as.c
===
--- clang/test/Driver/aix-as.c
+++ clang/test/Driver/aix-as.c
@@ -9,7 +9,6 @@
 // CHECK-AS32: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" "powerpc-ibm-aix7.1.0.0"
 // CHECK-AS32: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS32: "-a32" 
-// CHECK-AS32: "-u" 
 // CHECK-AS32: "-many" 
 
 // Check powerpc64-ibm-aix7.1.0.0, 64-bit.
@@ -20,7 +19,6 @@
 // CHECK-AS64: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" "powerpc64-ibm-aix7.1.0.0"
 // CHECK-AS64: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS64: "-a64" 
-// CHECK-AS64: "-u" 
 // CHECK-AS64: "-many"
 
 // Check powerpc-ibm-aix7.1.0.0, 32-bit. -Xassembler  option. 
@@ -32,7 +30,6 @@
 // CHECK-AS32-Xassembler: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" "powerpc-ibm-aix7.1.0.0"
 // CHECK-AS32-Xassembler: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS32-Xassembler: "-a32" 
-// CHECK-AS32-Xassembler: "-u" 
 // CHECK-AS32-Xassembler: "-many"
 // CHECK-AS32-Xassembler: "-w"
 
@@ -45,7 +42,6 @@
 // CHECK-AS64-Wa: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" "powerpc64-ibm-aix7.1.0.0"
 // CHECK-AS64-Wa: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS64-Wa: "-a64" 
-// CHECK-AS64-Wa: "-u" 
 // CHECK-AS64-Wa: "-many"
 // CHECK-AS64-Wa: "-v"
 // CHECK-AS64-Wa: "-w"
@@ -60,13 +56,10 @@
 // CHECK-AS32-MultiInput-NOT: warning:
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
Index: clang/lib/Driver/ToolChains/AIX.cpp
===
--- clang/lib/Driver/ToolChains/AIX.cpp
+++ clang/lib/Driver/ToolChains/AIX.cpp
@@ -44,12 +44,6 @@
 CmdArgs.push_back("-a64");
   }
 
-  // Accept an 

[PATCH] D84356: [AIX] remote -u from the clang when invoke aix as assembler

[Digger via Phabricator via cfe-commits]

DiggerLin created this revision.
DiggerLin added reviewers: jasonliu, yuanwu, hubert.reinterpretcast.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D84356

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c


Index: clang/test/Driver/aix-as.c
===
--- clang/test/Driver/aix-as.c
+++ clang/test/Driver/aix-as.c
@@ -9,7 +9,6 @@
 // CHECK-AS32: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" 
"powerpc-ibm-aix7.1.0.0"
 // CHECK-AS32: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS32: "-a32" 
-// CHECK-AS32: "-u" 
 // CHECK-AS32: "-many" 
 
 // Check powerpc64-ibm-aix7.1.0.0, 64-bit.
@@ -20,7 +19,6 @@
 // CHECK-AS64: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" 
"powerpc64-ibm-aix7.1.0.0"
 // CHECK-AS64: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS64: "-a64" 
-// CHECK-AS64: "-u" 
 // CHECK-AS64: "-many"
 
 // Check powerpc-ibm-aix7.1.0.0, 32-bit. -Xassembler  option. 
@@ -32,7 +30,6 @@
 // CHECK-AS32-Xassembler: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" 
"powerpc-ibm-aix7.1.0.0"
 // CHECK-AS32-Xassembler: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS32-Xassembler: "-a32" 
-// CHECK-AS32-Xassembler: "-u" 
 // CHECK-AS32-Xassembler: "-many"
 // CHECK-AS32-Xassembler: "-w"
 
@@ -45,7 +42,6 @@
 // CHECK-AS64-Wa: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" 
"powerpc64-ibm-aix7.1.0.0"
 // CHECK-AS64-Wa: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS64-Wa: "-a64" 
-// CHECK-AS64-Wa: "-u" 
 // CHECK-AS64-Wa: "-many"
 // CHECK-AS64-Wa: "-v"
 // CHECK-AS64-Wa: "-w"
@@ -60,13 +56,10 @@
 // CHECK-AS32-MultiInput-NOT: warning:
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
Index: clang/lib/Driver/ToolChains/AIX.cpp
===
--- clang/lib/Driver/ToolChains/AIX.cpp
+++ clang/lib/Driver/ToolChains/AIX.cpp
@@ -44,12 +44,6 @@
 CmdArgs.push_back("-a64");
   }
 
-  // Accept an undefined symbol as an extern so that an error message is not
-  // displayed. Otherwise, undefined symbols are flagged with error messages.
-  // FIXME: This should be removed when the assembly generation from the
-  // compiler is able to write externs properly.
-  CmdArgs.push_back("-u");
-
   // Accept any mixture of instructions.
   // On Power for AIX and Linux, this behaviour matches that of GCC for both 
the
   // user-provided assembler source case and the compiler-produced assembler


Index: clang/test/Driver/aix-as.c
===
--- clang/test/Driver/aix-as.c
+++ clang/test/Driver/aix-as.c
@@ -9,7 +9,6 @@
 // CHECK-AS32: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" "powerpc-ibm-aix7.1.0.0"
 // CHECK-AS32: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS32: "-a32" 
-// CHECK-AS32: "-u" 
 // CHECK-AS32: "-many" 
 
 // Check powerpc64-ibm-aix7.1.0.0, 64-bit.
@@ -20,7 +19,6 @@
 // CHECK-AS64: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" "powerpc64-ibm-aix7.1.0.0"
 // CHECK-AS64: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS64: "-a64" 
-// CHECK-AS64: "-u" 
 // CHECK-AS64: "-many"
 
 // Check powerpc-ibm-aix7.1.0.0, 32-bit. -Xassembler  option. 
@@ -32,7 +30,6 @@
 // CHECK-AS32-Xassembler: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" "powerpc-ibm-aix7.1.0.0"
 // CHECK-AS32-Xassembler: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS32-Xassembler: "-a32" 
-// CHECK-AS32-Xassembler: "-u" 
 // CHECK-AS32-Xassembler: "-many"
 // CHECK-AS32-Xassembler: "-w"
 
@@ -45,7 +42,6 @@
 // CHECK-AS64-Wa: {{.*}}clang{{(.exe)?}}" "-cc1" "-triple" "powerpc64-ibm-aix7.1.0.0"
 // CHECK-AS64-Wa: "{{.*}}as{{(.exe)?}}" 
 // CHECK-AS64-Wa: "-a64" 
-// CHECK-AS64-Wa: "-u" 
 // CHECK-AS64-Wa: "-many"
 // CHECK-AS64-Wa: "-v"
 // CHECK-AS64-Wa: "-w"
@@ -60,13 +56,10 @@
 // CHECK-AS32-MultiInput-NOT: warning:
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
 // CHECK-AS32-MultiInput: "{{.*}}as{{(.exe)?}}"
 // CHECK-AS32-MultiInput: "-a32"
-// CHECK-AS32-MultiInput: "-u"
 // CHECK-AS32-MultiInput: "-many"
Index: clang/lib/Driver/ToolChains/AIX.cpp
===
--- clang/lib/Driver/ToolChains/AIX.cpp
+++ clang/lib/Driver/ToolChains/AIX.cpp
@@ -44,12 +44,6 @@
 CmdArgs.push_back("-a64");
   }
 
-  // Accept an undefined symbol as an extern so that an error message is not
-  // displayed. 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa2c8cd18128d: [AIX] emit .extern and .weak directive linkage 
(authored by DiggerLin).

Changed prior to commit:
  https://reviews.llvm.org/D76932?vs=261004=261219#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -36,7 +36,7 @@
 ; OBJ-NEXT:   NumberOfSections: 2
 ; OBJ-NEXT:   TimeStamp: None (0x0)
 ; OBJ-NEXT:   SymbolTableOffset: 0x13C
-; OBJ-NEXT:   SymbolTableEntries: 24
+; OBJ-NEXT:   SymbolTableEntries: 26
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
@@ -86,7 +86,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1A
-; RELOC-NEXT: Symbol: globalA (20)
+; RELOC-NEXT: Symbol: globalA (22)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -94,7 +94,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1E
-; RELOC-NEXT: Symbol: globalB (22)
+; RELOC-NEXT: Symbol: globalB (24)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -104,7 +104,7 @@
 ; RELOC-NEXT: Section (index: 2) .data {
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x70
-; RELOC-NEXT:   Symbol: arr (12)
+; RELOC-NEXT:   Symbol: arr (14)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -112,7 +112,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x74
-; RELOC-NEXT:   Symbol: .foo (4)
+; RELOC-NEXT:   Symbol: .foo (6)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -120,7 +120,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x78
-; RELOC-NEXT:   Symbol: TOC (18)
+; RELOC-NEXT:   Symbol: TOC (20)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -128,7 +128,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x80
-; RELOC-NEXT:   Symbol: globalA (8)
+; RELOC-NEXT:   Symbol: globalA (10)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -136,7 +136,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x84
-; RELOC-NEXT:   Symbol: globalB (10)
+; RELOC-NEXT:   Symbol: globalB (12)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -168,6 +168,26 @@
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
 ; SYM-NEXT: Index: 2
+; SYM-NEXT: Name: bar
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT:   Index: 3
+; SYM-NEXT:   SectionLen: 0
+; SYM-NEXT:   ParameterHashIndex: 0x0
+; SYM-NEXT:   TypeChkSectNum: 0x0
+; SYM-NEXT:   SymbolAlignmentLog2: 0
+; SYM-NEXT:   SymbolType: XTY_ER (0x0)
+; SYM-NEXT:   StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:   StabInfoIndex: 0x0
+; SYM-NEXT:   StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT: Index: 4
 ; SYM-NEXT: Name: .text
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -175,7 +195,7 @@
 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT: NumberOfAuxEntries: 1
 ; SYM-NEXT: CSECT Auxiliary Entry {
-; SYM-NEXT:   Index: 3
+; SYM-NEXT:   Index: 5
 ; SYM-NEXT:   SectionLen: 64
 ; SYM-NEXT:   ParameterHashIndex: 0x0
 ; SYM-NEXT:   TypeChkSectNum: 0x0
@@ -187,7 +207,7 @@
 ; SYM-NEXT: }
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
-; SYM-NEXT: Index: 4
+; SYM-NEXT: Index: 6
 ; SYM-NEXT: Name: .foo
 ; SYM-NEXT: Value 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 261004.
DiggerLin marked an inline comment as done.
DiggerLin added a comment.

take out the functionality  of "remove -u from clang"


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -36,7 +36,7 @@
 ; OBJ-NEXT:   NumberOfSections: 2
 ; OBJ-NEXT:   TimeStamp: None (0x0)
 ; OBJ-NEXT:   SymbolTableOffset: 0x13C
-; OBJ-NEXT:   SymbolTableEntries: 24
+; OBJ-NEXT:   SymbolTableEntries: 26
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
@@ -86,7 +86,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1A
-; RELOC-NEXT: Symbol: globalA (20)
+; RELOC-NEXT: Symbol: globalA (22)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -94,7 +94,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1E
-; RELOC-NEXT: Symbol: globalB (22)
+; RELOC-NEXT: Symbol: globalB (24)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -104,7 +104,7 @@
 ; RELOC-NEXT: Section (index: 2) .data {
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x70
-; RELOC-NEXT:   Symbol: arr (12)
+; RELOC-NEXT:   Symbol: arr (14)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -112,7 +112,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x74
-; RELOC-NEXT:   Symbol: .foo (4)
+; RELOC-NEXT:   Symbol: .foo (6)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -120,7 +120,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x78
-; RELOC-NEXT:   Symbol: TOC (18)
+; RELOC-NEXT:   Symbol: TOC (20)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -128,7 +128,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x80
-; RELOC-NEXT:   Symbol: globalA (8)
+; RELOC-NEXT:   Symbol: globalA (10)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -136,7 +136,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x84
-; RELOC-NEXT:   Symbol: globalB (10)
+; RELOC-NEXT:   Symbol: globalB (12)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -168,6 +168,26 @@
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
 ; SYM-NEXT: Index: 2
+; SYM-NEXT: Name: bar
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT:   Index: 3
+; SYM-NEXT:   SectionLen: 0
+; SYM-NEXT:   ParameterHashIndex: 0x0
+; SYM-NEXT:   TypeChkSectNum: 0x0
+; SYM-NEXT:   SymbolAlignmentLog2: 0
+; SYM-NEXT:   SymbolType: XTY_ER (0x0)
+; SYM-NEXT:   StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:   StabInfoIndex: 0x0
+; SYM-NEXT:   StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT: Index: 4
 ; SYM-NEXT: Name: .text
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -175,7 +195,7 @@
 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT: NumberOfAuxEntries: 1
 ; SYM-NEXT: CSECT Auxiliary Entry {
-; SYM-NEXT:   Index: 3
+; SYM-NEXT:   Index: 5
 ; SYM-NEXT:   SectionLen: 64
 ; SYM-NEXT:   ParameterHashIndex: 0x0
 ; SYM-NEXT:   TypeChkSectNum: 0x0
@@ -187,7 +207,7 @@
 ; SYM-NEXT: }
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
-; SYM-NEXT: Index: 4
+; SYM-NEXT: Index: 6
 ; SYM-NEXT: Name: .foo
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -195,8 +215,8 @@
 ; SYM-NEXT: 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 259057.
DiggerLin marked an inline comment as done.
DiggerLin added a comment.

address comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -36,7 +36,7 @@
 ; OBJ-NEXT:   NumberOfSections: 2
 ; OBJ-NEXT:   TimeStamp: None (0x0)
 ; OBJ-NEXT:   SymbolTableOffset: 0x13C
-; OBJ-NEXT:   SymbolTableEntries: 24
+; OBJ-NEXT:   SymbolTableEntries: 26
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
@@ -86,7 +86,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1A
-; RELOC-NEXT: Symbol: globalA (20)
+; RELOC-NEXT: Symbol: globalA (22)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -94,7 +94,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1E
-; RELOC-NEXT: Symbol: globalB (22)
+; RELOC-NEXT: Symbol: globalB (24)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -104,7 +104,7 @@
 ; RELOC-NEXT: Section (index: 2) .data {
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x70
-; RELOC-NEXT:   Symbol: arr (12)
+; RELOC-NEXT:   Symbol: arr (14)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -112,7 +112,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x74
-; RELOC-NEXT:   Symbol: .foo (4)
+; RELOC-NEXT:   Symbol: .foo (6)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -120,7 +120,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x78
-; RELOC-NEXT:   Symbol: TOC (18)
+; RELOC-NEXT:   Symbol: TOC (20)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -128,7 +128,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x80
-; RELOC-NEXT:   Symbol: globalA (8)
+; RELOC-NEXT:   Symbol: globalA (10)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -136,7 +136,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x84
-; RELOC-NEXT:   Symbol: globalB (10)
+; RELOC-NEXT:   Symbol: globalB (12)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -168,6 +168,26 @@
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
 ; SYM-NEXT: Index: 2
+; SYM-NEXT: Name: bar
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT:   Index: 3
+; SYM-NEXT:   SectionLen: 0
+; SYM-NEXT:   ParameterHashIndex: 0x0
+; SYM-NEXT:   TypeChkSectNum: 0x0
+; SYM-NEXT:   SymbolAlignmentLog2: 0
+; SYM-NEXT:   SymbolType: XTY_ER (0x0)
+; SYM-NEXT:   StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:   StabInfoIndex: 0x0
+; SYM-NEXT:   StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT: Index: 4
 ; SYM-NEXT: Name: .text
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -175,7 +195,7 @@
 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT: NumberOfAuxEntries: 1
 ; SYM-NEXT: CSECT Auxiliary Entry {
-; SYM-NEXT:   Index: 3
+; SYM-NEXT:   Index: 5
 ; SYM-NEXT:   SectionLen: 64
 ; SYM-NEXT:   ParameterHashIndex: 0x0
 ; SYM-NEXT:   TypeChkSectNum: 0x0
@@ -187,7 +207,7 @@
 ; SYM-NEXT: }
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
-; SYM-NEXT: Index: 4
+; SYM-NEXT: Index: 6
 ; SYM-NEXT: Name: .foo
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin marked 2 inline comments as done.
DiggerLin added inline comments.



Comment at: llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp:2146
   }
 }
 

hubert.reinterpretcast wrote:
> Replicate the
> ```
> llvm_unreachable("Unknown linkage type!");
> ```
> here before falling off the end of a function that does not return `void`.
thanks



Comment at: llvm/test/CodeGen/PowerPC/aix-extern-weak.ll:45
+
+; CHECK-NOT:  .weak   .foo_ext_weak_ref
+; COMMON: .csect  .data[RW]

hubert.reinterpretcast wrote:
> This has a prefix that is not checked by the `RUN` lines. Note also that it 
> would only prevent the appearance of the subject line until the next positive 
> match. Running FileCheck a second time on the same output may be necessary to 
> check that it does not appear anywhere in an active manner. The passive 
> method is to count on the block of `COMMON-NEXT` to exclude it.
thanks for let me know


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[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 258732.
DiggerLin marked 2 inline comments as done.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -36,7 +36,7 @@
 ; OBJ-NEXT:   NumberOfSections: 2
 ; OBJ-NEXT:   TimeStamp: None (0x0)
 ; OBJ-NEXT:   SymbolTableOffset: 0x13C
-; OBJ-NEXT:   SymbolTableEntries: 24
+; OBJ-NEXT:   SymbolTableEntries: 26
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
@@ -86,7 +86,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1A
-; RELOC-NEXT: Symbol: globalA (20)
+; RELOC-NEXT: Symbol: globalA (22)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -94,7 +94,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1E
-; RELOC-NEXT: Symbol: globalB (22)
+; RELOC-NEXT: Symbol: globalB (24)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -104,7 +104,7 @@
 ; RELOC-NEXT: Section (index: 2) .data {
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x70
-; RELOC-NEXT:   Symbol: arr (12)
+; RELOC-NEXT:   Symbol: arr (14)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -112,7 +112,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x74
-; RELOC-NEXT:   Symbol: .foo (4)
+; RELOC-NEXT:   Symbol: .foo (6)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -120,7 +120,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x78
-; RELOC-NEXT:   Symbol: TOC (18)
+; RELOC-NEXT:   Symbol: TOC (20)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -128,7 +128,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x80
-; RELOC-NEXT:   Symbol: globalA (8)
+; RELOC-NEXT:   Symbol: globalA (10)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -136,7 +136,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x84
-; RELOC-NEXT:   Symbol: globalB (10)
+; RELOC-NEXT:   Symbol: globalB (12)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -168,6 +168,26 @@
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
 ; SYM-NEXT: Index: 2
+; SYM-NEXT: Name: bar
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT:   Index: 3
+; SYM-NEXT:   SectionLen: 0
+; SYM-NEXT:   ParameterHashIndex: 0x0
+; SYM-NEXT:   TypeChkSectNum: 0x0
+; SYM-NEXT:   SymbolAlignmentLog2: 0
+; SYM-NEXT:   SymbolType: XTY_ER (0x0)
+; SYM-NEXT:   StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:   StabInfoIndex: 0x0
+; SYM-NEXT:   StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT: Index: 4
 ; SYM-NEXT: Name: .text
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -175,7 +195,7 @@
 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT: NumberOfAuxEntries: 1
 ; SYM-NEXT: CSECT Auxiliary Entry {
-; SYM-NEXT:   Index: 3
+; SYM-NEXT:   Index: 5
 ; SYM-NEXT:   SectionLen: 64
 ; SYM-NEXT:   ParameterHashIndex: 0x0
 ; SYM-NEXT:   TypeChkSectNum: 0x0
@@ -187,7 +207,7 @@
 ; SYM-NEXT: }
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
-; SYM-NEXT: Index: 4
+; SYM-NEXT: Index: 6
 ; SYM-NEXT: Name: .foo
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -195,8 +215,8 @@
 ; SYM-NEXT: StorageClass: 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 258442.
DiggerLin added a comment.

I think I address all the comments. thanks hubert.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -36,7 +36,7 @@
 ; OBJ-NEXT:   NumberOfSections: 2
 ; OBJ-NEXT:   TimeStamp: None (0x0)
 ; OBJ-NEXT:   SymbolTableOffset: 0x13C
-; OBJ-NEXT:   SymbolTableEntries: 24
+; OBJ-NEXT:   SymbolTableEntries: 26
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
@@ -86,7 +86,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1A
-; RELOC-NEXT: Symbol: globalA (20)
+; RELOC-NEXT: Symbol: globalA (22)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -94,7 +94,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1E
-; RELOC-NEXT: Symbol: globalB (22)
+; RELOC-NEXT: Symbol: globalB (24)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -104,7 +104,7 @@
 ; RELOC-NEXT: Section (index: 2) .data {
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x70
-; RELOC-NEXT:   Symbol: arr (12)
+; RELOC-NEXT:   Symbol: arr (14)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -112,7 +112,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x74
-; RELOC-NEXT:   Symbol: .foo (4)
+; RELOC-NEXT:   Symbol: .foo (6)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -120,7 +120,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x78
-; RELOC-NEXT:   Symbol: TOC (18)
+; RELOC-NEXT:   Symbol: TOC (20)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -128,7 +128,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x80
-; RELOC-NEXT:   Symbol: globalA (8)
+; RELOC-NEXT:   Symbol: globalA (10)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -136,7 +136,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x84
-; RELOC-NEXT:   Symbol: globalB (10)
+; RELOC-NEXT:   Symbol: globalB (12)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -168,6 +168,26 @@
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
 ; SYM-NEXT: Index: 2
+; SYM-NEXT: Name: bar
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT:   Index: 3
+; SYM-NEXT:   SectionLen: 0
+; SYM-NEXT:   ParameterHashIndex: 0x0
+; SYM-NEXT:   TypeChkSectNum: 0x0
+; SYM-NEXT:   SymbolAlignmentLog2: 0
+; SYM-NEXT:   SymbolType: XTY_ER (0x0)
+; SYM-NEXT:   StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:   StabInfoIndex: 0x0
+; SYM-NEXT:   StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT: Index: 4
 ; SYM-NEXT: Name: .text
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -175,7 +195,7 @@
 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT: NumberOfAuxEntries: 1
 ; SYM-NEXT: CSECT Auxiliary Entry {
-; SYM-NEXT:   Index: 3
+; SYM-NEXT:   Index: 5
 ; SYM-NEXT:   SectionLen: 64
 ; SYM-NEXT:   ParameterHashIndex: 0x0
 ; SYM-NEXT:   TypeChkSectNum: 0x0
@@ -187,7 +207,7 @@
 ; SYM-NEXT: }
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
-; SYM-NEXT: Index: 4
+; SYM-NEXT: Index: 6
 ; SYM-NEXT: Name: .foo
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -195,8 +215,8 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 258432.
DiggerLin added a comment.

handle getSymbol returning a function descriptor symbol after rebase on the 
D78045 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -36,7 +36,7 @@
 ; OBJ-NEXT:   NumberOfSections: 2
 ; OBJ-NEXT:   TimeStamp: None (0x0)
 ; OBJ-NEXT:   SymbolTableOffset: 0x13C
-; OBJ-NEXT:   SymbolTableEntries: 24
+; OBJ-NEXT:   SymbolTableEntries: 26
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
@@ -86,7 +86,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1A
-; RELOC-NEXT: Symbol: globalA (20)
+; RELOC-NEXT: Symbol: globalA (22)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -94,7 +94,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1E
-; RELOC-NEXT: Symbol: globalB (22)
+; RELOC-NEXT: Symbol: globalB (24)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -104,7 +104,7 @@
 ; RELOC-NEXT: Section (index: 2) .data {
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x70
-; RELOC-NEXT:   Symbol: arr (12)
+; RELOC-NEXT:   Symbol: arr (14)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -112,7 +112,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x74
-; RELOC-NEXT:   Symbol: .foo (4)
+; RELOC-NEXT:   Symbol: .foo (6)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -120,7 +120,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x78
-; RELOC-NEXT:   Symbol: TOC (18)
+; RELOC-NEXT:   Symbol: TOC (20)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -128,7 +128,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x80
-; RELOC-NEXT:   Symbol: globalA (8)
+; RELOC-NEXT:   Symbol: globalA (10)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -136,7 +136,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x84
-; RELOC-NEXT:   Symbol: globalB (10)
+; RELOC-NEXT:   Symbol: globalB (12)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -168,6 +168,26 @@
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
 ; SYM-NEXT: Index: 2
+; SYM-NEXT: Name: bar
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT:   Index: 3
+; SYM-NEXT:   SectionLen: 0
+; SYM-NEXT:   ParameterHashIndex: 0x0
+; SYM-NEXT:   TypeChkSectNum: 0x0
+; SYM-NEXT:   SymbolAlignmentLog2: 0
+; SYM-NEXT:   SymbolType: XTY_ER (0x0)
+; SYM-NEXT:   StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:   StabInfoIndex: 0x0
+; SYM-NEXT:   StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT: Index: 4
 ; SYM-NEXT: Name: .text
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -175,7 +195,7 @@
 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT: NumberOfAuxEntries: 1
 ; SYM-NEXT: CSECT Auxiliary Entry {
-; SYM-NEXT:   Index: 3
+; SYM-NEXT:   Index: 5
 ; SYM-NEXT:   SectionLen: 64
 ; SYM-NEXT:   ParameterHashIndex: 0x0
 ; SYM-NEXT:   TypeChkSectNum: 0x0
@@ -187,7 +207,7 @@
 ; SYM-NEXT: }
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
-; SYM-NEXT: Index: 4
+; SYM-NEXT: Index: 6
 ; SYM-NEXT: Name: .foo
 ; SYM-NEXT: Value 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin marked 7 inline comments as done.
DiggerLin added inline comments.



Comment at: llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:1496
+
+MCSymbol *Name = getSymbol();
+if (TM.getTargetTriple().isOSBinFormatXCOFF() && !F.isIntrinsic()) {

hubert.reinterpretcast wrote:
> DiggerLin wrote:
> > jasonliu wrote:
> > > This block of code and D78045 will have conflict. One of us will need to 
> > > rebase.
> > the one who land later will rebase.
> My understanding is that this would need a semantic reconciliation. I'd like 
> to see the rebase of this patch before approving. Also, this would be another 
> place to look into for the follow-up mentioned in 
> https://reviews.llvm.org/D78045?id=257331#inline-714634 @jasonliu.
rebase the patch on the D78045



Comment at: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1641
 
-  // External global variables are already handled.
-  if (GV->isDeclaration())
+  if (GV->isDeclaration()) {
+emitLinkage(GV, Csect->getQualNameSymbol());

hubert.reinterpretcast wrote:
> This should probably be `isDeclarationForLinker`. It seems we need a larger 
> followup for `AvailableExternallyLinkage` that would involve checking our 
> calls to `isDeclaration`:
> 
> ```
> define void @_Z1gv() {
> entry:
>   call void @_Z1fIiEvv()
>   ret void
> }
> 
> ; Function Attrs: inlinehint nounwind
> define available_externally void @_Z1fIiEvv() #0 {
> entry:
>   ret void
> }
> 
> attributes #0 = { inlinehint nounwind }
> ```

   bool isDeclarationForLinker() const {
 if (hasAvailableExternallyLinkage())
   return true;
 
 return isDeclaration();
   }
 
since we do not deal with AvailableExternallyLinkage in 
AsmPrinter::emitLinkage()

if change to isDeclarationForLinker here , it will hit a report_fatal_error.


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[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 258409.
DiggerLin marked 2 inline comments as done.
DiggerLin added a comment.

rebase the patch on the D78045  and address 
comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -36,7 +36,7 @@
 ; OBJ-NEXT:   NumberOfSections: 2
 ; OBJ-NEXT:   TimeStamp: None (0x0)
 ; OBJ-NEXT:   SymbolTableOffset: 0x13C
-; OBJ-NEXT:   SymbolTableEntries: 24
+; OBJ-NEXT:   SymbolTableEntries: 26
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
@@ -86,7 +86,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1A
-; RELOC-NEXT: Symbol: globalA (20)
+; RELOC-NEXT: Symbol: globalA (22)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -94,7 +94,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1E
-; RELOC-NEXT: Symbol: globalB (22)
+; RELOC-NEXT: Symbol: globalB (24)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -104,7 +104,7 @@
 ; RELOC-NEXT: Section (index: 2) .data {
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x70
-; RELOC-NEXT:   Symbol: arr (12)
+; RELOC-NEXT:   Symbol: arr (14)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -112,7 +112,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x74
-; RELOC-NEXT:   Symbol: .foo (4)
+; RELOC-NEXT:   Symbol: .foo (6)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -120,7 +120,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x78
-; RELOC-NEXT:   Symbol: TOC (18)
+; RELOC-NEXT:   Symbol: TOC (20)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -128,7 +128,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x80
-; RELOC-NEXT:   Symbol: globalA (8)
+; RELOC-NEXT:   Symbol: globalA (10)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -136,7 +136,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x84
-; RELOC-NEXT:   Symbol: globalB (10)
+; RELOC-NEXT:   Symbol: globalB (12)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -168,6 +168,26 @@
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
 ; SYM-NEXT: Index: 2
+; SYM-NEXT: Name: bar
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT:   Index: 3
+; SYM-NEXT:   SectionLen: 0
+; SYM-NEXT:   ParameterHashIndex: 0x0
+; SYM-NEXT:   TypeChkSectNum: 0x0
+; SYM-NEXT:   SymbolAlignmentLog2: 0
+; SYM-NEXT:   SymbolType: XTY_ER (0x0)
+; SYM-NEXT:   StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:   StabInfoIndex: 0x0
+; SYM-NEXT:   StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT: Index: 4
 ; SYM-NEXT: Name: .text
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -175,7 +195,7 @@
 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT: NumberOfAuxEntries: 1
 ; SYM-NEXT: CSECT Auxiliary Entry {
-; SYM-NEXT:   Index: 3
+; SYM-NEXT:   Index: 5
 ; SYM-NEXT:   SectionLen: 64
 ; SYM-NEXT:   ParameterHashIndex: 0x0
 ; SYM-NEXT:   TypeChkSectNum: 0x0
@@ -187,7 +207,7 @@
 ; SYM-NEXT: }
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
-; SYM-NEXT: Index: 4
+; SYM-NEXT: Index: 6
 ; SYM-NEXT: Name: .foo
 ; SYM-NEXT: 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 257827.
DiggerLin marked 2 inline comments as done.
DiggerLin added a comment.

address comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -36,7 +36,7 @@
 ; OBJ-NEXT:   NumberOfSections: 2
 ; OBJ-NEXT:   TimeStamp: None (0x0)
 ; OBJ-NEXT:   SymbolTableOffset: 0x13C
-; OBJ-NEXT:   SymbolTableEntries: 24
+; OBJ-NEXT:   SymbolTableEntries: 26
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
@@ -86,7 +86,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1A
-; RELOC-NEXT: Symbol: globalA (20)
+; RELOC-NEXT: Symbol: globalA (22)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -94,7 +94,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1E
-; RELOC-NEXT: Symbol: globalB (22)
+; RELOC-NEXT: Symbol: globalB (24)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -104,7 +104,7 @@
 ; RELOC-NEXT: Section (index: 2) .data {
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x70
-; RELOC-NEXT:   Symbol: arr (12)
+; RELOC-NEXT:   Symbol: arr (14)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -112,7 +112,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x74
-; RELOC-NEXT:   Symbol: .foo (4)
+; RELOC-NEXT:   Symbol: .foo (6)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -120,7 +120,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x78
-; RELOC-NEXT:   Symbol: TOC (18)
+; RELOC-NEXT:   Symbol: TOC (20)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -128,7 +128,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x80
-; RELOC-NEXT:   Symbol: globalA (8)
+; RELOC-NEXT:   Symbol: globalA (10)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -136,7 +136,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x84
-; RELOC-NEXT:   Symbol: globalB (10)
+; RELOC-NEXT:   Symbol: globalB (12)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -168,6 +168,26 @@
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
 ; SYM-NEXT: Index: 2
+; SYM-NEXT: Name: bar
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT:   Index: 3
+; SYM-NEXT:   SectionLen: 0
+; SYM-NEXT:   ParameterHashIndex: 0x0
+; SYM-NEXT:   TypeChkSectNum: 0x0
+; SYM-NEXT:   SymbolAlignmentLog2: 0
+; SYM-NEXT:   SymbolType: XTY_ER (0x0)
+; SYM-NEXT:   StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:   StabInfoIndex: 0x0
+; SYM-NEXT:   StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT: Index: 4
 ; SYM-NEXT: Name: .text
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -175,7 +195,7 @@
 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT: NumberOfAuxEntries: 1
 ; SYM-NEXT: CSECT Auxiliary Entry {
-; SYM-NEXT:   Index: 3
+; SYM-NEXT:   Index: 5
 ; SYM-NEXT:   SectionLen: 64
 ; SYM-NEXT:   ParameterHashIndex: 0x0
 ; SYM-NEXT:   TypeChkSectNum: 0x0
@@ -187,7 +207,7 @@
 ; SYM-NEXT: }
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
-; SYM-NEXT: Index: 4
+; SYM-NEXT: Index: 6
 ; SYM-NEXT: Name: .foo
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin marked 8 inline comments as done.
DiggerLin added inline comments.



Comment at: llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:441
+  case GlobalValue::ExternalWeakLinkage:
+if (TM.getTargetTriple().isOSBinFormatXCOFF()) {
+  OutStreamer->emitSymbolAttribute(GVSym, MCSA_Weak);

jasonliu wrote:
> Maybe an assert on isOSBinFormatXCOFF is better?
> If not, could we remove the else and llvm_unreachable to let it fall through? 
> Will it have warnings?
> Or we could just only remove `else` here.
yes. remove else , and let it fall through , there is a warning.



Comment at: llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:1496
+
+MCSymbol *Name = getSymbol();
+if (TM.getTargetTriple().isOSBinFormatXCOFF() && !F.isIntrinsic()) {

jasonliu wrote:
> This block of code and D78045 will have conflict. One of us will need to 
> rebase.
the one who land later will rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932



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[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 257473.
DiggerLin added a comment.

address comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll
  llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Index: llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
===
--- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -36,7 +36,7 @@
 ; OBJ-NEXT:   NumberOfSections: 2
 ; OBJ-NEXT:   TimeStamp: None (0x0)
 ; OBJ-NEXT:   SymbolTableOffset: 0x13C
-; OBJ-NEXT:   SymbolTableEntries: 24
+; OBJ-NEXT:   SymbolTableEntries: 26
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
@@ -86,7 +86,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1A
-; RELOC-NEXT: Symbol: globalA (20)
+; RELOC-NEXT: Symbol: globalA (22)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -94,7 +94,7 @@
 ; RELOC-NEXT:   }
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT: Virtual Address: 0x1E
-; RELOC-NEXT: Symbol: globalB (22)
+; RELOC-NEXT: Symbol: globalB (24)
 ; RELOC-NEXT: IsSigned: No
 ; RELOC-NEXT: FixupBitValue: 0
 ; RELOC-NEXT: Length: 16
@@ -104,7 +104,7 @@
 ; RELOC-NEXT: Section (index: 2) .data {
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x70
-; RELOC-NEXT:   Symbol: arr (12)
+; RELOC-NEXT:   Symbol: arr (14)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -112,7 +112,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x74
-; RELOC-NEXT:   Symbol: .foo (4)
+; RELOC-NEXT:   Symbol: .foo (6)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -120,7 +120,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x78
-; RELOC-NEXT:   Symbol: TOC (18)
+; RELOC-NEXT:   Symbol: TOC (20)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -128,7 +128,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x80
-; RELOC-NEXT:   Symbol: globalA (8)
+; RELOC-NEXT:   Symbol: globalA (10)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -136,7 +136,7 @@
 ; RELOC-NEXT: }
 ; RELOC-NEXT: Relocation {
 ; RELOC-NEXT:   Virtual Address: 0x84
-; RELOC-NEXT:   Symbol: globalB (10)
+; RELOC-NEXT:   Symbol: globalB (12)
 ; RELOC-NEXT:   IsSigned: No
 ; RELOC-NEXT:   FixupBitValue: 0
 ; RELOC-NEXT:   Length: 32
@@ -168,6 +168,26 @@
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
 ; SYM-NEXT: Index: 2
+; SYM-NEXT: Name: bar
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT:   Index: 3
+; SYM-NEXT:   SectionLen: 0
+; SYM-NEXT:   ParameterHashIndex: 0x0
+; SYM-NEXT:   TypeChkSectNum: 0x0
+; SYM-NEXT:   SymbolAlignmentLog2: 0
+; SYM-NEXT:   SymbolType: XTY_ER (0x0)
+; SYM-NEXT:   StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:   StabInfoIndex: 0x0
+; SYM-NEXT:   StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT: Index: 4
 ; SYM-NEXT: Name: .text
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -175,7 +195,7 @@
 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT: NumberOfAuxEntries: 1
 ; SYM-NEXT: CSECT Auxiliary Entry {
-; SYM-NEXT:   Index: 3
+; SYM-NEXT:   Index: 5
 ; SYM-NEXT:   SectionLen: 64
 ; SYM-NEXT:   ParameterHashIndex: 0x0
 ; SYM-NEXT:   TypeChkSectNum: 0x0
@@ -187,7 +207,7 @@
 ; SYM-NEXT: }
 ; SYM-NEXT:   }
 ; SYM-NEXT:   Symbol {
-; SYM-NEXT: Index: 4
+; SYM-NEXT: Index: 6
 ; SYM-NEXT: Name: .foo
 ; SYM-NEXT: Value (RelocatableAddress): 0x0
 ; SYM-NEXT: Section: .text
@@ -195,8 +215,8 @@
 ; SYM-NEXT: StorageClass: 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 257319.
DiggerLin marked 2 inline comments as done.
DiggerLin added a comment.

address comment and add a new test case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-linkage.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll

Index: llvm/test/CodeGen/PowerPC/aix-weak.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-weak.ll
@@ -0,0 +1,358 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj  --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
+
+@foo_weak_p = global void (...)* bitcast (void ()* @foo_ref_weak to void (...)*), align 4
+@b = weak global i32 0, align 4
+
+define weak void @foo_weak(i32* %p)  {
+entry:
+  %p.addr = alloca i32*, align 4
+  store i32* %p, i32** %p.addr, align 4
+  %0 = load i32*, i32** %p.addr, align 4
+  %1 = load i32, i32* %0, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* %0, align 4
+  ret void
+}
+
+define weak void @foo_ref_weak()  {
+entry:
+  ret void
+}
+
+define i32 @main()  {
+entry:
+  %0 = load void (...)*, void (...)** @foo_weak_p, align 4
+  %callee.knr.cast = bitcast void (...)* %0 to void ()*
+  call void %callee.knr.cast()
+  call void @foo_weak(i32* @b)
+  call void @foo_ref_weak()
+  ret i32 0
+}
+
+; COMMON:  	.weak	foo_weak[DS]# -- Begin function foo_weak
+; COMMON-NEXT:  .weak	.foo_weak
+; COMMON-NEXT:  .align	4
+; COMMON-NEXT:  .csect foo_weak[DS]
+; BIT32-NEXT:   .long	.foo_weak   # @foo_weak
+; BIT32-NEXT:   .long	TOC[TC0]
+; BIT32-NEXT:   .long	0
+; BIT64-NEXT:   .llong	.foo_weak   # @foo_weak
+; BIT64-NEXT:   .llong	TOC[TC0]
+; BIT64-NEXT:   .llong	0
+; COMMON-NEXT:  .csect .text[PR]
+; COMMON-NEXT:  .foo_weak:
+
+; COMMON:	.weak	foo_ref_weak[DS]# -- Begin function foo_ref_weak
+; COMMON-NEXT:  .weak	.foo_ref_weak
+; COMMON-NEXT:  .align	4
+; COMMON-NEXT:  .csect foo_ref_weak[DS]
+; BIT32-NEXT:   .long	.foo_ref_weak   # @foo_ref_weak
+; BIT32-NEXT:   .long	TOC[TC0]
+; BIT32-NEXT:   .long	0
+; BIT64-NEXT:   .llong	.foo_ref_weak   # @foo_ref_weak
+; BIT64-NEXT:   .llong	TOC[TC0]
+; BIT64-NEXT:   .llong	0
+; COMMON-NEXT:  .csect .text[PR]
+; COMMON-NEXT:  .foo_ref_weak:
+
+; COMMON:  	.globl	main[DS]# -- Begin function main
+; COMMON-NEXT:  .globl	.main
+; COMMON-NEXT:  .align	4
+; COMMON-NEXT:  .csect main[DS]
+; BIT32-NEXT:   .long	.main   # @main
+; BIT32-NEXT:   .long	TOC[TC0]
+; BIT32-NEXT:   .long	0
+; BIT64-NEXT:   .llong	.main   # @main
+; BIT64-NEXT:   .llong	TOC[TC0]
+; BIT64-NEXT:   .llong	0
+; COMMON-NEXT:  .csect .text[PR]
+; COMMON-NEXT:  .main:
+
+; COMMON: 	.csect .data[RW]
+; COMMON-NEXT:  .globl	foo_weak_p
+; BIT32-NEXT:   .align	2
+; BIT64-NEXT:   .align	3
+; COMMON-NEXT:  foo_weak_p:
+; BIT32-NEXT:   .long	foo_ref_weak[DS]
+; BIT64-NEXT:   .llong	foo_ref_weak[DS]
+; COMMON-NEXT:  .weak	b
+; COMMON-NEXT:  .align	2
+; COMMON-NEXT:  b:
+; COMMON-NEXT:  .long	0   # 0x0
+; COMMON-NEXT:  .toc
+; COMMON-NEXT:  LC0:
+; COMMON-NEXT:  .tc foo_weak_p[TC],foo_weak_p
+; COMMON-NEXT:  LC1:
+; COMMON-NEXT:  .tc b[TC],b
+
+
+; CHECKSYM:  Symbols [
+; CHECKSYM-NEXT:   Symbol {
+; CHECKSYM-NEXT: Index: [[#Index:]]
+; CHECKSYM-NEXT: Name: .text
+; CHECKSYM-NEXT: Value 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

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DiggerLin marked 2 inline comments as done.
DiggerLin added inline comments.



Comment at: llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:1500
+  if (cast(Name)->hasContainingCsect())
+emitLinkage(, Name);
+

jasonliu wrote:
> DiggerLin wrote:
> > jasonliu wrote:
> > > 1. We need to rebase here, as it is called `hasRepresentedCsectSet()` 
> > > instead of `hasContainingCsect()` now.
> > > 2. I'm slightly worried here to rely on `hasRepresentedCsectSet()` to 
> > > check if a linkage should be emitted. This is based on the assumption 
> > > that we will not ever change our implementation for `.bl foo` to `.bl 
> > > foo[PR]`. But in https://reviews.llvm.org/D77080#inline-706207, we 
> > > discussed about this possibility. So this assumption might not be true in 
> > > the future. However, I'm not sure if there is another way to check if 
> > > this function have been called directly. 
> > > So if there is another way to check, we should pursue the alternative 
> > > instead. If there is not, then we need to add an assert here, like 
> > > `assert(Name->getName().equals(cast(Name)->getUnqualifiedName())`
> > >  to make sure we don't get a qualname here. 
> > > 3. 
> > > Have a comment here and tell people what we are doing here.
> > > For example, 
> > > // If there is a direct call to external function, then we need to emit 
> > > linkage for its function entry point. 
> > when we implement .bl foo to .bl foo[PR]
> > the SymbolName will change from .bl[SMC] and check the 
> > .bl[SMC]->hasRepresentedCsectSet()
> Yes, but foo[PR]->hasRepresentedCsectSet() will always return true, because 
> whenever we created a qualname will always have csect set. How will we know 
> if foo() function is called directly then? 
we only deal with extern function(we do not deal with definition function) 
here, for extern function, it not always has MCSectionXCOFF, it only create the 
extern function be called directly in the 
llvm/lib/CodeGen/MachineModuleInfo.cpp line 108~116, unless we delete the code 
later. if the code is not changed. for extern function foo , the .foo[PR] -> 
hasRepresentedCsectSet()  when directly call. otherwise false.


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[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

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DiggerLin updated this revision to Diff 256067.
DiggerLin marked 2 inline comments as done.
DiggerLin added a comment.

address comment and rebased the patch on D77080 
 [NFC][XCOFF][AIX] Refactor 
get/setContainingCsect


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Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll

Index: llvm/test/CodeGen/PowerPC/aix-weak.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-weak.ll
@@ -0,0 +1,358 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj  --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
+
+@foo_weak_p = global void (...)* bitcast (void ()* @foo_ref_weak to void (...)*), align 4
+@b = weak global i32 0, align 4
+
+define weak void @foo_weak(i32* %p)  {
+entry:
+  %p.addr = alloca i32*, align 4
+  store i32* %p, i32** %p.addr, align 4
+  %0 = load i32*, i32** %p.addr, align 4
+  %1 = load i32, i32* %0, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* %0, align 4
+  ret void
+}
+
+define weak void @foo_ref_weak()  {
+entry:
+  ret void
+}
+
+define i32 @main()  {
+entry:
+  %0 = load void (...)*, void (...)** @foo_weak_p, align 4
+  %callee.knr.cast = bitcast void (...)* %0 to void ()*
+  call void %callee.knr.cast()
+  call void @foo_weak(i32* @b)
+  call void @foo_ref_weak()
+  ret i32 0
+}
+
+; COMMON:  	.weak	foo_weak[DS]# -- Begin function foo_weak
+; COMMON-NEXT:  .weak	.foo_weak
+; COMMON-NEXT:  .align	4
+; COMMON-NEXT:  .csect foo_weak[DS]
+; BIT32-NEXT:   .long	.foo_weak   # @foo_weak
+; BIT32-NEXT:   .long	TOC[TC0]
+; BIT32-NEXT:   .long	0
+; BIT64-NEXT:   .llong	.foo_weak   # @foo_weak
+; BIT64-NEXT:   .llong	TOC[TC0]
+; BIT64-NEXT:   .llong	0
+; COMMON-NEXT:  .csect .text[PR]
+; COMMON-NEXT:  .foo_weak:
+
+; COMMON:	.weak	foo_ref_weak[DS]# -- Begin function foo_ref_weak
+; COMMON-NEXT:  .weak	.foo_ref_weak
+; COMMON-NEXT:  .align	4
+; COMMON-NEXT:  .csect foo_ref_weak[DS]
+; BIT32-NEXT:   .long	.foo_ref_weak   # @foo_ref_weak
+; BIT32-NEXT:   .long	TOC[TC0]
+; BIT32-NEXT:   .long	0
+; BIT64-NEXT:   .llong	.foo_ref_weak   # @foo_ref_weak
+; BIT64-NEXT:   .llong	TOC[TC0]
+; BIT64-NEXT:   .llong	0
+; COMMON-NEXT:  .csect .text[PR]
+; COMMON-NEXT:  .foo_ref_weak:
+
+; COMMON:  	.globl	main[DS]# -- Begin function main
+; COMMON-NEXT:  .globl	.main
+; COMMON-NEXT:  .align	4
+; COMMON-NEXT:  .csect main[DS]
+; BIT32-NEXT:   .long	.main   # @main
+; BIT32-NEXT:   .long	TOC[TC0]
+; BIT32-NEXT:   .long	0
+; BIT64-NEXT:   .llong	.main   # @main
+; BIT64-NEXT:   .llong	TOC[TC0]
+; BIT64-NEXT:   .llong	0
+; COMMON-NEXT:  .csect .text[PR]
+; COMMON-NEXT:  .main:
+
+; COMMON: 	.csect .data[RW]
+; COMMON-NEXT:  .globl	foo_weak_p
+; BIT32-NEXT:   .align	2
+; BIT64-NEXT:   .align	3
+; COMMON-NEXT:  foo_weak_p:
+; BIT32-NEXT:   .long	foo_ref_weak[DS]
+; BIT64-NEXT:   .llong	foo_ref_weak[DS]
+; COMMON-NEXT:  .weak	b
+; COMMON-NEXT:  .align	2
+; COMMON-NEXT:  b:
+; COMMON-NEXT:  .long	0   # 0x0
+; COMMON-NEXT:  .toc
+; COMMON-NEXT:  LC0:
+; COMMON-NEXT:  .tc foo_weak_p[TC],foo_weak_p
+; COMMON-NEXT:  LC1:
+; COMMON-NEXT:  .tc b[TC],b
+
+
+; CHECKSYM:  Symbols [
+; CHECKSYM-NEXT:   Symbol {
+; CHECKSYM-NEXT: Index: [[#Index:]]
+; CHECKSYM-NEXT: Name: 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

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DiggerLin marked 16 inline comments as done.
DiggerLin added inline comments.



Comment at: llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:1500
+  if (cast(Name)->hasContainingCsect())
+emitLinkage(, Name);
+

jasonliu wrote:
> 1. We need to rebase here, as it is called `hasRepresentedCsectSet()` instead 
> of `hasContainingCsect()` now.
> 2. I'm slightly worried here to rely on `hasRepresentedCsectSet()` to check 
> if a linkage should be emitted. This is based on the assumption that we will 
> not ever change our implementation for `.bl foo` to `.bl foo[PR]`. But in 
> https://reviews.llvm.org/D77080#inline-706207, we discussed about this 
> possibility. So this assumption might not be true in the future. However, I'm 
> not sure if there is another way to check if this function have been called 
> directly. 
> So if there is another way to check, we should pursue the alternative 
> instead. If there is not, then we need to add an assert here, like 
> `assert(Name->getName().equals(cast(Name)->getUnqualifiedName())`
>  to make sure we don't get a qualname here. 
> 3. 
> Have a comment here and tell people what we are doing here.
> For example, 
> // If there is a direct call to external function, then we need to emit 
> linkage for its function entry point. 
when we implement .bl foo to .bl foo[PR]
the SymbolName will change from .bl[SMC] and check the 
.bl[SMC]->hasRepresentedCsectSet()



Comment at: llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll:10
+  ret void
+}
+

jasonliu wrote:
> Do we also want to test WeakAnyLinkage?
WeakAnyLinkage should be weak
It has been tested in aix-weak.ll

define weak void @foo_weak(i32* %p)  {
entry:
  %p.addr = alloca i32*, align 4
  store i32* %p, i32** %p.addr, align 4
  %0 = load i32*, i32** %p.addr, align 4
  %1 = load i32, i32* %0, align 4
  %inc = add nsw i32 %1, 1
  store i32 %inc, i32* %0, align 4
  ret void
} 



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DiggerLin added inline comments.



Comment at: llvm/lib/MC/MCXCOFFStreamer.cpp:48
+Symbol->setStorageClass(XCOFF::C_WEAKEXT);
+Symbol->setExternal(true);
+break;

jasonliu wrote:
> Maybe we should just move `Symbol->setExternal(true);` outside of the switch, 
> as it is set for every attribute that we are going to emit. 
I think there is Symbol->setExternal(false ) in other switch cases later . 



Comment at: llvm/lib/MC/XCOFFObjectWriter.cpp:351
+  if (nameShouldBeInStringTable(ContainingCsect->getSectionName()))
+Strings.add(ContainingCsect->getSectionName());
+}

jasonliu wrote:
> We should `continue` here if the rest of the logic does not matter. 
thanks.


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[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

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DiggerLin updated this revision to Diff 254846.
DiggerLin marked 7 inline comments as done.
DiggerLin added a comment.

1. address comment
2. add two new test cases.
3. split a bit test case into three small test case.


Repository:
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Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-LinkOnceAnyLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-LinkOnceODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-WeakODRLinkage.ll
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-extern.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
  llvm/test/CodeGen/PowerPC/aix-weak.ll

Index: llvm/test/CodeGen/PowerPC/aix-weak.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-weak.ll
@@ -0,0 +1,358 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj  --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
+
+@foo_weak_p = global void (...)* bitcast (void ()* @foo_ref_weak to void (...)*), align 4
+@b = weak global i32 0, align 4
+
+define weak void @foo_weak(i32* %p)  {
+entry:
+  %p.addr = alloca i32*, align 4
+  store i32* %p, i32** %p.addr, align 4
+  %0 = load i32*, i32** %p.addr, align 4
+  %1 = load i32, i32* %0, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* %0, align 4
+  ret void
+}
+
+define weak void @foo_ref_weak()  {
+entry:
+  ret void
+}
+
+define i32 @main()  {
+entry:
+  %0 = load void (...)*, void (...)** @foo_weak_p, align 4
+  %callee.knr.cast = bitcast void (...)* %0 to void ()*
+  call void %callee.knr.cast()
+  call void @foo_weak(i32* @b)
+  call void @foo_ref_weak()
+  ret i32 0
+}
+
+; COMMON:  	.weak	foo_weak[DS]# -- Begin function foo_weak
+; COMMON-NEXT:  .weak	.foo_weak
+; COMMON-NEXT:  .align	4
+; COMMON-NEXT:  .csect foo_weak[DS]
+; BIT32-NEXT:   .long	.foo_weak   # @foo_weak
+; BIT32-NEXT:   .long	TOC[TC0]
+; BIT32-NEXT:   .long	0
+; BIT64-NEXT:   .llong	.foo_weak   # @foo_weak
+; BIT64-NEXT:   .llong	TOC[TC0]
+; BIT64-NEXT:   .llong	0
+; COMMON-NEXT:  .csect .text[PR]
+; COMMON-NEXT:  .foo_weak:
+
+; COMMON:	.weak	foo_ref_weak[DS]# -- Begin function foo_ref_weak
+; COMMON-NEXT:  .weak	.foo_ref_weak
+; COMMON-NEXT:  .align	4
+; COMMON-NEXT:  .csect foo_ref_weak[DS]
+; BIT32-NEXT:   .long	.foo_ref_weak   # @foo_ref_weak
+; BIT32-NEXT:   .long	TOC[TC0]
+; BIT32-NEXT:   .long	0
+; BIT64-NEXT:   .llong	.foo_ref_weak   # @foo_ref_weak
+; BIT64-NEXT:   .llong	TOC[TC0]
+; BIT64-NEXT:   .llong	0
+; COMMON-NEXT:  .csect .text[PR]
+; COMMON-NEXT:  .foo_ref_weak:
+
+; COMMON:  	.globl	main[DS]# -- Begin function main
+; COMMON-NEXT:  .globl	.main
+; COMMON-NEXT:  .align	4
+; COMMON-NEXT:  .csect main[DS]
+; BIT32-NEXT:   .long	.main   # @main
+; BIT32-NEXT:   .long	TOC[TC0]
+; BIT32-NEXT:   .long	0
+; BIT64-NEXT:   .llong	.main   # @main
+; BIT64-NEXT:   .llong	TOC[TC0]
+; BIT64-NEXT:   .llong	0
+; COMMON-NEXT:  .csect .text[PR]
+; COMMON-NEXT:  .main:
+
+; COMMON: 	.csect .data[RW]
+; COMMON-NEXT:  .globl	foo_weak_p
+; BIT32-NEXT:   .align	2
+; BIT64-NEXT:   .align	3
+; COMMON-NEXT:  foo_weak_p:
+; BIT32-NEXT:   .long	foo_ref_weak[DS]
+; BIT64-NEXT:   .llong	foo_ref_weak[DS]
+; COMMON-NEXT:  .weak	b
+; COMMON-NEXT:  .align	2
+; COMMON-NEXT:  b:
+; COMMON-NEXT:  .long	0   # 0x0
+; COMMON-NEXT:  .toc
+; COMMON-NEXT:  LC0:
+; COMMON-NEXT:  .tc foo_weak_p[TC],foo_weak_p
+; COMMON-NEXT:  LC1:
+; COMMON-NEXT:  .tc b[TC],b
+
+
+; CHECKSYM:  Symbols [
+; CHECKSYM-NEXT:   Symbol {
+; CHECKSYM-NEXT: Index: [[#Index:]]
+; CHECKSYM-NEXT: Name: .text
+; CHECKSYM-NEXT: Value 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 254252.
DiggerLin marked 3 inline comments as done.
DiggerLin added a comment.

address comment


Repository:
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Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

Index: llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
===
--- llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
+++ llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
@@ -20,6 +20,7 @@
 ;CHECK-NEXT: .align  2
 ;CHECK-NEXT: bar_ptr1:
 ;CHECK-NEXT: .long   bar[DS]
+;CHECK-NEXT: .extern foo[DS]
 
 ;CHECK64: .csect .data[RW]
 ;CHECK64-NEXT: .globl  foo_ptr
@@ -30,3 +31,4 @@
 ;CHECK64-NEXT: .align  3
 ;CHECK64-NEXT:bar_ptr1:
 ;CHECK64-NEXT: .llong  bar[DS]
+;CHECK64-NEXT: .extern foo[DS]
Index: llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
@@ -0,0 +1,628 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj  --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
+
+@bar_p = global i32 (...)* @bar_ref, align 4
+@foo_weak_p = global void (...)* bitcast (void ()* @foo_ref_weak to void (...)*), align 4
+@foo_ext_weak_p = global void (...)* bitcast (void ()* @foo_ext_weak to void (...)*), align 4
+@b = weak global i32 0, align 4
+@b_e = external global i32, align 4
+
+define weak void @foo_weak() #0 {
+entry:
+  ret void
+}
+
+define weak void @foo_ref_weak() #0 {
+entry:
+  ret void
+}
+
+define void @foo() #0 {
+entry:
+  ret void
+}
+
+declare i32 @bar_ref(...) #1
+
+declare extern_weak void @foo_ext_weak() #1
+
+define i32 @main() #0 {
+entry:
+  %call = call i32 @bar_extern(i32* @b)
+  call void @foo()
+  %0 = load i32 (...)*, i32 (...)** @bar_p, align 4
+  %callee.knr.cast = bitcast i32 (...)* %0 to i32 (i32*)*
+  %call1 = call i32 %callee.knr.cast(i32* @b_e)
+  %1 = load void (...)*, void (...)** @foo_weak_p, align 4
+  %callee.knr.cast2 = bitcast void (...)* %1 to void ()*
+  call void %callee.knr.cast2()
+  %2 = load void (...)*, void (...)** @foo_ext_weak_p, align 4
+  %callee.knr.cast3 = bitcast void (...)* %2 to void ()*
+  call void %callee.knr.cast3()
+  call void @foo_weak()
+  ret i32 0
+}
+
+declare i32 @bar_extern(i32*) #1
+
+; COMMON:  	.weak	foo_weak[DS]# -- Begin function foo_weak
+; COMMON-NEXT:	.weak	.foo_weak
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo_weak[DS]
+; BIT32-NEXT:	.long	.foo_weak   # @foo_weak
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo_weak   # @foo_weak
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo_weak:
+
+; COMMON:	.weak	foo_ref_weak[DS]# -- Begin function foo_ref_weak
+; COMMON-NEXT:	.weak	.foo_ref_weak
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo_ref_weak[DS]
+; BIT32-NEXT:	.long	.foo_ref_weak   # @foo_ref_weak
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo_ref_weak   # @foo_ref_weak
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo_ref_weak:
+
+; COMMON:  	.globl	foo[DS] # -- Begin function foo
+; COMMON-NEXT:	.globl	.foo
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo[DS]
+; BIT32-NEXT:	.long	.foo# @foo
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo# @foo
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo:
+
+; COMMON:  	.globl	main[DS]# -- Begin function main
+; COMMON-NEXT:	.globl	.main
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect main[DS]
+; BIT32-NEXT:	.long	.main   # @main
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin marked 3 inline comments as done.
DiggerLin added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1548
+
+  if (XCOFFSym->hasContainingCsect()) {
+MCSymbolXCOFF *QualName =

jasonliu wrote:
> I hope we can find a better solution here. IMO, we don't even want to 
> override this function in this patch. 
> GVSym should be the right one from what caller passed in. It's caller's 
> responsibility to pass in the right GVSym. 
> When caller calls emitLinkage, we should emitLinkage. It's weird when 
> emitLinkage is called, but none is emitted (when hasContainingCsect() returns 
> false).
In the function 
``` bool AsmPrinter::doFinalization(Module ) {
  // Emit remaining GOT equivalent globals.
  emitGlobalGOTEquivs();

  // Emit visibility info for declarations
  for (const Function  : M) {
  
}
```

there is  function name .llvm.stackprotector in the M. the function is declared 
. it go to emitLinkage();

we need 
if (XCOFFSym->hasContainingCsect()) { 

}

to exclude emit linkage for function .llvm.stackprotector

I think over it , do you have any good suggestion to distinguish 
.llvm.stackprotector from other extern declared function.


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[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin marked an inline comment as done.
DiggerLin added inline comments.



Comment at: llvm/include/llvm/MC/MCDirectives.h:47
+  MCSA_WeakReference,   ///< .weak_reference (MachO)
+  MCSA_WeakDefAutoPrivate   ///< .weak_def_can_be_hidden (MachO)
 };

@hubert.reinterpretcast , @jasonliu , do we need to create a NFC patch for the 
clang format problem of the above first ?


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[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 253579.
DiggerLin added a comment.

delete -u from clang test case aix-as.c


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76932/new/

https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/test/Driver/aix-as.c
  llvm/include/llvm/CodeGen/AsmPrinter.h
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

Index: llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
===
--- llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
+++ llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
@@ -15,6 +15,7 @@
 ;CHECK-NEXT: .globl  foo_ptr
 ;CHECK-NEXT: .align  2
 ;CHECK-NEXT: foo_ptr:
+;CHECK-NEXT: .extern foo[DS]
 ;CHECK-NEXT: .long   foo[DS]
 ;CHECK-NEXT: .globl  bar_ptr1
 ;CHECK-NEXT: .align  2
@@ -25,6 +26,7 @@
 ;CHECK64-NEXT: .globl  foo_ptr
 ;CHECK64-NEXT: .align  3
 ;CHECK64-NEXT:foo_ptr:
+;CHECK64-NEXT:  .extern foo[DS]
 ;CHECK64-NEXT: .llong  foo[DS]
 ;CHECK64-NEXT: .globl  bar_ptr1
 ;CHECK64-NEXT: .align  3
Index: llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
@@ -0,0 +1,628 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj  --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
+
+@bar_p = global i32 (...)* @bar_ref, align 4
+@foo_weak_p = global void (...)* bitcast (void ()* @foo_ref_weak to void (...)*), align 4
+@foo_ext_weak_p = global void (...)* bitcast (void ()* @foo_ext_weak to void (...)*), align 4
+@b = weak global i32 0, align 4
+@b_e = external global i32, align 4
+
+define weak void @foo_weak() #0 {
+entry:
+  ret void
+}
+
+define weak void @foo_ref_weak() #0 {
+entry:
+  ret void
+}
+
+define void @foo() #0 {
+entry:
+  ret void
+}
+
+declare i32 @bar_ref(...) #1
+
+declare extern_weak void @foo_ext_weak() #1
+
+define i32 @main() #0 {
+entry:
+  %call = call i32 @bar_extern(i32* @b)
+  call void @foo()
+  %0 = load i32 (...)*, i32 (...)** @bar_p, align 4
+  %callee.knr.cast = bitcast i32 (...)* %0 to i32 (i32*)*
+  %call1 = call i32 %callee.knr.cast(i32* @b_e)
+  %1 = load void (...)*, void (...)** @foo_weak_p, align 4
+  %callee.knr.cast2 = bitcast void (...)* %1 to void ()*
+  call void %callee.knr.cast2()
+  %2 = load void (...)*, void (...)** @foo_ext_weak_p, align 4
+  %callee.knr.cast3 = bitcast void (...)* %2 to void ()*
+  call void %callee.knr.cast3()
+  call void @foo_weak()
+  ret i32 0
+}
+
+declare i32 @bar_extern(i32*) #1
+
+; COMMON:  	.weak	foo_weak[DS]# -- Begin function foo_weak
+; COMMON-NEXT:	.weak	.foo_weak
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo_weak[DS]
+; BIT32-NEXT:	.long	.foo_weak   # @foo_weak
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo_weak   # @foo_weak
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo_weak:
+
+; COMMON:	.weak	foo_ref_weak[DS]# -- Begin function foo_ref_weak
+; COMMON-NEXT:	.weak	.foo_ref_weak
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo_ref_weak[DS]
+; BIT32-NEXT:	.long	.foo_ref_weak   # @foo_ref_weak
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo_ref_weak   # @foo_ref_weak
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo_ref_weak:
+
+; COMMON:  	.globl	foo[DS] # -- Begin function foo
+; COMMON-NEXT:	.globl	.foo
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo[DS]
+; BIT32-NEXT:	.long	.foo# @foo
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo# @foo
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo:
+
+; COMMON:  	.globl	main[DS]# -- Begin function main
+; COMMON-NEXT:	.globl	.main
+; COMMON-NEXT:	.align	4
+; 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin updated this revision to Diff 253281.
DiggerLin added a comment.

clang reformat


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  llvm/include/llvm/CodeGen/AsmPrinter.h
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

Index: llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
===
--- llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
+++ llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
@@ -15,6 +15,7 @@
 ;CHECK-NEXT: .globl  foo_ptr
 ;CHECK-NEXT: .align  2
 ;CHECK-NEXT: foo_ptr:
+;CHECK-NEXT: .extern foo[DS]
 ;CHECK-NEXT: .long   foo[DS]
 ;CHECK-NEXT: .globl  bar_ptr1
 ;CHECK-NEXT: .align  2
@@ -25,6 +26,7 @@
 ;CHECK64-NEXT: .globl  foo_ptr
 ;CHECK64-NEXT: .align  3
 ;CHECK64-NEXT:foo_ptr:
+;CHECK64-NEXT:  .extern foo[DS]
 ;CHECK64-NEXT: .llong  foo[DS]
 ;CHECK64-NEXT: .globl  bar_ptr1
 ;CHECK64-NEXT: .align  3
Index: llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
@@ -0,0 +1,628 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj  --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
+
+@bar_p = global i32 (...)* @bar_ref, align 4
+@foo_weak_p = global void (...)* bitcast (void ()* @foo_ref_weak to void (...)*), align 4
+@foo_ext_weak_p = global void (...)* bitcast (void ()* @foo_ext_weak to void (...)*), align 4
+@b = weak global i32 0, align 4
+@b_e = external global i32, align 4
+
+define weak void @foo_weak() #0 {
+entry:
+  ret void
+}
+
+define weak void @foo_ref_weak() #0 {
+entry:
+  ret void
+}
+
+define void @foo() #0 {
+entry:
+  ret void
+}
+
+declare i32 @bar_ref(...) #1
+
+declare extern_weak void @foo_ext_weak() #1
+
+define i32 @main() #0 {
+entry:
+  %call = call i32 @bar_extern(i32* @b)
+  call void @foo()
+  %0 = load i32 (...)*, i32 (...)** @bar_p, align 4
+  %callee.knr.cast = bitcast i32 (...)* %0 to i32 (i32*)*
+  %call1 = call i32 %callee.knr.cast(i32* @b_e)
+  %1 = load void (...)*, void (...)** @foo_weak_p, align 4
+  %callee.knr.cast2 = bitcast void (...)* %1 to void ()*
+  call void %callee.knr.cast2()
+  %2 = load void (...)*, void (...)** @foo_ext_weak_p, align 4
+  %callee.knr.cast3 = bitcast void (...)* %2 to void ()*
+  call void %callee.knr.cast3()
+  call void @foo_weak()
+  ret i32 0
+}
+
+declare i32 @bar_extern(i32*) #1
+
+; COMMON:  	.weak	foo_weak[DS]# -- Begin function foo_weak
+; COMMON-NEXT:	.weak	.foo_weak
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo_weak[DS]
+; BIT32-NEXT:	.long	.foo_weak   # @foo_weak
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo_weak   # @foo_weak
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo_weak:
+
+; COMMON:	.weak	foo_ref_weak[DS]# -- Begin function foo_ref_weak
+; COMMON-NEXT:	.weak	.foo_ref_weak
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo_ref_weak[DS]
+; BIT32-NEXT:	.long	.foo_ref_weak   # @foo_ref_weak
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo_ref_weak   # @foo_ref_weak
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo_ref_weak:
+
+; COMMON:  	.globl	foo[DS] # -- Begin function foo
+; COMMON-NEXT:	.globl	.foo
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo[DS]
+; BIT32-NEXT:	.long	.foo# @foo
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo# @foo
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo:
+
+; COMMON:  	.globl	main[DS]# -- Begin function main
+; COMMON-NEXT:	.globl	.main
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect main[DS]
+; BIT32-NEXT:	.long	.main 

[PATCH] D76932: [AIX] emit .extern and .weak directive linkage

[Digger via Phabricator via cfe-commits]

DiggerLin created this revision.
DiggerLin added reviewers: hubert.reinterpretcast, jasonliu, sfertile, daltenty.
Herald added subscribers: cfe-commits, kbarton, hiraditya, nemanjai.
Herald added a project: clang.
DiggerLin edited the summary of this revision.
Herald added a subscriber: wuzish.
DiggerLin edited the summary of this revision.
DiggerLin edited the summary of this revision.

1. emit .extern  and .weak directive linkage
2. delete -u option for as in clang.

the c source code for test case  aix-extern-weak.ll as 
bash> cat test_extern_weak_all.c

extern int bar_extern(int* ip);
extern int bar_ref();
extern int b_e;

__attribute__ ((weak)) void foo_weak(){
}

__attribute__ ((weak)) void foo_ref_weak(){
}

extern __attribute__ ((weak)) void foo_ext_weak(void);

void foo(){ }

int (*bar_p)() = bar_ref;
void (*foo_weak_p)() = foo_ref_weak;
void (*foo_ext_weak_p)() = foo_ext_weak;

int __attribute__ ((weak)) b;
int main() {

  bar_extern();
  foo();
  bar_p(_e);
  foo_weak_p();
  foo_ext_weak_p();
  foo_weak();

}


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76932

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  llvm/include/llvm/CodeGen/AsmPrinter.h
  llvm/include/llvm/MC/MCAsmInfo.h
  llvm/include/llvm/MC/MCDirectives.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCAsmInfoXCOFF.cpp
  llvm/lib/MC/MCAsmStreamer.cpp
  llvm/lib/MC/MCXCOFFStreamer.cpp
  llvm/lib/MC/XCOFFObjectWriter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
  llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

Index: llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
===
--- llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
+++ llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
@@ -15,6 +15,7 @@
 ;CHECK-NEXT: .globl  foo_ptr
 ;CHECK-NEXT: .align  2
 ;CHECK-NEXT: foo_ptr:
+;CHECK-NEXT: .extern foo[DS]
 ;CHECK-NEXT: .long   foo[DS]
 ;CHECK-NEXT: .globl  bar_ptr1
 ;CHECK-NEXT: .align  2
@@ -25,6 +26,7 @@
 ;CHECK64-NEXT: .globl  foo_ptr
 ;CHECK64-NEXT: .align  3
 ;CHECK64-NEXT:foo_ptr:
+;CHECK64-NEXT:  .extern foo[DS]
 ;CHECK64-NEXT: .llong  foo[DS]
 ;CHECK64-NEXT: .globl  bar_ptr1
 ;CHECK64-NEXT: .align  3
Index: llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
@@ -0,0 +1,628 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj  --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
+
+@bar_p = global i32 (...)* @bar_ref, align 4
+@foo_weak_p = global void (...)* bitcast (void ()* @foo_ref_weak to void (...)*), align 4
+@foo_ext_weak_p = global void (...)* bitcast (void ()* @foo_ext_weak to void (...)*), align 4
+@b = weak global i32 0, align 4
+@b_e = external global i32, align 4
+
+define weak void @foo_weak() #0 {
+entry:
+  ret void
+}
+
+define weak void @foo_ref_weak() #0 {
+entry:
+  ret void
+}
+
+define void @foo() #0 {
+entry:
+  ret void
+}
+
+declare i32 @bar_ref(...) #1
+
+declare extern_weak void @foo_ext_weak() #1
+
+define i32 @main() #0 {
+entry:
+  %call = call i32 @bar_extern(i32* @b)
+  call void @foo()
+  %0 = load i32 (...)*, i32 (...)** @bar_p, align 4
+  %callee.knr.cast = bitcast i32 (...)* %0 to i32 (i32*)*
+  %call1 = call i32 %callee.knr.cast(i32* @b_e)
+  %1 = load void (...)*, void (...)** @foo_weak_p, align 4
+  %callee.knr.cast2 = bitcast void (...)* %1 to void ()*
+  call void %callee.knr.cast2()
+  %2 = load void (...)*, void (...)** @foo_ext_weak_p, align 4
+  %callee.knr.cast3 = bitcast void (...)* %2 to void ()*
+  call void %callee.knr.cast3()
+  call void @foo_weak()
+  ret i32 0
+}
+
+declare i32 @bar_extern(i32*) #1
+
+; COMMON:  	.weak	foo_weak[DS]# -- Begin function foo_weak
+; COMMON-NEXT:	.weak	.foo_weak
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo_weak[DS]
+; BIT32-NEXT:	.long	.foo_weak   # @foo_weak
+; BIT32-NEXT:	.long	TOC[TC0]
+; BIT32-NEXT:	.long	0
+; BIT64-NEXT:	.llong	.foo_weak   # @foo_weak
+; BIT64-NEXT:	.llong	TOC[TC0]
+; BIT64-NEXT:	.llong	0
+; COMMON-NEXT:	.csect .text[PR]
+; COMMON-NEXT:.foo_weak:
+
+; COMMON:	.weak	foo_ref_weak[DS]# -- Begin function foo_ref_weak
+; COMMON-NEXT:	.weak	.foo_ref_weak
+; COMMON-NEXT:	.align	4
+; COMMON-NEXT:	.csect foo_ref_weak[DS]
+; BIT32-NEXT:	.long