[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:3
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \
+// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \
+// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - %s | \

Jim wrote:
> zve64d has implied f and d.
I misunderstand it. Please ignore the comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158259/new/

https://reviews.llvm.org/D158259

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158402: [Clang][RISCV] Add vcreate intrinsics for RVV tuple types

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:2833
   }
+  let Name = "vcreate_v",
+  UnMaskedPolicyScheme = NonePolicy,

Can we add a blank line before this.



Comment at: clang/include/clang/Basic/riscv_vector.td:2848
+  }] in {
+// foreach type = TypeList in {
+  foreach nf = NFList in {

Does this forget to be removed?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158402/new/

https://reviews.llvm.org/D158402

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:3
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \
+// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \
+// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - %s | \

zve64d has implied f and d.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:90
+//
+vfloat32m1_t add_f32(vfloat32m1_t a, vfloat32m1_t b) {
+  return a + b;

Do we support operation for vfloat16 here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158259/new/

https://reviews.llvm.org/D158259

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157353: [RISCV] Remove pre-defined macro test for b extension. NFC.

[Jim Lin via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG767ca3a70d6d: [RISCV] Remove pre-defined macro test for b 
extension. NFC. (authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157353/new/

https://reviews.llvm.org/D157353

Files:
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -16,8 +16,6 @@
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_b {{.*$}}
-// CHECK-NOT: __riscv_bitmanip {{.*$}}
 // CHECK-NOT: __riscv_zihintntl {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -165,7 +163,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
-// CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -180,7 +177,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbb -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
-// CHECK-ZBB-NOT: __riscv_b
 // CHECK-ZBB-EXT: __riscv_zbb 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -195,7 +191,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbc -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
-// CHECK-ZBC-NOT: __riscv_b
 // CHECK-ZBC-EXT: __riscv_zbc 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -210,7 +205,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbs -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
-// CHECK-ZBS-NOT: __riscv_b
 // CHECK-ZBS-EXT: __riscv_zbs 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -16,8 +16,6 @@
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_b {{.*$}}
-// CHECK-NOT: __riscv_bitmanip {{.*$}}
 // CHECK-NOT: __riscv_zihintntl {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -165,7 +163,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
-// CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -180,7 +177,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbb -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
-// CHECK-ZBB-NOT: __riscv_b
 // CHECK-ZBB-EXT: __riscv_zbb 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -195,7 +191,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbc -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
-// CHECK-ZBC-NOT: __riscv_b
 // CHECK-ZBC-EXT: __riscv_zbc 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -210,7 +205,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbs -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
-// CHECK-ZBS-NOT: __riscv_b
 // CHECK-ZBS-EXT: __riscv_zbs 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157353: [RISCV] Remove pre-defined macro test for b extension. NFC.

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD.
Herald added a project: clang.

B extension has been removed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157353

Files:
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -16,8 +16,6 @@
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_b {{.*$}}
-// CHECK-NOT: __riscv_bitmanip {{.*$}}
 // CHECK-NOT: __riscv_zihintntl {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -165,7 +163,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
-// CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -180,7 +177,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbb -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
-// CHECK-ZBB-NOT: __riscv_b
 // CHECK-ZBB-EXT: __riscv_zbb 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -195,7 +191,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbc -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
-// CHECK-ZBC-NOT: __riscv_b
 // CHECK-ZBC-EXT: __riscv_zbc 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -210,7 +205,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbs -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
-// CHECK-ZBS-NOT: __riscv_b
 // CHECK-ZBS-EXT: __riscv_zbs 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -16,8 +16,6 @@
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_b {{.*$}}
-// CHECK-NOT: __riscv_bitmanip {{.*$}}
 // CHECK-NOT: __riscv_zihintntl {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -165,7 +163,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
-// CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -180,7 +177,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbb -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
-// CHECK-ZBB-NOT: __riscv_b
 // CHECK-ZBB-EXT: __riscv_zbb 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -195,7 +191,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbc -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
-// CHECK-ZBC-NOT: __riscv_b
 // CHECK-ZBC-EXT: __riscv_zbc 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -210,7 +205,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbs -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
-// CHECK-ZBS-NOT: __riscv_b
 // CHECK-ZBS-EXT: __riscv_zbs 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:33
+let Uses = [SSP] in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class RV_SSPop _rd, bits<5> _rs1, string opcodestr, string argstr> :

Two `let` lines can be merged?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:58
+def SSLoadX5: RV_SSPop<0b00101, 0b0, "ssload", "x5">;
+let Defs = [SSP] in {
+def SSPopChkX1: RV_SSPop<0b0, 0b1, "sspopchk", "x1">;

Add a blank line before this line.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

[Jim Lin via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1c1066797c5b: [AST] Simplify Type::isSizelessBuiltinType(). 
NFC. (authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156686/new/

https://reviews.llvm.org/D156686

Files:
  clang/lib/AST/Type.cpp


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,11 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,11 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 545921.
Jim added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156686/new/

https://reviews.llvm.org/D156686

Files:
  clang/lib/AST/Type.cpp


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,11 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,11 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Herald added subscribers: ctetreau, s.egerton, simoncook.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, wangpc.
Herald added a project: clang.

Reuse isSVESizelessBuiltinType() and isRVVSizelessBuiltinType().


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156686

Files:
  clang/lib/AST/Type.cpp


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,14 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType())
+return true;
+
+  if (isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,14 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType())
+return true;
+
+  if (isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D156507: [RISCV] Upgrade Zihintntl extension to version 1.0 and move out of experimental state.

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
jdoerfert, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, eopXD, MaskRay.
Herald added projects: clang, LLVM.

Zihintntl has been ratified from May 2023 according to 
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156507

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
  llvm/test/CodeGen/RISCV/nontemporal.ll
  llvm/test/CodeGen/RISCV/prefetch.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -1,15 +1,15 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
 
 c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntl-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc 

[PATCH] D154596: [RISCV] Fix required features checking with empty string

[Jim Lin via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8fe0449ac990: [RISCV] Fix required features checking with 
empty string (authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154596/new/

https://reviews.llvm.org/D154596

Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4481,7 +4481,7 @@
   bool FeatureMissing = false;
   SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',');
+  Features.split(ReqFeatures, ',', -1, false);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4481,7 +4481,7 @@
   bool FeatureMissing = false;
   SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',');
+  Features.split(ReqFeatures, ',', -1, false);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D154596: [RISCV] Fix required features checking with empty string

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

In D154596#4499757 , @wangpc wrote:

> In D154596#4499718 , @Jim wrote:
>
>> In D154596#4499647 , @wangpc wrote:
>>
>>> Can you give an example of intrinsic that doesn't require any extra 
>>> extension enabled?
>>
>> Like read/write csr intrinsics that we add for convenient usage doesn't need 
>> any extra extension enabled.
>
> It seems that `zicsr` is related.
> I am not opposed to this change, just out of curiosity. :-)

read/write csr is not a good example for the newest isa spec. In older isa spec 
2.2, it is included in base i extension.
Anyway. just want to add some intrinsics and them generate corresponding 
instruction that is in base i extension.
And it is reasonable if keep required feature string empty should imply no 
features/extensions required.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154596/new/

https://reviews.llvm.org/D154596

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D154596: [RISCV] Fix required features checking with empty string

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

In D154596#4499647 , @wangpc wrote:

> Can you give an example of intrinsic that doesn't require any extra extension 
> enabled?

Like read/write csr intrinsics that we add for convenient usage doesn't need 
any extra extension enabled.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154596/new/

https://reviews.llvm.org/D154596

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D154596: [RISCV] Fix required features checking with empty string

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

Kindly ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154596/new/

https://reviews.llvm.org/D154596

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D154596: [RISCV] Fix required features checking with empty string

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Herald added subscribers: jobnoorman, VincentWu, vkmr, luismarques, 
sameer.abuasal, s.egerton, benna, psnobl, PkmX, rogfer01, shiva0217, 
kito-cheng, simoncook, arichardson.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD.
Herald added a project: clang.

In our downstream, we define some intrinsics that don't require any
extension enabled. Such as

TARGET_BUILTIN(__builtin_riscv_xxx, "LiLi", "nc", "")

But `split` function's `KeepEmpty` argument isn't True. Got the error message

error: builtin requires at least one of the following extensions support to be 
enabled : ''

when we use our customized intrinsic.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154596

Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4481,7 +4481,7 @@
   bool FeatureMissing = false;
   SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',');
+  Features.split(ReqFeatures, ',', -1, false);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4481,7 +4481,7 @@
   bool FeatureMissing = false;
   SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',');
+  Features.split(ReqFeatures, ',', -1, false);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi

[Jim Lin via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG612b7e10a9af: [RISCV] Change the type of argument to clz and 
ctz from ZiZi/WiWi to iUZi/iUWi (authored by Jim).

Changed prior to commit:
  https://reviews.llvm.org/D153235?vs=532790=534425#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153235/new/

https://reviews.llvm.org/D153235

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,19 +34,22 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
 // RV64ZBB-LABEL: @clz_64(
 // RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 
false)
-// RV64ZBB-NEXT:ret i64 [[TMP1]]
+// RV64ZBB-NEXT:store i64 [[TMP1]], ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:[[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:ret i32 [[TMP2]]
 //
-long clz_64(long a) {
+int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,18 +61,21 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
-// RV64ZBB-NEXT:ret i64 [[TMP1]]
+// RV64ZBB-NEXT:store i64 [[TMP1]], ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:[[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:ret i32 [[TMP2]]
 //
-long ctz_64(long a) {
+int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -34,6 +34,6 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,10 +18,10 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb")
-TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
-TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "iUZi", "nc", "zbb|xtheadbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "iUWi", "nc", "zbb|xtheadbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "iUWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,19 +34,22 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUi/iULi

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 532790.
Jim added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153235/new/

https://reviews.llvm.org/D153235

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,7 +34,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -46,7 +46,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long clz_64(long a) {
+int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,7 +58,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
@@ -70,6 +70,6 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long ctz_64(long a) {
+int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -34,6 +34,6 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,10 +18,10 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb")
-TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
-TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "iUZi", "nc", "zbb|xtheadbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "iUWi", "nc", "zbb|xtheadbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "iUWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,7 +34,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -46,7 +46,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long clz_64(long a) {
+int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,7 +58,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
@@ -70,6 +70,6 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long ctz_64(long a) {
+int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV32ZBB-NEXT:ret i32 

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUi/iULi

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay.
Herald added a project: clang.

In clang/include/clang/Basic/Builtins.def, the argument type of __builtin_clz 
and __builtin_ctz
are defined `iUi` and __builtin_clzl and __builtin_ctzl are defined `iULi`.

clz/ctz are similar to RISC-V's clz_32 and ctz_32.
clzl/ctzl are similar to RISC-V's clz_64 and ctz_64.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153235

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,7 +34,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -46,7 +46,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long clz_64(long a) {
+long clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,7 +58,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
@@ -70,6 +70,6 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long ctz_64(long a) {
+long ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -34,6 +34,6 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,10 +18,10 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb")
-TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
-TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "iUi", "nc", "zbb|xtheadbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "iULi", "nc", "zbb|xtheadbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "iULi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,7 +34,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -46,7 +46,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long clz_64(long a) {
+long clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,7 +58,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
@@ 

[PATCH] D150945: [RISCV] Add missing test for ctz_32 on RV64

[Jim Lin via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG33d3d51d77a7: [RISCV] Add missing test for ctz_32 on RV64 
(authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150945/new/

https://reviews.llvm.org/D150945

Files:
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
+}
+
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
+}
+
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150945: [RISCV] Add missing test for ctz_32 on RV64

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Apparently, both of clz and ctz should have tests for _32 version on RV64.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150945

Files:
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
+}
+
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
+}
+
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

In D95588#3622052 , @sunshaoce wrote:

> Hello @Jim! We are developing the P extension, are you still maintaining this 
> patch? Or would you mind co-development together?

Yes, I am still on developing the P extension. But it seems spec has the issue 
https://github.com/riscv/riscv-p-spec/issues/137 need to clarify.
And some instruction (CLZ, FSR and FSRI) in Zbpbo only be aliased to B 
extension on RV32. It is complicated if P extension are enabled on RV64.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128604: [RISCV] Support Zbpbo extension v0.9.11

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:471
+   Sched<[WriteCMix, ReadCMix, ReadCMix, ReadCMix]>;
 def FSR  : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>;

FSR and FSRI only exist on RV32 for Zbpbo.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:492
+
+let Predicates = [HasStdExtZbbOrZbpbo] in
 def CLZ  : RVBUnary<0b011, 0b0, 0b001, OPC_OP_IMM, "clz">,

CLZ only exist on RV32 for Zbpbo.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 433612.
Jim added a comment.
Herald added subscribers: sunshaoce, StephenFan, arichardson.
Herald added a project: All.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108189/new/

https://reviews.llvm.org/D108189

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -178,3 +178,12 @@
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+
+.attribute arch, "rv32ip0p96"
+# CHECK: attribute  5, "rv32i2p0_p0p96_zpn0p96_zpsfoperand0p96"
+
+.attribute arch, "rv32izpn0p96"
+# CHECK: attribute  5, "rv32i2p0_zpn0p96"
+
+.attribute arch, "rv32izpsfoperand0p96"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p96"
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -105,6 +105,10 @@
 {"zbr", RISCVExtensionVersion{0, 93}},
 {"zbt", RISCVExtensionVersion{0, 93}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+
+{"p", RISCVExtensionVersion{0, 96}},
+{"zpn", RISCVExtensionVersion{0, 96}},
+{"zpsfoperand", RISCVExtensionVersion{0, 96}},
 };
 
 static bool stripExperimentalPrefix(StringRef ) {
@@ -595,7 +599,7 @@
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
 // Currently LLVM supports only "mafdcbv".
-StringRef SupportedStandardExtension = "mafdcbv";
+StringRef SupportedStandardExtension = "mafdcbpv";
 if (!SupportedStandardExtension.contains(C))
   return createStringError(errc::invalid_argument,
"unsupported standard user-level extension '%c'",
@@ -769,6 +773,7 @@
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsP[] = {"zpn", "zpsfoperand"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -783,6 +788,7 @@
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"p"}, {ImpliedExtsP}},
 {{"v"}, {ImpliedExtsV}},
 {{"zdinx"}, {ImpliedExtsZdinx}},
 {{"zfh"}, {ImpliedExtsZfh}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -222,6 +222,34 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 96000{{$}}
+// CHECK-P-EXT: __riscv_zpn 96000{{$}}
+// CHECK-P-EXT: __riscv_zpsfoperand 96000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 96000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 96000{{$}}
+
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32iv1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -452,6 +452,63 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBA %s
 // RV32-ZBA: "-target-feature" "+zba"
 
+// RUN: %clang -target 

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim marked an inline comment as done.
Jim added inline comments.



Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll:4360
 ; LMULMAX1-RV64-NEXT:vid.v v10
+; LMULMAX1-RV64-NEXT:vadd.vi v11, v10, 2
+; LMULMAX1-RV64-NEXT:lui a2, %hi(.LCPI132_2)

The change for this testcase is that GPRJALR regclass is subsumed by 
GPR32Pair_with_gpr32_pair_lo_in_GPRNoX0X2 regclass.
And register pressure calculation is different.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim marked 2 inline comments as done.
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:909
+
+// kmar64 has a aliased instruction kmada32 belong to zpn sub-extension on 
RV64.
+let DecoderNamespace = "RISCV32Zpsfoperand_",

Jim wrote:
> jrtc27 wrote:
> > Having the same instruction in two different extensions under two different 
> > names is insane. Currently this implementation lets you use the "wrong" 
> > name for kmar64 with Zpn. But I would prefer the spec weren't crazy.
> I am still working on fixing it (from spec or ...) . But it is spec issue.
Remove alias inst first. I will discuss with P-extension maintainer on this 
issue.
Could this issue be fixed by a future revision?



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:228
+
+def GPR32Pair : RegisterClass<"RISCV", [untyped], 64, (add GPR32Pairs)> {
+  let Size = 64;

jrtc27 wrote:
> Jim wrote:
> > jrtc27 wrote:
> > > Why is this untyped?
> > GPR32Pair has untyped type. 
> > In code generation, It captures some operation with i64 type supported by 
> > Zpsoperand to untyped during legalization. 
> > In my mind, untyped is used to be represented special type don't need any 
> > legalization.
> > I refer to ARMRegisterInfo.td that defines GPRPair with untyped.
> So, presumably it can't be i64 because that would then make i64 a legal type? 
> Maybe that's fine, maybe it's not, but alternatively it could be typed as 
> v2i32 here (can include v4i16 and v8i8 too) and cast if/when needed. Craig 
> maybe you have thoughts on this? But untyped always feels like laziness to me 
> that results in TableGen being unable to help you when it comes to type 
> checking, with rare exceptions.
All of operation node having untyped operands are customized SDNode lowered in 
RISCVISelLowering.cpp.  And matched to a specific pattern. 
untyped couldn't be as v2i32, v4i16 or v8i8 in the same time. The operand type 
has been checked in custom lowering.

The lowering for operation with specific operand types (v2i32, v4i16, v8i8 or 
i64 in this case) would be set cutsom and lowered to customized SDNode (This 
SDNode has untyped operands). 
Different operand types with the same operation are lowered to different 
customized SDNode.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 407770.
Jim added a comment.
Herald added a subscriber: pcwang-thead.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108189/new/

https://reviews.llvm.org/D108189

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -163,3 +163,12 @@
 
 .attribute arch, "rv32i_zk1p0"
 # CHECK: attribute  5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+
+.attribute arch, "rv32ip0p96"
+# CHECK: attribute  5, "rv32i2p0_p0p96_zpn0p96_zpsfoperand0p96"
+
+.attribute arch, "rv32izpn0p96"
+# CHECK: attribute  5, "rv32i2p0_zpn0p96"
+
+.attribute arch, "rv32izpsfoperand0p96"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p96"
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -99,6 +99,10 @@
 {"zbp", RISCVExtensionVersion{0, 93}},
 {"zbr", RISCVExtensionVersion{0, 93}},
 {"zbt", RISCVExtensionVersion{0, 93}},
+
+{"p", RISCVExtensionVersion{0, 96}},
+{"zpn", RISCVExtensionVersion{0, 96}},
+{"zpsfoperand", RISCVExtensionVersion{0, 96}},
 };
 
 static bool stripExperimentalPrefix(StringRef ) {
@@ -589,7 +593,7 @@
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
 // Currently LLVM supports only "mafdcbv".
-StringRef SupportedStandardExtension = "mafdcbv";
+StringRef SupportedStandardExtension = "mafdcbpv";
 if (!SupportedStandardExtension.contains(C))
   return createStringError(errc::invalid_argument,
"unsupported standard user-level extension '%c'",
@@ -754,6 +758,7 @@
 static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
+static const char *ImpliedExtsP[] = {"zpn", "zpsfoperand"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -768,6 +773,7 @@
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"p"}, {ImpliedExtsP}},
 {{"v"}, {ImpliedExtsV}},
 {{"zfh"}, {ImpliedExtsZfh}},
 {{"zfhmin"}, {ImpliedExtsZfhmin}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -211,6 +211,34 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 96000{{$}}
+// CHECK-P-EXT: __riscv_zpn 96000{{$}}
+// CHECK-P-EXT: __riscv_zpsfoperand 96000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 96000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 96000{{$}}
+
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32iv1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -397,6 +397,63 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBA %s
 // RV32-ZBA: "-target-feature" "+zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557
+
+let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add

Is register pair only on RV32 for used as f64?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+X10_PD, X12_PD, X14_PD, X16_PD,

Is XLenRI correct for GPRPF64? RV32 has size 32.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.
Herald added a subscriber: eopXD.

In D108189#3188343 , @zixuan-wu wrote:

> Hi, @Jim.
> What time is P extension going to upstream to community since it's been no 
> update for some months?

Hi @zixuan-wu,

From RVP 0.9.7, it has lots of changes (new sub-extension Zbpbo). I am still 
working on it.
Sorry for reply late.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108189/new/

https://reviews.llvm.org/D108189

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D116509: [Builtins] Add missing the macro 'y' description in comments

[Jim Lin via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9b70ddaff6e1: [Builtins] Add missing the macro y 
description in comments (authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116509/new/

https://reviews.llvm.org/D116509

Files:
  clang/include/clang/Basic/Builtins.def


Index: clang/include/clang/Basic/Builtins.def
===
--- clang/include/clang/Basic/Builtins.def
+++ clang/include/clang/Basic/Builtins.def
@@ -26,6 +26,7 @@
 //  i -> int
 //  h -> half (__fp16, OpenCL)
 //  x -> half (_Float16)
+//  y -> half (__bf16)
 //  f -> float
 //  d -> double
 //  z -> size_t


Index: clang/include/clang/Basic/Builtins.def
===
--- clang/include/clang/Basic/Builtins.def
+++ clang/include/clang/Basic/Builtins.def
@@ -26,6 +26,7 @@
 //  i -> int
 //  h -> half (__fp16, OpenCL)
 //  x -> half (_Float16)
+//  y -> half (__bf16)
 //  f -> float
 //  d -> double
 //  z -> size_t
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D116509: [Builtins] Add missing the macro 'y' description in comments

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Jim requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116509

Files:
  clang/include/clang/Basic/Builtins.def


Index: clang/include/clang/Basic/Builtins.def
===
--- clang/include/clang/Basic/Builtins.def
+++ clang/include/clang/Basic/Builtins.def
@@ -26,6 +26,7 @@
 //  i -> int
 //  h -> half (__fp16, OpenCL)
 //  x -> half (_Float16)
+//  y -> half (__bf16)
 //  f -> float
 //  d -> double
 //  z -> size_t


Index: clang/include/clang/Basic/Builtins.def
===
--- clang/include/clang/Basic/Builtins.def
+++ clang/include/clang/Basic/Builtins.def
@@ -26,6 +26,7 @@
 //  i -> int
 //  h -> half (__fp16, OpenCL)
 //  x -> half (_Float16)
+//  y -> half (__bf16)
 //  f -> float
 //  d -> double
 //  z -> size_t
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim marked 7 inline comments as done.
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:909
+
+// kmar64 has a aliased instruction kmada32 belong to zpn sub-extension on 
RV64.
+let DecoderNamespace = "RISCV32Zpsfoperand_",

jrtc27 wrote:
> Having the same instruction in two different extensions under two different 
> names is insane. Currently this implementation lets you use the "wrong" name 
> for kmar64 with Zpn. But I would prefer the spec weren't crazy.
I am still working on fixing it (from spec or ...) . But it is spec issue.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:228
+
+def GPR32Pair : RegisterClass<"RISCV", [untyped], 64, (add GPR32Pairs)> {
+  let Size = 64;

jrtc27 wrote:
> Why is this untyped?
GPR32Pair has untyped type. 
In code generation, It captures some operation with i64 type supported by 
Zpsoperand to untyped during legalization. 
In my mind, untyped is used to be represented special type don't need any 
legalization.
I refer to ARMRegisterInfo.td that defines GPRPair with untyped.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

In D95588#3003090 , @Jim wrote:

> Any feedback? I think this patch is good enough to be accepted.

Ping? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

Any feedback? I think this patch is good enough to be accepted.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.93

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 372058.
Jim added a comment.

Update to 0.96 and remove Zprvsfextra


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108189/new/

https://reviews.llvm.org/D108189

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,6 +36,9 @@
 .attribute arch, "rv32ib"
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
+.attribute arch, "rv32ip"
+# CHECK: attribute  5, "rv32i2p0_p0p96_zpn0p96_zpsfoperand0p96"
+
 .attribute arch, "rv32iv"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
@@ -72,6 +75,12 @@
 .attribute arch, "rv32izbt"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
+.attribute arch, "rv32izpn"
+# CHECK: attribute  5, "rv32i2p0_zpn0p96"
+
+.attribute arch, "rv32izpsfoperand"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p96"
+
 .attribute arch, "rv32ifzfh"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -20,6 +20,9 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV32P %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zpn %s -o - | FileCheck --check-prefix=RV32ZPN %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zpsfoperand %s -o - | FileCheck --check-prefix=RV32ZPSFOPERAND %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -40,6 +43,9 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zpn %s -o - | FileCheck --check-prefix=RV64ZPN %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zpsfoperand %s -o - | FileCheck --check-prefix=RV64ZPSFOPERAND %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
@@ -61,6 +67,9 @@
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
 ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV32P: .attribute 5, "rv32i2p0_p0p96_zpn0p96_zpsfoperand0p96"
+; RV32ZPN: .attribute 5, "rv32i2p0_zpn0p96"
+; RV32ZPSFOPERAND: .attribute 5, "rv32i2p0_zpsfoperand0p96"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -82,6 +91,9 @@
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
 ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV64P: .attribute 5, "rv64i2p0_p0p96_zpn0p96_zpsfoperand0p96"
+; RV64ZPN: .attribute 5, "rv64i2p0_zpn0p96"
+; RV64ZPSFOPERAND: .attribute 5, "rv64i2p0_zpsfoperand0p96"
 
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -50,6 +50,7 @@
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
 {"b", RISCVExtensionVersion{0, 93}},
+{"p", RISCVExtensionVersion{0, 96}},
 {"v", RISCVExtensionVersion{0, 10}},
 {"zba", RISCVExtensionVersion{0, 93}},
 {"zbb", RISCVExtensionVersion{0, 93}},
@@ -63,6 +64,9 @@
 {"zbt", RISCVExtensionVersion{0, 93}},
 {"zbproposedc", RISCVExtensionVersion{0, 93}},
 
+{"zpn", RISCVExtensionVersion{0, 96}},
+{"zpsfoperand", RISCVExtensionVersion{0, 96}},
+
 {"zvamo", RISCVExtensionVersion{0, 10}},
 {"zvlsseg", RISCVExtensionVersion{0, 10}},
 
@@ -600,6 +604,11 

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

Ping? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

Hi, @jrtc27

About the concern the invalid combination RV32 + zprvsfextra on riscv 
attribute, 
I upload a patch D108189  based on 
@kito-cheng 's patch D105168  to forbid 
emitting rv32+zprvsfextra  arch string.
And It also deny to accept `rv32izprvsfextra` 
https://reviews.llvm.org/differential/changeset/?ref=2787775.

Patch D108189  have not emitted and accepted 
invalid arch string combined from rv32 and  zprvsfextra.

Thanks for feedback.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108189: [RISCV] Add arch attribute support for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 370484.
Jim added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Base on D105168  to support arch features, 
arch attributes and
preprocessor definitions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108189/new/

https://reviews.llvm.org/D108189

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch-invalid.s
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,6 +36,12 @@
 .attribute arch, "rv32ib"
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
+.attribute arch, "rv32ip"
+# CHECK: attribute  5, "rv32i2p0_p0p93_zpn0p93_zpsfoperand0p93"
+
+.attribute arch, "rv64ip"
+# CHECK: attribute  5, "rv64i2p0_p0p93_zpn0p93_zprvsfextra0p93_zpsfoperand0p93"
+
 .attribute arch, "rv32iv"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
@@ -72,6 +78,15 @@
 .attribute arch, "rv32izbt"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
+.attribute arch, "rv32izpn"
+# CHECK: attribute  5, "rv32i2p0_zpn0p93"
+
+.attribute arch, "rv32izpsfoperand"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p93"
+
+.attribute arch, "rv64izprvsfextra"
+# CHECK: attribute  5, "rv64i2p0_zprvsfextra0p93"
+
 .attribute arch, "rv32ifzfh"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
Index: llvm/test/MC/RISCV/attribute-arch-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/attribute-arch-invalid.s
@@ -0,0 +1,3 @@
+# RUN: not llvm-mc %s -triple=riscv32 -filetype=asm 2>&1 | FileCheck %s
+
+.attribute arch, "rv32izprvsfextra" # CHECK: :[[@LINE]]:18: error: invalid arch name 'rv32izprvsfextra', standard user-level extension 'zprvsfextra' requires 'rv64'
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -20,6 +20,9 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV32P %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zpn %s -o - | FileCheck --check-prefix=RV32ZPN %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zpsfoperand %s -o - | FileCheck --check-prefix=RV32ZPSFOPERAND %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -40,6 +43,10 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zpn %s -o - | FileCheck --check-prefix=RV64ZPN %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zpsfoperand %s -o - | FileCheck --check-prefix=RV64ZPSFOPERAND %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zprvsfextra %s -o - | FileCheck --check-prefix=RV64ZPRVSFEXTRA %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
@@ -61,6 +68,9 @@
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
 ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV32P: .attribute 5, "rv32i2p0_p0p93_zpn0p93_zpsfoperand0p93"
+; RV32ZPN: .attribute 5, "rv32i2p0_zpn0p93"
+; RV32ZPSFOPERAND: .attribute 5, "rv32i2p0_zpsfoperand0p93"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -82,6 +92,10 @@
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
 ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV64P: .attribute 5, 

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:416
+ExtensionInfoIterator->Version.Minor);
+  if (ExtName == "e") {
+if (XLen != 32)

Could this checking put before ISAInfo->addExtension...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105168/new/

https://reviews.llvm.org/D105168

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:387
+ExtensionInfoIterator->Version.Minor);
+  if (ExtName == "e")
+HasE = true;

Does this need to check it is invalid if XLen is 64?



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:394
+  if (!HasE)
+ISAInfo->addExtension("i", 2, 0);
+

Why not get the version of i from SupportedExtensions?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105168/new/

https://reviews.llvm.org/D105168

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim marked an inline comment as done.
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:186-188
+   [FeatureExtZpsfoperand,
+FeatureExtZpn,
+FeatureExtZprvsfextra]>;

jrtc27 wrote:
> Jim wrote:
> > jrtc27 wrote:
> > > These aren't correct? RV64 doesn't have Zpsfoperand and RV32 doesn't have 
> > > Zprvsfextra.
> > RV64 has Zpsfoperand extension that just has normal GPRs as operands (RV32 
> > has even/odd paired-register operand).
> > 
> > RV32 doesn't have Zprvsfextra. All of instruction in Zprvsfextra are 
> > defined in Predicates = [HasStdExtZprvsfextra, IsRV64].
> > 
> > If P is enabled, it means Zpn+Zpsfoperand enabled on RV32, and 
> > Zpn+Zpsfoperand+Zprvsfextra enabled on RV64.
> My concern is that the internal inflexibility is going to leak out of LLVM, 
> such as into the .riscv.attributes section, and thus produce broken binaries 
> because they claim they need Zprvsfextra on RV32, which is an invalid 
> combination.
> 
> And if Zpsfoperand exists for RV64 then it shouldn't be called 
> `Paired-register operand 'P' Instructions`, because the operands are only 
> paired on RV32.
I upload a new patch https://reviews.llvm.org/D108189 to support P extension 's 
arch string.
If rv32izprvsfextra (Zprvsfextra on RV32) accepted from *.s arch attribute, it 
emits error message to forbid this invalid combination.
Before emitting _zprvsfextra string, it would check RV64 is enabled.

If llc is given -mattr=+experimental-zprvsfextra on RV32, it would be ignored.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

Hi @jrtc27, any further feedback? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 365359.
Jim added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95589/new/

https://reviews.llvm.org/D95589

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -423,6 +423,82 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOVERS %s
+// RV32-EXPERIMENTAL-ZPN-NOVERS: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-BADVERS %s
+// RV32-EXPERIMENTAL-ZPN-BADVERS: error: invalid arch name 'rv32izpn0p1'
+// RV32-EXPERIMENTAL-ZPN-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPN-GOODVERS: "-target-feature" "+experimental-zpn"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: error: invalid arch name 'rv32izpsfoperand0p1'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS: "-target-feature" "+experimental-zpsfoperand"
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG %s
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: error: invalid arch name 'rv64izprvsfextra'
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck 

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 365358.
Jim added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95590/new/

https://reviews.llvm.org/D95590

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -218,6 +218,46 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-32P-EXT %s
+// CHECK-32P-EXT: __riscv_p 93000
+// CHECK-32P-EXT: __riscv_zpn 93000
+// CHECK-32P-EXT: __riscv_zpsfoperand 93000
+// CHECK-32P-NOT: __riscv_zprvsfextra
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-64P-EXT %s
+// CHECK-64P-EXT: __riscv_p 93000
+// CHECK-64P-EXT: __riscv_zpn 93000
+// CHECK-64P-EXT: __riscv_zprvsfextra 93000
+// CHECK-64P-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izprvsfextra0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPRVSFEXTRA-EXT %s
+// CHECK-ZPRVSFEXTRA-NOT: __riscv_p
+// CHECK-ZPRVSFEXTRA-EXT: __riscv_zprvsfextra 93000
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32iv0p10 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
@@ -43,6 +44,9 @@
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
+  bool HasZpn = false;
+  bool HasZpsfoperand = false;
+  bool HasZprvsfextra = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -181,6 +181,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "93000");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "1");
 Builder.defineMacro("__riscv_vector");
@@ -219,6 +222,15 @@
   if (HasZbt)
 Builder.defineMacro("__riscv_zbt", "93000");
 
+  if (HasZpn)
+Builder.defineMacro("__riscv_zpn", "93000");
+
+  if (HasZpsfoperand)
+Builder.defineMacro("__riscv_zpsfoperand", "93000");
+
+  if (HasZprvsfextra)
+Builder.defineMacro("__riscv_zprvsfextra", "93000");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh", "1000");
 
@@ -266,6 +278,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -278,6 +291,9 @@
   .Case("experimental-zbr", HasZbr)
   .Case("experimental-zbs", HasZbs)
   .Case("experimental-zbt", HasZbt)
+  .Case("experimental-zpn", HasZpn)
+  .Case("experimental-zpsfoperand", HasZpsfoperand)
+  .Case("experimental-zprvsfextra", HasZprvsfextra)
   .Case("experimental-zfh", HasZfh)
   .Case("experimental-zvamo", HasZvamo)
   .Case("experimental-zvlsseg", HasZvlsseg)
@@ -300,6 +316,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = 

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

Kindly ping? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 363372.
Jim added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95589/new/

https://reviews.llvm.org/D95589

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -423,6 +423,82 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOVERS %s
+// RV32-EXPERIMENTAL-ZPN-NOVERS: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-BADVERS %s
+// RV32-EXPERIMENTAL-ZPN-BADVERS: error: invalid arch name 'rv32izpn0p1'
+// RV32-EXPERIMENTAL-ZPN-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPN-GOODVERS: "-target-feature" "+experimental-zpn"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: error: invalid arch name 'rv32izpsfoperand0p1'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS: "-target-feature" "+experimental-zpsfoperand"
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG %s
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: error: invalid arch name 'rv64izprvsfextra'
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck 

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 363371.
Jim added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95590/new/

https://reviews.llvm.org/D95590

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -218,6 +218,46 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-32P-EXT %s
+// CHECK-32P-EXT: __riscv_p 93000
+// CHECK-32P-EXT: __riscv_zpn 93000
+// CHECK-32P-EXT: __riscv_zpsfoperand 93000
+// CHECK-32P-NOT: __riscv_zprvsfextra
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-64P-EXT %s
+// CHECK-64P-EXT: __riscv_p 93000
+// CHECK-64P-EXT: __riscv_zpn 93000
+// CHECK-64P-EXT: __riscv_zprvsfextra 93000
+// CHECK-64P-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izprvsfextra0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPRVSFEXTRA-EXT %s
+// CHECK-ZPRVSFEXTRA-NOT: __riscv_p
+// CHECK-ZPRVSFEXTRA-EXT: __riscv_zprvsfextra 93000
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32iv0p10 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
@@ -43,6 +44,9 @@
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
+  bool HasZpn = false;
+  bool HasZpsfoperand = false;
+  bool HasZprvsfextra = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -181,6 +181,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "93000");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "1");
 Builder.defineMacro("__riscv_vector");
@@ -219,6 +222,15 @@
   if (HasZbt)
 Builder.defineMacro("__riscv_zbt", "93000");
 
+  if (HasZpn)
+Builder.defineMacro("__riscv_zpn", "93000");
+
+  if (HasZpsfoperand)
+Builder.defineMacro("__riscv_zpsfoperand", "93000");
+
+  if (HasZprvsfextra)
+Builder.defineMacro("__riscv_zprvsfextra", "93000");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh", "1000");
 
@@ -266,6 +278,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -278,6 +291,9 @@
   .Case("experimental-zbr", HasZbr)
   .Case("experimental-zbs", HasZbs)
   .Case("experimental-zbt", HasZbt)
+  .Case("experimental-zpn", HasZpn)
+  .Case("experimental-zpsfoperand", HasZpsfoperand)
+  .Case("experimental-zprvsfextra", HasZprvsfextra)
   .Case("experimental-zfh", HasZfh)
   .Case("experimental-zvamo", HasZvamo)
   .Case("experimental-zvlsseg", HasZvlsseg)
@@ -300,6 +316,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = 

[PATCH] D107248: [RISCV] Define preprocessor definitions for 'P' extension

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107248

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -218,6 +218,46 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-32P-EXT %s
+// CHECK-32P-EXT: __riscv_p 93000
+// CHECK-32P-EXT: __riscv_zpn 93000
+// CHECK-32P-EXT: __riscv_zpsfoperand 93000
+// CHECK-32P-NOT: __riscv_zprvsfextra
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-64P-EXT %s
+// CHECK-64P-EXT: __riscv_p 93000
+// CHECK-64P-EXT: __riscv_zpn 93000
+// CHECK-64P-EXT: __riscv_zprvsfextra 93000
+// CHECK-64P-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izprvsfextra0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPRVSFEXTRA-EXT %s
+// CHECK-ZPRVSFEXTRA-NOT: __riscv_p
+// CHECK-ZPRVSFEXTRA-EXT: __riscv_zprvsfextra 93000
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32iv0p10 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
@@ -43,6 +44,9 @@
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
+  bool HasZpn = false;
+  bool HasZpsfoperand = false;
+  bool HasZprvsfextra = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -181,6 +181,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "93000");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "1");
 Builder.defineMacro("__riscv_vector");
@@ -219,6 +222,15 @@
   if (HasZbt)
 Builder.defineMacro("__riscv_zbt", "93000");
 
+  if (HasZpn)
+Builder.defineMacro("__riscv_zpn", "93000");
+
+  if (HasZpsfoperand)
+Builder.defineMacro("__riscv_zpsfoperand", "93000");
+
+  if (HasZprvsfextra)
+Builder.defineMacro("__riscv_zprvsfextra", "93000");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh", "1000");
 
@@ -266,6 +278,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -278,6 +291,9 @@
   .Case("experimental-zbr", HasZbr)
   .Case("experimental-zbs", HasZbs)
   .Case("experimental-zbt", HasZbt)
+  .Case("experimental-zpn", HasZpn)
+  .Case("experimental-zpsfoperand", 

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

@jrtc27 Any more feedback? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim marked 8 inline comments as done.
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:442
+
+if (STI.getFeatureBits()[RISCV::FeatureExtZpsfoperand] &&
+!STI.getFeatureBits()[RISCV::Feature64Bit]) {

jrtc27 wrote:
> The table is called RISCV32POnly but you're checking for Zpsfoperand 
> (whatever that mouthful of an extension is). Which is it?
Rename RISCV32POnly to RISCV32Zpsfoperand. 
This is for the instruction with even/odd paired-register operands on RV32. 

In RISCV32Zpsfoperand, two kinds of instruction defined for the same 
instruction in spec, one for RV32 with even/odd paired-register operands 
defined in RISCV32Zpsfoperand table , the other one for RV64 with normal GPR 
operands.





Comment at: llvm/lib/Target/RISCV/RISCV.td:186-188
+   [FeatureExtZpsfoperand,
+FeatureExtZpn,
+FeatureExtZprvsfextra]>;

jrtc27 wrote:
> These aren't correct? RV64 doesn't have Zpsfoperand and RV32 doesn't have 
> Zprvsfextra.
RV64 has Zpsfoperand extension that just has normal GPRs as operands (RV32 has 
even/odd paired-register operand).

RV32 doesn't have Zprvsfextra. All of instruction in Zprvsfextra are defined in 
Predicates = [HasStdExtZprvsfextra, IsRV64].

If P is enabled, it means Zpn+Zpsfoperand enabled on RV32, and 
Zpn+Zpsfoperand+Zprvsfextra enabled on RV64.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:216
+// Dummy zero register for pairing with X0.
+def ZERO : RISCVReg<0, "0">;
+

jrtc27 wrote:
> Ew, this is a gross quirk of the register pair instructions. ZERO is not a 
> good name for it though, that's the ABI name for x0 so already taken and is 
> pretty confusing. I assume LLVM doesn't like it if you create a register pair 
> that is (X0, X0)?
Rename it to REG_PAIR_WITH_X0.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:226-228
+def GPRPair : RegisterClass<"RISCV", [untyped], 64, (add GPRPairs)> {
+  let Size = 64;
+}

jrtc27 wrote:
> IMO the register class should be GPR32Pair not GPRPair unless you also make 
> it have a sensible interpretation for RV32 (which seems like a waste of time)
Rename it to GPR32Pair.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69
 
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;

jrtc27 wrote:
> Jim wrote:
> > Jim wrote:
> > > luismarques wrote:
> > > > jrtc27 wrote:
> > > > > This assumes RV32, and is not clear it applies to register pairs
> > > > What's the best way to address this?
> > > sub_lo and sub_hi are only used for GPRPair register class to extract a 
> > > register from pair registers on RV32.
> > Do you mean that sub_lo and sub_hi only used on RV32? Does it need to 
> > rename or ..?
> Yes, these should have names that make it clear they're for each half of a 
> 2*32-bit register pair. Otherwise it sounds like they're the 32-bit hi and lo 
> halves of the 64-bit registers on RV64.
Rename it to gpr_pair_lo and gpr_pair_hi


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

In D95588#2898470 , @jrtc27 wrote:

> Oh, technically none of the clang changes belong in this patch. Those are for 
> the Clang driver and preprocessor, not the MC layer which is purely llvm.

I move the clang changes to D95589  and D95590 
.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 361088.
Jim added a comment.

Recover it. Split arch version for P extension of D95588 
 to this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95589/new/

https://reviews.llvm.org/D95589

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -423,6 +423,82 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOVERS %s
+// RV32-EXPERIMENTAL-ZPN-NOVERS: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-BADVERS %s
+// RV32-EXPERIMENTAL-ZPN-BADVERS: error: invalid arch name 'rv32izpn0p1'
+// RV32-EXPERIMENTAL-ZPN-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPN-GOODVERS: "-target-feature" "+experimental-zpn"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: error: invalid arch name 'rv32izpsfoperand0p1'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS: "-target-feature" "+experimental-zpsfoperand"
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG %s
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: error: invalid arch name 'rv64izprvsfextra'
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv64-unknown-elf 

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 361087.
Jim added a comment.

Recover it. Split preprocessor definitions part of D95588 
 to this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95590/new/

https://reviews.llvm.org/D95590

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -218,6 +218,46 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-32P-EXT %s
+// CHECK-32P-EXT: __riscv_p 93000
+// CHECK-32P-EXT: __riscv_zpn 93000
+// CHECK-32P-EXT: __riscv_zpsfoperand 93000
+// CHECK-32P-NOT: __riscv_zprvsfextra
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-64P-EXT %s
+// CHECK-64P-EXT: __riscv_p 93000
+// CHECK-64P-EXT: __riscv_zpn 93000
+// CHECK-64P-EXT: __riscv_zprvsfextra 93000
+// CHECK-64P-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izprvsfextra0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPRVSFEXTRA-EXT %s
+// CHECK-ZPRVSFEXTRA-NOT: __riscv_p
+// CHECK-ZPRVSFEXTRA-EXT: __riscv_zprvsfextra 93000
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32iv0p10 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
@@ -43,6 +44,9 @@
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
+  bool HasZpn = false;
+  bool HasZpsfoperand = false;
+  bool HasZprvsfextra = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -181,6 +181,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "93000");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "1");
 Builder.defineMacro("__riscv_vector");
@@ -219,6 +222,15 @@
   if (HasZbt)
 Builder.defineMacro("__riscv_zbt", "93000");
 
+  if (HasZpn)
+Builder.defineMacro("__riscv_zpn", "93000");
+
+  if (HasZpsfoperand)
+Builder.defineMacro("__riscv_zpsfoperand", "93000");
+
+  if (HasZprvsfextra)
+Builder.defineMacro("__riscv_zprvsfextra", "93000");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh", "1000");
 
@@ -266,6 +278,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -278,6 +291,9 @@
   .Case("experimental-zbr", HasZbr)
   .Case("experimental-zbs", HasZbs)
   .Case("experimental-zbt", HasZbt)
+  .Case("experimental-zpn", HasZpn)
+  .Case("experimental-zpsfoperand", HasZpsfoperand)
+  .Case("experimental-zprvsfextra", HasZprvsfextra)
   .Case("experimental-zfh", HasZfh)
   .Case("experimental-zvamo", HasZvamo)
   .Case("experimental-zvlsseg", HasZvlsseg)
@@ 

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

ping? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69
 
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;

Jim wrote:
> luismarques wrote:
> > jrtc27 wrote:
> > > This assumes RV32, and is not clear it applies to register pairs
> > What's the best way to address this?
> sub_lo and sub_hi are only used for GPRPair register class to extract a 
> register from pair registers on RV32.
Do you mean that sub_lo and sub_hi only used on RV32? Does it need to rename or 
..?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69
 
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;

luismarques wrote:
> jrtc27 wrote:
> > This assumes RV32, and is not clear it applies to register pairs
> What's the best way to address this?
sub_lo and sub_hi are only used for GPRPair register class to extract a 
register from pair registers on RV32.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

Ping? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

Any comments? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

ping? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

Any comments? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D103313: [RISCV][Clang] Implement support for zmmul-experimental

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

It should add arch string tests such as in clang/test/Driver/riscv-arch.c.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103313/new/

https://reviews.llvm.org/D103313

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D101426: [RISCV] Update subset naming convertion for the latest spec

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

GCC has been updated from 
https://github.com/gcc-mirror/gcc/commit/ca1a9763a1f635d2687ebd5009dd61d4fd0ab5fb#diff-622e89d94803bb804711d5d492a5d4dfa60399bd7a5a7e70a49155534aa6a81f


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101426/new/

https://reviews.llvm.org/D101426

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D101426: [RISCV] Update subset naming convertion for the latest spec

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Update arch string rules for the latest spec 20191213. It introduced
new multi-letter extension prefix with 'h' and 'z', and drop `sx`.
And the canonical order is 's', 'h', 'z' and 'x'.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101426

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -181,31 +181,25 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32xabc -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
-// RV32X: error: invalid arch name 'rv32xabc',
-// RV32X: first letter should be 'e', 'i' or 'g'
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32sxabc -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32SX %s
-// RV32SX: error: invalid arch name 'rv32sxabc',
-// RV32SX: first letter should be 'e', 'i' or 'g'
-
 // RUN: %clang -target riscv32-unknown-elf -march=rv32sabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32S %s
 // RV32S: error: invalid arch name 'rv32sabc',
 // RV32S: first letter should be 'e', 'i' or 'g'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ix -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X-NAME %s
-// RV32X-NAME: error: invalid arch name 'rv32ix',
-// RV32X-NAME: non-standard user-level extension name missing after 'x'
+// RUN: %clang -target riscv32-unknown-elf -march=rv32habc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32H %s
+// RV32H: error: invalid arch name 'rv32habc',
+// RV32H: first letter should be 'e', 'i' or 'g'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32isx -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32SX-NAME %s
-// RV32SX-NAME: error: invalid arch name 'rv32isx',
-// RV32SX-NAME: non-standard supervisor-level extension
-// RV32SX-NAME: name missing after 'sx'
+// RUN: %clang -target riscv32-unknown-elf -march=rv32zabc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32Z %s
+// RV32Z: error: invalid arch name 'rv32zabc',
+// RV32Z: first letter should be 'e', 'i' or 'g'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32xabc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
+// RV32X: error: invalid arch name 'rv32xabc',
+// RV32X: first letter should be 'e', 'i' or 'g'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32is -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32S-NAME %s
@@ -213,31 +207,53 @@
 // RV32S-NAME: standard supervisor-level extension
 // RV32S-NAME: name missing after 's'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ix_s_sx -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ALL-NAME %s
-// RV32ALL-NAME: error: invalid arch name 'rv32ix_s_sx',
-// RV32ALL-NAME: non-standard user-level extension
-// RV32ALL-NAME: name missing after 'x'
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ih -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32H-NAME %s
+// RV32H-NAME: error: invalid arch name 'rv32ih',
+// RV32H-NAME: standard hypervisor-level extension
+// RV32H-NAME: name missing after 'h'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X-UNS %s
-// RV32X-UNS: error: invalid arch name 'rv32ixabc',
-// RV32X-UNS: unsupported non-standard user-level extension 'xabc'
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iz -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32Z-NAME %s
+// RV32Z-NAME: error: invalid arch name 'rv32iz',
+// RV32Z-NAME: standard machine-level extension
+// RV32Z-NAME: name missing after 'z'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ix -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X-NAME %s
+// RV32X-NAME: error: invalid arch name 'rv32ix',
+// RV32X-NAME: non-standard extension name missing after 'x'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32is_h_z_x -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ALL-NAME %s
+// RV32ALL-NAME: error: invalid arch name 'rv32is_h_z_x',
+// RV32ALL-NAME: standard supervisor-level extension
+// RV32ALL-NAME: name missing after 's'
 
 // RUN: %clang -target riscv32-unknown-elf 

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

In D99158#2695125 , @craig.topper 
wrote:

> Also can you please explain the vector codegen plan at a high level? Do you 
> intend to support auto vectorization or just using vector_size in C?

Currently, it just supports vector type operation (like v4i8+v4i8=>add8) in my 
local patch.




Comment at: llvm/test/CodeGen/RISCV/rvp/intrinsics-rv32p.ll:25
+  %1 = bitcast i32 %b.coerce to <4 x i8>
+  %2 = tail call <4 x i8> @llvm.riscv.add8.v4i8(<4 x i8> %0, <4 x i8> %1)
+  %3 = bitcast <4 x i8> %2 to i32

craig.topper wrote:
> I'm still not clear why we need to have two different ways to do the same 
> operation. Why isn't the C interface all scalar types or all vector types? 
> How do users choose which interface to use?
I will ask P extension intrinsic designer about your concern.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 338414.
Jim added a comment.

Fix typo.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/rv32p.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/rv64p.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoP.td
  llvm/test/CodeGen/RISCV/rvp/intrinsics-rv32p.ll
  llvm/test/CodeGen/RISCV/rvp/intrinsics-rv64p.ll

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:762
+  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
+setOperationAction(Opc, VT, Expand);
+

craig.topper wrote:
> You probably need handling for insert_vector_elt and extract_vector_elt or 
> some of the expansions will probably break.
I will implement it in another patch for codegen.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 338017.
Jim added a comment.

1. Updating D99158 : [RISCV][WIP] Implement 
intrinsics for P extension #
2. Enter a brief description of the changes included in this update.
3. The first line is used as subject, next lines as comment. #
4. If you intended to create a new revision, use:
5. $ arc diff --create

Only define 1 kind of intrinsic for most intructions, which
operand type and result type are the same scalar or vector type.
But s[z]unpkd* instructions have two kinds of intrinsics, extra
one has operand element width is half of result element width but
with more elements.

Refine code for IR codegen in CGBuiltin.cpp to look like B extension's 
implementation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/rv32p.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/rv64p.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoP.td
  llvm/test/CodeGen/RISCV/rvp/intrinsics-rv32p.ll
  llvm/test/CodeGen/RISCV/rvp/intrinsics-rv64p.ll

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

[Jim Lin via Phabricator via cfe-commits]

Jim accepted this revision.
Jim added a comment.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100266/new/

https://reviews.llvm.org/D100266

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1217
+defm vmv_x : RVVOp0BuiltinSet<"vmv_x_s", "csil",
+   [["s", "ve", "ev"],
+["s", "UvUe", "UeUv"]]>;

Indent



Comment at: clang/include/clang/Basic/riscv_vector.td:1221
+defm vmv_s : RVVOutBuiltinSet<"vmv_s_x", "csil",
+   [["x", "v", "vve"],
+["x", "Uv", "UvUvUe"]]>;

Indent


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100266/new/

https://reviews.llvm.org/D100266

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

[Jim Lin via Phabricator via cfe-commits]

Jim added a reviewer: Jim.
Jim added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:993
+defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil",
+   [["v", "Uv", "UvUv"]]>;
+defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd",

And below.



Comment at: clang/include/clang/Basic/riscv_vector.td:1001
+["x", "Uv", "UvUe"]]>;
+}
 

I am not sure that indent is needed inside let expression. In some cases, it 
don't have indent.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100266/new/

https://reviews.llvm.org/D100266

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D71541: [NFC] [Clang]: fix spelling mistake in assert message

[Jim Lin via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8a2d375a77bf: [NFC] [Clang]: fix spelling mistake in assert 
message (authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71541/new/

https://reviews.llvm.org/D71541

Files:
  clang/lib/AST/VTableBuilder.cpp


Index: clang/lib/AST/VTableBuilder.cpp
===
--- clang/lib/AST/VTableBuilder.cpp
+++ clang/lib/AST/VTableBuilder.cpp
@@ -487,7 +487,7 @@
 bool VCallOffsetMap::MethodsCanShareVCallOffset(const CXXMethodDecl *LHS,
 const CXXMethodDecl *RHS) {
   assert(VTableContextBase::hasVtableSlot(LHS) && "LHS must be virtual!");
-  assert(VTableContextBase::hasVtableSlot(RHS) && "LHS must be virtual!");
+  assert(VTableContextBase::hasVtableSlot(RHS) && "RHS must be virtual!");
 
   // A destructor can share a vcall offset with another destructor.
   if (isa(LHS))


Index: clang/lib/AST/VTableBuilder.cpp
===
--- clang/lib/AST/VTableBuilder.cpp
+++ clang/lib/AST/VTableBuilder.cpp
@@ -487,7 +487,7 @@
 bool VCallOffsetMap::MethodsCanShareVCallOffset(const CXXMethodDecl *LHS,
 const CXXMethodDecl *RHS) {
   assert(VTableContextBase::hasVtableSlot(LHS) && "LHS must be virtual!");
-  assert(VTableContextBase::hasVtableSlot(RHS) && "LHS must be virtual!");
+  assert(VTableContextBase::hasVtableSlot(RHS) && "RHS must be virtual!");
 
   // A destructor can share a vcall offset with another destructor.
   if (isa(LHS))
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D71541: [NFC] [Clang]: fix spelling mistake in assert message

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 336752.
Jim added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71541/new/

https://reviews.llvm.org/D71541

Files:
  clang/lib/AST/VTableBuilder.cpp


Index: clang/lib/AST/VTableBuilder.cpp
===
--- clang/lib/AST/VTableBuilder.cpp
+++ clang/lib/AST/VTableBuilder.cpp
@@ -487,7 +487,7 @@
 bool VCallOffsetMap::MethodsCanShareVCallOffset(const CXXMethodDecl *LHS,
 const CXXMethodDecl *RHS) {
   assert(VTableContextBase::hasVtableSlot(LHS) && "LHS must be virtual!");
-  assert(VTableContextBase::hasVtableSlot(RHS) && "LHS must be virtual!");
+  assert(VTableContextBase::hasVtableSlot(RHS) && "RHS must be virtual!");
 
   // A destructor can share a vcall offset with another destructor.
   if (isa(LHS))


Index: clang/lib/AST/VTableBuilder.cpp
===
--- clang/lib/AST/VTableBuilder.cpp
+++ clang/lib/AST/VTableBuilder.cpp
@@ -487,7 +487,7 @@
 bool VCallOffsetMap::MethodsCanShareVCallOffset(const CXXMethodDecl *LHS,
 const CXXMethodDecl *RHS) {
   assert(VTableContextBase::hasVtableSlot(LHS) && "LHS must be virtual!");
-  assert(VTableContextBase::hasVtableSlot(RHS) && "LHS must be virtual!");
+  assert(VTableContextBase::hasVtableSlot(RHS) && "RHS must be virtual!");
 
   // A destructor can share a vcall offset with another destructor.
   if (isa(LHS))
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706
+
+  setOperationAction(ISD::BITCAST, VT, Legal);
+

Jim wrote:
> craig.topper wrote:
> > What about bitcast from float/double to any of these vector types? I'm 
> > guess that's not legal.
> Yes, it is not legal bitcast from float/double to any of these vector types.
> All operations of these vector types have been expanded on line 760.
> Only bitcast from/to v4i8/v2i16, v8i8/v4i16/v2i32 to/from i32, i64 are legal.
Oh, it is a issue. I will try to fix it.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 335428.
Jim added a comment.

Subtarget.hasStdExtP() -> Subtarget.hasStdExtZpn() for addRegisterClass


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/rv32p.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/rv64p.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoP.td
  llvm/test/CodeGen/RISCV/rvp/intrinsics-rv32p.ll
  llvm/test/CodeGen/RISCV/rvp/intrinsics-rv64p.ll

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:17944
+
+  // P extension
+#define EMIT_BUILTIN(NAME, INT) \

I have concern here. It has lots of duplicate code if the code style is the 
same as B in the top.
And the name of macro is not good.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

[Jim Lin via Phabricator via cfe-commits]

Jim abandoned this revision.
Jim added a comment.
Herald added a subscriber: vkmr.

Merge this patch into https://reviews.llvm.org/D95588


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95589/new/

https://reviews.llvm.org/D95589

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

[Jim Lin via Phabricator via cfe-commits]

Jim abandoned this revision.
Jim added a comment.
Herald added a subscriber: vkmr.

Merge this patch into https://reviews.llvm.org/D95588


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95590/new/

https://reviews.llvm.org/D95590

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706
+
+  setOperationAction(ISD::BITCAST, VT, Legal);
+

craig.topper wrote:
> What about bitcast from float/double to any of these vector types? I'm guess 
> that's not legal.
Yes, it is not legal bitcast from float/double to any of these vector types.
All operations of these vector types have been expanded on line 760.
Only bitcast from/to v4i8/v2i16, v8i8/v4i16/v2i32 to/from i32, i64 are legal.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 335416.
Jim edited the summary of this revision.
Jim added a comment.

Address comments.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/rv32p.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/rv64p.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoP.td
  llvm/test/CodeGen/RISCV/rvp/intrinsics-rv32p.ll
  llvm/test/CodeGen/RISCV/rvp/intrinsics-rv64p.ll

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:26
+
+} // TargetPrefix = "riscv"
+

How about put it between Atomics and Vector to follow canonical order?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99320/new/

https://reviews.llvm.org/D99320

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99631: [RISCV] Refine pre-define macro tests

[Jim Lin via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG32ca5a037ab9: [RISCV] Refine pre-define macro tests 
(authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99631/new/

https://reviews.llvm.org/D99631

Files:
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -4,14 +4,20 @@
 // RUN: -o - | FileCheck %s
 
 // CHECK-NOT: __riscv_div
+// CHECK-NOT: __riscv_m
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
-// CHECK-NOT: __riscv_compressed
-// CHECK-NOT: __riscv_bitmanip
+// CHECK-NOT: __riscv_a 200
+// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_f 200
+// CHECK-NOT: __riscv_d
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
-// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_c 200
+// CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_b
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_zba
 // CHECK-NOT: __riscv_zbb
 // CHECK-NOT: __riscv_zbc
@@ -24,6 +30,8 @@
 // CHECK-NOT: __riscv_zbs
 // CHECK-NOT: __riscv_zbt
 // CHECK-NOT: __riscv_zfh
+// CHECK-NOT: __riscv_v
+// CHECK-NOT: __riscv_vector
 // CHECK-NOT: __riscv_zvamo
 // CHECK-NOT: __riscv_zvlsseg
 
@@ -61,30 +69,6 @@
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
 
-// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// CHECK-C-EXT: __riscv_c 200
-// CHECK-C-EXT: __riscv_compressed 1
-
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// CHECK-B-EXT: __riscv_b 93000
-// CHECK-B-EXT: __riscv_bitmanip 1
-// CHECK-B-EXT: __riscv_zba 93000
-// CHECK-B-EXT: __riscv_zbb 93000
-// CHECK-B-EXT: __riscv_zbc 93000
-// CHECK-B-EXT: __riscv_zbe 93000
-// CHECK-B-EXT: __riscv_zbf 93000
-// CHECK-B-EXT: __riscv_zbm 93000
-// CHECK-B-EXT: __riscv_zbp 93000
-// CHECK-B-EXT: __riscv_zbr 93000
-// CHECK-B-EXT: __riscv_zbs 93000
-// CHECK-B-EXT: __riscv_zbt 93000
-
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x c -E -dM %s \
@@ -109,104 +93,158 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_c 200
+// CHECK-C-EXT: __riscv_compressed 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv32iv0p10 -x c -E -dM %s \
-// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: -march=rv32ib0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv64iv0p10 -x c -E -dM %s \
-// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p10 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p10 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p10 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p10 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// CHECK-V-EXT: __riscv_v 1
-// CHECK-V-EXT: __riscv_vector 1
-// CHECK-V-EXT: __riscv_zvamo 1
-// CHECK-V-EXT: __riscv_zvlsseg 1
+// RUN: -march=rv64ib0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 93000
+// CHECK-B-EXT: __riscv_bitmanip 1
+// CHECK-B-EXT: __riscv_zba 93000
+// CHECK-B-EXT: __riscv_zbb 93000
+// CHECK-B-EXT: __riscv_zbc 93000
+// 

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:28
+TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr")
+

I don't know why it doesn't use __rv__* prefix directly?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99009/new/

https://reviews.llvm.org/D99009

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99631: [RISCV] Refine pre-define macro tests

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Jim added reviewers: craig.topper, simoncook, HsiangKai.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, jfb, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

1. Undefined macro test for rv32i and rv64i.
  1. Reorder it with canonical order.
  2. Add missing  undefined macro check.
  3. Append defined value to `__riscv_a`, `__riscv_f` and `__riscv_c` to 
distinguish with `__riscv_arch_test`, `__riscv_cmodel_medlow` and 
`__riscv_float_abi_soft`. They have the same prefix.
2. Move abi macro test below f and d.
3. Unify coding style for newline.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99631

Files:
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -4,14 +4,20 @@
 // RUN: -o - | FileCheck %s
 
 // CHECK-NOT: __riscv_div
+// CHECK-NOT: __riscv_m
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
-// CHECK-NOT: __riscv_compressed
-// CHECK-NOT: __riscv_bitmanip
+// CHECK-NOT: __riscv_a 200
+// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_f 200
+// CHECK-NOT: __riscv_d
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
-// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_c 200
+// CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_b
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_zba
 // CHECK-NOT: __riscv_zbb
 // CHECK-NOT: __riscv_zbc
@@ -24,6 +30,8 @@
 // CHECK-NOT: __riscv_zbs
 // CHECK-NOT: __riscv_zbt
 // CHECK-NOT: __riscv_zfh
+// CHECK-NOT: __riscv_v
+// CHECK-NOT: __riscv_vector
 // CHECK-NOT: __riscv_zvamo
 // CHECK-NOT: __riscv_zvlsseg
 
@@ -61,30 +69,6 @@
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
 
-// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// CHECK-C-EXT: __riscv_c 200
-// CHECK-C-EXT: __riscv_compressed 1
-
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// CHECK-B-EXT: __riscv_b 93000
-// CHECK-B-EXT: __riscv_bitmanip 1
-// CHECK-B-EXT: __riscv_zba 93000
-// CHECK-B-EXT: __riscv_zbb 93000
-// CHECK-B-EXT: __riscv_zbc 93000
-// CHECK-B-EXT: __riscv_zbe 93000
-// CHECK-B-EXT: __riscv_zbf 93000
-// CHECK-B-EXT: __riscv_zbm 93000
-// CHECK-B-EXT: __riscv_zbp 93000
-// CHECK-B-EXT: __riscv_zbr 93000
-// CHECK-B-EXT: __riscv_zbs 93000
-// CHECK-B-EXT: __riscv_zbt 93000
-
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x c -E -dM %s \
@@ -109,104 +93,158 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_c 200
+// CHECK-C-EXT: __riscv_compressed 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv32iv0p10 -x c -E -dM %s \
-// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: -march=rv32ib0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv64iv0p10 -x c -E -dM %s \
-// RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p10 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p10 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p10 -x c -E -dM %s \
-// RUN: -o - | 

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

[Jim Lin via Phabricator via cfe-commits]

Jim added a comment.

In D99158#2645796 , @craig.topper 
wrote:

> What are we gaining from making the intrinsics use vector types if no vector 
> operations are supported other than the intrinsics? Why can't we just use an 
> xlen integer type?

It can support other operations. I will upload a patch for codegen pattern 
later.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99158/new/

https://reviews.llvm.org/D99158

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D98923: [Driver] Pass -fexperimental-strict-floating-point to cc1 if it is specified

[Jim Lin via Phabricator via cfe-commits]

Jim abandoned this revision.
Jim added a comment.

In D98923#2638061 , @craig.topper 
wrote:

> Isn't OPT_fexperimental_strict_floating_point marked as a CC1Option in 
> Options.td. Can the driver even recognize it?
>
> Can you use -Xclang -fexperimental-strict-floating-point for your use case?

Hi, Thanks your suggestion, I would use -Xclang 
-fexperimental-strict-floating-point  for my test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98923/new/

https://reviews.llvm.org/D98923

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D98923: [Driver] Pass -fexperimental-strict-floating-point to cc1 if it is specified

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Jim added a reviewer: kpn.
Jim requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

In my case, it has to enable strict floating-point by driver for default 
unsupported target.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98923

Files:
  clang/lib/Driver/ToolChains/Clang.cpp


Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -5386,6 +5386,9 @@
   if (Args.hasArg(options::OPT_fexperimental_new_constant_interpreter))
 CmdArgs.push_back("-fexperimental-new-constant-interpreter");
 
+  if (Args.hasArg(options::OPT_fexperimental_strict_floating_point))
+CmdArgs.push_back("-fexperimental-strict-floating-point");
+
   if (Arg *A = Args.getLastArg(options::OPT_fbracket_depth_EQ)) {
 CmdArgs.push_back("-fbracket-depth");
 CmdArgs.push_back(A->getValue());


Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -5386,6 +5386,9 @@
   if (Args.hasArg(options::OPT_fexperimental_new_constant_interpreter))
 CmdArgs.push_back("-fexperimental-new-constant-interpreter");
 
+  if (Args.hasArg(options::OPT_fexperimental_strict_floating_point))
+CmdArgs.push_back("-fexperimental-strict-floating-point");
+
   if (Arg *A = Args.getLastArg(options::OPT_fbracket_depth_EQ)) {
 CmdArgs.push_back("-fbracket-depth");
 CmdArgs.push_back(A->getValue());
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

[Jim Lin via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG678241795c95: [RISCV] Dont emit #undef BUILTIN from 
RISCVVEmitter.cpp (authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98682/new/

https://reviews.llvm.org/D98682

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -881,7 +881,6 @@
 else
   OS << "\"\")\n";
   }
-  OS << "\n#undef BUILTIN\n";
   OS << "#undef RISCVV_BUILTIN\n";
 }
 
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,3 +17,5 @@
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+#undef BUILTIN
+#undef TARGET_BUILTIN


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -881,7 +881,6 @@
 else
   OS << "\"\")\n";
   }
-  OS << "\n#undef BUILTIN\n";
   OS << "#undef RISCVV_BUILTIN\n";
 }
 
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,3 +17,5 @@
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+#undef BUILTIN
+#undef TARGET_BUILTIN
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

[Jim Lin via Phabricator via cfe-commits]

Jim updated this revision to Diff 330888.
Jim added a comment.

Address @craig.topper 's comment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98682/new/

https://reviews.llvm.org/D98682

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -881,7 +881,6 @@
 else
   OS << "\"\")\n";
   }
-  OS << "\n#undef BUILTIN\n";
   OS << "#undef RISCVV_BUILTIN\n";
 }
 
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,3 +17,5 @@
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+#undef BUILTIN
+#undef TARGET_BUILTIN


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -881,7 +881,6 @@
 else
   OS << "\"\")\n";
   }
-  OS << "\n#undef BUILTIN\n";
   OS << "#undef RISCVV_BUILTIN\n";
 }
 
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,3 +17,5 @@
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+#undef BUILTIN
+#undef TARGET_BUILTIN
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Jim added reviewers: khchen, craig.topper.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

In BuiltinsRISCV.def, other extension 's intrinsics need to be defined by using 
macro BUILTIN.
So, it shouldn't undefine macro BUILTIN in the end of declaration for V 
intrinsics.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98682

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -881,7 +881,6 @@
 else
   OS << "\"\")\n";
   }
-  OS << "\n#undef BUILTIN\n";
   OS << "#undef RISCVV_BUILTIN\n";
 }
 
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,3 +17,4 @@
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+#undef BUILTIN


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -881,7 +881,6 @@
 else
   OS << "\"\")\n";
   }
-  OS << "\n#undef BUILTIN\n";
   OS << "#undef RISCVV_BUILTIN\n";
 }
 
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,3 +17,4 @@
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+#undef BUILTIN
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1744
+  // which multi-lib should be used.
+  return ScanGCCMultilibConfig(D, TargetTriple, Path, Args, MultilibOutput,
+   Result);

scanGCCMultilibConfig ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97916/new/

https://reviews.llvm.org/D97916

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1703
+}
+  }
+  Ms.emplace_back(Multilib);

Do you have plan to support other kind of options to build multilib?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97916/new/

https://reviews.llvm.org/D97916

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:89
+#define BUILTIN(ID, TYPE, ATTRS)   
\
+  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsRISCV.def"

Should it put together with `getTargetBuiltins` function?




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93446/new/

https://reviews.llvm.org/D93446

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:89
+#define BUILTIN(ID, TYPE, ATTRS)   
\
+  {"__builtin_rvv_" #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsRISCV.def"

craig.topper wrote:
> khchen wrote:
> > Jim wrote:
> > > Builtins for other extension don't have "__builtin_rvv_" prefix.
> > maybe we could rename BuiltinsRISCV.def as BuiltinsRVV.def, and other 
> > extension defines their own .def file?
> > 
> > @Jim do you have any suggestion?
> Don't most targets pass the full name with the prefix to the BUILTIN macro?
Most of targets pass the full name with the prefix to the BUILTIN macro.
It can define the full name with the prefix in BuiltinsRISCV.def


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93446/new/

https://reviews.llvm.org/D93446

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2
 
-RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_m_vl, "q4Ssq4bq4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_vl, "q2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_m_vl, "q2Siq2bq2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_vl, "q1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_vl, "q16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_m_vl, "q16Scq16bq16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_vl, "q8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_m_vl, "q8Ssq8bq8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_vl, "q4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_m_vl, "q4Siq4bq4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_vl, "q2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_vl, "q32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_m_vl, "q32Scq32bq32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_vl, "q16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_m_vl, "q16Ssq16bq16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_vl, "q8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_m_vl, "q8Siq8bq8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_vl, "q4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_vl, "q64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_m_vl, "q64Scq64bq64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_vl, "q32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_m_vl, "q32Ssq32bq32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_vl, "q16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_m_vl, "q16Siq16bq16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_vl, "q8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_vl, "q4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_m_vl, "q4Scq4bq4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_vl, "q2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_m_vl, "q2Ssq2bq2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_vl, "q1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_m_vl, "q1Siq1bq1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_vl, "q2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_m_vl, "q2Scq2bq2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_vl, "q1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_m_vl, "q1Ssq1bq1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_vl, "q1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_m_vl, "q1Scq1bq1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_vl, "q8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_m_vl, "q8Scq8bq8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_vl, "q4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_m_vl, "q4Ssq4bq4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_vl, "q2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_m_vl, "q2Siq2bq2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_vl, "q1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_vl, "q16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_m_vl, "q16Scq16bq16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_vl, "q8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_m_vl, "q8Ssq8bq8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_vl, "q4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_m_vl, "q4Siq4bq4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_vl, "q2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_vl, "q32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_m_vl, "q32Scq32bq32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_vl, "q16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_m_vl, "q16Ssq16bq16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_vl, "q8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_m_vl, "q8Siq8bq8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_vl, "q4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_vl, "q64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_m_vl, "q64Scq64bq64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_vl, "q32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_m_vl, "q32Ssq32bq32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_vl, "q16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_m_vl, "q16Siq16bq16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_vl, "q8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_vl, "q4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_m_vl, "q4Scq4bq4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_vl, "q2Ssq2SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_m_vl, 

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: llvm/docs/CommandGuide/tblgen.rst:141
 
-  Generate RISCV compressed instructions.
+  Generate RISC-V compressed instructions.
 

It is typo fix. Could you fix it in a separate patch?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95016/new/

https://reviews.llvm.org/D95016

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2
 
-RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_m_vl, "q4Ssq4bq4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_vl, "q2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_m_vl, "q2Siq2bq2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_vl, "q1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_vl, "q16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_m_vl, "q16Scq16bq16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_vl, "q8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_m_vl, "q8Ssq8bq8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_vl, "q4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_m_vl, "q4Siq4bq4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_vl, "q2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_vl, "q32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_m_vl, "q32Scq32bq32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_vl, "q16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_m_vl, "q16Ssq16bq16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_vl, "q8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_m_vl, "q8Siq8bq8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_vl, "q4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_vl, "q64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_m_vl, "q64Scq64bq64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_vl, "q32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_m_vl, "q32Ssq32bq32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_vl, "q16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_m_vl, "q16Siq16bq16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_vl, "q8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_vl, "q4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_m_vl, "q4Scq4bq4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_vl, "q2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_m_vl, "q2Ssq2bq2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_vl, "q1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_m_vl, "q1Siq1bq1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_vl, "q2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_m_vl, "q2Scq2bq2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_vl, "q1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_m_vl, "q1Ssq1bq1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_vl, "q1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_m_vl, "q1Scq1bq1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_vl, "q8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_m_vl, "q8Scq8bq8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_vl, "q4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_m_vl, "q4Ssq4bq4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_vl, "q2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_m_vl, "q2Siq2bq2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_vl, "q1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_vl, "q16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_m_vl, "q16Scq16bq16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_vl, "q8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_m_vl, "q8Ssq8bq8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_vl, "q4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_m_vl, "q4Siq4bq4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_vl, "q2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_vl, "q32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_m_vl, "q32Scq32bq32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_vl, "q16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_m_vl, "q16Ssq16bq16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_vl, "q8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_m_vl, "q8Siq8bq8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_vl, "q4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_vl, "q64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_m_vl, "q64Scq64bq64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_vl, "q32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_m_vl, "q32Ssq32bq32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_vl, "q16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_m_vl, "q16Siq16bq16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_vl, "q8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_vl, "q4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_m_vl, "q4Scq4bq4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_vl, "q2Ssq2SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_m_vl, 

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:11127
+def err_riscvv_builtin_not_useable : Error<
+   "builtin requires 'V' extension support to be enabled">;
 } // end of sema component.

Add blank line.
Is it "err_riscvv_builtin_not_enabled"?



Comment at: clang/lib/Basic/Targets/RISCV.cpp:89
+#define BUILTIN(ID, TYPE, ATTRS)   
\
+  {"__builtin_rvv_" #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsRISCV.def"

Builtins for other extension don't have "__builtin_rvv_" prefix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93446/new/

https://reviews.llvm.org/D93446

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.



Comment at: clang/test/CodeGen/RISCV/vadd.c:22
+{
+return __builtin_rvv_vadd_vv_i8m1_vl(arg_0, arg_1, arg_2);
+}

Is it necessary with prefix "__builtin_"?
Refer to 
https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv_intrinsic_funcs_vl/06_vector_integer_arithmetic_functions.md.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93446/new/

https://reviews.llvm.org/D93446

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Jim added reviewers: craig.topper, HsiangKai, kito-cheng, jrtc27, luismarques.
Herald added subscribers: frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95590

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -109,6 +109,12 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32ip0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64ip0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 9
+
 // RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
 // RUN:   -march=rv32iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -149,6 +149,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "9");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "100");
 Builder.defineMacro("__riscv_vector");
@@ -210,6 +213,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -244,6 +248,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = true;
+else if (Feature == "+experimental-p")
+  HasP = true;
 else if (Feature == "+experimental-v")
   HasV = true;
 else if (Feature == "+experimental-zba")


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -109,6 +109,12 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ip0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ip0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 9
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN:   -march=rv32iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -149,6 +149,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "9");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "100");
 Builder.defineMacro("__riscv_vector");
@@ -210,6 +213,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -244,6 +248,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = true;
+else 

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

[Jim Lin via Phabricator via cfe-commits]

Jim created this revision.
Jim added reviewers: craig.topper, HsiangKai, jrtc27, kito-cheng, luismarques.
Herald added subscribers: frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Support arch feature for experimental 'P' extension with version 0.9.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95589

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -369,6 +369,25 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
 // RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,6 +62,8 @@
   Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
   Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "93"};
+  if (Ext == "p")
+return RISCVExtensionVersion{"0", "9"};
   if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
 return RISCVExtensionVersion{"1", "0"};
   if (Ext == "zfh")
@@ -427,6 +429,9 @@
   Features.push_back("+experimental-zbs");
   Features.push_back("+experimental-zbt");
   break;
+case 'p':
+  Features.push_back("+experimental-p");
+  break;
 case 'v':
   Features.push_back("+experimental-v");
   Features.push_back("+experimental-zvamo");


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -369,6 +369,25 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
 // RUN: %clang