[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

Thanks for your review, @fpallares.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via cfe-commits]

fpallares added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:542
 defm VMSGT_V : VALU_IV_X_I<"vmsgt", 0b01>;
+}
 

Minor nit: Add comment here (for the other `let RVVConstraint = NoConstraint` 
blocks below as well).


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via cfe-commits]

fpallares accepted this revision.
fpallares added a comment.
This revision is now accepted and ready to land.

Aside from the minor nit below this patch LGTM. Thanks a lot for all the 
changes @HsiangKai.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via cfe-commits]

fpallares added a comment.

Thanks for the update @HsiangKai.

I've noticed that we aren't handling the exceptions that state that the `V0` 
constraint shouldn't be enforced for instructions that generate masks or for 
reductions.

For instance the following (valid) instructions are rejected:

  vmslt.vv v0, v2, v3, v0.t

  vredsum.vs v0, v1, v2, v0.t




Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:776
 }
-return "";
+llvm_unreachable("Unknown SEW.");
   }

evandro wrote:
> I'd rather the first case be the `default` case and that it would call 
> `llvm_unreachabe()` instead.
I believe the LLVM Coding Standards recommend against `default` labels in 
switches over enums:

> -Wswitch warns if a switch, without a default label, over an enumeration does 
> not cover every enumeration value. If you write a default label on a fully 
> covered switch over an enumeration then the -Wswitch warning won’t fire when 
> new elements are added to that enumeration.


See 
https://llvm.org/docs/CodingStandards.html#don-t-use-default-labels-in-fully-covered-switches-over-enumerations
 .


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D80802#2155802 , @fpallares wrote:

> Apologies we didn't identify this earlier but with the change of the mask 
> register layout (`MLEN=1`) the overlap constraints involving the mask 
> register were modified:
>
> //**RVV-0.8, Section 5.3. Vector Masking:**//
>
> > The destination vector register group for a masked vector instruction can 
> > only overlap the source mask register (v0) when LMUL=1. Otherwise, an 
> > illegal instruction exception is raised.
>
> //**RVV-0.9, Section 5.3. Vector Masking:**//
>
> > The destination vector register group for a masked vector instruction 
> > cannot overlap the source mask register (v0), unless the destination vector 
> > register is being written with a mask value (e.g., comparisons) or the 
> > scalar result of a reduction. Otherwise, an illegal instruction exception 
> > is raised.
>
> The change was introduced in this commit 
> .
>
> From my understanding, with this change an instruction such as the following 
> should be rejected in RVV-0.9:
>
>   vadd.vv v0, v1, v2, v0.t
>
>
> Also note that `vadc`/`vsbc` already have this behaviour.


Indeed, I did not take care of the mask register constraint for instructions. I 
will handle it in the next revision.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Evandro Menezes via Phabricator via cfe-commits]

evandro added a comment.

Just a couple of nits, but otherwise it LGTM.




Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:776
 }
-return "";
+llvm_unreachable("Unknown SEW.");
   }

I'd rather the first case be the `default` case and that it would call 
`llvm_unreachabe()` instead.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:796
 }
-return "";
+llvm_unreachable("Unknown LMUL.");
   }

Ditto.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Simon Cook via Phabricator via cfe-commits]

simoncook added a comment.

In D80802#2156221 , @HsiangKai wrote:

> The modification is put in D81213 .


Ah ok, missed that, thanks for pointing it out


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D80802#2155432 , @simoncook wrote:

> Since this patch replaces 0.8 support with 0.9, it should include an update 
> to the version check in `clang/lib/Driver/ToolChains/Arch/RISCV.cpp` to match.


The modification is put in D81213 .


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via cfe-commits]

fpallares added a comment.

Apologies we didn't identify this earlier but with the change of the mask 
register layout (`MLEN=1`) the overlap constraints involving the mask register 
were modified:

//**RVV-0.8, Section 5.3. Vector Masking:**//

> The destination vector register group for a masked vector instruction can 
> only overlap the source mask register (v0) when LMUL=1. Otherwise, an illegal 
> instruction exception is raised.

//**RVV-0.9, Section 5.3. Vector Masking:**//

> The destination vector register group for a masked vector instruction cannot 
> overlap the source mask register (v0), unless the destination vector register 
> is being written with a mask value (e.g., comparisons) or the scalar result 
> of a reduction. Otherwise, an illegal instruction exception is raised.

The change was introduced in this commit 
.

From my understanding, with this change an instruction such as the following 
should be rejected in RVV-0.9:

  vadd.vv   v0, v1, v2, v0.t

Also note that `vadc`/`vsbc` already have this behaviour.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Simon Cook via Phabricator via cfe-commits]

simoncook added a comment.

Since this patch replaces 0.8 support with 0.9, it should include an update to 
the version check in `clang/lib/Driver/ToolChains/Arch/RISCV.cpp` to match.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked an inline comment as done.
HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:99
 // load vd, (rs1), vm
 class VUnitStrideLoad

fpallares wrote:
> I believe that with the changes introduced in the encoding of the loads and 
> stores we can do without the `mop` parameter in most of the classes here:
> 
> | class   | replace `mop` by   |
> |---|--|
> | `VUnitStrideLoad` | `MOPLDUnitStride` (i.e. `00`) |
> | `VStridedLoad` | `MOPLDStrided` (i.e. `10`) |
> | `VIndexedLoad` | `MOPLDIndexed` (i.e. `11`) |
> | `VUnitStrideStore` | `MOPSTUnitStride` (i.e. `00`) |
> | `VStridedStore` | `MOPLDStrided` (i.e. `10`) |
> 
> We still need to keep the parameter for the `VIndexedStore` class since it 
> can take `MOPSTIndexedOrder` (i.e. `11`) or `MOPSTIndexedUnord` (i.e. `01`).
> 
> Does this make sense to you?
It makes sense. Thanks.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via cfe-commits]

fpallares added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:99
 // load vd, (rs1), vm
 class VUnitStrideLoad

I believe that with the changes introduced in the encoding of the loads and 
stores we can do without the `mop` parameter in most of the classes here:

| class   | replace `mop` by   |
|---|--|
| `VUnitStrideLoad` | `MOPLDUnitStride` (i.e. `00`) |
| `VStridedLoad` | `MOPLDStrided` (i.e. `10`) |
| `VIndexedLoad` | `MOPLDIndexed` (i.e. `11`) |
| `VUnitStrideStore` | `MOPSTUnitStride` (i.e. `00`) |
| `VStridedStore` | `MOPLDStrided` (i.e. `10`) |

We still need to keep the parameter for the `VIndexedStore` class since it can 
take `MOPSTIndexedOrder` (i.e. `11`) or `MOPSTIndexedUnord` (i.e. `01`).

Does this make sense to you?


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked an inline comment as done.
HsiangKai added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2386
+CheckReg = Inst.getOperand(3).getReg();
 }
+if (DestReg == CheckReg)

fpallares wrote:
> fpallares wrote:
> > With the suggestion above, this could be further simplified to:
> > 
> > ```
> > ​if ((TargetFlags & RISCV::OneInput && Inst.getNumOperands() == 3) || 
> > Inst.getNumOperands() == 4)
> > ​  return Error(Loc, "The destination vector register group cannot 
> > overlap"
> > ​" the mask register.");
> > ```
> I see you have updated the patch and removed the `if` that checked whether we 
> were dealing with the masked versions of the instructions (by checking the 
> number of operands). IIUC that check is still necessary so we don't report an 
> error for unmasked instruction.
> 
> For example, from my understanding the following instruction is correct, but 
> we will be reporting an error.
> ```
> viota.m v0, v2
> ```
Good catch. Thank you.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via cfe-commits]

fpallares added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2386
+CheckReg = Inst.getOperand(3).getReg();
 }
+if (DestReg == CheckReg)

fpallares wrote:
> With the suggestion above, this could be further simplified to:
> 
> ```
> ​if ((TargetFlags & RISCV::OneInput && Inst.getNumOperands() == 3) || 
> Inst.getNumOperands() == 4)
> ​  return Error(Loc, "The destination vector register group cannot 
> overlap"
>   ​" the mask register.");
> ```
I see you have updated the patch and removed the `if` that checked whether we 
were dealing with the masked versions of the instructions (by checking the 
number of operands). IIUC that check is still necessary so we don't report an 
error for unmasked instruction.

For example, from my understanding the following instruction is correct, but we 
will be reporting an error.
```
viota.m v0, v2
```


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

I've gone through and can't see any obvious issues. I defer to one of the 
RISC-V Vector extension usual suspects for giving a LGTM on the detail of the 
altered instructions etc. Once we have that, this looks good to land IMHO.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via cfe-commits]

fpallares added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2367
+Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM ||
+Opcode == RISCV::VSBC_VXM) {
+  if (DestReg == RISCV::V0)

I think we might not need to treat `vadc` and `vsbc` specially here. Since 
those have 4 operands they should fall on the `else` branch of the next 
`if-else` block:

```
if (Inst.getNumOperands() == 4)
  CheckReg = Inst.getOperand(3).getReg();
```

And that should produce the expected result. Did I miss some other reason why 
those should be treated separately?


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via cfe-commits]

fpallares added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2362
+  }
+  if (TargetFlags & RISCV::VMConstraint) {
+// vadc, vsbc are special cases.

Given that this constraint has no effect when `DestReg != RISCV::V0`, we could 
simplify the logic by adding this to the condition:

```
​  if (TargetFlags & RISCV::VMConstraint && DestReg == RISCV::V0) {
```

Then the `DestReg` checks within the block can go away.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2386
+CheckReg = Inst.getOperand(3).getReg();
 }
+if (DestReg == CheckReg)

With the suggestion above, this could be further simplified to:

```
​if ((TargetFlags & RISCV::OneInput && Inst.getNumOperands() == 3) || 
Inst.getNumOperands() == 4)
​  return Error(Loc, "The destination vector register group cannot overlap"
​" the mask register.");
```


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Roger Ferrer Ibanez via Phabricator via cfe-commits]

rogfer01 added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:796
 }
 return "";
   }

Minor nit that we missed in the patch of 0.8: can you replace this return with

```lang=cpp
llvm_unreachable();
```

as recommended in the second paragraph of 
https://llvm.org/docs/CodingStandards.html#don-t-use-default-labels-in-fully-covered-switches-over-enumerations

Ditto in `getSEWStr` above.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via cfe-commits]

fpallares added a comment.

Hi @HsiangKai, thanks for the patch. So far everything looks good aside from a 
couple of minor nits.




Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1638
+
+  if (getLexer().getKind() == AsmToken::EndOfStatement) {
+Operands.push_back(RISCVOperand::createVType(

While the spec currently states that specifying the `vta` and `mta` in 
`vsetvli` is not mandatory, it also states that not specifying them should be 
deprecated. Therefore, I'm not sure we should allow specifying the `vta` 
without specifying the `mta`.



Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp:172
+  bool MaskedoffAgnostic = Imm & 0x80;
+  if (TailAgnostic || MaskedoffAgnostic) {
+if (TailAgnostic)

Given that the use of `vsetvli` without these flags should be deprecated, I'd 
recommend printing them always, even if it more verbose.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Evandro Menezes via Phabricator via cfe-commits]

evandro added a comment.

Again, the `clang` part should be split in another patch and be made a child of 
D81188 .




Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:297
+LMUL_F8 = 5,
+LMUL_F4 = 6,
+LMUL_F2 = 7

This and the next value don't need to be specified.


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 267447.

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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/ext.s
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/invalid.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/snippet.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/vsetvl.s

Index: llvm/test/MC/RISCV/rvv/vsetvl.s
===
--- llvm/test/MC/RISCV/rvv/vsetvl.s
+++ llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -8,12 +8,72 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+vsetvli a2, a0, e32,m1
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 
+
+vsetvli a2, a0, e32,m2
+# CHECK-INST: vsetvli a2, a0, e32,m2
+# CHECK-ENCODING: [0x57,0x76,0x95,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 00 
+
 vsetvli a2, a0, e32,m4
 # CHECK-INST: vsetvli a2, a0, e32,m4
 # CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 76 a5 00 
 
+vsetvli a2, a0, e32,m8
+# CHECK-INST: vsetvli a2, a0, e32,m8
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 00 
+
+vsetvli a2, a0, e32,mf2
+# CHECK-INST: vsetvli a2, a0, e32,mf2
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 02 
+
+vsetvli a2, a0, e32,mf4
+# CHECK-INST: vsetvli a2, a0, e32,mf4
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 02 
+
+vsetvli a2, a0, e32,mf8
+# CHECK-INST: vsetvli a2, a0, e32,mf8
+# CHECK-ENCODING: [0x57,0x76,0x95,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 02 
+
+vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 0c 
+
+vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 08 
+
+vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-ENCODING: [0x57,0x76,0x85,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 04 
+
+vsetvli a2, a0, e32,m1,tu,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 
+
 vsetvl a2, a0, a1
 # CHECK-INST: vsetvl a2, a0, a1
 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
Index: llvm/test/MC/RISCV/rvv/store.s
===
--- llvm/test/MC/RISCV/rvv/store.s
+++ llvm/test/MC/RISCV/rvv/store.s
@@ -8,200 +8,296 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vsb.v v24, (a0), v0.t
-# CHECK-INST: vsb.v v24, (a0), v0.t
+vse8.v v24, (a0), v0.t
+# CHECK-INST: vse8.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 00 
 
-vsb.v v24, (a0)
-# CHECK-INST: vsb.v v24, (a0)
+vse8.v v24, (a0)
+# CHECK-INST: vse8.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 02 
 
-vsh.v v24, (a0), v0.t
-# CHECK-INST: vsh.v v24, (a0), v0.t
+vse16.v v24, (a0), v0.t
+# CHECK-INST: vse16.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 05 00 
 
-vsh.v v24, (a0)
-# CHECK-INST: vsh.v v24, (a0)
+vse16.v v24, (a0)
+# CHECK-INST: vse16.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Fangrui Song via Phabricator via cfe-commits]

MaskRay added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1213
 SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
-return Error(ErrorLoc,
- "operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]");
+return Error(
+ErrorLoc,

Bad indentation



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1617
 
+if (getLexer().getKind() == AsmToken::EndOfStatement) {
+  Operands.push_back(RISCVOperand::createVType(Sew, Lmul, Fractional, false,

Bad indentation


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80802/new/

https://reviews.llvm.org/D80802



___
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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 267239.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80802/new/

https://reviews.llvm.org/D80802

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/ext.s
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/invalid.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/snippet.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/vsetvl.s

Index: llvm/test/MC/RISCV/rvv/vsetvl.s
===
--- llvm/test/MC/RISCV/rvv/vsetvl.s
+++ llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -8,12 +8,72 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+vsetvli a2, a0, e32,m1
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 
+
+vsetvli a2, a0, e32,m2
+# CHECK-INST: vsetvli a2, a0, e32,m2
+# CHECK-ENCODING: [0x57,0x76,0x95,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 00 
+
 vsetvli a2, a0, e32,m4
 # CHECK-INST: vsetvli a2, a0, e32,m4
 # CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 76 a5 00 
 
+vsetvli a2, a0, e32,m8
+# CHECK-INST: vsetvli a2, a0, e32,m8
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 00 
+
+vsetvli a2, a0, e32,mf2
+# CHECK-INST: vsetvli a2, a0, e32,mf2
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 02 
+
+vsetvli a2, a0, e32,mf4
+# CHECK-INST: vsetvli a2, a0, e32,mf4
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 02 
+
+vsetvli a2, a0, e32,mf8
+# CHECK-INST: vsetvli a2, a0, e32,mf8
+# CHECK-ENCODING: [0x57,0x76,0x95,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 02 
+
+vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 0c 
+
+vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 08 
+
+vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-ENCODING: [0x57,0x76,0x85,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 04 
+
+vsetvli a2, a0, e32,m1,tu,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 
+
 vsetvl a2, a0, a1
 # CHECK-INST: vsetvl a2, a0, a1
 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
Index: llvm/test/MC/RISCV/rvv/store.s
===
--- llvm/test/MC/RISCV/rvv/store.s
+++ llvm/test/MC/RISCV/rvv/store.s
@@ -8,200 +8,296 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vsb.v v24, (a0), v0.t
-# CHECK-INST: vsb.v v24, (a0), v0.t
+vse8.v v24, (a0), v0.t
+# CHECK-INST: vse8.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 00 
 
-vsb.v v24, (a0)
-# CHECK-INST: vsb.v v24, (a0)
+vse8.v v24, (a0)
+# CHECK-INST: vse8.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 02 
 
-vsh.v v24, (a0), v0.t
-# CHECK-INST: vsh.v v24, (a0), v0.t
+vse16.v v24, (a0), v0.t
+# CHECK-INST: vse16.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 05 00 
 
-vsh.v v24, (a0)
-# CHECK-INST: vsh.v v24, (a0)
+vse16.v v24, (a0)
+# CHECK-INST: vse16.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x02]
 #