[PATCH] D60539: Add -std=c++14 language standard option to tests that require C++14 default

amyk created this revision. amyk added reviewers: ilya-biryukov, sammccall, ioeric, hokein, akyrtzi, yvvan. amyk added projects: clang, LLVM. Herald added subscribers: kadircet, arphaman, dexonsmith, jkorous. On one of the platforms that we build on, we build with the CMake macro,

[PATCH] D77542: [PowerPC] Treat 'Z' inline asm constraint as a true memory constraint

amyk added inline comments. Comment at: clang/lib/Basic/Targets/PPC.h:277 break; case 'Q': // Memory operand that is an offset from a register (it is // usually better to use `m' or `es' in asm statements) Just curious, but does this

[PATCH] D77542: [PowerPC] Treat 'Z' inline asm constraint as a true memory constraint

amyk added inline comments. Comment at: clang/lib/Basic/Targets/PPC.h:277 break; case 'Q': // Memory operand that is an offset from a register (it is // usually better to use `m' or `es' in asm statements) nemanjai wrote: > amyk wrote:

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

amyk added a comment. I believe we're also missing `IsISA3_1 = false;` in `PPCSubtarget.cpp`. Comment at: llvm/lib/Target/PowerPC/PPC.td:338 + // still exist with the exception of those we know are Power9 specific. + list P10AdditionalFeatures = [DirectivePwr10]; + list

[PATCH] D80294: Add support for vmsumudm

amyk added a comment. I think this overall looks good, but just curious, why was the builtin support removed? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80294/new/ https://reviews.llvm.org/D80294 ___ cfe-commits mailing list

[PATCH] D80294: Add support for vmsumudm

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1365 +// Vector Multiply-Sum +def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm, Maybe we can put this definition near the other VMSUM instructions? Since

[PATCH] D80294: Add support for vmsumudm

amyk accepted this revision. amyk added a comment. Thanks for explaining. This LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80294/new/ https://reviews.llvm.org/D80294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D82725: [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang

amyk added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82725/new/ https://reviews.llvm.org/D82725 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D82726: [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

amyk added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82726/new/ https://reviews.llvm.org/D82726 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGefa57f9a7adb: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang (authored by amyk). Changed prior to commit:

[PATCH] D87671: [PowerPC] Implement Vector String Isolate Builtins in Clang/LLVM

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:925 + "vstribr", "$vT, $vB", IIC_VecGeneral, +[(set v16i8:$vT, + (int_ppc_altivec_vstribr

[PATCH] D87671: [PowerPC] Implement Vector String Isolate Builtins in Clang/LLVM

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, nemanjai, saghir. amyk added projects: PowerPC, LLVM. Herald added subscribers: shchenz, hiraditya. Herald added a project: clang. amyk requested review of this revision. This patch implements the vector string isolate

[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

amyk requested changes to this revision. amyk added a comment. This revision now requires changes to proceed. A question I have is, is it possible for the 128-bit vector modulo instructions be open coded? Comment at: clang/lib/Headers/altivec.h:17394 +static __inline__ vector

[PATCH] D87729: [PowerPC] Implement the 128-bit Vector Divide Extended Builtins in Clang/LLVM

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, Conanap, nemanjai. amyk added projects: LLVM, PowerPC. Herald added subscribers: shchenz, hiraditya. Herald added a project: clang. amyk requested review of this revision. This patch implements the 128-bit vector divide

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk added a comment. @nemanjai Could you please take another look to see if I have addressed your comments? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500 ___

[PATCH] D86795: [PowerPC] Implement builtins for xvcvspbf16 and xvcvbf16spn

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG0c2d872d5dec: [PowerPC] Implement builtins for xvcvspbf16 and xvcvbf16spn (authored by amyk). Changed prior to commit:

[PATCH] D82675: [PowerPC] Implement Vector Extract Mask builtins in LLVM/Clang

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc7ec3a7e338c: [PowerPC] Implement Vector Extract Mask builtins in LLVM/Clang (authored by amyk). Changed prior to commit:

[PATCH] D82609: [PowerPC] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk added inline comments. Comment at: llvm/test/CodeGen/PowerPC/p10-vector-divide.ll:59 + +define <4 x i32> @test_vdivesw(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vdivesw: NeHuang wrote: > nit: do we also need `_intrinsic` in the name as the test

[PATCH] D86795: [PowerPC] Implement builtins for xvcvspbf16 and xvcvbf16spn

amyk created this revision. amyk added reviewers: bsaleil, lei, nemanjai, power-llvm-team, PowerPC. amyk added projects: LLVM, PowerPC. Herald added subscribers: llvm-commits, cfe-commits, shchenz, hiraditya. Herald added a project: clang. amyk requested review of this revision. This patch adds

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 287142. amyk added a comment. Address review comments: - Further consolidate the custom codegen of the two builtins - Add SemaChecking for if the third argument is a constant, if the third argument is in range and if the second argument is the same type as the

[PATCH] D82609: [PowerPC] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG76b0f99ea854: [PowerPC] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang (authored by amyk). Changed prior to commit:

[PATCH] D82725: [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang

amyk added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82725/new/ https://reviews.llvm.org/D82725 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D82726: [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

amyk added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82726/new/ https://reviews.llvm.org/D82726 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

amyk updated this revision to Diff 287434. amyk added a comment. Update clang test names for `vec_expandm`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 Files:

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 287444. amyk added a comment. Update to address clang-format. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500 Files: clang/include/clang/Basic/BuiltinsPPC.def

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 293313. amyk added a comment. Address Nemanja's review comments: - More specific comments when bitcasting the inputs - Pull out conditions to bitcast the input, use ternary op depending if the input is 32 or 64-bits - Create new static function to check if a

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 293779. amyk added a comment. - Updated the `isEltOfVectorTy()` to the correct semantics; making it take in a vector type and then getting the element type within the function. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG6b136b19cbe4: [Power10] Implement custom codegen for the vec_replace_elt and… (authored by amyk). Changed prior to commit:

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk added a comment. @nemanjai Would you please take another look to see if I have addressed your comments when you get a chance? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500

[PATCH] D87729: [PowerPC] Implement the 128-bit Vector Divide Extended Builtins in Clang/LLVM

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb3147058dec7: [PowerPC] Implement the 128-bit Vector Divide Extended Builtins in Clang/LLVM (authored by amyk). Repository: rG LLVM Github

[PATCH] D87671: [PowerPC] Implement Vector String Isolate Builtins in Clang/LLVM

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG079757b551f3: [PowerPC] Implement Vector String Isolate Builtins in Clang/LLVM (authored by amyk). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D88278: [PowerPC] Add builtins for xvtdiv(dp|sp) and xvtsqrt(dp|sp).

amyk accepted this revision as: amyk. amyk added a comment. This revision is now accepted and ready to land. Overall I think this LGTM. Please correct me if I am wrong but I think the description of the functions need to be updated to: int vec_test_swdiv(vector double v1, vector double v2);

[PATCH] D82725: [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG37e7673c21af: [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang (authored by amyk). Changed prior to commit:

[PATCH] D84968: [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:846 + +let Predicates = [MMA] in { + def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)), Just my opinion but maybe we can put this block under the

[PATCH] D82725: [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang

amyk updated this revision to Diff 292634. amyk added a comment. - Rebased patch. - Update patch to remove unnecessary immediate handling. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82725/new/ https://reviews.llvm.org/D82725 Files:

[PATCH] D86819: [PowerPC][Power10] Implementation of 128-bit Binary Vector Rotate builtins

amyk added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:4 // RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \ -// RUN: -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK +// RUN: -o - | FileCheck %s

[PATCH] D82725: [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10054 + + case Intrinsic::ppc_altivec_mtvsrbm: { +// The llvm.ppc.altivec.mtvsrbm intrinsic can correspond to two different steven.zhang wrote: > Can we handle this inside

[PATCH] D82726: [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2c3bc918db35: [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang (authored by amyk). Changed prior to commit:

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp:653 // On P7, P8 or P9 we have a cache line size of 128. unsigned Directive = ST->getCPUDirective(); Should this comment be updated to include P10 as well?

[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

amyk accepted this revision. amyk added a comment. This revision is now accepted and ready to land. This LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80758/new/ https://reviews.llvm.org/D80758

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: nemanjai, lei, stefanp, saghir, power-llvm-team. amyk added a project: LLVM. Herald added subscribers: shchenz, hiraditya. Herald added a project: clang. This patch implements builtins for the following prototypes: unsigned long long

[PATCH] D80941: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: nemanjai, lei, stefanp, saghir, power-llvm-team, hfinkel. amyk added a project: LLVM. Herald added subscribers: shchenz, hiraditya. Herald added a project: clang. This patch implements builtins for the following prototypes: unsigned long long

[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

amyk updated this revision to Diff 267648. amyk added a comment. Updated a typo within the comment in `llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80935/new/ https://reviews.llvm.org/D80935

[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: lei, stefanp, nemanjai, saghir, power-llvm-team. Herald added subscribers: llvm-commits, cfe-commits, shchenz, hiraditya. Herald added projects: clang, LLVM. amyk updated this revision to Diff 267648. amyk added a comment. Updated a typo within

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

amyk accepted this revision. amyk added a comment. This LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https://reviews.llvm.org/D80020 ___ cfe-commits mailing list

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

amyk accepted this revision. amyk added a comment. I think this looks good aside from the comments I had. Comment at: llvm/lib/Target/PowerPC/PPCSubtarget.h:142 bool IsISA3_0; + bool IsISA3_1; bool UseLongCalls; Missing `IsISA3_1 = false;` in

[PATCH] D87729: [PowerPC] Implement the 128-bit Vector Divide Extended Builtins in Clang/LLVM

amyk added a comment. In D87729#2275667 , @Conanap wrote: > Looks like there's some unit test failures; could you double check? We discussed offline; I've tested this again afterwards and looked into failures. Unit tests failures are not a result of

[PATCH] D87804: [PowerPC][Power10] Implement Vector signed/unsigned __int128 overloads for the comparison builtins

amyk accepted this revision. amyk added a comment. This revision is now accepted and ready to land. Forgot to approve this patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87804/new/ https://reviews.llvm.org/D87804

[PATCH] D87910: [PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins in Clang/LLVM

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, nemanjai, saghir, Conanap. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. amyk requested review of this revision. This patch implements the vec_[all|any]_[eq | ne | lt | gt | le |

[PATCH] D87671: [PowerPC] Implement Vector String Isolate Builtins in Clang/LLVM

amyk updated this revision to Diff 292830. amyk added a comment. Address clang-format concerns. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87671/new/ https://reviews.llvm.org/D87671 Files: clang/include/clang/Basic/BuiltinsPPC.def

[PATCH] D87804: [PowerPC][Power10] Implement Vector signed/unsigned __int128 overloads for the comparison builtins

amyk added a comment. Please address clang-format issues and Lei's comments. Other than that, I think the patch LGTM. Comment at: llvm/test/CodeGen/PowerPC/vec_cmpq.ll:14 +; CHECK-LABEL: v1si128_cmp: +; CHECK: vcmpequq 2, 2, 3 +} lei wrote: > please add the

[PATCH] D87910: [PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins in Clang/LLVM

amyk updated this revision to Diff 293161. amyk added a comment. Updated identation/formatting of code in `CGExprScalar.cpp` and `altivec.h`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87910/new/ https://reviews.llvm.org/D87910 Files:

[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

amyk accepted this revision. amyk added a comment. This revision is now accepted and ready to land. Thanks for open coding. Aside from Nemanja's nits, I believe all my concerns have been addressed. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87394/new/

[PATCH] D81748: [PowerPC] Add MMA builtin decoding and definitions

amyk added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:2050 + QualType DecodeTypeStr(const char *, const ASTContext , + ASTContext::GetBuiltinTypeError , I think it might be good to add a small comment here/in

[PATCH] D84277: [PowerPC][Power10] Fix vins*vlx instructions to have i32 arguments.

amyk created this revision. amyk added reviewers: power-llvm-team, nemanjai, PowerPC, rzurob. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. Previously, the vins*vlx instructions were incorrectly defined with i64 as the second argument. This patches

[PATCH] D84291: [PowerPC][Power10] Fix the Test LSB by Byte (xvtlsbb) Builtins Implementation

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, nemanjai, rzurob. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. The implementation of the `xvtlsbb` builtins/intrinsics were not correct as the intrinsics previously used `i1`

[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

amyk updated this revision to Diff 283065. amyk added a comment. Rebased the patch and removed MC tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 Files: clang/include/clang/Basic/BuiltinsPPC.def

[PATCH] D82726: [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

amyk updated this revision to Diff 283109. amyk added a comment. Rebased patch and removed MC tests from the patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82726/new/ https://reviews.llvm.org/D82726 Files:

[PATCH] D82725: [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang

amyk updated this revision to Diff 283113. amyk added a comment. Rebased patch, and removed MC tests from the original patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82725/new/ https://reviews.llvm.org/D82725 Files:

[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:881 + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1144 +(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>; + def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)), +(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>; amyk

[PATCH] D85453: [PowerPC] Implement __int128 vector divide operations

amyk accepted this revision as: amyk. amyk added a comment. This revision is now accepted and ready to land. Overall LGTM. Comment at: llvm/test/CodeGen/PowerPC/p10-vector-divide.ll:53 + +define <1 x i128> @test_vdivsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone { +;

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk added a comment. I realized I didn't put a comment on this earlier but this overall LGTM, but I think it would be good to see if @nemanjai has any additional comments on this patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/

[PATCH] D82609: [PowerPC] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82609/new/ https://reviews.llvm.org/D82609 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc4e574323210: [PowerPC] Implement low-order Vector Modulus Builtins, and add Vector… (authored by amyk). Changed prior to commit:

[PATCH] D84197: [PowerPC][Power10] Vector String Isolate instruction definitions and MC Tests

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG93fd8dbdc250: [PowerPC] Add Vector String Isolate instruction definitions and MC Tests (authored by Conanap, committed by amyk). Repository: rG

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk accepted this revision. amyk added inline comments. This revision is now accepted and ready to land. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:703 +vector signed __int128 test_vec_xl_sext_i8(void) { + // CHECK: load i8 + // CHECK: sext i8 It

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk accepted this revision. amyk added a comment. This revision is now accepted and ready to land. Thanks for addressing the comments. LGTM. Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:10 + +; These tests ensure that vector shift quadword builtins are correctly

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1100 + +if (Subtarget.isISA3_1()) { + setOperationAction(ISD::SRA, MVT::v1i128, Legal); amyk wrote: > No brackets are needed here. > > Also, I think it might make sense

[PATCH] D84622: [PowerPC] Implement Vector Extract Low/High Order Builtins in LLVM/Clang

amyk accepted this revision. amyk added a comment. I think overall it LGTM and the indentation can be addressed when committing. Comment at: clang/lib/Headers/altivec.h:17082 +/* vec_extractl */ +static __inline__ vector unsigned long long __ATTRS_o_ai vec_extractl(

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added inline comments. Comment at: clang/lib/Headers/altivec.h:17217 + +/* vs[l | r | ra] */ +static __inline__ vector unsigned __int128 __ATTRS_o_ai Add a space after this comment. Comment at: clang/lib/Headers/altivec.h:17227

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

amyk updated this revision to Diff 274239. amyk added a comment. Updated revision to: - add the MC test cases into `vsx.s` and `vsx.txt`. - create a test file called `builtins-ppc-p10vsx.ll` to place all Power10 VSX builtins tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk updated this revision to Diff 274260. amyk added a comment. Updated the patch to move the MC/llc tests into the appropriate files. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82467/new/ https://reviews.llvm.org/D82467 Files:

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

amyk added a comment. @lei Could you please take another look at this to see if this change is OK? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 ___

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

amyk accepted this revision as: amyk. amyk added a comment. This revision is now accepted and ready to land. This LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83364/new/ https://reviews.llvm.org/D83364

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk marked 2 inline comments as done. amyk added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:79 +vector signed int test_vec_dive_si(void) { + // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32> + // CHECK-NEXT: ret <4 x i32> lei wrote:

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk marked 2 inline comments as done. amyk added inline comments. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:339 +BUILTIN(__builtin_altivec_vec_replace_elt, "V4UiV4UiULLiIi", "t") +BUILTIN(__builtin_altivec_vec_replace_unaligned, "V4UiV4UiULLiIi", "t")

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk created this revision. amyk added reviewers: PowerPC, power-llvm-team, nemanjai, lei. amyk added projects: LLVM, PowerPC, clang. Herald added a subscriber: shchenz. This patch implements custom codegen for the `vec_replace_elt` and `vec_replace_unaligned` builtins. These builtins map to

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 276804. amyk added a comment. Updated for clang format changes. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/CodeGen/CGBuiltin.cpp

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk added a comment. Please update this patch to remove the instruction defs and MC tests. Also, you can update the patch to put your backend llc tests in the file I've introduced in: https://reviews.llvm.org/D82467 Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:14

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rG62f5ba624bfb: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang (authored by amyk). Changed prior to commit: https://reviews.llvm.org/D82431?vs=274667=277646#toc Repository: rG

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk added a comment. I think the patterns for the load instructions may have accidentally been deleted. Please add them back to the patch. Thank you. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added inline comments. Comment at: clang/lib/Headers/altivec.h:17151 + +/* vector shifts for quadwords */ +/* vs[l | r | raq] */ I think we can remove `/* vector shifts for quadwords */`. Then, we can add a new line after `/* vs[l | r | raq] */` for

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added inline comments. Comment at: clang/lib/Headers/altivec.h:17153 +/* vs[l | r | raq] */ +static __inline__ vector unsigned __int128 __ATTRS_o_ai +vec_slq(vector unsigned __int128 __a, vector unsigned __int128 __b) { I believe there are supposed to be

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 278019. amyk edited the summary of this revision. amyk added a parent revision: D83497: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.. amyk added a comment. Corrected the patch as it previously caused errors to

[PATCH] D83516: [PowerPC][Power10] 128-bit Binary Integer Operation instruction definitions and MC Tests

amyk accepted this revision. amyk added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83516/new/ https://reviews.llvm.org/D83516 ___ cfe-commits mailing list

[PATCH] D83497: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.

amyk updated this revision to Diff 277153. amyk retitled this revision from "[PowerPC][Power10] Fix the VINSW instruction to have an i32 argument." to "[PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.". amyk edited the summary of this revision. amyk

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 276853. amyk added a comment. Fix assignment of variable. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500 Files: clang/include/clang/Basic/BuiltinsPPC.def

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk requested changes to this revision. amyk added a comment. This revision now requires changes to proceed. This will need to be rebased against your 2608 instruction definitions patch. But yes, I believe you are missing the clang and llc test case for this patch. Requesting changes due to

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

This revision was automatically updated to reflect the committed changes. Closed by commit rG5ffec4672028: [PowerPC][Power10] Add Instruction definition/MC Tests for Load/Store Rightmost… (authored by Conanap, committed by amyk). Changed prior to commit:

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 276844. amyk added a comment. Address review comments - update comments - pull out common code Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500 Files:

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk marked 3 inline comments as done. amyk added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14273 +// The third argument to vec_replace_elt will be emitted to either +// the vinsw or vinsd instruction. It must be a compile time constant. +

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

amyk updated this revision to Diff 274667. amyk added a comment. Update patch to: - place MC tests in correct files Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 Files:

[PATCH] D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests

amyk updated this revision to Diff 274679. amyk edited the summary of this revision. amyk added a parent revision: D82584: [PowerPC][Power10] Exploit the High Order Vector Multiply Instructions on Power10. amyk added a comment. Rebased patch. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk updated this revision to Diff 274680. amyk edited the summary of this revision. amyk added a parent revision: D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests. amyk added a comment. Rebase patch, remove MC tests

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk updated this revision to Diff 274672. amyk added a comment. Update the patch to place MC tests into appropriate files. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82467/new/ https://reviews.llvm.org/D82467 Files:

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk marked an inline comment as done. amyk added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:108 + signed char *__c) { + // CHECK-BE: store i8 %{{.+}}, i8* %{{.+}}, align 1 + // CHECK-LE: store i8 %{{.+}}, i8* %{{.+}},

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk updated this revision to Diff 276881. amyk added a comment. Rebased patch, and addressed review comments of having a single `CHECK`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82467/new/ https://reviews.llvm.org/D82467 Files:

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

amyk added inline comments. Comment at: clang/test/Parser/p10-vector-bool-128.c:1 +// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu

[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

amyk marked an inline comment as done. amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCScheduleP9.td:47 + let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops, + IsISA3_1]; lei wrote: > Are

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