[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
amyk added inline comments. Comment at: llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll:5 ; CHECK-LABEL: TestULT: -; CHECK: xscmpudp +; CHECK: fcmpu ; CHECK: blr nemanjai wrote: > Why do we not emit the VSX instructions here any longer? How are crbits > related? Nemanja and I discussed this outside of the revision. This test case is ran with FastISel by default. It looks like for fcmp ULT/UEQ/UGT/OLE/ONE/OGE, we're not able to find a compare predicate, so we don't use FastIISel for these changed test cases. With my patch (turning on CR bits), we end up matching to fcmpu in the td patterns, but when CR bits are not present, we match to the VSX instructions in PPCISelDAGToDAG. This should be something we investigate at a later date. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124060/new/ https://reviews.llvm.org/D124060 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
amyk marked an inline comment as done.
Closed by commit rG2534dc120a4c: [PowerPC] Enable CR bits support for Power8
and above. (authored by amyk).
Changed prior to commit:
https://reviews.llvm.org/D124060?vs=425417=426439#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
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Files:
clang/docs/ClangCommandLineReference.rst
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-crbits.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/test/CodeGen/PowerPC/addegluecrash.ll
llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
Index: llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
===
--- llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
+++ llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
@@ -45,6 +45,7 @@
; CHECK-LE-LABEL: i32_ZextLoad_i1:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:clrldi r3, r3, 63
; CHECK-LE-NEXT:pstb r3, GlobSt1@PCREL(0), 1
; CHECK-LE-NEXT:blr
;
@@ -53,6 +54,7 @@
; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
; CHECK-BE-NEXT:addis r4, r2, GlobSt1@toc@ha
; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:clrldi r3, r3, 63
; CHECK-BE-NEXT:stb r3, GlobSt1@toc@l(r4)
; CHECK-BE-NEXT:blr
entry:
@@ -77,11 +79,11 @@
; CHECK-LE-NEXT:paddi r3, 0, Glob1@PCREL, 1
; CHECK-LE-NEXT:paddi r4, 0, Glob2@PCREL, 1
; CHECK-LE-NEXT:bl Decl@notoc
-; CHECK-LE-NEXT:plbz r4, GlobLd1@PCREL(0), 1
-; CHECK-LE-NEXT:cmplwi r3, 0
-; CHECK-LE-NEXT:li r3, 1
-; CHECK-LE-NEXT:iseleq r3, 0, r3
-; CHECK-LE-NEXT:and r3, r3, r4
+; CHECK-LE-NEXT:cmpwi cr1, r3, 0
+; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:andi. r3, r3, 1
+; CHECK-LE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-LE-NEXT:setbc r3, 4*cr5+lt
; CHECK-LE-NEXT:addi r1, r1, 32
; CHECK-LE-NEXT:ld r0, 16(r1)
; CHECK-LE-NEXT:mtlr r0
@@ -100,12 +102,12 @@
; CHECK-BE-NEXT:addi r4, r4, Glob2@toc@l
; CHECK-BE-NEXT:bl Decl
; CHECK-BE-NEXT:nop
-; CHECK-BE-NEXT:addis r4, r2, GlobLd1@toc@ha
-; CHECK-BE-NEXT:cmplwi r3, 0
-; CHECK-BE-NEXT:li r3, 1
-; CHECK-BE-NEXT:lbz r4, GlobLd1@toc@l(r4)
-; CHECK-BE-NEXT:iseleq r3, 0, r3
-; CHECK-BE-NEXT:and r3, r3, r4
+; CHECK-BE-NEXT:cmpwi cr1, r3, 0
+; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
+; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:andi. r3, r3, 1
+; CHECK-BE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-BE-NEXT:setbc r3, 4*cr5+lt
; CHECK-BE-NEXT:addi r1, r1, 112
; CHECK-BE-NEXT:ld r0, 16(r1)
; CHECK-BE-NEXT:mtlr r0
Index: llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
===
--- llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -7,11 +7,11 @@
; CHECK: # %bb.0: # %entry
; CHECK-NEXT:xscvdpsxws 0, 1
; CHECK-NEXT:mffprwz 3, 0
-; CHECK-NEXT:xori 3, 3, 65534
-; CHECK-NEXT:cntlzw 3, 3
-; CHECK-NEXT:srwi 4, 3, 5
-; CHECK-NEXT:# implicit-def: $x3
-; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:cmplwi 3, 65534
+; CHECK-NEXT:crmove 20, 2
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:li 3, 1
+; CHECK-NEXT:isel 3, 3, 4, 20
; CHECK-NEXT:blr
entry:
%conv = fptoui double %a to i16
Index: llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
===
--- llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
+++ llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
@@ -5,25 +5,19 @@
define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; CHECK-LABEL: une_ppcf128:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xscmpudp cr7, f2, f4
-; CHECK-NEXT:mfocrf r4, 1
-; CHECK-NEXT:rlwinm r4, r4, 31, 31, 31
-; CHECK-NEXT:xori r4, r4, 1
-; CHECK-NEXT:and r4, r3, r4
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xori r3, r3, 1
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r5, 1
-; CHECK-NEXT:rlwinm r5, r5, 31, 31, 31
-; CHECK-NEXT:xori r5, r5, 1
-; CHECK-NEXT:and r3, r3, r5
-; CHECK-NEXT:or r3, r3, r4
-; CHECK-NEXT:# kill: def $r4 killed $r3
+; CHECK-NEXT:fcmpu cr0, f1, f3
+; CHECK-NEXT:crmove 4*cr5+lt, eq
+; CHECK-NEXT:fcmpu cr1,
[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
shchenz added inline comments.
Comment at: clang/lib/Basic/Targets/PPC.cpp:519
.Default(false);
+ Features["crbits"] = llvm::StringSwitch(CPU)
+.Case("ppc64le", true)
shchenz wrote:
> nemanjai wrote:
> > shchenz wrote:
> > > amyk wrote:
> > > > shchenz wrote:
> > > > > If we set the `+crbits` by the arch name, do we still need the
> > > > > customization (Turn on crbits for O2 and above) in
> > > > > `computeFSAdditions()`?
> > > > Yeah, that's a good point. I looked into this previously, and it
> > > > appears that addition of `-mcrbits` inside `computeFSAdditions()` may
> > > > still be necessary.
> > > >
> > > > In particular, we have test cases that test pre-POWER8 with
> > > > optimizations on (or, if no optimization level is provided, then -O2 is
> > > > assumed the default). In these cases, much of the code changes if the
> > > > customization inside `computeFSAdditions()` is removed because we would
> > > > no longer be using crbits pre-P8.
> > > hmm, OK, then we still have the same issue that this patch fixes for
> > > pre-POWER8. I'm ok with leaving it for now as IMO Power7/Power6 should
> > > not be major versions for PowerPC.
> > Up until Power8, the only instructions we had that require `crbits` were
> > CR-logicals (which existed since the POWER architecture - i.e. before
> > PowerPC). In Power8, we added BCD instructions that also require `crbits`.
> > So that's why we turn it on for Power8 and up.
> Fail enough.
haha, I mean fair
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[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
shchenz added inline comments.
Comment at: clang/lib/Basic/Targets/PPC.cpp:519
.Default(false);
+ Features["crbits"] = llvm::StringSwitch(CPU)
+.Case("ppc64le", true)
nemanjai wrote:
> shchenz wrote:
> > amyk wrote:
> > > shchenz wrote:
> > > > If we set the `+crbits` by the arch name, do we still need the
> > > > customization (Turn on crbits for O2 and above) in
> > > > `computeFSAdditions()`?
> > > Yeah, that's a good point. I looked into this previously, and it appears
> > > that addition of `-mcrbits` inside `computeFSAdditions()` may still be
> > > necessary.
> > >
> > > In particular, we have test cases that test pre-POWER8 with optimizations
> > > on (or, if no optimization level is provided, then -O2 is assumed the
> > > default). In these cases, much of the code changes if the customization
> > > inside `computeFSAdditions()` is removed because we would no longer be
> > > using crbits pre-P8.
> > hmm, OK, then we still have the same issue that this patch fixes for
> > pre-POWER8. I'm ok with leaving it for now as IMO Power7/Power6 should not
> > be major versions for PowerPC.
> Up until Power8, the only instructions we had that require `crbits` were
> CR-logicals (which existed since the POWER architecture - i.e. before
> PowerPC). In Power8, we added BCD instructions that also require `crbits`. So
> that's why we turn it on for Power8 and up.
Fail enough.
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[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
nemanjai added inline comments. Comment at: clang/docs/ClangCommandLineReference.rst:3566 +Control the CR-bit tracking feature on PowerPC. ``-mcrbits`` (the enablement of CR-bit tracking support) is the default for POWER8 and above. + ``` ... is the default for POWER8 and above as well as for all other CPUs when optimization is applied (-O2 and above). ``` But please check if it is also applied at -O1 and correct that statement accordingly. Comment at: llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll:5 ; CHECK-LABEL: TestULT: -; CHECK: xscmpudp +; CHECK: fcmpu ; CHECK: blr Why do we not emit the VSX instructions here any longer? How are crbits related? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124060/new/ https://reviews.llvm.org/D124060 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
nemanjai added inline comments.
Comment at: clang/lib/Basic/Targets/PPC.cpp:519
.Default(false);
+ Features["crbits"] = llvm::StringSwitch(CPU)
+.Case("ppc64le", true)
shchenz wrote:
> amyk wrote:
> > shchenz wrote:
> > > If we set the `+crbits` by the arch name, do we still need the
> > > customization (Turn on crbits for O2 and above) in
> > > `computeFSAdditions()`?
> > Yeah, that's a good point. I looked into this previously, and it appears
> > that addition of `-mcrbits` inside `computeFSAdditions()` may still be
> > necessary.
> >
> > In particular, we have test cases that test pre-POWER8 with optimizations
> > on (or, if no optimization level is provided, then -O2 is assumed the
> > default). In these cases, much of the code changes if the customization
> > inside `computeFSAdditions()` is removed because we would no longer be
> > using crbits pre-P8.
> hmm, OK, then we still have the same issue that this patch fixes for
> pre-POWER8. I'm ok with leaving it for now as IMO Power7/Power6 should not be
> major versions for PowerPC.
Up until Power8, the only instructions we had that require `crbits` were
CR-logicals (which existed since the POWER architecture - i.e. before PowerPC).
In Power8, we added BCD instructions that also require `crbits`. So that's why
we turn it on for Power8 and up.
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[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
shchenz accepted this revision as: shchenz.
shchenz added a comment.
This revision is now accepted and ready to land.
LGTM. Thanks for fixing.
Comment at: clang/lib/Basic/Targets/PPC.cpp:519
.Default(false);
+ Features["crbits"] = llvm::StringSwitch(CPU)
+.Case("ppc64le", true)
amyk wrote:
> shchenz wrote:
> > If we set the `+crbits` by the arch name, do we still need the
> > customization (Turn on crbits for O2 and above) in `computeFSAdditions()`?
> Yeah, that's a good point. I looked into this previously, and it appears that
> addition of `-mcrbits` inside `computeFSAdditions()` may still be necessary.
>
> In particular, we have test cases that test pre-POWER8 with optimizations on
> (or, if no optimization level is provided, then -O2 is assumed the default).
> In these cases, much of the code changes if the customization inside
> `computeFSAdditions()` is removed because we would no longer be using crbits
> pre-P8.
hmm, OK, then we still have the same issue that this patch fixes for
pre-POWER8. I'm ok with leaving it for now as IMO Power7/Power6 should not be
major versions for PowerPC.
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[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
amyk marked an inline comment as done.
amyk added inline comments.
Comment at: clang/lib/Basic/Targets/PPC.cpp:519
.Default(false);
+ Features["crbits"] = llvm::StringSwitch(CPU)
+.Case("ppc64le", true)
shchenz wrote:
> If we set the `+crbits` by the arch name, do we still need the customization
> (Turn on crbits for O2 and above) in `computeFSAdditions()`?
Yeah, that's a good point. I looked into this previously, and it appears that
addition of `-mcrbits` inside `computeFSAdditions()` may still be necessary.
In particular, we have test cases that test pre-POWER8 with optimizations on
(or, if no optimization level is provided, then -O2 is assumed the default). In
these cases, much of the code changes if the customization inside
`computeFSAdditions()` is removed because we would no longer be using crbits
pre-P8.
Comment at: clang/test/Driver/ppc-crbits.cpp:50
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
shchenz wrote:
> Do we need some cases for AIX?
Thanks, I've added some.
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[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
amyk updated this revision to Diff 425417.
amyk added a comment.
Address review comments of adding documentation to
`clang/docs/ClangCommandLineReference.rst` and adding AIX checks to
`clang/test/Driver/ppc-crbits.cpp`.
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Files:
clang/docs/ClangCommandLineReference.rst
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-crbits.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/test/CodeGen/PowerPC/addegluecrash.ll
llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
Index: llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
===
--- llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
+++ llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
@@ -45,6 +45,7 @@
; CHECK-LE-LABEL: i32_ZextLoad_i1:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:clrldi r3, r3, 63
; CHECK-LE-NEXT:pstb r3, GlobSt1@PCREL(0), 1
; CHECK-LE-NEXT:blr
;
@@ -53,6 +54,7 @@
; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
; CHECK-BE-NEXT:addis r4, r2, GlobSt1@toc@ha
; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:clrldi r3, r3, 63
; CHECK-BE-NEXT:stb r3, GlobSt1@toc@l(r4)
; CHECK-BE-NEXT:blr
entry:
@@ -77,11 +79,11 @@
; CHECK-LE-NEXT:paddi r3, 0, Glob1@PCREL, 1
; CHECK-LE-NEXT:paddi r4, 0, Glob2@PCREL, 1
; CHECK-LE-NEXT:bl Decl@notoc
-; CHECK-LE-NEXT:plbz r4, GlobLd1@PCREL(0), 1
-; CHECK-LE-NEXT:cmplwi r3, 0
-; CHECK-LE-NEXT:li r3, 1
-; CHECK-LE-NEXT:iseleq r3, 0, r3
-; CHECK-LE-NEXT:and r3, r3, r4
+; CHECK-LE-NEXT:cmpwi cr1, r3, 0
+; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:andi. r3, r3, 1
+; CHECK-LE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-LE-NEXT:setbc r3, 4*cr5+lt
; CHECK-LE-NEXT:addi r1, r1, 32
; CHECK-LE-NEXT:ld r0, 16(r1)
; CHECK-LE-NEXT:mtlr r0
@@ -100,12 +102,12 @@
; CHECK-BE-NEXT:addi r4, r4, Glob2@toc@l
; CHECK-BE-NEXT:bl Decl
; CHECK-BE-NEXT:nop
-; CHECK-BE-NEXT:addis r4, r2, GlobLd1@toc@ha
-; CHECK-BE-NEXT:cmplwi r3, 0
-; CHECK-BE-NEXT:li r3, 1
-; CHECK-BE-NEXT:lbz r4, GlobLd1@toc@l(r4)
-; CHECK-BE-NEXT:iseleq r3, 0, r3
-; CHECK-BE-NEXT:and r3, r3, r4
+; CHECK-BE-NEXT:cmpwi cr1, r3, 0
+; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
+; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:andi. r3, r3, 1
+; CHECK-BE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-BE-NEXT:setbc r3, 4*cr5+lt
; CHECK-BE-NEXT:addi r1, r1, 112
; CHECK-BE-NEXT:ld r0, 16(r1)
; CHECK-BE-NEXT:mtlr r0
Index: llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
===
--- llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -7,11 +7,11 @@
; CHECK: # %bb.0: # %entry
; CHECK-NEXT:xscvdpsxws 0, 1
; CHECK-NEXT:mffprwz 3, 0
-; CHECK-NEXT:xori 3, 3, 65534
-; CHECK-NEXT:cntlzw 3, 3
-; CHECK-NEXT:srwi 4, 3, 5
-; CHECK-NEXT:# implicit-def: $x3
-; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:cmplwi 3, 65534
+; CHECK-NEXT:crmove 20, 2
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:li 3, 1
+; CHECK-NEXT:isel 3, 3, 4, 20
; CHECK-NEXT:blr
entry:
%conv = fptoui double %a to i16
Index: llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
===
--- llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
+++ llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
@@ -5,25 +5,19 @@
define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; CHECK-LABEL: une_ppcf128:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xscmpudp cr7, f2, f4
-; CHECK-NEXT:mfocrf r4, 1
-; CHECK-NEXT:rlwinm r4, r4, 31, 31, 31
-; CHECK-NEXT:xori r4, r4, 1
-; CHECK-NEXT:and r4, r3, r4
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xori r3, r3, 1
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r5, 1
-; CHECK-NEXT:rlwinm r5, r5, 31, 31, 31
-; CHECK-NEXT:xori r5, r5, 1
-; CHECK-NEXT:and r3, r3, r5
-; CHECK-NEXT:or r3, r3, r4
-; CHECK-NEXT:# kill: def $r4 killed $r3
+; CHECK-NEXT:fcmpu cr0, f1, f3
+; CHECK-NEXT:crmove 4*cr5+lt, eq
+; CHECK-NEXT:fcmpu cr1, f2, f4
+; CHECK-NEXT:crmove 4*cr5+gt, 4*cr1+eq
+; CHECK-NEXT:crnot 4*cr5+gt, 4*cr5+gt
+; CHECK-NEXT:crand 4*cr5+gt, 4*cr5+lt,
[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
shchenz added a comment.
> This patch turns on support for CR bit accesses for Power8 and above. The
> reason why CR bits are turned on as the default for Power8 and above is that
> because later architectures make use of builtins and instructions that
> require CR bit accesses (such as the use of setbc in the vector string
> isolate predicate and bcd builtins on Power10).
Maybe we also can add some comments in `docs/ClangCommandLineReference.rst` to
explicitly say that `-mcrbits` will be default to on when PowerPC arch is no
smaller than 8. I believe some cr-bit operations also exist on Power7 or even
Power6?
Comment at: clang/lib/Basic/Targets/PPC.cpp:519
.Default(false);
+ Features["crbits"] = llvm::StringSwitch(CPU)
+.Case("ppc64le", true)
If we set the `+crbits` by the arch name, do we still need the customization
(Turn on crbits for O2 and above) in `computeFSAdditions()`?
Comment at: clang/test/Driver/ppc-crbits.cpp:50
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
Do we need some cases for AIX?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D124060/new/
https://reviews.llvm.org/D124060
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[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.
amyk created this revision.
amyk added reviewers: PowerPC, nemanjai, power-llvm-team.
amyk added projects: LLVM, clang, PowerPC.
Herald added subscribers: shchenz, hiraditya.
Herald added a project: All.
amyk requested review of this revision.
Herald added a subscriber: cfe-commits.
This patch turns on support for CR bit accesses for Power8 and above. The
reason why CR bits are turned
on as the default for Power8 and above is that because later architectures make
use of builtins and
instructions that require CR bit accesses (such as the use of `setbc` in the
vector string isolate predicate
and bcd builtins on Power10).
This patch also adds the clang portion to allow for turning on CR bits in the
front end if the user so desires to.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D124060
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-crbits.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/test/CodeGen/PowerPC/addegluecrash.ll
llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
Index: llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
===
--- llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
+++ llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
@@ -45,6 +45,7 @@
; CHECK-LE-LABEL: i32_ZextLoad_i1:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:clrldi r3, r3, 63
; CHECK-LE-NEXT:pstb r3, GlobSt1@PCREL(0), 1
; CHECK-LE-NEXT:blr
;
@@ -53,6 +54,7 @@
; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
; CHECK-BE-NEXT:addis r4, r2, GlobSt1@toc@ha
; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:clrldi r3, r3, 63
; CHECK-BE-NEXT:stb r3, GlobSt1@toc@l(r4)
; CHECK-BE-NEXT:blr
entry:
@@ -77,11 +79,11 @@
; CHECK-LE-NEXT:paddi r3, 0, Glob1@PCREL, 1
; CHECK-LE-NEXT:paddi r4, 0, Glob2@PCREL, 1
; CHECK-LE-NEXT:bl Decl@notoc
-; CHECK-LE-NEXT:plbz r4, GlobLd1@PCREL(0), 1
-; CHECK-LE-NEXT:cmplwi r3, 0
-; CHECK-LE-NEXT:li r3, 1
-; CHECK-LE-NEXT:iseleq r3, 0, r3
-; CHECK-LE-NEXT:and r3, r3, r4
+; CHECK-LE-NEXT:cmpwi cr1, r3, 0
+; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:andi. r3, r3, 1
+; CHECK-LE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-LE-NEXT:setbc r3, 4*cr5+lt
; CHECK-LE-NEXT:addi r1, r1, 32
; CHECK-LE-NEXT:ld r0, 16(r1)
; CHECK-LE-NEXT:mtlr r0
@@ -100,12 +102,12 @@
; CHECK-BE-NEXT:addi r4, r4, Glob2@toc@l
; CHECK-BE-NEXT:bl Decl
; CHECK-BE-NEXT:nop
-; CHECK-BE-NEXT:addis r4, r2, GlobLd1@toc@ha
-; CHECK-BE-NEXT:cmplwi r3, 0
-; CHECK-BE-NEXT:li r3, 1
-; CHECK-BE-NEXT:lbz r4, GlobLd1@toc@l(r4)
-; CHECK-BE-NEXT:iseleq r3, 0, r3
-; CHECK-BE-NEXT:and r3, r3, r4
+; CHECK-BE-NEXT:cmpwi cr1, r3, 0
+; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
+; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:andi. r3, r3, 1
+; CHECK-BE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-BE-NEXT:setbc r3, 4*cr5+lt
; CHECK-BE-NEXT:addi r1, r1, 112
; CHECK-BE-NEXT:ld r0, 16(r1)
; CHECK-BE-NEXT:mtlr r0
Index: llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
===
--- llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -7,11 +7,11 @@
; CHECK: # %bb.0: # %entry
; CHECK-NEXT:xscvdpsxws 0, 1
; CHECK-NEXT:mffprwz 3, 0
-; CHECK-NEXT:xori 3, 3, 65534
-; CHECK-NEXT:cntlzw 3, 3
-; CHECK-NEXT:srwi 4, 3, 5
-; CHECK-NEXT:# implicit-def: $x3
-; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:cmplwi 3, 65534
+; CHECK-NEXT:crmove 20, 2
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:li 3, 1
+; CHECK-NEXT:isel 3, 3, 4, 20
; CHECK-NEXT:blr
entry:
%conv = fptoui double %a to i16
Index: llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
===
--- llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
+++ llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
@@ -5,25 +5,19 @@
define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; CHECK-LABEL: une_ppcf128:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xscmpudp cr7, f2, f4
-; CHECK-NEXT:mfocrf r4, 1
-; CHECK-NEXT:rlwinm r4, r4, 31, 31, 31
-; CHECK-NEXT:xori r4, r4, 1
-; CHECK-NEXT:and r4, r3, r4
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xori r3, r3, 1
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r5, 1
-;
