OK, so I picked up the package from HaoRan LCD company and examined
their LCDs. Two observations, one expected, the other unexpected:
The expected observation: the end of the FPC tail that is meant to go
into a connector has straight edges, the corners are sharp 90 deg, no
rounding.
The
> [...] this idea will NOT work for our FreeCalypso handset. Our PCB will
> have 8 layers with lots of traces on every layer (intricate 2+4+2 HDI
> structure with inner buried vias and two levels of staggered microvias
> on each side), and the width of the PCB will extend only slightly past
> the
Hello FC community,
An update on the FreeCalypso handset project: I am still in the process
of evaluating candidate LCDs from different vendors. All of the
candidate LCD manufacturers I am evaluating are based in Shenzhen,
China - that city seems to be the world capital for fast-turn
electronic
Hi Mychaela,
You are unfortunately correct, that trace is on L6. Looking at L7
and bottom layers, there are many traces and I can't see any easy way
that trace could be cut without a PhD in PCB microsurgery. :/
> > BTW is there an easter egg in the PCB layout? I can read "TimLee Allen
> > Shawn
Hi DS!
> Looking at the project in Altium, it seems the signal trace from D5 to
> U201 sits at the bottom layer.
Do you have the ability to run Altium and open the PcbDoc natively?
If so, highlight the net named FDP. I don't have the ability to run
Altium myself (no Windows), but looking at the
On Sat, Apr 07, 2018 at 06:21:15PM -0800, Mychaela Falconia wrote:
> And we still need to fix and close the sleep mode bug. I have a high
> confidence in my current hypothesis that FDP driving the flash chip's
> reset line is the culprit, but it looks like we won't be able to test
> it
