* Rudolf Marek [EMAIL PROTECTED] [080218 23:30]:
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Hash: SHA1
Hi all
I'm attaching the patch which should fix both problems. Fix the undefined u8
type and the bitpos selection in currently unused pnp_read_enable function.
Signed-off-by: Rudolf Marek
On Tue, 19 Feb 2008, [EMAIL PROTECTED] wrote:
Quoting Peter Stuge [EMAIL PROTECTED]:
[..]
dd if=/dev/ioport bs=1 skip=$[0xbasehere] count=asmanyasyouwant | xxd
3. What is the pipe xxd for?
The default output of dd is stdout, so it writes stdout to file xxd.
However, why not use of=xxd
Sorry for joining in late. I wrote a utility a while ago that dumped the
GPIO registers of an ICH7. Maybe your registers look pretty similar.
My output is something like:
Intel Southbridge: 8086:27b8
GPIOBASE = 0x0480
gpiobase+0x: 0x1f1ff7c0
gpiobase+0x0004: 0xe0e8efc3
gpiobase+0x0008:
On Tue, Feb 19, 2008 at 09:17:17AM +0200, Mart Raudsepp wrote:
So basically it would be nice if setting up the serial port on
DDC pins would be a configurable thing.
As it should be! The 5536 code needs to learn how to control it, and
there could be a setting in the dts - for starters.
Or
* Martin-Éric Racine [EMAIL PROTECTED] [080215 19:34]:
Thankfully, most of them are easily fixed:
* News should be called ChangeLog and include the name of whoever made
each change.
* Each source file (c, h, S) must include proper copyright notice and
credits at the top.
* The build
On Tue, Feb 19, 2008 at 08:49:41AM +0200, Mart Raudsepp wrote:
Ühel kenal päeval, E, 2008-02-18 kell 08:12, kirjutas ron minnich:
Isn't just about any LX800 board going to put FLASH on the cs5536?
You have three places it can be and the DIVIL_BALL_OPTS MSR registry
needs to match that. If
Quoting Stefan Reinauer [EMAIL PROTECTED]:
Sorry for joining in late. I wrote a utility a while ago that dumped the
GPIO registers of an ICH7. Maybe your registers look pretty similar.
My output is something like:
Intel Southbridge: 8086:27b8
GPIOBASE = 0x0480
gpiobase+0x: 0x1f1ff7c0
Russell Whitaker skrev:
On Tue, 19 Feb 2008, [EMAIL PROTECTED] wrote:
Quoting Peter Stuge [EMAIL PROTECTED]:
[..]
dd if=/dev/ioport bs=1 skip=$[0xbasehere] count=asmanyasyouwant | xxd
3. What is the pipe xxd for?
The default output of dd is stdout, so it
On 2008-02-19 07:36 Stefan Reinauer said the following:
any details? I had no problems compiling it with
GNU C Library stable release version 2.7 (20071106)
gcc version 4.3.0 20080131 (experimental) [trunk revision 131976] (SUSE Linux)
This is what I get building it on the default
Hi all,
Just a note. Isadump util form Lm-sensors can do the SIO dumps as well
as flat io dumps. It can even unlock the SIO with a key :)
Supports SIO LDNs etc etc.
Rudolf
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* Carl-Daniel Hailfinger [EMAIL PROTECTED] [080216 22:12]:
LAR headers do not save information as to code vs. data, etc.
Our choices are:
1. continue with ELF support (though I do not intend to ever use it :-)
But the ELF support outside the LAR utility should be protected by ifdef
to
Quoting Tom Sylla [EMAIL PROTECTED]:
The dump tool is the way to go now, but just to answer a couple of your
questions:
[EMAIL PROTECTED] wrote:
OK, so lets clarify?
GPIOBASE?GPIO Base Address (LPC I/F?D31:F0)
31:16 Reserved
15:6 Base Address ? R/W. Provides the 64 bytes of I/O space for
The dump tool is the way to go now, but just to answer a couple of your
questions:
[EMAIL PROTECTED] wrote:
OK, so lets clarify?
GPIOBASE?GPIO Base Address (LPC I/F?D31:F0)
31:16 Reserved
15:6 Base Address ? R/W. Provides the 64 bytes of I/O space for GPIO.
5:1 Reserved
0 Resource
* [EMAIL PROTECTED] [EMAIL PROTECTED] [080219 15:40]:
I wish you would have brought this up earlier
Sorry. I had it on my CF disk for a while :(
As Ron said btw, this type of tool is incredibly useful, as you doubtless
know. I think we should mofify it for all the ICH's and add it to
Author: jcrouse
Date: 2008-02-19 16:47:25 +0100 (Tue, 19 Feb 2008)
New Revision: 119
Modified:
buildrom-devel/config/platforms/db800.conf
buildrom-devel/config/platforms/dbe61.conf
buildrom-devel/config/platforms/norwich.conf
Log:
[BUILDROM] Update Coreboot revision for Geode platforms
Author: jcrouse
Date: 2008-02-19 16:47:25 +0100 (Tue, 19 Feb 2008)
New Revision: 119
Modified:
buildrom-devel/config/platforms/db800.conf
buildrom-devel/config/platforms/dbe61.conf
buildrom-devel/config/platforms/norwich.conf
Log:
[BUILDROM] Update Coreboot revision for Geode platforms
On 19/02/08 05:59 -0700, Myles Watson wrote:
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of Jordan Crouse
Myles very nicely made all targets use the filename coreboot.rom,
and taught buildrom how to use that filename. Unfortunately, the
* Roman Kononov [EMAIL PROTECTED] [080219 16:12]:
On 2008-02-19 07:36 Stefan Reinauer said the following:
any details? I had no problems compiling it with GNU C Library stable
release version 2.7 (20071106)
gcc version 4.3.0 20080131 (experimental) [trunk revision 131976] (SUSE
Linux)
* Jordan Crouse [EMAIL PROTECTED] [080219 16:58]:
[BUILDROM] conslidate the V2 Geode targets
All the Geode targets are the same, so consolidate them into a single
target - this will make the forthcoming VSA changes much easier to
maintain.
Signed-off-by: Jordan Crouse [EMAIL PROTECTED]
Mikhail Savchenko wrote:
I’m already patch the Config.lb target source file basing the lspci output
Looking for parameters I should get for properly edit Option.lb target
source file, can anybody assist me at this?
Not sure, are you looking for this one?
Quoting Stefan Reinauer [EMAIL PROTECTED]:
* [EMAIL PROTECTED] [EMAIL PROTECTED] [080219 17:29]:
Vendor ID: rca, part ID: rm4100
Found chipset ICH4/ICH4-L, enabling flash write... OK.
NOT FOUND rca:rm4100
M50FW080 found at physical address 0xfff0.
Flash part is M50FW080 (1024 KB).
SO, this might be a good chance for a tutorial on how to figure out
what's up. We should start with the GPIO dump and work from there.
Do you have a gpio dump yet?
ron
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Next up on the path to openvsa, I present a patch to consolidate
all of the Geode V2 targets into a single file. Every one of the Geode LX
targets are identical, and consolidating them into a single file saves
us much hassle.
If in the future, one platform needs a patch that the others don't,
Quoting ron minnich [EMAIL PROTECTED]:
SO, this might be a good chance for a tutorial on how to figure out
what's up. We should start with the GPIO dump and work from there.
Do you have a gpio dump yet?
ron
Not yet, I am at work. I will work on it tonight when I get home.
Thanks - Joe
On 2/19/08, Jordan Crouse [EMAIL PROTECTED] wrote:
On 19/02/08 19:09 +0200, Martin-Éric Racine wrote:
On 2/19/08, Stefan Reinauer [EMAIL PROTECTED] wrote:
* Roman Kononov [EMAIL PROTECTED] [080219 16:12]:
On 2008-02-19 07:36 Stefan Reinauer said the following:
any details? I had no
I think we should store boot settings in a LAR file.
Just simple keyword value pairs
serial=
etc. etc.
The question is, when do we read/parse/act on this file? We could do
it at any time.
E.g. the serial port stuff could be done in initram, etc.
ron
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Quoting [EMAIL PROTECTED]:
Hello,
I am having issues with flashrom. It can read the bios ok and even
verify it but when I try to write it I get this:
[EMAIL PROTECTED] util]# flashrom -w test
Calibrating delay loop... OK.
Found coreboot table at 0x0530.
Vendor ID: rca, part ID: rm4100
Quoting Stefan Reinauer [EMAIL PROTECTED]:
* [EMAIL PROTECTED] [EMAIL PROTECTED] [080219 15:40]:
I wish you would have brought this up earlier
Sorry. I had it on my CF disk for a while :(
As Ron said btw, this type of tool is incredibly useful, as you doubtless
know. I think we should
Am Dienstag, den 19.02.2008, 16:07 +0100 schrieb Stefan Reinauer:
Drop entry and load address out of the LAR format. Instead, we define
a
coreboot native blob format which looks like the following and pack
it _into_ the lar.
++
| MAGIC |
On 2/19/08, Stefan Reinauer [EMAIL PROTECTED] wrote:
* Roman Kononov [EMAIL PROTECTED] [080219 16:12]:
On 2008-02-19 07:36 Stefan Reinauer said the following:
any details? I had no problems compiling it with GNU C Library stable
release version 2.7 (20071106)
gcc version 4.3.0 20080131
* [EMAIL PROTECTED] [EMAIL PROTECTED] [080219 17:29]:
Vendor ID: rca, part ID: rm4100
Found chipset ICH4/ICH4-L, enabling flash write... OK.
NOT FOUND rca:rm4100
M50FW080 found at physical address 0xfff0.
Flash part is M50FW080 (1024 KB).
ERASE FAILED @0, val 92!
After this I
On 2/19/08, Stefan Reinauer [EMAIL PROTECTED] wrote:
* Martin-Éric Racine [EMAIL PROTECTED] [080215 19:34]:
Thankfully, most of them are easily fixed:
* News should be called ChangeLog and include the name of whoever made
each change.
* Each source file (c, h, S) must include proper
I'm already patch the Config.lb target source file basing the lspci output
Looking for parameters I should get for properly edit Option.lb target
source file, can anybody assist me at this?
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Author: jcrouse
Date: 2008-02-19 19:03:58 +0100 (Tue, 19 Feb 2008)
New Revision: 120
Added:
buildrom-devel/packages/coreboot-v2/geodelx.mk
Modified:
buildrom-devel/config/platforms/alix1c.conf
buildrom-devel/config/platforms/db800.conf
buildrom-devel/config/platforms/dbe61.conf
Author: jcrouse
Date: 2008-02-19 19:05:23 +0100 (Tue, 19 Feb 2008)
New Revision: 121
Removed:
buildrom-devel/packages/coreboot-v2/alix1c.mk
buildrom-devel/packages/coreboot-v2/msm800sev.mk
buildrom-devel/packages/coreboot-v2/norwich.mk
Log:
Argh - these didn't get deleted from the
Author: jcrouse
Date: 2008-02-19 19:03:58 +0100 (Tue, 19 Feb 2008)
New Revision: 120
Added:
buildrom-devel/packages/coreboot-v2/geodelx.mk
Modified:
buildrom-devel/config/platforms/alix1c.conf
buildrom-devel/config/platforms/db800.conf
buildrom-devel/config/platforms/dbe61.conf
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Thanks,
r3109
Rudolf
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Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFHuzzE3J9wPJqZRNURAsJhAJ44hHQv9SF9IEIzxC+Nl5s4A8HmtgCff6Nz
64DJRHSDKo0Dz5jfdlRTEio=
=wGIy
Author: ruik
Date: 2008-02-19 21:30:25 +0100 (Tue, 19 Feb 2008)
New Revision: 3109
Modified:
trunk/coreboot-v2/src/devices/pnp_device.c
Log:
I'm attaching the patch which should fix both problems. Fix the
undefined u8 type and the bitpos selection in currently unused
pnp_read_enable
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Personally I would really prefer if we didn't need ACPI. Marc/Jordan
- do you know if there's an easy way to short-circuit the PSB BIOS
structure in the kernel powernow driver?
Hmm the PSB works only for singlecores :/
Rudolf
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On 19/02/08 22:00 +0100, Rudolf Marek wrote:
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Hash: SHA1
Personally I would really prefer if we didn't need ACPI. Marc/Jordan
- do you know if there's an easy way to short-circuit the PSB BIOS
structure in the kernel powernow driver?
Hmm the PSB works
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer ruik checked in revision 3109 to
the coreboot source repository and caused the following
changes:
Change Log:
I'm attaching the patch which should fix both problems. Fix the
undefined u8 type and the
Carl-Daniel Hailfinger wrote:
On 18.02.2008 23:55, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
it seems that executing VSA requires vm86 to be useful. Since we
unconditionally execute the VSA, we should unconditionally require vm86
support (PCI_OPTION_ROM_RUN_VM86) via Kconfig for Geode
Author: jcrouse
Date: 2008-02-19 22:52:36 +0100 (Tue, 19 Feb 2008)
New Revision: 122
Removed:
buildrom-devel/packages/vsa/olpc_vsa.64k.bin
Log:
Hmm - somehow we had this big 64k blob sitting around and nobody noticed. :)
Trivial deletion of unused code.
Signed-off-by: Jordan Crouse [EMAIL
Hi,
I'm trying to download the latest AMD Geode LX VSA from
http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.01.bin.gz
but it seems, the file is corrupted:
$ gunzip amd_vsa_lx_1.01.bin.gz
gzip: amd_vsa_lx_1.01.bin.gz: not in gzip format
$
Any hint what to do?
Best
This is the third patch in the update to the brave new VSA world.
This fixes up the VSA fetching to understand the upstream version
that is not nrv2b compressed, and we do the compressing and
padding locally within buildrom. I also remove most of the VSA
brains from the coreboot-v2 file. (See
Hi
I just checked around a bit and saw that at least part of my motherboard is
supported by Coreboot but its not on any of the lists.
Its a Asus P4PE. A old Pentium 4 motherboard with a Intel 82845PE MCH
northbridge and a Intel 82801DA ICH 4 southbridge.
Attached is the output of various
On Wed, Feb 20, 2008 at 11:00:00AM +1000, Nick Stallman wrote:
a Intel 82845PE MCH northbridge
This is the main problem. I don't think anyone has both documentation
and time for this at the moment. :\
and a Intel 82801DA ICH 4 southbridge.
The rest of the board should be fairly
Hi Ronald,
On Mon, Feb 18, 2008 at 10:45:23PM +0100, Ronald Hoogenboom wrote:
Finally, now I know it's working (at least the part that I'm patching
here...), here is the patch that uses PIO mode read from SPI rom with
lzma decompression.
This patch allows direct out-of-SPI-flash boot of a
Hello!
I believe this was covered before we moved the AMD VSA binary source code
over to the current location. It turns out that despite the presence of a gz
prefix after the file type, it was placed there as a plain binary blob.
Rename it to the name without the .gz at the end and then gzip -9
This is a first file for the dbe62. I am adding this so others can see
where to get the data sheet and maybe
help me get the right values in. :-)
thanks
ron
First file for dbe62. This is a different part, and timing, than dbe61
so they can not share this file.
Signed-off-by: Ronald G. Minnich
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