Hi Carl-Daniel,
Carl-Daniel Hailfinger schrieb:
On 11.05.2009 19:44, Frieder Ferlemann wrote:
I don't know whether this proposal really makes sense
but 8051 based Embedded Controlers are very likely to
have 0x02 (the opcode for LJMP) at address 0x and
at some of its IRQ entry points at
Hi, all,
The new auto-generated acpi table doesn't seem to be correct on dbm690t.
Dose anybody have any idea?
Joe
Please check the dmesg:
Booting 'Ubuntu 8.04, kernel 2.6.24-amd2-generic-serial'
root (hd0,0)
kernel /boot/vmlinuz-2.6.24-amd2-generic
root=UUID=7bb9e8a5-cbc0-4104-92a3-628
Hi Christian,
thanks for your patch.
A detailed review follows. Don't let the review discourage you,
Makefiles are always controversial. It is entirely possible someone will
post a different review which tells you all changes are good.
On 09.05.2009 04:32, Christian Ruppert wrote:
Hey guys,
Hi Zheng,
On 12.05.2009 10:38, Bao, Zheng wrote:
The new auto-generated acpi table doesn't seem to be correct on dbm690t.
Thanks for testing this. That problem is very unfortunate.
Dose anybody have any idea?
Is there a way to dump an ACPI table from coreboot in hex after it is
#134: flashrom crashes systems with WPCE775L embedded controller on LPC bus
+---
Reporter: Timo Juhani Lindfors timo.lindf...@… | Owner:
somebody
Type: defect
Hi,
It seemes like no table is found. Maybe it is problem of Seabios/Hightables?
Does seabios find the acpi tables?
Rudolf
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On Mon, 11 May 2009 20:54:38 +0200, Quentin RAMEAU quinq...@gmail.com
wrote:
Hi,
I have got a Veriton FP2 (
http://www.acersupport.com/desktop/html/vfp2.html)
with a S511P motherboard, Intel 82815 northbridge and 82801BA
southbridge.
I can do tests on it (socketed plcc32 bios and
Hello,
This may be a dumb question, but I was wondering, can I use SeaBIOS as a
payload without loading assembly blob roms?
I ask this because I am going to be running custom VGA code after VM86
excicutes the vga rom and returns back to coreboot. I don't think this
would be possible for SeaBIOS,
Hi,
You can either use LGPL VGA bios from http://www.nongnu.org/vgabios/ (use VGA
only image) or you can use vga bios from kevin just right in the Seabios.
But if you dont need any - I use SeaBIOS without any option ROMs and it works
too. (grub boots and boots kernel)
Rudolf
--
coreboot
It seems that you are right.
This error comes up when we add HAVE_HIGH_TABLES in k8/Config.lb
The payload I use is filo which is somehow old. Do I have to use the
SeaBios?
Zheng
-Original Message-
From: Rudolf Marek [mailto:r.ma...@assembler.cz]
Sent: Tuesday, May 12, 2009 5:13 PM
To:
Sorry I forgot to answer. Just dont put there any option rom (no BDF defines, no
cbfs rom module)
Rudolf
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Bao, Zheng wrote:
It seems that you are right.
This error comes up when we add HAVE_HIGH_TABLES in k8/Config.lb
The payload I use is filo which is somehow old. Do I have to use the
SeaBios?
Not have to. It should work like this too. Maybe you can try with some debug
level - Seabios will
Hello,
I'm about to order some DIP8 SPI flashes size 1MB. If someone is from europe I
think I can send them just like a normal letter.
Farnell wants 5EUR for postage, but I have in plan to use some local distributor
so I hope to be like 2EUR.
They have also 512KB
Am 12.05.2009 10:38, schrieb Bao, Zheng:
Hi, all,
The new auto-generated acpi table doesn't seem to be correct on dbm690t.
Dose anybody have any idea?
[0.00] ACPI: RSDP signature @ 0x810F0400 checksum 0
[0.00] ACPI: RSDP 000F0400, 0024 (r2 CORE )
With both
#134: flashrom crashes systems with WPC876x/WPCE775x embedded controller on LPC
bus
+---
Reporter: Timo Juhani Lindfors timo.lindf...@… | Owner:
somebody
Type:
Dear list(s),
This is the final patch that got everything working for me with the HP dl145g3.
I would like to remind you that this firmware enables the hardware
virtualization on the AMD cpu's on the machine. That feature was
explicitly disabled by the factory BIOS.
Due to an error in the VGAROM
Hi,
Thats very nice! I just wanted to ask if you know in what register/MSR gets the
SVM disabled. Or maybe Marc will know?
Thanks,
Rudolf
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Please check the coreboot log.
Based on the dmesg, The kernel can find the RSD PTR in 0xf0400. But who
knows what happens next?
Zheng
-
Devices initialized
High Tables Base is 3fff.
Writing IRQ routing tables to 0xf...write_pirq_routing_table done.
Writing IRQ routing
On Tue, 12 May 2009 12:53:43 +0200, Rudolf Marek r.ma...@assembler.cz
wrote:
Hi,
You can either use LGPL VGA bios from http://www.nongnu.org/vgabios/ (use
VGA
only image) or you can use vga bios from kevin just right in the Seabios.
I don't know if this is an option, I don't want it to
Ok, but do you have vga output or just serial console.
if VGA is initialized in coreboot - use the free VGA bios as ROM for Seabios.
Will SeaBIOS know vga has already been initialized and send output to the
vga screen?
No it needs some bios (I think)
Rudolf
--
coreboot mailing list:
On Tue, 12 May 2009 14:06:00 +0200, Rudolf Marek r.ma...@assembler.cz
wrote:
Ok, but do you have vga output or just serial console.
if VGA is initialized in coreboot - use the free VGA bios as ROM for
Seabios.
oh so it just acts as a dummy rom for SeaBIOS?
--
Thanks,
Joseph Smith
Joseph Smith wrote:
On Tue, 12 May 2009 14:06:00 +0200, Rudolf Marek r.ma...@assembler.cz
wrote:
Ok, but do you have vga output or just serial console.
if VGA is initialized in coreboot - use the free VGA bios as ROM for
Seabios.
oh so it just acts as a dummy rom for SeaBIOS?
Yes its
On Mon, May 11, 2009 at 10:32 AM, ron minnich rminn...@gmail.com wrote:
attached.
This came up when cbfs (correctly) diagnosed a rom as corrupt ... it
was a bug in cbfs, but that's how it's supposed to work -- catch a bad
rom at build time, not boot time.
+ csize = headersize(name);
+
Author: myles
Date: 2009-05-12 15:43:34 +0200 (Tue, 12 May 2009)
New Revision: 4271
Modified:
trunk/coreboot-v2/src/devices/device.c
trunk/coreboot-v2/src/include/device/device.h
Log:
Use the debugging functions to print out the tree and resources.
Signed-off-by: Myles Watson
On Mon, May 11, 2009 at 4:53 PM, Carl-Daniel Hailfinger
c-d.hailfinger.devel.2...@gmx.net wrote:
On 12.05.2009 00:49, Myles Watson wrote:
This patch is how I like to use the debugging functions I just committed.
Signed-off-by: Myles Watson myle...@gmail.com
Nice. If it survives abuild, it
On Tue, May 12, 2009 at 02:01:19AM +0200, Peter Stuge wrote:
Luc Verhaegen wrote:
This patch adds support for the Epox 8k5a2 motherboard
All good with the fixes you've mentioned.
Acked-by: Peter Stuge pe...@stuge.se
An updated version of the patch was already committed in r490, see
mails
On 12.05.2009 15:46, Uwe Hermann wrote:
See patch.
We should also rename w49f002u.c in another patch to something more
generic, that code is in no way specific to the w49f002u. Maybe
even put the only function in that file (byte-wise JEDEC writes of one
page/sector) into jedec.c?
Sounds
Quick review below, I didn't yet find the time to test on hardware, will
hopefully be able to do that today.
+ val = 0;
+ val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
The 'val = 0' should no be needed if you do pci_read_config8()
right after that.
+ val |= 0x06;
+
+
Author: uwe
Date: 2009-05-12 16:01:14 +0200 (Tue, 12 May 2009)
New Revision: 4272
Modified:
trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex
Log:
Fix pdflatex build issues (trivial).
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified:
Author: myles
Date: 2009-05-12 16:03:12 +0200 (Tue, 12 May 2009)
New Revision: 4273
Added:
trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb
Log:
Trivially copy Config.lb to Config-abuild.lb to fix asus/m2v-mx_se.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Myles Watson
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer myles checked in revision 4271 to
the coreboot repository. This caused the following
changes:
Change Log:
Use the debugging functions to print out the tree and resources.
Signed-off-by: Myles Watson
+#ifdef CONFIG_VIDEO_MB
+/* check for VGA reserved memory
+* possible CONFIG_VIDEO_MB values are 512(kb) and 1(mb)
+*/
+if (CONFIG_VIDEO_MB == 512) {
+tomk -= 512;
+printk_debug(Allocating 512KB of RAM
Author: myles
Date: 2009-05-12 16:14:54 +0200 (Tue, 12 May 2009)
New Revision: 4274
Added:
trunk/coreboot-v2/targets/tyan/s2891/Config-abuild.lb
trunk/coreboot-v2/targets/tyan/s2892/Config-abuild.lb
Log:
I guess a couple of function calls pushed these boards over the 0x1700 edge on
the
On Tue, May 12, 2009 at 8:12 AM, Joseph Smith j...@settoplinux.org wrote:
+#ifdef CONFIG_VIDEO_MB
+ /* check for VGA reserved memory
+ * possible CONFIG_VIDEO_MB values are 512(kb) and 1(mb)
+ */
+ if (CONFIG_VIDEO_MB == 512) {
+
Author: uwe
Date: 2009-05-12 16:24:25 +0200 (Tue, 12 May 2009)
New Revision: 4275
Modified:
trunk/coreboot-v2/documentation/Makefile
Log:
There's no 'svg2pdf' in Debian AFAICT, probably the same problem on
other systems too.
So, check for svg2pdf, convert, and inkscape and use the first one
On Tue, May 12, 2009 at 03:55:27PM +0200, Carl-Daniel Hailfinger wrote:
We should also rename w49f002u.c in another patch to something more
generic, that code is in no way specific to the w49f002u. Maybe
even put the only function in that file (byte-wise JEDEC writes of one
page/sector)
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer uwe checked in revision 4272 to
the coreboot repository. This caused the following
changes:
Change Log:
Fix pdflatex build issues (trivial).
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe
#131: New flashrom motherboard support
-+--
Reporter: anonymous | Owner: somebody
Type: enhancement| Status: new
Priority: trivial|
This would be a great success story to have on the wiki!
Especially given that part of the result was a *more* capable machine,
with hardware working that the vendor disabled.
ron
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Dear coreboot readers!
This is the automatic build system of coreboot.
The developer myles checked in revision 4273 to
the coreboot repository. This caused the following
changes:
Change Log:
Trivially copy Config.lb to Config-abuild.lb to fix asus/m2v-mx_se.
Signed-off-by: Myles Watson
On Tue, 12 May 2009 08:18:20 -0600, Myles Watson myle...@gmail.com wrote:
On Tue, May 12, 2009 at 8:12 AM, Joseph Smith j...@settoplinux.org
wrote:
+#ifdef CONFIG_VIDEO_MB
+ /* check for VGA reserved memory
+ * possible CONFIG_VIDEO_MB values are 512(kb) and
1(mb)
Author: rminnich
Date: 2009-05-12 17:06:54 +0200 (Tue, 12 May 2009)
New Revision: 4276
Modified:
trunk/coreboot-v2/util/cbfstool/fs.c
Log:
This fixes a rather silly bug in cbfs with filenames 16 characters.
Tested to booting linux with qemu.
Signed-off-by: Ronald G. Minnich
On Mon, May 11, 2009 at 11:32:49PM +0200, Carl-Daniel Hailfinger wrote:
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Acked-by: Uwe Hermann u...@hermann-uwe.de
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org |
On Tue, May 12, 2009 at 6:05 AM, Myles Watson myle...@gmail.com wrote:
On Mon, May 11, 2009 at 10:32 AM, ron minnich rminn...@gmail.com wrote:
attached.
This came up when cbfs (correctly) diagnosed a rom as corrupt ... it
was a bug in cbfs, but that's how it's supposed to work -- catch a bad
On Mon, May 11, 2009 at 07:40:39PM +0200, Carl-Daniel Hailfinger wrote:
There are various reasons why a SPI command can fail. Among others, I
have seen the following problems:
- The SPI opcode is not supported by the controller. ICH-style
controllers exhibit this if SPI config is locked down.
Author: myles
Date: 2009-05-12 17:15:07 +0200 (Tue, 12 May 2009)
New Revision: 4277
Modified:
trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Config.lb
trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb
trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer myles checked in revision 4274 to
the coreboot repository. This caused the following
changes:
Change Log:
I guess a couple of function calls pushed these boards over the 0x1700 edge on
the build server.
Add
On Tue, May 12, 2009 at 5:44 AM, samuel samuel.verstra...@gmail.com wrote:
Dear list(s),
This is the final patch that got everything working for me with the HP
dl145g3.
I would like to remind you that this firmware enables the hardware
virtualization on the AMD cpu's on the machine. That
Author: hailfinger
Date: 2009-05-12 17:38:55 +0200 (Tue, 12 May 2009)
New Revision: 498
Modified:
trunk/jedec.c
trunk/sst_fwhub.c
trunk/w39v040c.c
trunk/w39v080fa.c
Log:
Use helper functions chip_{read,write}[bwl] to access flash chips.
The semantic patch I used in r418 to make the
On 12.05.2009 17:09, Uwe Hermann wrote:
On Mon, May 11, 2009 at 11:32:49PM +0200, Carl-Daniel Hailfinger wrote:
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Acked-by: Uwe Hermann u...@hermann-uwe.de
Thanks, committed in r498.
Regards,
Carl-Daniel
--
if failing for me with a seabios payload. Not a filo payload, mind you.
The failure is odd. It seems to be dying at first instruction with a
triple fault.
Anyway, ideas welcome :-)
Devices initialized
Copying Interrupt Routing Table to 0x000f... done.
Moving GDT to 0x500...ok
Multiboot
+ csize = headersize(name);
+
+ strcpy(c-magic, COMPONENT_MAGIC);
+
+ c-offset = htonl(csize);
I think this code would be clearer without csize.
+ c-offset = htonl(headersize(name));
csize is used one other place in that function. I did not change it as
On Tue, May 12, 2009 at 5:50 AM, Rudolf Marek r.ma...@assembler.cz wrote:
Hi,
Thats very nice! I just wanted to ask if you know in what register/MSR gets
the SVM disabled. Or maybe Marc will know?
The details are in the Fam 10 BKDG section 2.16 - BIOS support for SVM Disable
Congratulations
-Original Message-
From: coreboot-bounces+mylesgw=gmail@coreboot.org [mailto:coreboot-
bounces+mylesgw=gmail@coreboot.org] On Behalf Of ron minnich
Sent: Tuesday, May 12, 2009 9:45 AM
To: coreboot
Subject: [coreboot] qemu, v2, latest
if failing for me with a seabios
On Tue, 12 May 2009 11:05:59 -0400, Joseph Smith j...@settoplinux.org
wrote:
On Tue, 12 May 2009 08:18:20 -0600, Myles Watson myle...@gmail.com
wrote:
On Tue, May 12, 2009 at 8:12 AM, Joseph Smith j...@settoplinux.org
wrote:
+#ifdef CONFIG_VIDEO_MB
+ /* check for VGA
On Tue, May 12, 2009 at 8:56 AM, Myles Watson myle...@gmail.com wrote:
Payload is overwriting Coreboot tables.
I don't see this line in mine. Could you try HAVE_LOW_TABLES=0 and see if
that fixes it for you? If so we can try to debug why having both doesn't
work. If not we can compare
On Tue, May 12, 2009 at 7:44 AM, samuel samuel.verstra...@gmail.com wrote:
Because SeaBIOS does not support AHCI SATA it can not start the
bootable drive of the machine so i had to add filo to seabios to
manage booting:
./cbfstool coreboot.rom add-payload filo.elf img/FILO
I think you may
On 09.05.2009 04:07, Uwe Hermann wrote:
See patch.
The code may have some potential for simplification, but it basically
works. I already used the output of the new -z option in the
http://coreboot.org/Flashrom page, please check if there are errors in
the output (or code).
Add a
On Tue, May 12, 2009 at 10:20 AM, Tom Sylla tsy...@gmail.com wrote:
On Tue, May 12, 2009 at 7:44 AM, samuel samuel.verstra...@gmail.com wrote:
Because SeaBIOS does not support AHCI SATA it can not start the
bootable drive of the machine so i had to add filo to seabios to
manage booting:
Hey Carl,
On Tuesday 12 May 2009 10:59:28 Carl-Daniel Hailfinger wrote:
Hi Christian,
thanks for your patch.
A detailed review follows. Don't let the review discourage you,
Makefiles are always controversial. It is entirely possible someone will
post a different review which tells you all
On Tue, May 12, 2009 at 10:12 AM, ron minnich rminn...@gmail.com wrote:
On Tue, May 12, 2009 at 8:56 AM, Myles Watson myle...@gmail.com wrote:
Payload is overwriting Coreboot tables.
I don't see this line in mine. Could you try HAVE_LOW_TABLES=0 and see if
that fixes it for you? If so we
I'll just have coreboot dump the first 32 bytes of memory at entry
point to make sure it's what I think it is.
If you can test latest coreboot with latest qemu I'd be interested.
It triple faults for me too. I was using 0.9.1, and I downloaded 0.10.4.
Has anyone tried CONFIG_COMPRESS=0
On Tue, 12 May 2009 14:30:31 +0200, Rudolf Marek r.ma...@assembler.cz
wrote:
Joseph Smith wrote:
On Tue, 12 May 2009 14:06:00 +0200, Rudolf Marek r.ma...@assembler.cz
wrote:
Ok, but do you have vga output or just serial console.
if VGA is initialized in coreboot - use the free VGA bios
On Tue, May 12, 2009 at 06:31:15PM +0200, Carl-Daniel Hailfinger wrote:
Please make sure the ... unknown SPI chip variants are not listed.
Status: Broken ends up as ?.
True, but I'd like to fix these issues in a different patch, this one's
quite huge and invasive already.
IMHO the wiki
On Tue, May 12, 2009 at 10:03:56PM +0200, Uwe Hermann wrote:
On Tue, May 12, 2009 at 06:31:15PM +0200, Carl-Daniel Hailfinger wrote:
Please make sure the ... unknown SPI chip variants are not listed.
Status: Broken ends up as ?.
True, but I'd like to fix these issues in a different patch,
Exciting!, ron
From: Google Alerts [mailto:googlealerts-nore...@google.com]
Google News Alert for: cme group
CME Group Dives Into 'Coreboot' and Other Linux Open Source Projects
Wall Street Technology - New York,NY,USA
By Ivy Schmerken CME Group, the world's largest derivatives exchange
OK, the score at present for qemu
latest tree, filo payload, boots fine
latest tree, seabios, triple fault.
Note that seabios loads to f.
I am going to try to validate the payload after it is copied out now.
ron
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Myles Watson wrote:
The controller has normal PATA emulation mode, as well as its own
QDMA SATA mode (in lieu of AHCI).
Are you saying that FILO shouldn't be working, or that SeaBIOS
should be working?
SeaBIOS should be working, as long as the controller is in PATA mode.
The controller
SST25 chips do not support page program, only byte program.
Downgrade the chips from 256-byte writes to 1-byte writes. This fixes
writing to them on ICH/VIA SPI masters.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-sst_1byte_write/flashchips.c
On Tue, May 12, 2009 at 12:46 PM, Myles Watson myle...@gmail.com wrote:
I think you may still be able to get this part working without FILO,
but I am not sure how. The HT1000 SATA is not AHCI, so support for
AHCI won't actually help. The controller has normal PATA emulation
mode, as well as
On 07.05.2009 19:02, fengyuning1...@gmail.com wrote:
Print the value of offset in hex. Hex values are easier to debug.
Signed-off-by: FENG Yu Ning fengyuning1...@gmail.com
Index: trunk/ichspi.c
===
--- trunk/ichspi.c
On Tue, May 12, 2009 at 3:45 PM, Tom Sylla tsy...@gmail.com wrote:
On Tue, May 12, 2009 at 12:46 PM, Myles Watson myle...@gmail.com wrote:
I think you may still be able to get this part working without FILO,
but I am not sure how. The HT1000 SATA is not AHCI, so support for
AHCI won't actually
Hi Samuel,
could I interest you in writing a small success story for our wiki? It
might get used for some promotional material as well.
On 12.05.2009 16:51, ron minnich wrote:
This would be a great success story to have on the wiki!
Especially given that part of the result was a *more*
I told them about us (coreboot devs) around 5 years ago. I also told
them we could reduce their trading transaction time by about 4-5 orders
of magnitude. Maybe that will happen as well?
-Bari
ron minnich wrote:
Exciting!, ron
From: Google Alerts [mailto:googlealerts-nore...@google.com]
On 12.05.2009 22:06, Uwe Hermann wrote:
On Tue, May 12, 2009 at 10:03:56PM +0200, Uwe Hermann wrote:
On Tue, May 12, 2009 at 06:31:15PM +0200, Carl-Daniel Hailfinger wrote:
Please make sure the ... unknown SPI chip variants are not listed.
Status: Broken ends up as ?.
True,
On Thu, Apr 30, 2009 at 08:40:16PM -0600, Myles Watson wrote:
On Thu, Apr 30, 2009 at 8:26 PM, Kevin O'Connor ke...@koconnor.net wrote:
On Thu, Apr 30, 2009 at 09:18:45PM -0400, Ward Vandewege wrote:
So - here's the problem with the sgabios approach. Unless I'm
misunderstanding how this
Carl-Daniel Hailfinger wrote:
AFAIK %p already prints the 0x before the hex value, so buf=%p would be
preferable.
Yes, I made a mistake. Maybe the C library on his system is reponsible
for the no 0x output?
http://www.coreboot.org/pipermail/coreboot/2009-May/047736.html
Other than that, I
On Tue, May 12, 2009 at 06:50:26AM -0400, Joseph Smith wrote:
This may be a dumb question, but I was wondering, can I use SeaBIOS as a
payload without loading assembly blob roms?
I ask this because I am going to be running custom VGA code after VM86
excicutes the vga rom and returns back to
On Tue, May 12, 2009 at 09:21:12AM -0600, Myles Watson wrote:
On Tue, May 12, 2009 at 5:44 AM, samuel samuel.verstra...@gmail.com wrote:
Because SeaBIOS does not support AHCI SATA it can not start the
bootable drive of the machine so i had to add filo to seabios to
manage booting:
Heh.
On Tue, 12 May 2009 21:26:04 -0400, Kevin O'Connor ke...@koconnor.net
wrote:
On Tue, May 12, 2009 at 06:50:26AM -0400, Joseph Smith wrote:
This may be a dumb question, but I was wondering, can I use SeaBIOS as a
payload without loading assembly blob roms?
I ask this because I am going to be
See patch.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Add support for 3COM NICs as external programmer and Atmel AT49BV512.
This allows flashrom to identify, read, write, erase and verify flash chips
Wow, using nics as programmers, Nice work!
What is next vga cards :-)
Acked-by: Joseph Smith j...@settoplinux.org
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Author: linux_junkie
Date: 2009-05-13 04:47:14 +0200 (Wed, 13 May 2009)
New Revision: 4278
Modified:
trunk/coreboot-v2/src/southbridge/intel/i82801xx/Config.lb
Log:
Oops forgot small part. Set up PIRQs in mainboard Config.lb for IP1000 and
RM4100 instead of using the ones in i82801xx_lpc.c.
Author: myles
Date: 2009-05-13 04:48:58 +0200 (Wed, 13 May 2009)
New Revision: 4279
Modified:
trunk/coreboot-v2/util/cbfstool/fs.c
Log:
Remove a shadowed variable and an unnecessary local variable in cbfstool/fs.c.
It is nearly trivial.
Signed-off-by: Myles Watsonmyle...@gmail.com
Acked-by:
On Tue, May 12, 2009 at 08:16:47PM -0400, Ward Vandewege wrote:
I'm seeing the exact same issue on m57sli (which is also mcp55 based,
however). Has anyone else tried coreboot + SeaBIOS + grub with serial?
This looks to be an issue with SeaBIOS serial port detection. Can you
retry with the
-Original Message-
From: Kevin O'Connor [mailto:ke...@koconnor.net]
On Tue, May 12, 2009 at 09:21:12AM -0600, Myles Watson wrote:
On Tue, May 12, 2009 at 5:44 AM, samuel samuel.verstra...@gmail.com
wrote:
Because SeaBIOS does not support AHCI SATA it can not start the
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer linux_junkie checked in revision 4278 to
the coreboot repository. This caused the following
changes:
Change Log:
Oops forgot small part. Set up PIRQs in mainboard Config.lb for IP1000 and
RM4100 instead of
On Tue, May 12, 2009 at 09:58:11PM -0400, Joseph Smith wrote:
Well it would be hard to fit 2 years of research into this email but in a
nut shell I am going to be doing some direct framebuffer manipulation to
get the tv-out working. I need to do this AFTER the VGA ROM runs and sets
up the
On Tue, May 12, 2009 at 6:16 AM, Joseph Smith j...@settoplinux.org wrote:
On Mon, 11 May 2009 20:54:38 +0200, Quentin RAMEAU quinq...@gmail.com
wrote:
Hi,
I have got a Veriton FP2 (
http://www.acersupport.com/desktop/html/vfp2.html)
with a S511P motherboard, Intel 82815 northbridge
On Tue, 12 May 2009 23:16:28 -0400, Corey Osgood corey.osg...@gmail.com
wrote:
On Tue, May 12, 2009 at 6:16 AM, Joseph Smith j...@settoplinux.org
wrote:
On Mon, 11 May 2009 20:54:38 +0200, Quentin RAMEAU quinq...@gmail.com
wrote:
Hi,
I have got a Veriton FP2 (
On Tue, May 12, 2009 at 09:05:09PM -0600, Myles Watson wrote:
I actually couldn't find anything different in the file between how the
registers were programmed. I didn't look for too long. I've since been
told that the Broadcom chip we're talking about doesn't have AHCI, so I
don't know...
On Tue, 12 May 2009 23:13:54 -0400, Kevin O'Connor ke...@koconnor.net
wrote:
On Tue, May 12, 2009 at 09:58:11PM -0400, Joseph Smith wrote:
Well it would be hard to fit 2 years of research into this email but in
a
nut shell I am going to be doing some direct framebuffer manipulation to
get
On Wed, 13 May 2009 05:07:25 +0200, coreboot information
i...@coresystems.de wrote:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer linux_junkie checked in revision 4278 to
the coreboot repository. This caused the following
changes:
Change Log:
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