Hi,
I messed up and added some harmless code right before pushing this change.
Just that it wasn't harmless. I'm sorry.
Anyway, with this patch, ACPI works again for setups with both
HAVE_HIGH_TABLES and HAVE_LOW_TABLES, as the RSDP contains valid data now
(without it the RSDT is bogus: it is
It doesn't fix the HIGH_TABLES issue on dbm690t.
Zheng
-Original Message-
From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org] On Behalf Of Patrick Georgi
Sent: Wednesday, May 13, 2009 2:46 PM
To: coreboot@coreboot.org
Subject: [coreboot] [PATCH]Fix ACPI in
On 13.05.2009 04:19, Joseph Smith wrote:
Wow, using nics as programmers, Nice work!
What is next vga cards :-)
I have some code to read the flash on ATI r5xx cards. This could fit
nicely in here. I need to update that branch to current flashrom.
Regards,
Carl-Daniel
--
Author: oxygene
Date: 2009-05-13 11:49:44 +0200 (Wed, 13 May 2009)
New Revision: 95
Modified:
trunk/filo/i386/segment.c
Log:
Only use CB_MEM_RAM entries of the memory map to
determine the target of the FILO relocation routine.
Without that, FILO considers reserved areas as valid
targets, too
On 13.05.2009 04:10, Uwe Hermann wrote:
Add support for 3COM NICs as external programmer and Atmel AT49BV512.
This allows flashrom to identify, read, write, erase and verify flash chips
on (some) 3COM network cards. The patch uses the external programmer
infrastructure, the network card is
Am 13.05.2009 12:29, schrieb Patrick Georgi:
Tested on Kontron. Together with the other patch by me this morning and the
commited FILO change, ACPI and e820 tables are seen correctly by Linux.
One change:
In src/boot/selfboot.c
unsigned long required_bounce_size = 0;
should be
unsigned long
On Tue, May 12, 2009 at 4:57 PM, Uwe Hermann u...@hermann-uwe.de wrote:
Quick review below, I didn't yet find the time to test on hardware, will
hopefully be able to do that today.
+ val = 0;
+ val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
The 'val = 0' should no be needed if
Author: uwe
Date: 2009-05-13 13:36:06 +0200 (Wed, 13 May 2009)
New Revision: 499
Added:
trunk/nic3com.c
Modified:
trunk/Makefile
trunk/flash.h
trunk/flashchips.c
trunk/flashrom.8
trunk/flashrom.c
Log:
Add support for 3COM NICs as external programmer and Atmel AT49BV512.
This
On Wed, May 13, 2009 at 12:05:32PM +0200, Carl-Daniel Hailfinger wrote:
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Thanks, r499.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Author: hailfinger
Date: 2009-05-13 13:40:08 +0200 (Wed, 13 May 2009)
New Revision: 500
Modified:
trunk/flash.h
trunk/ichspi.c
trunk/spi.c
trunk/spi.h
Log:
There are various reasons why a SPI command can fail. Among others, I
have seen the following problems:
- The SPI opcode is not
Author: uwe
Date: 2009-05-13 14:01:57 +0200 (Wed, 13 May 2009)
New Revision: 501
Modified:
trunk/nic3com.c
Log:
Fix nic3com.c build issues on *BSD (trivial).
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified: trunk/nic3com.c
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org]
On Behalf Of Patrick Georgi
Sent: Wednesday, May 13, 2009 12:46 AM
To: coreboot@coreboot.org
Subject: [coreboot] [PATCH]Fix ACPI in HIGH-and-LOW tables configuration
Hi,
I messed up
Am 13.05.2009 14:20, schrieb Myles Watson:
Can you move the declaration of high_rsdp too? One less #if.
high_table_end changes in the meantime. I could store it somewhere else,
but I'm not sure if that's a cleaner solution
I don't see how this changes the functionality. Which variable are
On Wed, May 13, 2009 at 6:28 AM, Patrick Georgi patr...@georgi-clan.de wrote:
Am 13.05.2009 14:20, schrieb Myles Watson:
Can you move the declaration of high_rsdp too? One less #if.
high_table_end changes in the meantime. I could store it somewhere else, but
I'm not sure if that's a cleaner
2009/5/13 Uwe Hermann u...@hermann-uwe.de
On Wed, May 13, 2009 at 12:05:32PM +0200, Carl-Daniel Hailfinger wrote:
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Thanks, r499.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
On Wed, 13 May 2009 11:34:11 +0200, Carl-Daniel Hailfinger
c-d.hailfinger.devel.2...@gmx.net wrote:
On 13.05.2009 04:19, Joseph Smith wrote:
Wow, using nics as programmers, Nice work!
What is next vga cards :-)
I have some code to read the flash on ATI r5xx cards. This could fit
nicely
On Wed, 13 May 2009 00:01:58 -0400, Joseph Smith j...@settoplinux.org
wrote:
On Wed, 13 May 2009 05:07:25 +0200, coreboot information
i...@coresystems.de wrote:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer linux_junkie checked in revision
That is cool.
yu ning
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On Wed, 13 May 2009 15:29:44 +0200, Peter Stuge pe...@stuge.se wrote:
Joseph Smith wrote:
If you have an alternate solution I am all ears.
coreboot runs VGA BIOS in emulator
coreboot runs bayou
bayou runs your tweak payload
bayou then runs SeaBIOS
SeaBIOS runs legacy bootloader
Joseph Smith wrote:
Ah bayou, the legacy of Jordan...
It's good stuff. I bet it's just a config option to run the included
payloads in sequence instead of with a menu.
//Peter
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Ok, I get your point Myles.
I did do it a little different on the i830. I just added an extra variable
so if CONFIG_VIDEO_MB is 0 it doesn't really do anything. Then it subtracts
from tomk afterwards, like this:
int igd_memory = 0;
if (CONFIG_VIDEO_MB == 512) {
igd_memory =
On Wed, 13 May 2009 15:51:14 +0200, Peter Stuge pe...@stuge.se wrote:
Joseph Smith wrote:
Ah bayou, the legacy of Jordan...
It's good stuff. I bet it's just a config option to run the included
payloads in sequence instead of with a menu.
I agree bayou is cool:-)
I will have to take a
Hi
Tested with 3COM 3C905C: EtherLink 10/100 PCI (TX)
http://www.coreboot.org/pipermail/coreboot/2009-May/048163.html
--- flashchips.c.old2009-05-13 15:53:07.0 +0200
+++ flashchips.c2009-05-13 15:53:56.0 +0200
@@ -1375,7 +1375,7 @@
.model_id =
int igd_memory = 0;
if (CONFIG_VIDEO_MB == 512) {
igd_memory = (CONFIG_VIDEO_MB);
} else {
igd_memory = (CONFIG_VIDEO_MB * 1024);
}
If you made the 512(K) 0.5 (MB), then you wouldn't need the if.
tomk -= (CONFIG_VIDEO_MB * 1024);
I think CONFIG_VIDEO_MB=512 is misleading.
Hi
Tested with 3COM 3C905C: EtherLink 10/100 PCI (TX)
http://www.coreboot.org/pipermail/coreboot/2009-May/048163.html
Signed-off-by: Mateusz Murawski mat...@tlen.pl
--- flashchips.c.old2009-05-13 15:53:07.0 +0200
+++ flashchips.c2009-05-13 15:53:56.0 +0200
@@ -1375,7
Carl-Daniel Hailfinger wrote:
Downgrade the chips from 256-byte writes to 1-byte writes. This fixes
writing to them on ICH/VIA SPI masters.
Acked-by: FENG Yu Ning fengyuning1...@gmail.com
Some other issue. write_256 really means write_pagesize in ichspi.
Maybe comment it somewhere?
yu ning
Author: oxygene
Date: 2009-05-13 16:39:59 +0200 (Wed, 13 May 2009)
New Revision: 4280
Modified:
trunk/coreboot-v2/src/arch/i386/boot/tables.c
Log:
Make ACPI with low and high tables work again. The RSDP contained a
bogus RSDT pointer due to a wrong order of commands.
Signed-off-by: Patrick
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 4280 to
the coreboot repository. This caused the following
changes:
Change Log:
Make ACPI with low and high tables work again. The RSDP contained a
bogus RSDT pointer due to a wrong
Hello there,
let me point out that the recent code to use 3x905C
as a flashrom programmer, will almost certainly fail
for the predecessor 3c905B-TX (id 0x9055). The reason
being that there is a bug where the mii unit interferes.
Thus one needs to put the media subsystem into state 0x06,
i.e.
Author: uwe
Date: 2009-05-13 17:57:38 +0200 (Wed, 13 May 2009)
New Revision: 502
Modified:
trunk/flashchips.c
Log:
Mark SST 39VF512 as fully tested.
Tested with 3COM 3C905C: EtherLink 10/100 PCI (TX)
http://www.coreboot.org/pipermail/coreboot/2009-May/048163.html
Signed-off-by: Mateusz
Author: oxygene
Date: 2009-05-13 18:27:25 +0200 (Wed, 13 May 2009)
New Revision: 4281
Modified:
trunk/coreboot-v2/src/arch/i386/boot/boot.c
trunk/coreboot-v2/src/arch/ppc/boot/boot.c
trunk/coreboot-v2/src/boot/elfboot.c
trunk/coreboot-v2/src/boot/selfboot.c
See attached.
Thanks,
Ward.
--
Ward Vandewege w...@fsf.org
Free Software Foundation - Senior Systems Administrator
Add support for human-friendly component string types for the cbfstool add
command.
Signed-off-by: Ward Vandewege w...@gnu.org
Index: add.c
Hi
Tested on MSI MS-7191
flashrom v0.9.0-r501
No coreboot table found.
Found chipset ATI SB400, enabling flash write... OK.
Calibrating delay loop... OK.
Found chip Winbond W39V040A (512 KB) at physical address 0xfff8.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
So if it not a dummy vga bios what registers does it set to initialize
graphics?
The standard VGA one.
The lower VESA compatable mmio registers?
Not VESA compatible, because VESA does not define any std regs/
Is there a list of vga compatable
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Thanks!
Rudolf
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iEYEARECAAYFAkoLJLgACgkQ3J9wPJqZRNXh+wCg3/UiaR4RGVfdI5HSuL08YuOC
2VgAn39k2Fx7CM+ub18DrZugHAwC2bmE
=Il3M
See attached.
Thanks,
Ward.
--
Ward Vandewege w...@fsf.org
Free Software Foundation - Senior Systems Administrator
This patch fixes a segfault when a file too large to fit is added to a rom
image.
Signed-off-by: Ward Vandewege w...@gnu.org
Index: fs.c
This patch fixes a segfault when a file too large to fit is added to a rom
image.
Signed-off-by: Ward Vandewege w...@gnu.org
Index: fs.c
===
--- fs.c(revision 4281)
+++ fs.c(working copy)
@@ -99,7 +99,7 @@
{
Author: myles
Date: 2009-05-13 22:08:28 +0200 (Wed, 13 May 2009)
New Revision: 4282
Modified:
trunk/coreboot-v2/util/cbfstool/add.c
trunk/coreboot-v2/util/newconfig/config.g
Log:
Add support for human-friendly component string types for the cbfstool add
command.
Make use of it in config.g
On Wed, May 13, 2009 at 10:57 AM, Ward Vandewege w...@gnu.org wrote:
See attached.
I used it to make the magic '48' go away in config.g
Rev. 4282
Thanks,
Myles
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Author: ward
Date: 2009-05-13 22:11:04 +0200 (Wed, 13 May 2009)
New Revision: 4283
Modified:
trunk/coreboot-v2/util/cbfstool/fs.c
Log:
This patch fixes a segfault when a file too large to fit is added to a rom
image.
Signed-off-by: Ward Vandewege w...@gnu.org
Acked-by: Myles Watson
On Wed, May 13, 2009 at 02:06:30PM -0600, Myles Watson wrote:
This patch fixes a segfault when a file too large to fit is added to a rom
image.
Signed-off-by: Ward Vandewege w...@gnu.org
Index: fs.c
===
--- fs.c
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer myles checked in revision 4282 to
the coreboot repository. This caused the following
changes:
Change Log:
Add support for human-friendly component string types for the cbfstool add
command.
Make use of it in
not work. Boot log:
http://ward.vandewege.net/coreboot/seabios/20090513-seabios-no-serial-debug.cap
If CONFIG_DEBUG_SERIAL is set to 1, the bug persists, but sgabios works.
Boot log:
http://ward.vandewege.net/coreboot/seabios/20090513-seabios-serial-debug-grub-serial-slowness.cap
Thoughts
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer ward checked in revision 4283 to
the coreboot repository. This caused the following
changes:
Change Log:
This patch fixes a segfault when a file too large to fit is added to a rom
image.
Signed-off-by: Ward
On Wed, May 13, 2009 at 3:15 PM, ron minnich rminn...@gmail.com wrote:
ah, I had some changes I asked Ward to make.
Ward, if you make the changes, they are Acked-by: Ronald G. Minnich
rminn...@gmail.com
Sorry. I was a little too excited about that one.
Myles
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coreboot mailing list:
I didn't understand what was going on in tables.c, and it seemed a
little fragile.
These three patches try to help that out. I would only recommend the
first two, but all three is closer to maintaining the functionality we
had.
When you're reviewing, it will be helpful to note that rom_tables_*
Mats Erik Andersson wrote:
let me point out that the recent code to use 3x905C
as a flashrom programmer, will almost certainly fail
for the predecessor 3c905B-TX (id 0x9055).
Good info. I remember those 905B cards had all sorts of issues.
//Peter
--
coreboot mailing list:
ah, I had some changes I asked Ward to make.
Ward, if you make the changes, they are Acked-by: Ronald G. Minnich
rminn...@gmail.com
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Mateusz Murawski wrote:
Signed-off-by: Mateusz Murawski matowy at tlen.pl
r503
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On 13.05.2009 16:38, FENG Yu Ning wrote:
Carl-Daniel Hailfinger wrote:
Downgrade the chips from 256-byte writes to 1-byte writes. This fixes
writing to them on ICH/VIA SPI masters.
Acked-by: FENG Yu Ning fengyuning1...@gmail.com
Thanks, committed in r504.
Some other issue.
On 13.05.2009 16:33, Mateusz Murawski wrote:
Hi
Tested with 3COM 3C905C: EtherLink 10/100 PCI (TX)
http://www.coreboot.org/pipermail/coreboot/2009-May/048163.html
Signed-off-by: Mateusz Murawski mat...@tlen.pl
Thanks, committed by Uwe in r502.
Regards,
Carl-Daniel
--
On Wed, 2009-05-13 at 14:51 +0200, Carl-Daniel Hailfinger wrote:
Generic status register prettyprinting for SST25*. Even if we don't tell
the user about the areas the block locking bits correspond to, printing
a detailed list of which lock bits are set is a definite improvement.
Author: hailfinger
Date: 2009-05-14 00:51:27 +0200 (Thu, 14 May 2009)
New Revision: 505
Modified:
trunk/spi.c
Log:
Generic status register prettyprinting for SST25*. Even if we don't tell
the user about the areas the block locking bits correspond to, printing
a detailed list of which lock bits
On 14.05.2009 00:48, Cristi Magherusan wrote:
On Wed, 2009-05-13 at 14:51 +0200, Carl-Daniel Hailfinger wrote:
Generic status register prettyprinting for SST25*. Even if we don't tell
the user about the areas the block locking bits correspond to, printing
a detailed list of which lock bits
On Tue, May 12, 2009 at 11:09 AM, ron minnich rminn...@gmail.com wrote:
The next big step in my view is setting a flash-friendly value of zero.
Do you mean flashrom-friendly value of 0xFF?
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On 14.05.2009 03:31, Peter Stuge wrote:
Carl-Daniel Hailfinger wrote:
On some boards (with LPC flash) the SPI_BaseAddr is 0. The code did
not check for that condition and assumed the BAR was really at
address zero.
The problem is of course, still, that it's impossible to really
On 14.05.2009 04:05, Peter Stuge wrote:
Carl-Daniel Hailfinger wrote:
MMCONF_BASE_ADDRESS, EXT_CONF_BASE_ADDRESS and DEFAULT_PCIEXBAR
have the same purpose.
We need exactly one variable for the base address and another one
for the size of that area.
Yes.
Ideas
Carl-Daniel Hailfinger wrote:
The docs are not yet public, so I don't know.
The question was for someone else who knows.
I guess you're using the SPI BAR value as part of the heuristic.
Since accessing the SPI master is completely impossible if the SPI
BAR is located at 0x0
Sure, but a
Carl-Daniel Hailfinger wrote:
+ @echo -n $(SVNVERSION) flashrom-$(VERSION)/.svnversion
That's pretty ugly.
//Peter
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on Tuesday just prior to sending my email.
On Wed, May 13, 2009 at 04:29:27PM -0400, Ward Vandewege wrote:
If CONFIG_DEBUG_SERIAL is set to 1, the bug persists, but sgabios works.
Boot log:
http://ward.vandewege.net/coreboot/seabios/20090513-seabios-serial-debug-grub-serial-slowness.cap
+ show_all_devs(BIOS_DEBUG, Before Phase 3.);
Maybe go easy with phases and numbers in v2 until there's a formal
specification?
Yep. I missed that one.
yes,. We don't have numbers in v2 and we don't want to introduce them
part-way.
All or none :-)
No problem.
It's probably
Myles Watson wrote:
When you're reviewing, it will be helpful to note that rom_tables_* ==
LOW_TABLES, high_tables_* == HIGH_TABLES, and low_tables==
coreboot-specific very low tables.
Maybe they should be renamed to better show what they are.
Yes. I didn't rename them yet to make it
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org]
On Behalf Of Bao, Zheng
Sent: Wednesday, May 13, 2009 9:04 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] [v2] r4280 - trunk/coreboot-v2/src/arch/i386/boot
I have to say it still
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