Re: [coreboot] [PATCH] mkelfImage: set kernel_alignment so 2.6.31+work

Peter Stuge pe...@stuge.se writes: Eric W. Biederman wrote: At the moment I want to mandate a bzImage for x86, but I'm not certain if that is practical the way we build images for coreboot. .. I think I need to ensure that linux builds a bImage. So that you can have an uncompress

Re: [coreboot] [PATCH] mkelfImage: set kernel_alignment so 2.6.31+work

On Wed, Oct 6, 2010 at 1:43 AM, Eric W. Biederman ebied...@xmission.com wrote: Peter Stuge pe...@stuge.se writes: Eric W. Biederman wrote: At the moment I want to mandate a bzImage for x86, but I'm not certain if that is practical the way we build images for coreboot. .. I think I need to

Re: [coreboot] RE : RE : RE : [PATCH] Re: RE : RE : First coreboot build for Tyan s2895 K8WE mobo with seabios payload, computer starts, but graphical ubuntu 64bits is crashing

On Wed, Oct 6, 2010 at 10:24 AM, STEMMELIN, FREDERIC (FREDERIC)** CTR ** frederic.stemme...@alcatel-lucent.com wrote: Hello, i have just tried, and it fails. Good to know. Thanks. I created a new folder, downloaded latest coreboot and seabios version (no patching at all). Build both

[coreboot] [PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

See patch. Next steps will be: - Remove .c file includes from 440BX board's romstage.c files. - Add L2 cache support from Keith Hui, and split CPU models before that, as needed by that patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org |

Re: [coreboot] [PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

Am 06.10.2010 19:17, schrieb Uwe Hermann: Convert all Intel 440BX boards to Cache-as-RAM (CAR). - Add select CACHE_AS_RAM in src/cpu/intel/slot_1/Kconfig. - Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Remove select

[coreboot] [commit] r5917 - in trunk/src: cpu/intel/slot_1 mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/asus/p2b mainboard/asus/p2b-d mainboard/asus/p2b-d

Author: uwe Date: Wed Oct 6 21:32:39 2010 New Revision: 5917 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5917 Log: Convert all Intel 440BX boards to Cache-as-RAM (CAR). - Add select CACHE_AS_RAM in src/cpu/intel/slot_1/Kconfig. - Add the following in

Re: [coreboot] [PATCH try 2] Reduce duplicate definition in CAR code.

On 10/6/10 10:23 AM, Uwe Hermann wrote: They're only used once per cache_as_ram.inc file, but every such file has that list, so putting the list in an mtrr_defs.inc or the like and using .include mtrr_defs.inc in every cache_as_ram.inc would be nice IMHO. They're not necessarily the same on

[coreboot] [PATCH] correct setting of non-posted option in RS780 function ProgK8TempMmioBase

RS780 function ProgK8TempMmioBase is setting a reserved bit in the AMD processor 'MMIO Limit Address Register'. I suspect it is because of a typo where 0x80 was entered as 0x8. If 0x80 is used, then the strap configuration register accesses become non-posted, which is how the Shiner reference BIOS

Re: [coreboot] [PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

2010/10/6 Uwe Hermann u...@hermann-uwe.de See patch. Here is a fix for building on 32-bit platforms: Index: src/northbridge/intel/i440bx/raminit.c === --- src/northbridge/intel/i440bx/raminit.c (revision 5917) +++

Re: [coreboot] [PATCH] correct setting of non-posted option in RS780 function ProgK8TempMmioBase

Nice one! Acked-by: Rudolf Marek r.ma...@assembler.cz Thanks for working on this, Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

On 10/6/10 2:27 PM, Idwer Vollering wrote: 2010/10/6 Uwe Hermann u...@hermann-uwe.de mailto:u...@hermann-uwe.de See patch. Here is a fix for building on 32-bit platforms: Index: src/northbridge/intel/i440bx/raminit.c ===

[coreboot] [PATCH] Fix bootswitch of SATA/PATA

Hello, Following patch fixes the boot_switch_sata_ide logic. It can swap primary / secondary IDE channel with SATA (in IDE mode). The bug was that setup was done in wrong device. Signed-off-by: Rudolf Marek r.ma...@assembler.cz Thanks, Rudolf Index: sb700_ide.c

Re: [coreboot] [PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

2010/10/7 Stefan Reinauer stefan.reina...@coresystems.de On 10/6/10 2:27 PM, Idwer Vollering wrote: 2010/10/6 Uwe Hermann u...@hermann-uwe.de See patch. Here is a fix for building on 32-bit platforms: Index: src/northbridge/intel/i440bx/raminit.c

[coreboot] [PATCH] fix UDMA settings in SB700

Hello, Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install and even after hard reset in linux (DMA seems lockup). The fix should not have any influence for Linux because the IDE driver

Re: [coreboot] [PATCH] correct setting of non-posted option in RS780 function ProgK8TempMmioBase

Hi I forgot, please fix also RS690_cnm.c code please. Thanks, Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot