Hi Peter,
Thank you for your response.
Our development board is based on Intel Crown Bay evaluation board with Intel
Atom E660 processor and IO Controller Hub EG20T.
Could you recommend Intel board from list of supported ones, which is most
similar to our and could serve as starting point for
Hi Stefan,
Thank you for your response.
What is the Wiki you mentioned in your mail?
So far, I've found only three pieces of information on coreboot web site:
http://www.coreboot.org/Documentation
http://qa.coreboot.org/docs/doxygen/
http://www.coreboot.org/Developer_Manual
Did I miss
Author: svens
Date: Wed Apr 20 10:57:53 2011
New Revision: 6524
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6524
Log:
pci1x2x: use devicetree register configuration
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Added:
Author: svens
Date: Wed Apr 20 10:58:08 2011
New Revision: 6525
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6525
Log:
pci1x2x: add PCI1510 device IDs
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Modified:
Author: svens
Date: Wed Apr 20 10:58:16 2011
New Revision: 6526
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6526
Log:
pci1x2x: use pci_ops set_subsystem instead of custom code
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Author: svens
Date: Wed Apr 20 10:58:30 2011
New Revision: 6527
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6527
Log:
pci1x2x: use cardbus_read_resources()/cardbus_enable_resources()
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Stefan Reinauer
Author: svens
Date: Wed Apr 20 10:58:38 2011
New Revision: 6528
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6528
Log:
pci1x2x: remove latency/bridge control/cacheline size settings
Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.
Author: svens
Date: Wed Apr 20 11:05:37 2011
New Revision: 6529
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6529
Log:
PC87384: remove unused init function
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Sven Schnelle sv...@stackframe.org
Modified:
Author: svens
Date: Wed Apr 20 11:12:17 2011
New Revision: 6530
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6530
Log:
Add Lenovo ThinkPad T60
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Added:
Hi Stefan,
Stefan Reinauer stefan.reina...@coreboot.org writes:
* Sven Schnelle sv...@stackframe.org [110419 21:47]:
Signed-off-by: Sven Schnelle sv...@stackframe.org
Will that also need a change in the nokia IP530 board's devicetree.cb?
Of course. Added the neccessary subsystemid statement
Excerpts from Stefan Reinauer's message of Tue Apr 19 21:30:35 -0400 2011:
* Philippe LeCavalier supp...@plecavalier.com [110419 20:22]:
[..]
If your BIOS works for you, you should consider keeping it.
Porting coreboot to a new mainboard is a significant effort and you will
have to make
Am Mittwoch, den 20.04.2011, 09:07 -0400 schrieb Philippe LeCavalier:
[…]
To ensure I fully comprehend the risk here...Backing up the BIOS isn't
my insurance policy; I'd actually have to replace the chip?
Yes. When you flash coreboot to your only chip and it does not work you
have no means to
2011/4/20 David Bein d.b...@f5.com:
Hello Idwer,
Hello David,
Thank you very much for the assistance. I assume
that something like: nvramtool -c 0 will force the
newly booted bios to re-compute the checksum on the cmos?
I assume you want to save the current contents with nvramtool -b
Hi Rudolf,
Thanks for your email. I tried with your way, but the RTC0 device still
is not visible.
either from /dev/ or /sys/class/ directory.
I also extract DSDT table from Original BIOS,
Device(RTC0)
{
Name(_HID, EISAID(PNP0B00))
Name(CRS0,
repository service wrote:
+++ trunk/src/mainboard/lenovo/t60/acpi/dock.asl Wed Apr 20 11:12:17
2011(r6530)
@@ -53,15 +53,39 @@
Method(_STA, 0, NotSerialized)
{
- Return (DSTA)
+ Return (DSTA)
}
I modified the config to skip the other option roms, and it solved my
problem. Thanks
Regards,
Jiang
On Tue, Apr 19, 2011 at 9:15 PM, Stefan Reinauer
stefan.reina...@coreboot.org wrote:
* Jiang Wang jwang...@gmail.com [110419 23:56]:
Hi,
I tried to use an external PCI network card ( 8254pi)
* Philippe LeCavalier supp...@plecavalier.com [110420 15:07]:
Excerpts from Stefan Reinauer's message of Tue Apr 19 21:30:35 -0400 2011:
* Philippe LeCavalier supp...@plecavalier.com [110419 20:22]:
[..]
If your BIOS works for you, you should consider keeping it.
Porting coreboot to a
Hello,
Quoting Philippe LeCavalier supp...@plecavalier.com:
To ensure I fully comprehend the risk here...Backing up the BIOS isn't
my insurance policy; I'd actually have to replace the chip? Once I've
got a clear understanding of the worst-case scenario I'll feel stronger
about making a
Acked-by: Patrick Georgi patr...@georgi-clan.de
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Author: stepan
Date: Wed Apr 20 23:11:22 2011
New Revision: 6532
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6532
Log:
Simplify coreboot's console/console.h
- shift most (romcc) code out of console.h into arch/x86/lib/romcc_console.c
- rename arch/x86/lib/printk_init.c to
Author: stepan
Date: Wed Apr 20 23:14:05 2011
New Revision: 6533
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6533
Log:
drop excessive newline in uart8250.c
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Modified:
* Peter Stuge pe...@stuge.se [110420 18:03]:
+++ trunk/src/mainboard/lenovo/t60/cmos.layout Wed Apr 20 11:12:17
2011(r6530)
@@ -107,6 +107,7 @@
1048 4 r 0C0DRT1
1052 4 r 0C1DRT1
+1060 1 e 1
Author: stepan
Date: Thu Apr 21 00:23:56 2011
New Revision: 6534
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6534
Log:
drop dead code from sb800 bootblock
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Modified:
See patch.
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an example.
Signed-off-by: Stefan Reinauer reina...@google.com
Index: src/Kconfig
===
--- src/Kconfig (revision 6533)
+++ src/Kconfig (working copy)
On Wed, Apr 20, 2011 at 9:07 AM, Philippe LeCavalier
supp...@plecavalier.com wrote:
Excerpts from Stefan Reinauer's message of Tue Apr 19 21:30:35 -0400 2011:
* Philippe LeCavalier supp...@plecavalier.com [110419 20:22]:
[..]
If your BIOS works for you, you should consider keeping it.
On Wed, Apr 20, 2011 at 4:59 PM, David Hendricks dhend...@google.com wrote:
On Wed, Apr 20, 2011 at 3:49 PM, Stefan Reinauer reina...@google.com
wrote:
See patch.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Very cool -- Serial debug
On Wed, Apr 20, 2011 at 3:49 PM, Stefan Reinauer reina...@google.comwrote:
See patch.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Very cool -- Serial debug on laptops and other small x86 devices! :-)
For those looking to try it out,
Is anyone using gcc 4.6.0 for coreboot builds yet? New with gcc 4.6.0
is warning -Wunused-but-set-variable. Borland compilers offered this
useful warning 25 years ago, but until now others generally do not.
My interest in gcc 4.6.0 is for using the improved link time optimization
to reduce code
On Wed, Apr 20, 2011 at 7:59 PM, David Hendricks dhend...@google.com wrote:
On Wed, Apr 20, 2011 at 3:49 PM, Stefan Reinauer reina...@google.com
wrote:
See patch.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Very cool -- Serial debug
29 matches
Mail list logo
