Paul Menzel via coreboot wrote:
> find out what parts take too long to read for example?
Nothing will "take too long to read" - the emulator always replies
quickly.
> Are there tools available to help work with these traces, and for
> example map certain areas to the corresponding code?
The
Dear coreboot folks,
At work, I have access to a Dediprog EM100Pro, and I am currently to
use it to test coreboot on the Asus KGPE-D16.
The utility em100 for the emulator [1], also provides the switch `
--trace`, and the output looks like below [2].
```
Time: 00. command # 1 :
Dear Nico,
Am Sonntag, den 08.01.2017, 15:23 +0100 schrieb Nico Huber:
> On 08.01.2017 14:38, Paul Menzel via coreboot wrote:
> > looking at the coreboot CBMEM console messages board status repository,
> > you’ll find a lot of truncated preram CBMEM console messages.
> >
> > Currently the
Dear Daniel,
Thank you for keeping us in the loop.
Am Samstag, den 11.02.2017, 16:14 +0100 schrieb Daniel Kulesz:
> To answer my question myself: It works partially.
>
> > 1.) Samsung M393B1K70DH0-YK0
> >
> > Type: DDR3 DIMM 240-Pin, reg ECC • Ranks/Banks: dual rank, x4 • Modules: 1x
> >
On Fri, 10 Feb 2017 00:37:57 -0500
"taii...@gmx.com" wrote:
> On 02/09/2017 06:46 PM, Daniel Kulesz via coreboot wrote:
>
> > Hi,
> >
> > I just compiled and flashed the lastest master on my KGPE-D16 with pretty
> > much the default config. My board has only one of the CPU
To answer my question myself: It works partially.
> 1.) Samsung M393B1K70DH0-YK0
>
> Type: DDR3 DIMM 240-Pin, reg ECC • Ranks/Banks: dual rank, x4 • Modules: 1x
> 8GB • JEDEC: PC3L-12800R • Voltage: 1.35V
>
I got 8 of these working with one CPU package on the KGPE-D16 with one of the
latest
Zoran Stojsavljevic wrote:
> crucial question from me: how Coreboot will work if instead SeaBIOS
> GRUB2 is the payload chosen
Instead of SeaBIOS reading MBR, GRUB2 will read its configuration
file and operate accordingly.
//Peter
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coreboot mailing list: coreboot@coreboot.org
Hi
In patch [1] "util/nvramtool: Bail out on unaligned multi-byte entries"
was found that coreboot does not support options that span multiple
bytes and are not aligned.
I tried to fix the affected boards by this in [2].
I modes some options around in cmos.layout of some boards.This can be a
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