Re: [coreboot] [flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

Hi, On 02.09.2017 21:02, Nicola Corna wrote: > September 2, 2017 5:39 PM, "Nico Huber" <nic...@gmx.de> wrote: >> From the original op menu these are probably unneeded: byte program >> (0x02), either one of the block erasers (0x20 and 0xd8) and the fast >>

Re: [coreboot] [flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

at all. For the record, this commit enabled the SPI lockdown (e.g. locked the OPMENU). Which was previously only set after resume by accident. > > As suggested by Nico Huber, I tried with `-p > internal:ich_spi_mode=hwseq`, without success (log attached). > Ah, I see why it didn'

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?

Hi, On 23.08.2017 06:00, taii...@gmx.com wrote: > Just because a board lacks active developers doesn't mean that no one is > using it. right, and we won't stop anybody from using them in the future. Please keep in mind, when a board is removed from the tree that only means that the people

Re: [coreboot] Question about finalization of SMM

On 18.08.2017 09:20, Shawn wrote: > On Tue, Aug 15, 2017 at 1:04 PM, Persmule wrote: >> Hi all, >> >> When using chipsec ( https://github.com/chipsec/chipsec ) to analyse >> possible vulnerabilities inside coreboot systems, I noticed that on >> several intel-based systems

Re: [coreboot] x86 : Puzzles about init IDT

Hi, On 16.08.2017 05:17, 王翔 wrote: > The source code may have a problem when the IDT is initialized. > This code is located in `src/cpu/x86/16bit/entry16.inc`. > -- > movw%cs, %ax > shlw

Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

(All what I remember from an Ivy Bridge VBT.) Nico > > > Zheng > > ____ > From: Nico Huber <nic...@gmx.de> > Sent: Wednesday, August 9, 2017 6:29 PM > To: Zheng Bao; coreboot@coreboot.org > Subject: Re: [coreboot] [Broadwell-U]How th

Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

On 08.08.2017 05:39, Zheng Bao wrote: > In text mode, > only one display can be enabled. > > > Can this enabled display port be DDI1 or DDI2? > > I just extracted VBIOS from BIOS provided on board. I assume the display > ports are enabled based on the board settings. > > Can I just set

Re: [coreboot] Lenovo X220t variants with SMD-Flash-ROMs

Hi Philipp, On 05.08.2017 21:58, Philipp Stanner wrote: Do we have any idea what exactly they do to update the firmware internally? Well, I don't. Though, the flash chip is usually only partially protected (something like the upper 128KiB?). They probably only update the unprotected part or

Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

On 06.08.2017 05:18, Zheng Bao wrote: At which stage do you want to enables these ports? in the OS? or during boot? if the latter, which payload do you use? Zheng: I want to enable these display port during boot. The payload is SeaBIOS. You have to set your VGA BIOS to a VESA mode AFAIK. In

Re: [coreboot] Lenovo X1 carbon 3460 Screen stays black

On 05.08.2017 16:47, John Lewis wrote: Howdy, In your config file you have: # CONFIG_VGA_BIOS is not set in coreboot, which will mean that coreboot doesn't setup the display, but in your SeaBIOS config you have: CONFIG_SEABIOS_VGA_COREBOOT=y which will try to reuse whatever coreboot has

Re: [coreboot] Lenovo X1 carbon 3460 Screen stays black

On 05.08.2017 15:40, Jo wrote: Hello Guys, I wanted to get coreboot on my Lenovo X1 Carbon 1gen (3460) , so i followed the tutorial, however after flashing it, the screen stayed black.So i flashed the Vendorbios back and im kinda stuck now, help would be really appreciated. This is my*config

Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

Hi Zheng, On 04.08.2017 04:35, Zheng Bao wrote: I need to clarify my question. For Broadwell-U, are there internal 3 display ports? Is the first one set statically as eDP? the first (DDI0 or DDI-A) is eDP only. The other two can be used for DP, HDMI/DVI or both (aka DP++ or dual-mode DP).

Re: [coreboot] Broadwell-U hangs at VGA init (update)

of issue do you mean? Um, to quote yourself: >> It seems that the ME is not 100% right. and your log had this somewhere in romstage: >> ERROR: ME failed to respond Nico > > 2017年8月2日 18:58于 Nico Huber <nico.hu...@secunet.com>写道： > On 02.08.2017 04:23, Zheng Bao wro

Re: [coreboot] Broadwell-U hangs at VGA init (update)

> <fishb...@hotmail.com> > Sent: Tuesday, August 1, 2017 1:51 PM > To: Matt DeVillier > Cc: Nico Huber; stefan.reina...@coreboot.org; coreboot@coreboot.org > Subject: Re: [coreboot] Broadwell-U hangs at VGA init (update) > > > Refcode is added and VGA BIOS

Re: [coreboot] Anybody going to SHA hacker camp?

On 01.08.2017 12:13, Nico Rikken wrote: > Is anybody of the Coreboot community going to the SHA hacker camp the > coming weekend? Perhaps we can meet up. I'll also bring some Coreboot- > flashed T400's and X200 for sale. > https://wiki.sha2017.org/w/User:Nico I'll be there. Though, haven't

Re: [coreboot] About Paging, Realmode and what is going on

On 31.07.2017 13:48, Philipp Stanner wrote: > Well, many thanks. > > I didn't expect it to work that way. Would be interesting to know what > Windows 7 needs BIOS calls for. It seems to be their policy to have a boot loader (and probably kernel) that can't work on its own. So Windows (including

Re: [coreboot] Broadwell-U hangs at VGA init

Hi Zheng, On 30.07.2017 16:13, Zheng Bao wrote: > I have got the mrc.bin and mem init has got passed. > Now the new problem is that it hangs at VGA init. > > static void igd_setup_panel(struct device *dev) > { > config_t *conf = dev->chip_info; > u32 reg32; > > /* Setup Digital Port Hotplug */

Re: [coreboot] Haswell port

Hi Konstantin, On 29.07.2017 06:57, Konstantin Novikov wrote: > Hello again, coreboot community! > > Thanks a lot Zoran Stojsavljevic and Nico Huber for their help and answers. > You're lead us in "GFX-way", so it was a right direction. > At first, we're added our

Re: [coreboot] Haswell port

Hello Konstantin, On 26.07.2017 13:40, Konstantin Novikov wrote: > Hello, Zoran. > > So, we closed that issue. Function northbridge_init() didn't executed, > because we didn't had structure with desktop pci_driver. Memory map was > builded, SeaBIOS now works correctly (boot from DVD and HDD).

Re: [coreboot] REcon MTL 2017 talk on coreboot

Hi Trammell, On 26.07.2017 12:01, Trammell Hudson wrote: > Yuriy Bulygin and Oleksandr Bazhaniuk's coreboot presentation at REcon > Montreal 2017: > > https://recon.cx/2017/montreal/resources/slides/RECON-MTL-2017-DiggingIntoTheCoreOfBoot.pdf > > They recap the MMIO BAR issue (previously

Re: [coreboot] T530: Cleaning Intel ME currently does not work <--> CPU fan won't start

On 24.07.2017 22:33, David Hobach wrote: >> P.S.: Just tested the current ME-cleaner version with the OEM BIOS >> version: The CPU fan did spin - even after hard resets. >> >> So >> a) The issue is only related to coreboot. >> b) It is possible to do better here. > > I gave it one last shot and

Re: [coreboot] T530: Cleaning Intel ME currently does not work <--> CPU fan won't start

sets in GPIO mode. David, can you > dump gpios from system with running ME (can be done by 'inteltool -g'). GPIO62 is set to native mode. Nico > > > 20.07.2017 20:58, Nico Huber пишет: >> Hi David, >> >> On 20.07.2017 18:44, David Hobach wrote: >>> Dear all, &g

Re: [coreboot] T530: Cleaning Intel ME currently does not work <--> CPU fan won't start

Hi David, On 20.07.2017 18:44, David Hobach wrote: > Dear all, > > just tested two coreboot + SeaBios images on a T530 that were identical > except one time with ME and one time without (using the compile option, > rev 54db255529ce8afc689ae425c24b7fb1d45654e8). > > Unfortunately it seems that

Re: [coreboot] Cherry Trail Support

Hi Arne, On 16.07.2017 11:48, Arne Zachlod wrote: > Hi all, > > I got a GPD Pocket with an Atom X7-Z8750 (Cherry Trail). currently unsupported, AFAIK. > > I would like to use coreboot with it, but there seems to be no support > for Cherry Trail, is support for this platform planned/worked on

Re: [coreboot] question on libgfxinit DP port number

On 18.07.2017 11:05, Iru Cai wrote: > Thanks, Nico > > > On 2017年07月18日 16:20, Nico Huber wrote: >> Hi Iru, >> >> On 18.07.2017 09:28, Iru Cai wrote: >>> Hi, >>> >>> I found the mainboard DP port doesn't have output before kernel st

Re: [coreboot] question on libgfxinit DP port number

Hi Iru, On 18.07.2017 09:28, Iru Cai wrote: > Hi, > > I found the mainboard DP port doesn't have output before kernel starts in > hp/2570p (https://review.coreboot.org/c/20489/). After I added DP3 and > HDMI3 in port list, the DP port had output, and cbmem log said it's DP3. > However, xrandr

Re: [coreboot] "Qemu_coreboot_coreinfo.zip" is corrupted

Hi, On 17.07.2017 14:23, Utku Gültopu wrote: > Hello, > > I am trying to run the "coreinfo" payload on Qemu using the prebuilt > image from the link: > > http://www.coreboot.org/images/0/06/Qemu_coreboot_coreinfo.zip > > However, the ZIP file seems to be corrupted, I cannot extract the >

Re: [coreboot] Using Intel e3800 pcu spi to program flash

Hello Graham, the SPI controller for the boot firmware is usually treated as sepa- rated from the OS and therefore not advertised in ACPI. AFAIK, Linux also doesn't have a driver for it. We usually use flashrom [1] to access the firmware flash. It has a special programmer target called

Re: [coreboot] USB, IDE and SATA inizialitation

Hi Vincenzo, On 11.07.2017 18:13, ingegneriafore...@alice.it wrote: > Hello everybody, i'm new of this mailing list and is the first time i > see the coreboot code (however I know the processors based on Intel > Architecture and its language). However I apologize in advance with you > if i

Re: [coreboot] ultimate VGABIOS extraction! +NEW working way for AMD laptop's discrete GPU

Hi, On 07.07.2017 20:03, Mike Banon wrote: > === ROM locations examples for 0x0 - 0x42F00 dump made while 16GB RAM: > > 0x000512000 - broken integrated graphics ROM, first "ghost" > 0x3250D9020 - broken integrated graphics ROM, second "ghost" > 0x3578FB000 - broken integrated graphics ROM,

Re: [coreboot] x86: best approach to debug consumer hardware?

On 08.07.2017 15:43, Andrey Korolyov wrote: >> From git logs it looks like configuring the clockgen was needed for the >> x60/t60 port for deeper c-states to work. I'd try to dump the clockgen >> configuration on smbus with block operations ('i2cdump #smbus 0x69 s') >> and configure it using block

Re: [coreboot] Discussion about fixing dead code / ACPI TRAP

On 01.07.2017 15:20, Patrick Rudolph wrote: > Hello community, > I'll want to start a discussion about fixing dead code. > > How it all started: > I tried to run docking code on Lenovo T400 and found it's not working. > While investigation it turns out that the ACPI TRAP mechanism is being >

Re: [coreboot] Discussion about fixing dead code / ACPI TRAP

On 06.07.2017 17:37, Peter Stuge wrote: > Stefan Reinauer wrote: >> (it was just copy-catted around from my original i945 implementation) >> But I don't think that we should remove the knowledge from the code base. > > So it is a technology showcase and not required code. It might have started

Re: [coreboot] GRUB2 is not displaying Hard disk (hd0) partition

On 06.07.2017 16:53, Dhanasekar Jaganathan wrote: > Hi Nico, > >> You can get used to the (ahci*) numbering, or in case you need to sup- >> port both schemes with the same config file: My default `grub.cfg` >> generated by grub-mkconfig works around these differences with the >> `search` command

Re: [coreboot] x86: best approach to debug consumer hardware?

On 06.07.2017 07:20, Zoran Stojsavljevic wrote: > Top of Low Usable RAM 00d0h??? Any explanation for that? The simplest and most obvious explanation turned out to be true, the register is encoded as multiples of 16MiB. Nico -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] x86: best approach to debug consumer hardware?

I'd start with examining the coreboot console log. Are there resource conflicts? Are all APs initialized? Was the microcode updated for all of them? etc... If you don't have it already, you can grab the log from your running non-smp OS with `cbmem -c` (see util/cbmem/ in the coreboot tree). Feel

Re: [coreboot] GRUB2 is not displaying Hard disk (hd0) partition

Hi Dhanasekar, On 05.07.2017 16:23, Dhanasekar Jaganathan wrote: > Hi All, > > In GRUB2 command prompt, I am not seeing hard disk partitions like *(hd0), > (hd0,msdos1),* Instead I am seeing* (ahci4), (ahci4,msdos1).* the (hd*) numbering refers to those disks the BIOS has enumerated and

Re: [coreboot] Ethernet/Wifi not working with coreboot/seabios/me_cleaner on a Thinkpad x230

Hi, On 03.07.2017 17:23, Marcel Maci wrote: > > Hi, I've flashed coreboot with seaBIOS and me_cleaner to my Thinkpad > x230 and everything works fine except the network. Neither wifi nor > ethernet works. Could this be a problem with the gbe.bin I've used > (I extracted it with ifdtool -x from

Re: [coreboot] Ethernet/Wifi not working with coreboot/seabios/me_cleaner on a Thinkpad x230

On 04.07.2017 14:05, Martin Kepplinger wrote: > So you are talking about external SPI flashing. There are 2 flash chips and > the gbe part is in the "second", 8MB one, > > For the bios (coreboot with payload), you only need to access the "first", 4MB > chip, Please don't name the chips in that

Re: [coreboot] question on SMM

On 01.07.2017 02:08, ron minnich wrote: > On Fri, Jun 30, 2017 at 4:28 PM Nico Huber <nic...@gmx.de> wrote: > >> >> >> Sounds really doable, but I'm a bit confused here, maybe because I >> didn't look at SMM handlers for some time. Did you evaluate if you >&

Re: [coreboot] question on SMM

On 30.06.2017 19:46, ron minnich wrote: > Thanks for the good explanations. > > So I have a question for you all. We've been doing some testing of > linux-as-ramstage. We've done a proof of concept that linux can set up the > SMM handler at 0xa, the relocate stub at 0x38000, run the relocate

Re: [coreboot] question on SMM

Hi Ron, On 30.06.2017 06:25, ron minnich wrote: > there's something I am certain I don't understand about SMM on intel > chipsets. > > The question is pretty simple. Consider a system with a recent intel > chipset and flash. Is there some special secret sauce that disables writing > to flash

Re: [coreboot] How to give control to bootable USB

lowing files, > > */initrd.xz* > > */vmlinuz* > > */boot/boot.cat <http://boot.cat>* > > */boot/eltorito.img* > > */boot/grub/gurb.cfg* > > */boot/i386-PC/ *.mod (Lot of .mod files)* > > > Thanks, > Dhanasekar > > > >

Re: [coreboot] How to give control to bootable USB

Hi Dhanasekar, On 14.06.2017 11:21, Dhanasekar Jaganathan wrote: > Hi Taiidan, > > My USB ONIE installers don't have "isolinux/syslinux.cfg". It has > "boot/grub/grub.cfg". > > When I try to run "syslinux_configfile (usb0)/boot/grub/grub.cfg" in GRUB > command line, I am getting "*kernel

Re: [coreboot] CBFS mounting failure

Hi, On 14.06.2017 23:23, Gailu Singh wrote: > Hi Experts, > > We are using grub2 payload. > > When we configure coreboot with CONFIG_CBFS_SIZE and CONFIG_ROM_SIZE to be > same, grub fails to mount cbfsdisk. if you work with a modern x86 system that is expected. The flash chip isn't dedicated

Re: [coreboot] t420 MCE and crashing with ivy bridge cpu

Hello Marcus, I guess you are not alone: https://ticket.coreboot.org/issues/121 Looks like the same issue, on a T520 with Ivy Bridge CPU. According to some reports, the combination was working before. Maybe it's a regression. The combination is probably not often tested. Also, as you speak of

Re: [coreboot] FILO 0.6.0 payload bootloader - Bug Reports!

Hello Ivan, On 13.06.2017 23:51, Ivan Ivanov wrote: > Sadly "filo> kernel hda1:/vmlinuz" doesnt work as well: gives > Disk read error dev=1 drive=0 sector=0 this sounds much like the drive wasn't detected at all, not 100% sure though. If you enabled the libpayload AHCI driver, it should show

Re: [coreboot] ASUS KFSN4-DRE Automated Test Failure [master]

On 09.06.2017 17:27, Raptor Engineering Automated Coreboot Test Stand wrote: > The ASUS KFSN4-DRE fails verification for branch master as of commit > 43dcbfd85581de4f173953282a4917c1ee9a5922 > > The following tests failed: > VIDEO_FAILURE May be fixed with

Re: [coreboot] AMD EPYC and PSP

On 08.06.2017 16:48, Johnysecured88 via coreboot wrote: > Does anyone anticipate the new EPYC cpus not having PSP? Well, I don't. The answer is quite simple if you ask the question differently: Do you expect AMD to drop Netflix support? Nico -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] GRUB boot menu is not showing GRUB2

sive, so it's exactly 6MiB. Nico > > Please correct me, if I am wrong. > > Thanks, > Dhanasekar > > > On Wed, Jun 7, 2017 at 8:26 PM, Nico Huber <nico.hu...@secunet.com> wrote: > >> On 07.06.2017 16:49, Dhanasekar Jaganathan wrote: >>>

Re: [coreboot] GRUB boot menu is not showing GRUB2

run *make crossgcc-i386 CPUS=$(nproc)* and *make* crossgcc is only needed once. Nico > > Thanks, > Dhanaeskar > > On Wed, Jun 7, 2017 at 7:17 PM, Nico Huber <nico.hu...@secunet.com> wrote: > >> On 07.06.2017 15:38, Dhanasekar Jaganathan wrote: >>> Hi Nic

Re: [coreboot] GRUB boot menu is not showing GRUB2

On 07.06.2017 15:38, Dhanasekar Jaganathan wrote: > Hi Nico, > > Following is my complete Payload setting, > > 1.Add a payload -> (GRUB2) > 2.GRUB2 version -> (HEAD) > 3.Include GRUB2 runtime config file into ROM image = Y > 4.Gave the path of grub.cfg (which I copied from Fedora OS when booted

Re: [coreboot] GRUB boot menu is not showing GRUB2

On 07.06.2017 14:52, Dhanasekar Jaganathan wrote: > Hi Nico, > >> where do you expect to see the menu? a display? a serial console? In the >> former case, I expect you have to add a Video BIOS to your coreboot.rom >> (CONFIG_VGA_BIOS) and configure coreboot to run it (CONFIG_VGA_ROM_RUN). >> If

Re: [coreboot] GRUB boot menu is not showing GRUB2

Hi Dhanasekar, On 06.06.2017 16:53, Dhanasekar Jaganathan wrote: > Hi All, > > I am trying to boot *Intel Rangeley CPU/ Mohon Peak *board by Coreboot. I > am using *GRUB2 *as a Payload. > > In menuconfig, I have selected, > > Add a payload - *GRUB2* > GRUB2 Version - *HEAD*. > > My mSata has

Re: [coreboot] ASUS KFSN4-DRE Automated Test Failure [master]

On 06.06.2017 19:28, Raptor Engineering Automated Coreboot Test Stand wrote: > The ASUS KFSN4-DRE fails verification for branch master as of commit > 00b9f4c4b1cd95a6cafe2b1e66641ff0f113082e > > The following tests failed: > BOOT_FAILURE > > Commits since last successful test: > 00b9f4c

Re: [coreboot] VT-d support

On 05.06.2017 19:47, Zoran Stojsavljevic wrote: >> If you are lucky, you only need to add 20~30 lines to your chipset's code. > > Could you, please, show us an explicit example (of these 20 to 30 lines of > code)?! `src/northbridge/intel/sandybridge/iommu.c` and acpi_fill_dmar() in

Re: [coreboot] VT-d support

Hi, On 05.06.2017 18:58, Himanshu Chauhan wrote: > >> On 05-Jun-2017, at 10:19 PM, ron minnich wrote: >> >> The reason I ask about what you need is that on chromebooks the main >> coreboot support came down to 'don't disable anything’. > > I think its can’t just be

Re: [coreboot] Lenovo G505S blob status?

On 27.05.2017 03:29, taii...@gmx.com wrote: > Is it possible to init the graphics device without the radeon bios blob? > such as with openradeonbios or with linux (you could do a petietboot > solution to get graphics pre-OS) Yes, it's possible and has been done before (e.g. radeonhd and IIRC some

Re: [coreboot] Blobless coreboot on Sandy Bridge and Ivy Bridge?

On 26.05.2017 22:34, Thomasheidler wrote: > Is it possible to find out which Sandy/Ivy board supports native > ram/graphics init before buying one of them? For example, is there some > list that shows compatibility? No list that I know about. But it can be seen from the source (e.g. to support

Re: [coreboot] Blobless coreboot on Sandy Bridge and Ivy Bridge?

Hi, On 26.05.2017 21:35, Thomasheidler via coreboot wrote: > If one excludes any microcode and the VGA BIOS, is it possible to build if you use the integrated graphics, you don't need a VGA BIOS, there are replacement options. > a functioning, blobless coreboot for any Sandy Bridge or Ivy

[coreboot] Request to test graphics related Kconfig changes

Hi all, I've done a major rewrite of graphics related Kconfig settings and would like to see it more tested. The goals of the changes are roughly: * Provide choices for settings that were loose booleans before (e.g. the method to initialize gfx, the final framebuffer setting). * Avoid

Re: [coreboot] CONFIG_CBFS_SIZE vs CONFIG_ROM_SIZE

On 23.05.2017 18:49, Gailu Singh wrote: > Hi Experts, > > If we use CBFS_SIZE to be same as ROM_SIZE on our apollolake board grub > fails to load grub.cfg located in CBFS. Based on experiments we found that > grub.cfg is loaded correctly if we keep minimum difference of 64KB between > CBFS_SIZE

Re: [coreboot] Intel me problems

On 23.05.2017 00:58, Alejandro Flores wrote: > Ok, so the image John uploaded of a known good me is exactly the same as > the one I have been using that fails. The shasums match exactly. So I > thought maybe somehow it is getting corrupted when coreboot creates the > rom. I used the unhuffme

Re: [coreboot] Intel me problems

On 16.05.2017 16:22, Alejandro Flores wrote: > I have a new acer chromebook I have flashed with coreboot + seabios > payload. It boots to linux ok, but then powers off suddenly after 30 min > regardless of whether I am using it. > > I disabled hibernation and have been leaving it plugged in, but

Re: [coreboot] [RFC] Removing RTC configurable baud rate

On 12.05.2017 21:59, Arthur Heymans wrote: > Hi > > In the latest CCM[1] the question was raised whether someone still uses > the configuration option baud_rate from RTC nvram (CMOS) and if not > maybe think about removing this. > > The issues raised with this code were: > * they are an extra

Re: [coreboot] Help with i915

On 12.05.2017 14:26, Joshua Pincus wrote: > Hi Zoran, > > Please see my inline response below. > > On May 12, 2017 8:13 AM, "Zoran Stojsavljevic" < > zoran.stojsavlje...@gmail.com> wrote: >> >> Hello Joshua, >> >> You managed to confuse me, on the very high level.Why, you'll ask? >> >> [1] I

Re: [coreboot] Help with i915

On 11.05.2017 22:43, Joshua Pincus wrote: > Hey Folks, > > > I've been smacking my head against the wall for 2 weeks. I can't smack it > anymore. There's not much brain left at this point. Here's my issue: > > > I have a Broadwell system with HD Video/Audio support. When Windows 10 > runs

Re: [coreboot] Request for reviewing Coreboot/VBT

On 11.05.2017 11:29, Zoran Stojsavljevic wrote: > Hello Community, > > Here is the request for reviewing the latest and greatest WIKI Coreboot/VBT: > https://en.wikipedia.org/wiki/Coreboot/VBT Sigh, as you describe ongoing development details, some place like the coreboot wiki [1] might be a

Re: [coreboot] AMT bug

On 10.05.2017 00:25, taii...@gmx.com wrote: > On 05/09/2017 05:26 PM, taii...@gmx.com wrote: > >> On 05/08/2017 12:40 AM, ron minnich wrote: >> >>> >>> I am long past believing one can build secure platforms on any x86 >>> chipset. >>> This mess only strengthens that conviction. But there are

Re: [coreboot] Will we maintain Skylake/FSP1.1?

gt; > Thanks, > Youness. > > On Tue, May 9, 2017 at 11:19 AM, Aaron Durbin <adur...@google.com> wrote: > >> On Tue, May 9, 2017 at 10:14 AM, Nico Huber <nico.hu...@secunet.com> >> wrote: >>> Hi, >>> >>> I was walking through

Re: [coreboot] Will we maintain Skylake/FSP1.1?

On 09.05.2017 17:19, Aaron Durbin via coreboot wrote: > On Tue, May 9, 2017 at 10:14 AM, Nico Huber <nico.hu...@secunet.com> wrote: >> Hi, >> >> I was walking through the Skylake FSP1.1 support in coreboot and asked >> myself if it is worth to clean i

[coreboot] Will we maintain Skylake/FSP1.1?

Hi, I was walking through the Skylake FSP1.1 support in coreboot and asked myself if it is worth to clean it up and maintain the code? given that the upcoming release of Kabylake FSP should be able to supersede it (I presume it is?). Are there any plans yet to drop it once the next FSP is

Re: [coreboot] Remote security exploit in all 2008+ Intel platforms

On 03.05.2017 09:28, Zoran Stojsavljevic wrote: >> The reason we want to prioritize the ME vs. the FSP, is because a lot > more people were interested in getting rid of the ME, >> so it is a higher priority, *but the FSP is also going to be reversed > eventually and coreboot deblobbed entirely*. >

Re: [coreboot] Remote security exploit in all 2008+ Intel platforms

On 03.05.2017 01:39, Youness Alaoui wrote: > to answer Nico's other post: > I'm quite surprised and disappointed by your answer. You have every right > to say that you are disappointed or distrusting Purism due to past actions, > but I find it harsh for you to be repeatedly saying "fraud" and

Re: [coreboot] Anyone got an opinion, technical or otherwise, on this?

On 03.05.2017 16:31, Matt DeVillier wrote: > On Wed, May 3, 2017 at 4:17 AM, John Lewis wrote: > >> I think I've answered my own questions by checking out the menuconfig >> options, it looks to me as though up to and including Skylake is possible, >> and flashing internally

Re: [coreboot] BIOSBits ...

Hi Kashif, On 02.05.2017 23:04, Kashif Ali wrote: > Hi all, > > We modified coreboot for the OpenCellular project and looking to have test > suite for BIOS, specially during manufacturing. The OpenCellular is based > on Intel Atom E3845, similar to minnowboard. I came across biosbits.org, > have

Re: [coreboot] Remote security exploit in all 2008+ Intel platforms

On 02.05.2017 16:20, ron minnich wrote: > On Tue, May 2, 2017 at 3:54 AM Nico Huber <nico.hu...@secunet.com> wrote: > >> >> >> You sound much like their advertisement. >> >> > > OK, I'm done here. Have a nice project everyone. When people

Re: [coreboot] Remote security exploit in all 2008+ Intel platforms

On 02.05.2017 04:52, Youness Alaoui wrote: > Ron couldn't be more right when he says that you can't appreciate how much > work it is to go from a "it works" to a "it's tested/verified and made into > a *product* for actual users". It took me 6 months of work to finish the 4 > days of work that

Re: [coreboot] Remote security exploit in all 2008+ Intel platforms

On 02.05.2017 00:44, ron minnich wrote: > On Mon, May 1, 2017 at 1:17 PM Rene Shuster > wrote: > >> Yes Puri.sm has been debunked. >> > > I disagree. I've seen the systems. From what I can see, Puri.sm has made a > good faith effort to go as far possible *with modern

Re: [coreboot] ThinkPad X230 with working truncated ME and 11 MB space for payload

Hi Marek, On 17.04.2017 02:28, Marek Behun wrote: > So apparently disabling building relocatable kernel fixed the issue > with kvm. that seems pretty random. > > But I have now a different issue which renders my X230 useless with > completely stripped ME. It seems that native ram init does not

Re: [coreboot] Trouble initializing gfx on X200(s)

Hi Daniel, On 17.04.2017 02:11, Daniel Kulesz via coreboot wrote: > Hi folks, > > using the latest coreboot master, I tried several combinations and > various config options but I did not succeed to initialize gfx on a > X200s so that typical graphical boots work such as: > > - Ubuntu CD

Re: [coreboot] do i have to install gcc-multilib, in order to build coreboot 4.5?

Hi Zoran, On 07.04.2017 21:42, Zoran Stojsavljevic wrote: > You see, Nico... Here! > >> VBT is documented by intel-gpu-tools. There's intel_vbt_decode (former > intel_bios_decode) available >> https://cgit.freedesktop.org/xorg/app/intel-gpu-tools/tree/ > tools/intel_vbt_decode.c that will print

Re: [coreboot] VGA and Graphics

On 05.04.2017 17:16, ron minnich wrote: > Zoran, given that we still see _MP_ and even $PIR tables in BIOS, is it These are obsoleted standards. > possible that VBT might always be there even if it's not strictly needed? This is a table used by only one vendor and nobody intended to replace it

Re: [coreboot] VGA and Graphics

On 05.04.2017 17:03, Zoran Stojsavljevic wrote: > To Coreboot, > > http://www.uefi.org/sites/default/files/resources/UPFS11_P4_UEFI_GOP_AMD.pdf > > Please, read about GOP, and what GOP suppose to be. > > So, GOP actually need to replace vBIOS, VBT, legacy INT 10H, and complete > VBE 3.0

Re: [coreboot] VGA and Graphics

Hi Ron, On 04.04.2017 19:46, ron minnich wrote: > Igor, if you are going to say things like "AFAIK there is no public > description of these tables' layout and contents, only Intel knows how to > build and parse them.", it's really a good idea to back it up with a > primary source, especially

Re: [coreboot] Coreboot wiki: what license is the content under?

Hi Sam, On 02.04.2017 20:05, Sam Kuper wrote: > So, Creative Commons explicitly acknowledges that an adaptation of a > CC BY-licensed work can indeed be licensed under CC0 (or, at least, > that the adapter's contribution to the adaptation can be; which I note > would be the entire adaptation, in

Re: [coreboot] Coreboot wiki: what license is the content under?

On 01.04.2017 17:19, Sam Kuper wrote: > In the case of both CC BY and CC BY-SA, the rights granted to the > *recipient of the licensed work* include the freedom to create > adaptations and to distribute or publicly perform them, subject *only* > to a small list of restrictions. CC BY has a shorter

Re: [coreboot] Coreboot wiki: what license is the content under?

On 01.04.2017 01:39, Sam Kuper wrote: > On 31/03/2017, Nico Huber <nic...@gmx.de> wrote: >> On 31.03.2017 23:38, Sam Kuper wrote: >>> On 31/03/2017, David Hendricks <david.hendri...@gmail.com> wrote: >>>> On Fri, Mar 31, 2017 at 10:20 AM, Sam Kuper <

Re: [coreboot] Coreboot wiki: what license is the content under?

On 31.03.2017 23:38, Sam Kuper wrote: > On 31/03/2017, David Hendricks wrote: >> On Fri, Mar 31, 2017 at 10:20 AM, Sam Kuper wrote: >>> Also, to further address Patrick's point above about marketing >>> material: it is important that the

Re: [coreboot] Question about Intel HD graphics and FLR

Hi JP, On 30.03.2017 17:48, Joshua Pincus wrote: > Hi Zoran, > > Thanks for your reply. > > My situation is this: When the VM guest comes up the first time from a > system-level reset (aka power on), the Broadwell HD graphics device runs > fine. I see basic VGA both before and during the boot

Re: [coreboot] References to ich9gen in the wiki (was: Re: Fwd: Ethernet problem in x200)

On 29.03.2017 22:37, Denis 'GNUtoo' Carikli wrote: > Nico Huber <nico.hu...@secunet.com> wrote: >> I had this on my TODO list for some time. I think we should (if not >> already done) extend ifdtool to toggle whatever bit is needed to run >> without ME firmware. And

Re: [coreboot] [flashrom] flashrom and MacMini 2009

Hello Micha, On 27.03.2017 13:58, Michael Schröder wrote: > Dear folks, > > i am interested in using coreboot with a MacMini 2007 (core2duo). It > uses the same chipset (GM945) as the macbook2.1 which supported yet. > > I managed to read infos about the BIOS with flashrom. > The verbose output

[coreboot] References to ich9gen in the wiki (was: Re: Fwd: Ethernet problem in x200)

On 29.03.2017 10:52, Denis 'GNUtoo' Carikli wrote: >>> To get a working Ethernet with (3) you need to set a >>> valid mac address: >>> In the installation documentation, you are expected to use ich9gen, >>> however if you use it this way: $ ./ich9gen >>> It will not produce a valid MAC

Re: [coreboot] Fwd: Ethernet problem in x200

On 28.03.2017 01:39, Denis 'GNUtoo' Carikli wrote: > On Mon, 27 Mar 2017 16:14:53 +0200 > Zoran Stojsavljevic wrote: > >> [user@localhost projects]$ cat dmesg.txt | grep 00:19.0 >> [0.151652] pci :00:19.0: *[8086:294c*] type 00 class 0x02 >> [

Re: [coreboot] Fwd: Ethernet problem in x200

ico > > > 27 Mar 2017 17:33 tarihinde "Nico Huber" <nico.hu...@secunet.com> yazdı: > >> Hello Serdar, Zoran, >> >> On 27.03.2017 16:14, Zoran Stojsavljevic wrote: >>> [user@localhost projects]$ cat dmesg.txt | grep 00:19.0 >>> [

Re: [coreboot] Fwd: Ethernet problem in x200

Hello Serdar, Zoran, On 27.03.2017 16:14, Zoran Stojsavljevic wrote: > [user@localhost projects]$ cat dmesg.txt | grep 00:19.0 > [0.151652] pci :00:19.0: *[8086:294c*] type 00 class 0x02 > [0.151694] pci :00:19.0: reg 0x10: [mem 0xe160-0xe161] > [0.151707] pci

Re: [coreboot] Lenovo Thinkpad X201: cannot boot encrypted Debian w/Coreboot & GRUB2

On 24.03.2017 04:16, Sam Kuper wrote: > On 23/03/2017, Arthur Heymans wrote: >> Last option is hook up libgfxinit, an alternative Intel display init >> code written in ada/spark, which might set up display correctly... > > Nice. I will look into that when I get a chance. It

[coreboot] Can we please stop hiding semantic changes behind "found by checkpatch" (Re: New Defects reported by Coverity Scan for coreboot)

Hi all, don't get me wrong, I think style fixes are a good thing and appreciate that people take the time for it. However, if we do massive changes to comply with a tool like checkpatch.pl, we should make sure that single commits either change style only, or really fix something which should then

Re: [coreboot] Lenovo Thinkpad X201: cannot boot encrypted Debian w/Coreboot & GRUB2

Hi Sam, On 22.03.2017 17:03, Sam Kuper wrote: > Steps followed: > > ... > > - On spare PC, in Coreboot directory: > > -- make distclean && make nconfig > > -- Choose "Lenovo" as mainboard vendor. > > -- Choose "ThinkPad X201 / X201s / X201t" as mainboard. > > -- Choose "Add Intel

Re: [coreboot] Maintain boot order for multiple EFI based OS

Hi Zoran, On 22.03.2017 14:51, Zoran Stojsavljevic wrote: > Hello Sibi, > > The answer to your question lies outside of Coreboot domain. After bringing > Tiano Core, you need to bring the next phase of booting: OS boot loader. > The best for you is to use GRUB2. Then, from GRUB2 menu >

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