Am Sonntag, den 02.05.2010, 21:47 -0600 schrieb Marc Jones:
I was just looking at the same thing. I don't like the MTRR
manipulation that is happening in post_cache_as_ram.c. Doing 0-TOM is
a little tricky if the dimms are different sizes. It is easier to let
It's one MTRR per DIMM, where
Am Freitag, den 30.04.2010, 16:15 -0600 schrieb Marc Jones:
I'm working with amd/mahogany_fam10 mainboard and having problems in
ramstage. It is going through pci device scanning when it starts
finding the same devices again and malloc memory until it dies. It
also looks like it never goes
Hi,
the following sequence might help you to get your tree with local
changes across r5506 and r5507 without too much headache:
svn diff backup.diff
patch -R -p0 -i backup.diff
svn up
patch -l -p0 -i backup.diff
Please make sure that your local changes don't reintroduce whitespace
(eg. new
Am 26.04.2010 08:24, schrieb Dustin Harrison:
However, I don't really see how this flag gets set. Doing a 'grep -RH
CONFIG_SSE' points to the two makefile includes that add the enable_sse
code, but no references to setting the flag.
Such flags are set in Kconfig, and there the CONFIG_ prefix
Am 25.04.2010 12:41, schrieb Zheng Bao:
For the mainboard with AMD Family 10, if we make clean and make again,
it will fail. why?
After make clean, .c files created by iasl are still left in the build
folder, it will match the rule of
$(obj)/%.o: $(obj)/%.c $(obj)/config.h
@printf CC
an incomplete protection scheme with it.
Regards,
Patrick Georgi
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Am 20.04.2010 23:49, schrieb Stefan Reinauer:
This starts getting semi comprehensible... maybe a (short) comment why
this is done would be nice..
Done.
Also, does %config or *config work instead of mentioning all configs?
Yes, I didn't want to risk that we add some %config target that needs
Am 21.04.2010 17:45, schrieb Stefan Reinauer:
see patch
Yay!
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
So RAMBASE could be set to 1MB for all boards that use geode?
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...@coresystems.de
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
* move boot/acpi* boot/mp* boot/pir* to arch/i386/tables/ or
* move boot/acpi* to arch/i386/acpi
I'd like the tables to be as unified as possible (esp. when they're auto
generated at some point). So the first proposal sounds
Am 20.04.2010 17:59, schrieb Peter Stuge:
repository service wrote:
Make RAM init on i945GC work
..
-0x, 0x, /* nonexistant */
+0x00010402, 0x, /* DDR667 FSB533 - fake values */
Why fake? Can 945GC use DDR667?
Those values work (tested on
is that we don't have targets anymore. buildrom probably
needs some update for the coreboot build method.
Regards,
Patrick Georgi
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, just to run rm -rf $(obj) afterwards.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: Makefile
===
--- Makefile(Revision 5467)
+++ Makefile(Arbeitskopie)
@@ -70,7 +70,15 @@
DOXYGEN_OUTPUT_DIR := doxygen
Hi,
abuild's scanbuild support was broken, and we didn't noticed. Following
patch also cleans up some rough edges.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: util/abuild/abuild
===
--- util/abuild/abuild
Am 19.04.2010 15:08, schrieb Stefan Reinauer:
This hunk breaks compiling sconfig on my system. Changing it to the
following fixes it again:
+$(obj)/util/%.o: $(obj)/util/%.c $(obj)/config.h
This should be
+$(objutil)/%.o: $(objutil)/%.c $(obj)/config.h
+ printf HOSTCC $(subst
Am 19.04.2010 17:56, schrieb Patrick Georgi:
Am 19.04.2010 15:08, schrieb Stefan Reinauer:
This hunk breaks compiling sconfig on my system. Changing it to the
following fixes it again:
+$(obj)/util/%.o: $(obj)/util/%.c $(obj)/config.h
This should be
+$(objutil)/%.o: $(objutil)/%.c $(obj
, it's even useful for a single board build, as later rebuilds
(where utils don't require building) require a couple of seconds less.
The effect isn't as pronounced on unix-alikes.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/arch/i386/Makefile.bootblock.inc
Am 12.04.2010 06:41, schrieb Kevin O'Connor:
00.412: *post ddr_ram_setup()
00.415: Stage: loading fallback/coreboot_ram @ 0x4000 (163840 bytes), entry @
0x4000
01.369: coreboot-4.0-r5408M Mon Apr 12 00:19:03 EDT 2010 booting...
Indeed, the time to Stage:... is faster than romcc now. Just
Am 12.04.2010 08:28, schrieb Arne Georg Gleditsch:
The s2912_fam10 is missing the romstrap parts. When I try to enable the
romstrap linker scripts for TINY_BOOTBLOCK (instead of disabling TINY) I
get a different set of linker overlap errors.
r5410 fixes this issue here.
Patrick
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Am 12.04.2010 08:28, schrieb Arne Georg Gleditsch:
The s2912_fam10 is missing the romstrap parts. When I try to enable the
romstrap linker scripts for TINY_BOOTBLOCK (instead of disabling TINY) I
get a different set of linker overlap errors.
r5410 fixes this issue here.
Patrick
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-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/cpu/via/model_c7/Makefile.inc
===
--- src/cpu/via/model_c7/Makefile.inc (revision 5408)
+++ src/cpu/via/model_c7/Makefile.inc (working copy)
@@ -6,3 +6,5 @@
subdirs-y
Am 12.04.2010 15:39, schrieb Kevin O'Connor:
On Mon, Apr 12, 2010 at 11:56:45AM +0200, Patrick Georgi wrote:
Am 12.04.2010 06:41, schrieb Kevin O'Connor:
Indeed, the time to Stage:... is faster than romcc now. Just need
to fix that delay after Stage:..
Your other mail seems to indicate
Am 12.04.2010 17:18, schrieb Stefan Reinauer:
These boards have the same CPU socket, thus should be able to use CAR:
./src/mainboard/dell/s1850/Kconfig: select CPU_INTEL_SOCKET_MPGA604
./src/mainboard/intel/jarrell/Kconfig: select CPU_INTEL_SOCKET_MPGA604
Am 12.04.2010 17:25, schrieb Stefan Reinauer:
See patch
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 09.04.2010 21:41, schrieb Stefan Reinauer:
See patch
Boot tested on via/vt8454c, so
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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. They will however
require some refactoring if ROM mappings must be configured.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/Kconfig
===
--- src/Kconfig (revision 5399)
+++ src/Kconfig (working copy)
@@ -116,14
crt0_includes.h to crt0.S and runs this, instead of crt0.S.lb through
the assembler.
Minor clean up, but I hope it's clearer what's loaded when with this change.
It passes abuild.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/arch/i386/Makefile.bootblock.inc
(the
root_complex hack isn't acceptable for upstream)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 07.04.2010 18:13, schrieb Patrick Georgi:
Hi,
attached you'll find a couple of files:
Well, now..
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: util/sconfig/config.g
===
--- util/sconfig/config.g
Am 29.03.2010 03:54, schrieb Peter Stuge:
No problem. But is there a central place for the call, rather than in
every romstage.inc?
Not yet.
Patrick
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workaround than the abspath
hack.
But for now, this is good, so
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 28.03.2010 23:13, schrieb Stefan Reinauer:
While I think this patch is great and we definitely need it, there are
some things I'd like to discuss and improve, or back out if possible...
That part of the change wasn't one of my brightest moments.
Your patch (build.h handling, take 2) is much
Am 30.03.2010 01:05, schrieb Stefan Reinauer:
I wonder, how can we completely create pirq_tables dynamically... Is it
that hard?
*{0x00,(0x013)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8},
{0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
{0x00,(0x023)|0x0,
gives shorter command lines) and helps ccache
finding matches for checkouts in different directories (even though it
should normalize paths itself)
It's abuild tested.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/cpu/x86/smm/Makefile.inc
Hi,
sconfig, the tool to convert devicetree.cb into our internal
representation, warned about naming conflicts even if they were uncritical.
Make sconfig only complain about real conflicts.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: util/sconfig/config.g
Am 26.03.2010 17:20, schrieb Joseph Smith:
It looks for i386-elf-* in the util/crossgcc/xgcc/bin directory.
I use crossgcc out of my coreboot repo, by adding my cross gcc bin to my
$PATH.
Any way we could add another line that looks for crossgcc in the builders
$PATH?
Normally, I'd say
Am 26.03.2010 19:39, schrieb Stefan Reinauer:
Myles, are you sure that is dead code or is it just a missing
ACPI_SSDTX_NUM in Kconfig because noone cared to move the board to
Kconfig completely?
That would be relatively simple to figure out: if there are ssdt*.[ad]sl
or pci*.[ad]sl files around
Am 26.03.2010 20:25, schrieb Stefan Reinauer:
What information would be in those SSDTs if they were there?
On i945 we only generate one SSDT for the CPU frequency scaling code,
but it isn't compiled through iasl, so no AmlCode hacks.
If the code is there at compile time (which it has to be
); /* Set Gpio8 as input */
+ byte |= (1 5); /* Set Gpio8 as input */
That should also be Gpio9, right?
I can't test it, but it looks plausible. Assuming you tested it, and
with that comment fixed, it's
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
Patrick
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(thomson/ip1000) goes down
from 9 to 3 seconds when using 4 parallel build jobs.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 25.03.2010 18:02, schrieb Patrick Georgi:
Hi,
most of the tree was already ccache aware, with one exception: romcc.
This hurt, as on the non-CAR boards, this is a large non-parallelizable
part of the total build time.
This patch changes romcc to:
- accept -c and -S (and ignores them
Hi,
attached patch tells abuild to pass V=1 to make, so it's actually
verbose when such is requested.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: util/abuild/abuild
===
--- util/abuild/abuild (Revision 5290
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Updated patch: ccache defaults to no for CC, HOSTCC and ROMCC, and can
be configured by Kconfig.
abuild is extended to draw in ccache as well.
Complete abuild run on our build server:
without ccache: 17 minutes
first time with ccache
Am 24.03.2010 04:33, schrieb Bao, Zheng:
sed -i 's/printk_\([a-z]*\)(/printk(BIOS_\U\1\E, /g' *.c
Thank you, it's noted on http://www.coreboot.org/Flag_Days
Patrick
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Am 24.03.2010 22:20, schrieb Stefan Reinauer:
If they're not runtime patched that'd be a good idea... I think on
i945 we still patch them up, so const wont work there...
We patch up the resulting (ie. copied) ACPI data, or not? So the
original AmlCode can be const
Patrick
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Am 24.03.2010 22:01, schrieb Stefan Reinauer:
See patch
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 24.03.2010 22:02, schrieb Stefan Reinauer:
See patch
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 24.03.2010 22:02, schrieb Stefan Reinauer:
See patch
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 24.03.2010 22:03, schrieb Stefan Reinauer:
See patch...
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 24.03.2010 22:04, schrieb Stefan Reinauer:
See patch..
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 23.03.2010 09:24, schrieb Knut Kujat:
Morning,
I downloaded the latest revision and tried to compile it for my board
(supermicro h8qme-2+) but it fails compiling with:
Builds fine for me - you might have to remove the build directory
before rebuilding.
Patrick
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Am 18.03.2010 17:23, schrieb Peter Stuge:
+if (!((cpu_init_detectedx) || (!boot_cpu( {
+/* Nothing special needs to be done to find bus 0 */
+/* Allow the HT devices to be found */
+enumerate_ht_chain();
+/* sb600_lpc_port80(); */
+
boot_cpu()) {
Like this?
I also removed the failover.c files, which aren't used anymore (and were
pretty useless after the cleanup anyway)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/mainboard/iwill/dk8_htx/romstage.c
obsolete assumptions about the
config flags above.
The change is abuild tested, but not boot tested, I hope I didn't break
anything.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
...@gmail.com mailto:myle...@gmail.com
The non-ACPI warning stuff is
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
I didn't look into the ACPI stuff yet.
As for SSE2 warnings, just add a default n to its global definition in
src/cpu/Kconfig? (and to MMX and SSE, too)
That's also
Acked
Am 18.03.2010 20:46, schrieb Myles Watson:
I thought coreboot's name substitution was done after asl compiled the file.
Have you tried running iasl on the file outside the build process?
We generally pass asl code through CPP first, so we can use common
headers for address definitions in C and
-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/arch/i386/Makefile.inc
===
--- src/arch/i386/Makefile.inc (revision 5223)
+++ src/arch/i386/Makefile.inc (working copy)
@@ -42,7 +42,7
that are supposed to be _inc_luded
into some larger form (mostly by crt0_includes.h)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Peter Stuge pe...@stuge.se
Thanks, r5224
Patrick
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as coreboot.rom.tmp and renames the result after
all write operations succeeded. This helps should any of the operations
fail (eg. because the ELF parser in cbfstool is confused by the input file)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/arch/i386/Makefile.inc
Am 15.03.2010 01:11, schrieb Stefan Reinauer:
See patch... This patch allows me to compile coreboot with LLVM/clang.
To actually use LLVM/clang, I just hard coded it in xcompile for now:
This makes it configurable. Please test.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index
|= 4;
}
With the attached patch, this testcase, your testcase, and a full abuild
run work.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: util/romcc/romcc.c
===
--- util/romcc/romcc.c (Revision 5210)
+++ util/romcc
Am 15.03.2010 20:48, schrieb Stefan Reinauer:
The changes were merely trying to fix the segfaults, not implement or
change anything big. I think we do want fixes for segfaults. Always.
To be fair, the original issue wasn't a segfault, but an internal
compiler error - not exactly any more
build, but it's probably not worth the
trouble (it's harder to keep make clean and the likes working with such
an optimization)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/Kconfig
===
--- src/Kconfig
some useless jmp instructions) as
it has no side effects, so I can only verify it builds.
Please test it on your real world code.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: util/romcc/romcc.c
===
--- util/romcc
version is faster in this case.
Anyway, this patch removes a couple of files that don't need to exist
anymore, given that only K8 was using clear_memory.
Yay :-)
SIgned-off-by: Myles Watson myle...@gmail.com mailto:myle...@gmail.com
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
-by: Patrick Georgi patrick.geo...@coresystems.de
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Am 05.03.2010 17:53, schrieb Arne Georg Gleditsch:
Signed-off-by: Arne Georg Gleditsch arne.gledit...@numascale.com
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
and committed as r5197
The real fix would be to eliminate the uses of these config options
(they're useless since we
Hi,
attached patch should help devs to more easily understand the main
loop that includes Makefile.incs.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: Makefile
===
--- Makefile(revision 5186)
+++ Makefile
Am 01.03.2010 09:00, schrieb Bao, Zheng:
What I keep trying to make everyone understand is not what the rules we
should use to decide the stack size.
By now, I'm quite certain that the rule is wrong.
Binutils bug or not.
What I worry is the bug in the
crosstool will make the rule do the wrong
Pearson tpear...@raptorengineeringinc.com
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
and committed as r5179
Patrick
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Am 12.02.2010 01:42, schrieb tpear...@raptorengineeringinc.com:
Signed-off-by: Timothy Pearson tpear...@raptorengineeringinc.com
Committed in r5180, with changes to make it fit with recent changes in
the repository.
I'd be grateful if you could test the board with these changes and
report back
, but it should be
close.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/cpu/x86/lapic/lapic_cpu_init.c
===
--- src/cpu/x86/lapic/lapic_cpu_init.c (revision 5180)
+++ src/cpu/x86/lapic/lapic_cpu_init.c (working copy
Am 01.03.2010 17:23, schrieb Myles Watson:
However, this does not fix the bug in our stack size calculation.
I'm not quite sure if the patch does the right thing, but it should be
close.
I don't think we need to make the SMP check. Can't we just put in an assert
that checks for RAMBASE
be removed at some point.
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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* southbridge/sis/sis966
* northbridge/via/vx800
for the benefit of both image layouts.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/southbridge/nvidia/ck804/Makefile.inc
===
--- src/southbridge/nvidia/ck804
, etc. That seemed to be
overkill for the three uses of the variable (which isn't even globally
defined)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/mainboard/iwill/dk8_htx/Kconfig
===
--- src/mainboard/iwill
the merit of the
approach, instead of the actual selection of options to deprecate.
Patch is
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/Kconfig
===
--- src/Kconfig (revision 5174)
+++ src/Kconfig (working
Am 27.02.2010 15:41, schrieb Stefan Reinauer:
On 2/27/10 2:57 PM, Peter Stuge wrote:
Um..? Oh, ok, they aren't all bootsplash types. But, I think there
should be just one meaningful parameter for each file. My point is
that a bootsplash type is redundant, since a specific filename must
Am 28.02.2010 03:04, schrieb Carl-Daniel Hailfinger:
compatible. Your patch might be backwards compatible, but some of the
proposed extensions (option ROM naming and separate PCI ID storage) are not.
The only other user of option roms (SeaBIOS) uses a different type
number to prevent issues once
: It simply removes the separate
section and reserves an area at the same place, of the same size, just
in a way that works with the linker?
If so,
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
We can still sort out if we want to keep that (nonsensical
Am 26.02.2010 15:14, schrieb Myles Watson:
I would like to double check this before it gets committed. I only
tried it once, and the difference was very large. 3M of stack doesn't
seem right.
Those 3M are CONFIG_MAX_CPUS*CONFIG_STACK_SIZE, right?
I think there is some code that assigns a
of the bug Zheng
Bao is experiencing).
I'd say, commit this (as it fixes things for you). If it's not enough,
we can do the full change.
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Index: src/cpu/via/model_c3/Kconfig
===
--- src/cpu/via/model_c3/Kconfig(revision 5158)
+++ src/cpu/via/model_c3/Kconfig(working copy)
@@ -1,3 +1,4 @@
config CPU_VIA_C3
Am 25.02.2010 11:50, schrieb Joseph Smith:
I just have it running outside the coreboot directory, does that make a
difference?
Is it used by coreboot? (see .xcompile)
Were the patches applied? (We specifically fix the /-as-comment
feature in our version), but I know of some cases where patching
Am 25.02.2010 13:38, schrieb Joseph Smith:
So am I looking at this correctly?
It is using crossgcc correct?
Think so.
Maybe your crossgcc build failed on patching, too...
Patrick
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Am 25.02.2010 15:38, schrieb Myles Watson:
Just a data point: amd/serengeti_cheetah_fam10 works for me in SimNow
without any changes. (using crossgcc as toolchain)
I'm using crossgcc. The fact that it breaks and fixes itself depending on
seemingly unrelated changes means that it's broken and
Am 25.02.2010 16:27, schrieb Uwe Hermann:
Index: src/cpu/via/model_c3/Kconfig
===
--- src/cpu/via/model_c3/Kconfig (revision 5158)
+++ src/cpu/via/model_c3/Kconfig (working copy)
@@ -1,3 +1,4 @@
config CPU_VIA_C3
Hi,
the same thing I did with crt0s, just with ldscripts this time. Most
mainboard-Makefile.inc's look _very_ alike now.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/mainboard/Makefile.k8_ck804.inc
Hi,
Seems that I messed up the conversion of the coreboot_apc stuff over to
kconfig. Short version: It doesn't build, and we never noticed.
It affects amd/serengeti_cheetah and supermicro/h8dme, the other two APC
boards in newconfig lost that flag on transition
(amd/serengeti_cheetah_fam10 and
Am 24.02.2010 09:35, schrieb Knut Kujat:
The attached patch does several fixes so the H8QME-2+ boards builds and
boots successfully with Kconfig.
I also corrected some issues regarding mptables.
/Signed-off-by: Knut Kujat kn...@gap.upv.es
Acked-by: Patrick Georgi patrick.geo
Am 25.02.2010 06:14, schrieb Joseph Smith:
Anyone seen this error before?
/home/joe/coreboot/src/cpu/intel/model_6ex/cache_as_ram.inc: Assembler
messages:
/home/joe/coreboot/src/cpu/intel/model_6ex/cache_as_ram.inc:43: Error:
unbalanced parenthesis in operand 1.
Am 25.02.2010 02:46, schrieb Bao, Zheng:
I am pretty sure that you meet the same the same problem.
It seems to be ridiculous. Please check the maillist about this issue.
http://www.coreboot.org/pipermail/coreboot/2010-February/055730.html
If everything goes as I expected, the
Am 13.02.2010 01:07, schrieb Jonathan A. Kollasch:
Signed-off-by: Jonathan A. Kollasch jakll...@kollasch.net
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
and committed as r5147
Thanks,
Patrick
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Am 21.02.2010 23:08, schrieb Rudolf Marek:
Anyway, disabling the suspend/resume now. Its broken. Either cbmem stuff needs
to be fixed, or old functionality for suspend/resume with hole must be
restored,
Could you go to some detail as how cbmem must be fixed for your board?
I'd prefer that over
, especially as it's just a copy. Worst
case, the version string is incomplete, which is something we can live
with (just like before this commit).
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
Committed as r5149
Thanks,
Patrick
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coreboot mailing
Hi,
I'm currently working on the backlog we have with patches and wanted to
point out a nice tool we have for that.
On http://patchwork.coreboot.org/project/coreboot/list/ you can find a
patchwork installation which tracks our mailing list, keeping watch over
submitted patches and the
Am 25.10.2009 00:50, schrieb Stefan Reinauer:
Not sure if this is such a good idea.. Opinions?
Given that PS/2 is always at 0x60/0x64 and that the code has no sensible
behaviour in any other case, this seems like a good idea.
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
Not committing
for that.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/arch/i386/init/ldscript_failover.lb
===
--- src/arch/i386/init/ldscript_failover.lb (revision 5130)
+++ src/arch/i386/init/ldscript_failover.lb (working
Hi,
The debate about e7501 (dropping or risking broken code in the tree)
reminded me of an idea I had a while ago:
Do we want to establish a list of boards and their latest successfully
tested revision, and all maintainers/testers for each board that agree
to test changes regularily or on demand
Hi,
attached patch removes Kconfig entries that disable
WAIT_BEFORE_CPUS_INIT. It's disabled by default
(see src/cpu/x86/Kconfig)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/mainboard/gigabyte/m57sli/Kconfig
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