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On 4/24/10 5:28 PM, Kevin O'Connor wrote:
On Fri, Apr 23, 2010 at 11:01:34PM +0200, Stefan Reinauer wrote:
This patch cleans up the option rom code in coreboot significantly by
dropping all extra copies of vgabios.c and instead changing the code to
use oprom/x86.c with custom per-board
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Signed-off-by: Zheng Bao zheng@amd.com
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Try tracing the original BIOS and coreboot with SerialICE and compare
the differences ... It's a bunch of work but not as ugly as debugging
ROMCC assembler output... :-) http://www.serialice.com/
Stefan
On 22.04.2010, at 20:16, Dustin Harrison dustin.harri...@sutus.com
wrote:
I did a
On 4/21/10 6:13 PM, Patrick Georgi wrote:
Am 21.04.2010 17:45, schrieb Stefan Reinauer:
see patch
Yay!
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
So RAMBASE could be set to 1MB for all boards that use geode?
Unfortunately not yet... On the artecgroup dbe61 I get
On 4/21/10 8:14 PM, bari wrote:
Bonus points if you can include our hare ;-)
Regards,
Carl-Daniel
@+
@@@
:.+@@@
D src/arch/i386/smp/Makefile.inc
D src/arch/i386/smp/ioapic.c
D src/arch/i386/smp/mpspec.c
M src/arch/i386/boot/Makefile.inc
A + src/arch/i386/boot/mpspec.c
D src/arch/i386/init/car.S
M src/arch/i386/lib/Makefile.inc
A + src/arch/i386/lib/ioapic.c
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On 4/20/10 5:57 PM, Peter Stuge wrote:
Bernhard Wiedemann wrote:
This patch adds basic support for mainboard iBASE:MB899
based on Kontron 986LCD-M
Great to support new boards! :)
In the course of this work did you notice any natural parts which
could or should be factored out, to
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Make VSA code
... maybe a (short) comment why
this is done would be nice..
Also, does %config or *config work instead of mentioning all configs?
Other than that, Acked-by: Stefan Reinauer ste...@coresystems.de
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On 4/20/10 11:47 PM, Rudolf Marek wrote:
Does it work better like this?
/* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID) {
/* Power management controller */
dev =
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On 4/19/10 10:17 PM, Patrick Georgi wrote:
Am 19.04.2010 17:56, schrieb Patrick Georgi:
Am 19.04.2010 15:08, schrieb Stefan Reinauer:
This hunk breaks compiling sconfig on my system. Changing it to the
following fixes it again:
+$(obj)/util/%.o: $(obj)/util/%.c $(obj
On 4/19/10 11:21 PM, repository service wrote:
The following hardware doesn't work:
4x NIC 21143-PD
2x PCMCIA PCI1225PDV
No surprise.. there seems to be no mptable and a possibly incomplete
pirq table.
+device pci 0d.0 on end # NIC (DEC DECchip
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On 17.04.2010, at 16:41, Myles Watson myle...@gmail.com wrote:
This is a reminder to myself in case it is obvious to everyone else:
It seems very difficult to guarantee that the removal/insertion of a
print statement has no other effects.
Thanks for sharing this kind of information. This
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On 4/14/10 8:08 AM, Peter Stuge wrote:
A.Haq Abbad wrote:
So you advice me to install coreboot on it?
I wouldn't. You will brick the board.
the motherboard is not mentioned on the website, but the chipset is!
That doesn't help. Unless you want to spend some time (ranging
On 4/14/10 5:54 AM, Keith Hui wrote:
irq 9: nobody cared (try booting with the irqpoll option)
This is caused by setting fadt-sci_int without an irqoverride source in
the MADT.
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9,
On 4/14/10 4:18 AM, Dustin Harrison wrote:
I've put several print_info statements in romstage.c and narrowed it
down to the following line in i3100_early_lpc.c:
pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 7));
Further debug shows that in general I can not read a value
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/northbridge/amd/gx2/chipsetinit.c
===
--- src/northbridge/amd/gx2/chipsetinit.c (revision 5425)
+++ src/northbridge/amd/gx2/chipsetinit.c (working copy)
@@ -275,7
. Did you check v3?
Nor do I...
v3 never supported gx2.
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On 4/14/10 9:35 PM, Myles Watson wrote:
On Wed, Apr 14, 2010 at 1:22 PM, Stefan Reinauer
ste...@coresystems.de mailto:ste...@coresystems.de wrote:
On 4/14/10 6:44 PM, Myles Watson wrote:
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for romcc_io usage?
Stefan
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Am 12.04.2010 15:39, schrieb Kevin O'Connor:
On Mon, Apr 12, 2010 at 11:56:45AM +0200, Patrick Georgi wrote:
Am 12.04.2010 06:41, schrieb Kevin O'Connor:
Indeed, the time to Stage:... is faster than romcc now. Just need
to fix that delay after Stage:..
Your
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move stack location to RAMBASE + HIGH_MEMORY_SAVE
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/cpu/via/car/cache_as_ram.inc
===
--- src/cpu/via
See patch
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Drop
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move model_6ex car to a single file. No more .c files that only consist of a
single several pages long asm statement
Could use some renumbering of post codes, but that's good for another time.
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Index: src/cpu
Am 12.04.2010 17:18, schrieb Stefan Reinauer:
These boards have the same CPU socket, thus should be able to use CAR:
./src/mainboard/dell/s1850/Kconfig: select CPU_INTEL_SOCKET_MPGA604
./src/mainboard/intel/jarrell/Kconfig: select CPU_INTEL_SOCKET_MPGA604
./src/mainboard/intel
to be consistent and stop deleting them :-)
Stefan
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On 4/11/10 7:50 AM, repository service wrote:
Author: linux_junkie
Date: Sun Apr 11 07:50:08 2010
New Revision: 5402
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5402
Log:
Trivial changes to i82830 raminit.c for USE_PRINTK_IN_CAR.
Signed-off-by: Joseph Smith
On 4/10/10 5:37 PM, baiyin cai wrote:
hi,
it seem there is no shared.h under filo/fs/ which included in
squashfs_zilb.c which would caused build error while open
FSYS_SQUASHFS. it seems also useless.
just remove the declaration.
signed-off-by Cai Bai Yin caibaiyin@gmail.com
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On 04/11/2010 10:23 AM, Stefan Reinauer wrote:
Performing dummy read/write
Reading RAM at 0x2000 = 0xf5ba55aa
Writing RAM at 0x2000= 0x55aa55aa
Reading RAM at 0x2000 = 0x55aa55aa
So this read/write is only for debugging? It will break suspend/resume,
should you intend to go
See patch
add support for reading ip1000 gpios.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/mainboard/thomson/ip1000/mainboard.c
===
--- src/mainboard/thomson/ip1000/mainboard.c(revision 5402)
+++ src
See patch
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On 4/10/10 10:54 AM, Chi Min Wang wrote:
Hello
I am trying Coreboot on an Asus M2V-TVM
http://www.asus.com/product.aspx?P_ID=Axjo2m7xV4kUvbxScontent=specifications
based on VIA K8M890CE/8237Rplus which seems quite similar to M2V-MX SE
except superio(ITE 8712F vs 8716F) snd flashrom
On 4/10/10 10:22 AM, Marc Bertens wrote:
Hi all,
currently i have coreboot, seabios and sgabios running on Nokia IP530
(firewall) motherbord wih PIII, i440BX.
and that works great, with alot of help already from the #coreboot and
#flashrom irc rooms and all the people there, for that
On 4/10/10 1:06 PM, Marc Bertens wrote:
Op zaterdag 10-04-2010 om 12:55 uur [tijdzone +0200], schreef Stefan
Reinauer:
dumping mptable + pirq with the originally installed bios?
yes, but running the mptable tool give an error like that i should try
the -grope option, but i
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On 4/9/10 1:50 PM, Arne Georg Gleditsch wrote:
Stefan Reinauer ste...@coresystems.de writes:
I made a quick attempt at fixing this, but ran into linker script
problems like:
.../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld:
section .id loaded
On 4/9/10 5:31 PM, Arne Georg Gleditsch wrote:
Stefan Reinauer ste...@coresystems.de writes:
Ah, the error above may occur if changing significant parts of Kconfig
variables, such as tiny bootblock ;)
please remove build/ and try again.
I always do. :) This is reproducible
See patch
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See patch
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Drop
Hi,
I just updated our central upcoming infrastructure changes list.
http://www.coreboot.org/Infrastructure_Projects
If you can / want to work on any of these issues, step up now :-)
It's essential that we drop as many special cases from the code as
possible and only let new ones in if there
Acked-by: Stefan Reinauer ste...@coresystems.de
On 4/8/10 10:17 PM, Patrick Georgi wrote:
(retry, the first attempt seems to have been eaten by the list daemon)
Hi,
attached patch splits crt0.S.lb, adds the first part of it as first
element of crt0s, adds the second part as last element
/socket_mfcbga479/Kconfig(revision 0)
+++ src/cpu/intel/socket_mfcbga479/Kconfig(revision 0)
@@ -0,0 +1,5 @@
+config CPU_INTEL_SOCKET_MFCBGA479
+ bool
+ select CPU_INTEL_MODEL_6BX
Where is CPU_INTEL_MODEL_6BX defined?
With above issues fixed this is
Acked-by: Stefan Reinauer ste
On 4/8/10 11:32 PM, Joseph Smith wrote:
Index: src/cpu/intel/model_6bx/Kconfig
===
--- src/cpu/intel/model_6bx/Kconfig (revision 0)
+++ src/cpu/intel/model_6bx/Kconfig (revision 0)
@@ -0,0 +1,3 @@
+config CPU_INTEL_CORE
+
On 4/8/10 7:07 PM, Myles Watson wrote:
Here's one for all boards.
Signed-off-by: Myles Watson myle...@gmail.com mailto:myle...@gmail.com
Acked-by: Stefan Reinauer ste...@coresystems.de
Index: svn/src/mainboard/amd/dbm690t/acpi_tables.c
wasn't meant to be private only.
On 4/7/10 12:24 AM, Stefan Reinauer wrote:
On 4/7/10 12:06 AM, Myles Watson wrote:
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org]
On Behalf Of repository service
Sent: Tuesday, April 06
On 4/7/10 1:05 AM, secretoc...@gmx.de wrote:
Hi,
I've got an HP nx6310 notebook with Linux as operating system and I'm
thinking of trying coreboot to get rid of the non-free HP BIOS.
Though I'm quite confident that the chipset is supported, it'll be nice if
someone would confirm that and
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See patch
The error message is misleading, even for a SPEW, because
the slot is empty, it's NOT a bad ID (and the message is
more confusing than helpful even in SPEW)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/devices/pci_device.c
On 4/2/10 6:09 PM, ron minnich wrote:
On Fri, Apr 2, 2010 at 9:04 AM, Stefan Reinauer ste...@coresystems.de wrote:
See patch
I'm mixed on this one, but at the same time, I bet there are few
broken devices that return 0 as there were in the old days.
I wonder, what would we do
On 4/2/10 7:55 PM, Myles Watson wrote:
loglevel.diff:
Remove BIOS_EMERG, BIOS_ALERT, BIOS_CRIT, BIOS_NOTICE, BIOS_NEVER
I am not convinced that's a good idea. But let's hear what other people
say...
I didn't change their numerical values. They were rarely used.
BIOS_EMERG, BIOS_ALERT,
Dear students,
remember it's time to apply for a Google Summer of Code stipend for this
year. The registration period started on March 28th and it's soon over
again, so better hurry up and hand in your proposals today!
See more information and proposal ideas here: http://www.coreboot.org/GSoC
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See patch
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This patch makes the assumption that the code doing the cmos choice has
CONFIG_USE_OPTION_TABLE enabled.
Is this always the case?
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On 3/29/10 10:01 PM, Myles Watson wrote:
On Mon, Mar 29, 2010 at 1:14 PM, Stefan Reinauer
ste...@coresystems.de mailto:ste...@coresystems.de wrote:
This patch makes the assumption that the code doing the cmos
choice has CONFIG_USE_OPTION_TABLE enabled.
Is this always the case
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On 3/30/10 12:35 AM, Stefan Reinauer wrote:
On 3/30/10 12:15 AM, Myles Watson wrote:
Modified: trunk/src/arch/i386/include/arch/pirq_routing.h
==
--- trunk/src/arch/i386/include/arch/pirq_routing.h
On 3/30/10 12:43 AM, Myles Watson wrote:
On Mon, Mar 29, 2010 at 4:40 PM, Stefan Reinauer
ste...@coresystems.de mailto:ste...@coresystems.de wrote:
On 3/30/10 12:35 AM, Stefan Reinauer wrote:
On 3/30/10 12:15 AM, Myles Watson wrote:
Modified: trunk/src/arch/i386/include
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On 3/30/10 1:28 AM, Joseph Smith wrote:
Hello,
How hard would it be to point Kconfig to look for a defconfig in the
mainboard directory?
In util/kconfig/confdata.c:
Change:
const char conf_defname[] = arch/$ARCH/defconfig;
to point to:
const char conf_defname[] = ..
While I think this patch is great and we definitely need it, there are
some things I'd like to discuss and improve, or back out if possible...
On 3/27/10 6:18 PM, repository service wrote:
-all: $(obj)/config.h coreboot
+all: $(obj)/config.h $(obj)/build.h coreboot
endif
This will make
Does this patch make sense?
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On 3/29/10 12:52 AM, Peter Stuge wrote:
+quick_ram_check();
Maybe not so great. Rather than adding this function call to each and
every romstage, could we figure out a way to keep it centrally
instead? Maybe controlled by an NVRAM option?
It's not intended as an option.
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On 3/25/10 11:46 PM, Stefan Reinauer wrote:
On 3/25/10 11:07 PM, Myles Watson wrote:
@@ -273,8 +273,10 @@
acpi_create_facs(facs);
dsdt = (acpi_header_t *) current;
-current += AmlCode.length;
-memcpy((void *) dsdt, AmlCode, AmlCode.length);
+memcpy((void *) dsdt
Hi,
thank you very much for your review of the code...
On 3/27/10 4:14 PM, baiyin cai wrote:
there is an bug(at least in my eyes).
/main/grub/grub.c
line 937:
plen=strrchr(CMDLINE_TMP,'/') -(CMDLINE_TMP+7) +1;
function strrchr returns the pointer which is (char*), right?
it subtracts a
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Acked-by: Stefan Reinauer ste...@coresystems.de
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On 3/6/10 9:24 PM, yhlu wrote:
On Fri, Mar 5, 2010 at 10:26 AM, ron minnich rminn...@gmail.com
mailto:rminn...@gmail.com wrote:
What would coreboot need to do to support IPMI BMC?
need to use BT or KCS interface to tell FRU list esp for the devices
there is side band access from BMC
On 3/26/10 5:07 PM, Joseph Smith wrote:
Speaking of docs, any way we could get building libpayload on x86_64
documented?
I could not get it to build on AMD x86_64.
Look at FILO's build.sh script.
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On 3/26/10 5:36 PM, Joseph Smith wrote:
On Fri, 26 Mar 2010 17:09:31 +0100, Stefan Reinauer ste...@coresystems.de
wrote:
On 3/26/10 5:07 PM, Joseph Smith wrote:
Speaking of docs, any way we could get building libpayload on x86_64
documented?
I could not get it to build on AMD
On 3/26/10 6:06 PM, Joseph Smith wrote:
Just try the wiki once... it contains great information that just needs
to be cut and pasted into a shell... ;-)
ok cool. Then can
$ make CC=gcc -m32 LD=ld -b elf32-i386 HOSTCC=gcc AS=as --32
be used on libpayload as well?
I don't use
-
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On 3/26/10 7:43 PM, Myles Watson wrote:
On Fri, Mar 26, 2010 at 12:39 PM, Stefan Reinauer
ste...@coresystems.de mailto:ste...@coresystems.de wrote:
Myles, are you sure that is dead code or is it just a missing
ACPI_SSDTX_NUM in Kconfig because noone cared to move the board
On 3/25/10 5:25 AM, Joseph Smith wrote:
I keep getting this error:
CC mainboard/thomson/ip1000/crt0.initobj.o
romstage.c: Assembler messages:
romstage.c:2162: Error: junk `(0)' after expression
romstage.c:2166: Error: junk `(0)' after expression
make: ***
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On 3/25/10 5:45 PM, Myles Watson wrote:
The reason I object to the void* method was that it just masked the
problem so that gcc couldn't spot it. Casting to void* and back to a
struct seems equivalent to just having it declared two different ways.
I don't think it's masking the problem. It
On 3/25/10 6:04 PM, Patrick Georgi wrote:
Hi,
attached patch tells abuild to pass V=1 to make, so it's actually
verbose when such is requested.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
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On 3/25/10 7:54 PM, Myles Watson wrote:
A (maybe too obvious) variant would be to create a binary dsdt
instead of a C file and pack that into CBFS. It would reduce
coreboot size and allow to copy/decompress it right to cbmem
This would be fine with me. It's quite a bit more
server:
without ccache: 17 minutes
first time with ccache: 16 minutes
second time with ccache (same revision): 9 minutes
Still
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
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used anymore
* (define htoX macros for ppc)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
--- include/powerpc/arch/endian.h (revision 5296)
+++ include/powerpc/arch/endian.h (working copy)
@@ -38,4 +38,8 @@
#define ntohll(in) (in)
+#define htonw(in) ntohw(in)
+#define htonl
See patch
USB updates from our internal tree
- support MMC2 devices
- make usb stack more solid
- drop some unused functions
- fix lowspeed/speed naming
- add support for quirks
- improve usbhid driver
Signed-off-by: Stefan Reinauer ste...@coresystems.de
--- include/usb/usb.h (revision 5296
On 3/25/10 10:43 PM, Segher Boessenkool wrote:
It seems like others must have this problem of needing to force a binary
blob into a struct.
Just memcpy() it from the blob to the struct. If I remember your
code correctly, you copy it later anyway, so might as well do it
in one step.
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