[coreboot] Re: New to coreboot. Need pointer to startup sequence

Hey Edward, Which platform do you use kabylake, coffeelake, broadwell de or any other ? Best Regards, Philipp On 8/2/19 8:54 AM, Ranga Rao wrote: > Hi Edward, > > Raminit code is in src\drivers\intel\fsp1_1\ Raminit.c > > Function: fsp_memory_init(_memory_init_params); > > Best Regards >

[coreboot] Call For Participation - OSFC 3rd to 6th September 2019

." Cheers, Zaolin signature.asc Description: OpenPGP digital signature ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Intel® FSP External Architecture Specification v2.1 Has Been Released

ved could be posted to > https://github.com/IntelFsp/FSP/issues ? > >   > > Vincent > > *From:*Zaolin [mailto:zao...@das-labor.org] > *Sent:* Thursday, May 16, 2019 9:01 AM > *To:* Desimone, Nathaniel L ; > coreboot@coreboot.org > *Subject:* [coreboot] Re: Intel® FSP

[coreboot] Re: Intel® FSP External Architecture Specification v2.1 Has Been Released

Hey Nate, Would it be possible for us to influence future specifications as well. The community experienced some issues with the overall FSP-S design and we would like to discuss that with your team. Best Regards, Philipp On 16.05.19 04:36, Desimone, Nathaniel L wrote: > > Hi Everyone, > >  

[coreboot] Re: Building Coreboot Image for Opencellular

Hey Karthik, Every new Intel platform needs blobs. For OpenCellular you need to use the Intel FSP for Baytrail, Intel ME, Microcode and Intel Flash Descriptor. https://github.com/Telecominfraproject/OpenCellular/wiki/How-to-deploy-GBC-firmware#put-the-binaries-in-the-right-place Otherwise you

[coreboot] Re: ONIE EEPROM format

Hey Hannah, Not yet. On 15.04.19 22:05, hannah.willi...@dell.com wrote: > ONIE EEPROM signature.asc Description: OpenPGP digital signature ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Nvidia Optimus support, help needed

Sup, -> f8 on my Thinkpad W530 On 05.04.19 20:21, Patrick Rudolph wrote: > Hi folks, > In order to add Nvidia Optimus support on Lenovo laptops, I'm trying > to fix the last issues on [1], but I need your help to do some test on > Lenovo's firmware. > On Lenovo Sandy Bridge / Ivy Bridge series

[coreboot] Re: Caby lake support

There are Intel reference boards. You can find them in the code under: src/mainboard/intel/ A Kaby Lake reference board should be kblrvp. On 20.02.19 11:29, Mayuri Tendulkar wrote: > > Thanks for quick response. > >   > > I see below release- this support is added. > >   > >

Re: [coreboot] Further coreboot releases, setting new standards

FYI https://review.coreboot.org/c/coreboot/+/29820/3/MAINTAINERS#219 We will take care of the SoC support. I think Werner will jump in as well. On 28.11.18 22:04, Nico Huber wrote: > On 28.11.18 02:59, Jay Talbott wrote: >> Although I have participated in a number of reviews of coreboot patches,

Re: [coreboot] Kabylake H: SPI Transaction Error at Flash Offset d10000

. BR, Zaolin On 19.11.18 13:04, Jose Trujillo via coreboot wrote: > Thank you Christian, > > Works in my system too, Kabilake FSP2 issue? > The only small drawback is the disabled ability to upgrade coreboot from > itself which correct me if I am wrong is great in terms of security

[coreboot] FSP 1.0 Sandy-/Ivybridge removal

stuff or has complains about the current plan? BR, Zaolin signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] OSFC Tickets

Friendly reminder. 2 days until the ticket sale is closed. Buy your tickets now https://osfc.io/tickets -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Coffee Lake FSP Released

gt; >   > >   > > *From:*coreboot [mailto:coreboot-boun...@coreboot.org] *On Behalf Of > *Zaolin > *Sent:* Thursday, August 23, 2018 2:41 PM > *To:* ron minnich ; Patrick Georgi > > *Cc:* Desimone, Nathaniel L ; coreboot > > *Subject:* Re: [coreboot] Coffee Lake FSP Relea

Re: [coreboot] Coffee Lake FSP Released

@Nathaniel We found a perfect license for the Intel FSP: https://01.org/mcu-path-license-2018 On 8/23/18 6:35 PM, ron minnich wrote: > Yes, this redistribution issue does not affect just coreboot, it also > affects linuxboot users and OCP vendors. It would really be nice to > change the

Re: [coreboot] Porting Kabylake laptop

Hey Chris, yes it does. The PI interface is in terms of encapsulation somewhat cleaner then the FSP integration. I think that was Ron concern using PI instead of FSP. If we talking about full customization up to the bootblock and vboot2 support I would recommend to use coreboot in combination

Re: [coreboot] RV: Error booting with TPM enabled.

t;     .set_resources = hudson_lpc_set_resources, >     .enable_resources = hudson_lpc_enable_resources, > #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) >     .write_acpi_tables = acpi_write_hpet, > #endif >     .init = lpc_init, >     .scan_bus = scan_lpc_bus, >     .ops_pci = _pci, >   

Re: [coreboot] RV: Error booting with TPM enabled.

Hey, you miss the LPC ACPI path for your SoC. Just register the acpi_name method: https://review.coreboot.org/#/c/coreboot/+/25534/2/src/soc/intel/fsp_broadwell_de/southcluster.c I hope that helps. Best Regards, Philipp On 22.06.2018 12:18, Jorge Fernandez Monteagudo wrote: > Hi all, >

[coreboot] OSFC 2018

Dear Ladies and Gentlemen, We invite you to the Open Source Firmware Conference 2018 ( www.osfc.io ) which takes place at the 12th - 15th September in Erlangen, Germany. The OSFC 2018 is the first conference focusing exclusively on Open Source firmware. Therefore, our mission is to provide an

Re: [coreboot] SPI TPM question

Hey, The SPI tpm driver was written for tpm 2.0 only. You can try to add TPM to "depends on" as well and see what happens. Let us know if it works. :) Best Regards, Philipp On 15.05.2018 19:53, Jorge Fernandez Monteagudo wrote: > > Hi all! > > > This is my first message to the list. I would

Re: [coreboot] Why do we have FSP-S

You forgot Cavium Thunder X SoC support, Stefan ;) Finally coreboot supports it and there are no blobs on this platform. On 04.05.2018 20:01, Stefan Reinauer wrote: > * Timothy Pearson [180501 04:58]: >> -BEGIN PGP SIGNED MESSAGE- >> Hash: SHA256 >> >>

[coreboot] Open Source Firmware Conference 2018

Hi There! On behalf of the 9elements GmbH and the Siemens AG,  I would like to invite you to the Open Source Firmware Conference 2018, that is going to be held from **September 12th to 15th* *in Erlangen, Germany. Open source has revolutionised the process of software development. However,

Re: [coreboot] Coreboot events 2018

Last year I organized the European Coreboot Conference 2017 - ecc2017.coreboot.org . and this year I am the organizer of the Open Source Firmware Conference 2018 - www.osfc.io . So feel free to join us ;) On 22.04.2018 13:36, Alexey Borovikov wrote: > I want to visit in 2018 a conference on

Re: [coreboot] BIOS/CoreBoot/UBOOT

via IRC, my IRC handle is zaolin. Happy Hacking, Philipp On 12.04.2018 03:54, Raymond Yeung wrote: > > Thanks David for the detailed response. > > > My main motivation to go down Coreboot/UBOOT route is to attempt to > simplify the remaining boot-up to Linux.  Instead of us

Re: [coreboot] ECC2017: organized dinner on Thursday?

Hey, I have already organized the Dinner for Thursday and Friday. ;) Best Regards, Philipp On 10.10.2017 10:46, Goetz Salzmann wrote: > Dear list, > > looking at the ECC2017 Schedule there is an organized "Social Event" on > Friday. For Sat./Sun. we will probably have pizza in the hackcenter.

Re: [coreboot] [ANN] ECC 2017: Schedule and speakers published

Sure. All talks will be recorded and afterwards uploaded to our youtube channel ;) On 03.10.2017 14:09, Rene Shuster wrote: > Same here. Recorded presentations for later stream/download would be > very much appreciated. > > On Tue, Oct 3, 2017 at 7:42 AM, Rafael Machado >

Re: [coreboot] ECC’17: Fund developer travel costs

We can also help out to finding cheap hotels if needed. In order to do so, please contact Justine Spalik: justine.spa...@9elements.com On 22.09.2017 08:44, Paul Menzel wrote: > Dear coreboot folks, > > > The

[coreboot] Updated Invitation: Crazy Review Sunday @ Monthly on the second Sunday (CEST) (coreboot@coreboot.org)

BEGIN:VCALENDAR PRODID:-//Google Inc//Google Calendar 70.9054//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:REQUEST BEGIN:VTIMEZONE TZID:America/Denver X-LIC-LOCATION:America/Denver BEGIN:DAYLIGHT TZOFFSETFROM:-0700 TZOFFSETTO:-0600 TZNAME:MDT DTSTART:19700308T02

[coreboot] ECC'17 Call for papers is out now !

All information about the CFP can be found via https://ecc2017.coreboot.org/speakers Best Regards, Philipp ** signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] VT-d support

You are asking for VT-d support. You are talking about Intel platforms ? But for which specific platform you are asking for ? There are so many.. Am 05.06.2017 um 10:24 schrieb Himanshu Chauhan: > >> On 05-Jun-2017, at 9:41 PM, ron minnich wrote: >> >> >> >> On Mon, Jun 5,

[coreboot] Invitation european coreboot conference 2017 // Bochum // 26.-29.10.2017

projects (hackathon) as well as time to discuss the findings and results of the previous days. Tickets& further information: https://ecc2017.coreboot.org/ Call For Paper: 25.05.2017 - 26.08.2017 Thank you, Zaolin signature.asc Description: OpenPGP digital signature -- coreboot mailing

Re: [coreboot] Website pages are unreadable in a window or with a sidebar opened

You can easily fix it for yourself by pushing a new change to gerrit. Have fun! git clone ssh://your-usern...@review.coreboot.org:29418/homepage https://www.coreboot.org/Git On 04/21/2017 01:03 PM, Cordylus Interneter wrote: > Can be fixed by using max-width instead of max-device-width in the

Re: [coreboot] Where to get ME image/flash descriptors for the x220?

Have fun https://github.com/zaolin/coreboot-thinkpad-doc/tree/x220/firmware/splited On 03/13/2017 09:11 PM, taii...@gmx.com wrote: On 03/08/2017 01:29 PM, Igor Skochinsky wrote: Hello Taiidan, Alas, the 8duj28us.exe update and a few others I checked do not seem to contain the ME region

Re: [coreboot] The ECC 2017 web page

It depends on the browser if it uses hardware accerlation but I am gonna fix that for you. I will add some idle js which stops the video if not focused. Best Regards Zaolin On 03/03/2017 06:11 AM, ron minnich wrote: > That one web page, while not even visible, eats up 25% of the cpu on &g

Re: [coreboot] How to reduce formal issues with new contributions from corporations?

markdown files. It's also possible to use asciidoc or restructured Text for the documentation. Regards Zaolin On 02/28/2017 01:53 AM, taii...@gmx.com wrote: > On 02/27/2017 04:37 PM, Stefan Reinauer wrote: > >>> Should this documentation be moved to the repository? A lot of the >

Re: [coreboot] What payloads are easily usable with ARM targets?

Moin. phcoder ported GRUB2 for ARM. ;) I don't know if there are any plans to publish it. Best Regards Zaolin On 02/17/2017 09:28 AM, Paul Menzel via coreboot wrote: > Dear coreboot folks, > > > What payload can be easily build and used for ARM targets? > > If you have any

Re: [coreboot] coreboot assembly at 33c3

Hall 4 (Chaos West Assembly Hackcenter) towards hall 3. On 12/27/2016 05:16 AM, Jonathan Neuschäfer wrote: > On Tue, Dec 27, 2016 at 12:21:25AM +0100, Rudolf Marek wrote: >> Hi >> >> I think I seen this. I hope it is accurate. >> >> https://events.ccc.de/congress/2016/wiki/Assembly:Coreboot >>

Re: [coreboot] Rettungsboot

;) Best Regards Zaolin On 11/26/2016 11:47 PM, ron minnich wrote: > Oh, my fingers type too much for me now. > > The current set of (as you point out) not terrific options is a result > of linux growing too big for flash, and flash growing too SMALL for > linux, ca. 2002, when we adop

Re: [coreboot] Skylake FSP 1.1 without verstage?

Hey Trammell, congratulations ! I guess you are releasing the coreboot payload at the 33c3 ? Could you please submit a bug report at ticket.coreboot.org for that issue. Best Regards Philipp On 10/06/2016 01:25 AM, Trammell Hudson wrote: > On Wed, Oct 05, 2016 at 03:19:11PM -0500, Aaron Durbin

Re: [coreboot] Measuring the bootblock and adding a verstage

On 08/11/2016 05:33 PM, Trammell Hudson wrote: > On Thu, Aug 11, 2016 at 05:00:00PM +0200, Zaolin wrote: >> The whole TPM stack needs to be reworked until it can used for a >> measured boot. > Is it necessary to import the entire complexity of TSS for the measured >

Re: [coreboot] Measuring the bootblock and adding a verstage

Hey Trammell, No not really. Take a look at following patches: https://review.coreboot.org/#/c/10542/ https://review.coreboot.org/#/c/14038/ https://review.coreboot.org/#/c/14009/ https://review.coreboot.org/#/c/14134/ https://review.coreboot.org/#/c/14137/ https://review.coreboot.org/#/c/14135/

Re: [coreboot] buildgcc certs and signature hashes

Checkout my commit. Today I will upload a new version of it. https://review.coreboot.org/#/c/15170/ On 08/03/2016 03:52 PM, Trammell Hudson wrote: > It looks like the util/crossgcc/buildgcc script disables HTTPS cert > checks and doesn't have a way to verify the signatures or hashes of the >

Re: [coreboot] thinkpad t430s bios eeprom location

Hi, I did that more than 2 times with different Thinkpads. Just flash coreboot in order to access the EEPROM via i2c in operating system (see. i2c-tools). That's the easiest way I guess. Best Regards Zaolin On 06/11/2016 10:15 PM, Peter Stuge wrote: > Anthony Martin wrote: >> what's

Re: [coreboot] PC Engines APU2 support

Hi Piotr, > Hi all, > I'm working on support for PC Engines APU2 (AMD GX-412TC) board and I > finally manage to boot Voyage Linux and run memtest86+. There some > limitations and concerns that I have and hope you can advise how to > proceed. > > 1. Platform doesn't show anything on UART after

Re: [coreboot] How to protect binary in flash chip? OTP?

Hi Zheng, it is really hard to do that. I guess you'll need to have platform support for such a feature. Maybe you could ask Christopher Tarnovsky about such technologies (chris.tarnov...@ioactive.com). He is a kind guy and an expert when it comes to security chips/technologies on the hardware

Re: [coreboot] Community Meeting

Take a look at the brand new and shiny coreboot calender: https://www.coreboot.org/calendar.html ;) On 05/05/2016 04:06 AM, Kus wrote: > I wish I could attend but I can't. How often do these take place? > > 0xD81427AB.asc Description: application/pgp-keys signature.asc Description:

[coreboot] Community Meeting

rs who are interested in the same topic. -> For deeper information exchange split up in different jitsi meet channels and close meeting. 100) End ===== Best Regards Zaolin 0xD81427AB.asc Description: application/pgp-keys 0xD8142

[coreboot] Community Meeting

channels and close meeting. 100) End ===== Best Regards Zaolin 0xD81427AB.asc Description: application/pgp-keys signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Re : FOSDEM deadlines now!

I will be there. Regards Zaolin > [DEADLINE IS NOW+48 hours!] > Hi, > > thanks to Paul and Florentin for announcing they will come and thanks > to > Paul for submitting a talk! > > Who else is coming? > Do we want one or two tables? > > Regards, > Carl-D

Re: [coreboot] Linux kernel hangs

Hi, yep try this patch. Then it should work again. http://review.coreboot.org/#/c/12112/ Regards Zaolin > I'm testing the Lenovo T420 port[1]. After I saw some commits on > Sandy/Ivy RAM init and native graphics init code, I asked Nicolas > Reinecke to rebase and update the code

Re: [coreboot] coreboot on Lenovo T420

Hi Iru Cai, take a look at this http://review.coreboot.org/#/c/11765/ change. But beware there can be issues with that port. Regards Zaolin > Hi, > > I installed coreboot on my Lenovo ThinkPad T420 laptop today, and I'd > like to share some experience and hope some one can solve

Re: [coreboot] x230 - vgabios

65k size. If it's only one entry then you can stop here and use it as vgabios. 6) Get rom-parser https://github.com/awilliam/rom-parser and run it on the files. You will get printed some infos including the pci id. If the id matches with your graphics device use the it as vgabios. Regards Zaolin

Re: [coreboot] GRUB2 is too big as a payload in ThinkPad X201

Hi, simply fix this problems by increasing the cbfs size in menuconfig under the chipset section. Regards Zaolin Dear Iru, welcome to coreboot! Am Donnerstag, den 26.03.2015, 09:33 +0800 schrieb Iru Cai: I tried to use GRUB2 as a payload when building coreboot for ThinkPad X201

Re: [coreboot] x201t + windows7

Hi, have seen the same problem on all thinkpad product types supported by coreboot. Maybe someone should get a Windows Developer Edition and solve this bug ;) . Regards Zaolin Hi, I tried today a windows 7 installation usb stick and a cd disc. Both 32bit and 64bit. Both Windows' stopping

Re: [coreboot] Plans for upcoming Broadwell Thinkpads

Hi, let's say goodbye to all Intel notebooks produced by OEM's which are not Google ( Chromebooks ). Maybe the haswell/broadwell notebooks of Lenovo without U/Y processor can be used ( Thinkpad tXX xXX ). It depends if they are supporting Intel Boot Guard on the southbridge... Regards Zaolin

Re: [coreboot] Plans for upcoming Broadwell Thinkpads

and if they are locked down... Regards Zaolin On 02/06/2015 06:29 AM, Zaolin wrote: Hi, new thinkpad's can't be used anymore for coreboot. Especially the U and Y Intel CPU Series. They come with Intel Boot Guard and you are won't be able to boot anything which is unsigned and not approved by OEM

Re: [coreboot] Plans for upcoming Broadwell Thinkpads

. For more details take a look at Intel Boot Guard architecture. It could be also confirmed by Secunet AG and Google. Regards Zaolin I should probably not post about any Thinkpads till I get to test the T410s port... but anyway has anybody considered a port for the incoming Broadwell Thinkpads